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- From 2d2a4b860ef60b4d10754d2e690d6fc170571a83 Mon Sep 17 00:00:00 2001
- From: Hecanyang <[email protected]>
- Date: Sat, 23 Dec 2017 15:40:21 +0800
- Subject: [PATCH] arm64: dts: rockchip: add rk3328 ddr relate node
- except add note to existing dts file, also add ddr timing and de-skew's
- dts file.
- Change-Id: I92b7e9c2c6572babd4be00beadbbb75aae431707
- Signed-off-by: CanYang He <[email protected]>
- Signed-off-by: hmz007 <[email protected]>
- ---
- .../rockchip/rk3328-dram-2layer-timing.dtsi | 257 +++++++++++++++
- .../rockchip/rk3328-dram-default-timing.dtsi | 311 ++++++++++++++++++
- .../boot/dts/rockchip/rk3328-evb-android.dts | 9 +
- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 67 ++++
- 4 files changed, 644 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-2layer-timing.dtsi
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
- --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
- +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
- @@ -11,6 +11,7 @@
- #include <dt-bindings/power/rk3328-power.h>
- #include <dt-bindings/soc/rockchip,boot-mode.h>
- #include <dt-bindings/thermal/thermal.h>
- +#include "rk3328-dram-default-timing.dtsi"
-
- / {
- compatible = "rockchip,rk3328";
- @@ -1010,6 +1011,78 @@
- status = "disabled";
- };
-
- + dfi: dfi@ff790000 {
- + reg = <0x00 0xff790000 0x00 0x400>;
- + compatible = "rockchip,rk3328-dfi";
- + rockchip,grf = <&grf>;
- + status = "okay";
- + };
- +
- + dmc: dmc {
- + compatible = "rockchip,rk3328-dmc";
- + devfreq-events = <&dfi>;
- + clocks = <&cru SCLK_DDRCLK>;
- + clock-names = "dmc_clk";
- + operating-points-v2 = <&dmc_opp_table>;
- + ddr_timing = <&ddr_timing>;
- + upthreshold = <40>;
- + downdifferential = <20>;
- + auto-min-freq = <786000>;
- + auto-freq-en = <0>;
- + #cooling-cells = <2>;
- + status = "disabled";
- +
- + ddr_power_model: ddr_power_model {
- + compatible = "ddr_power_model";
- + dynamic-power-coefficient = <120>;
- + static-power-coefficient = <200>;
- + ts = <32000 4700 (-80) 2>;
- + thermal-zone = "soc-thermal";
- + };
- + };
- +
- + dmc_opp_table: dmc-opp-table {
- + compatible = "operating-points-v2";
- +
- + rockchip,leakage-voltage-sel = <
- + 1 10 0
- + 11 254 1
- + >;
- + nvmem-cells = <&logic_leakage>;
- + nvmem-cell-names = "ddr_leakage";
- +
- + opp-786000000 {
- + opp-hz = /bits/ 64 <786000000>;
- + opp-microvolt = <1075000>;
- + opp-microvolt-L0 = <1075000>;
- + opp-microvolt-L1 = <1050000>;
- + };
- + opp-798000000 {
- + opp-hz = /bits/ 64 <798000000>;
- + opp-microvolt = <1075000>;
- + opp-microvolt-L0 = <1075000>;
- + opp-microvolt-L1 = <1050000>;
- + };
- + opp-840000000 {
- + opp-hz = /bits/ 64 <840000000>;
- + opp-microvolt = <1075000>;
- + opp-microvolt-L0 = <1075000>;
- + opp-microvolt-L1 = <1050000>;
- + };
- + opp-924000000 {
- + opp-hz = /bits/ 64 <924000000>;
- + opp-microvolt = <1100000>;
- + opp-microvolt-L0 = <1100000>;
- + opp-microvolt-L1 = <1075000>;
- + };
- + opp-1056000000 {
- + opp-hz = /bits/ 64 <1056000000>;
- + opp-microvolt = <1175000>;
- + opp-microvolt-L0 = <1175000>;
- + opp-microvolt-L1 = <1150000>;
- + };
- + };
- +
- gic: interrupt-controller@ff811000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
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