OpenWrt_x86-r2s-r4s-r5s-N1/devices/common/patches/overclock-mt7621.patch

From cb934ac9c803e44b6d459fa1da774d2e92afcf9c Mon Sep 17 00:00:00 2001
From: garypang13 <[email protected]>
Date: Fri, 9 Oct 2020 16:23:31 +0800
Subject: [PATCH] Update 102-mt7621-fix-cpu-clk-add-clkdev.patch

---
 .../patches-5.4/102-mt7621-fix-cpu-clk-add-clkdev.patch   | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/linux/ramips/patches-5.4/102-mt7621-fix-cpu-clk-add-clkdev.patch b/target/linux/ramips/patches-5.4/102-mt7621-fix-cpu-clk-add-clkdev.patch
index 0c997a3f28f6..3d43c47eda00 100644
--- a/target/linux/ramips/patches-5.4/102-mt7621-fix-cpu-clk-add-clkdev.patch
+++ b/target/linux/ramips/patches-5.4/102-mt7621-fix-cpu-clk-add-clkdev.patch
@@ -65,7 +65,7 @@
  #define MT7621_GPIO_MODE_UART1		1
  #define MT7621_GPIO_MODE_I2C		2
  #define MT7621_GPIO_MODE_UART3_MASK	0x3
-@@ -111,49 +111,89 @@ static struct rt2880_pmx_group mt7621_pi
+@@ -111,49 +111,93 @@ static struct rt2880_pmx_group mt7621_pi
  	{ 0 }
  };
  
@@ -110,7 +110,7 @@
 +{
 +	u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
 +	u32 pll, prediv, fbdiv;
-+	u32 xtal_clk, cpu_clk, bus_clk;
++	u32 xtal_clk, cpu_clk, bus_clk,i;
 +	const static u32 prediv_tbl[] = {0, 1, 2, 2};
 +
 +	syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
@@ -154,6 +154,10 @@
 -			cpu_clk = 20 * fbdiv * 1000 * 1000;
 -		}
 +		pll = rt_memc_r32(MEMC_REG_CPU_PLL);
++		pll &= ~(0x7ff);
++		pll |=  (0x312);
++		rt_memc_w32(pll,MEMC_REG_CPU_PLL);
++		for(i=0;i<1024;i++);
 +		fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
 +		prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
 +		cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];