14-netcore-n60.patch 8.0 KB

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  1. From a8ddfc2e1025e2f35099b8757c7cf581cc87716b Mon Sep 17 00:00:00 2001
  2. From: aiamadeus <[email protected]>
  3. Date: Wed, 1 Nov 2023 20:25:18 +0800
  4. Subject: [PATCH] mediatek: add Netcore N60 support
  5. Connect to the router using ssh or telnet,
  6. username: useradmin, password is the web
  7. login password of the router.
  8. Signed-off-by: AnYun <[email protected]>
  9. ---
  10. .../mediatek/dts/mt7986a-netcore-n60.dts | 284 ++++++++++++++++++
  11. .../filogic/base-files/etc/board.d/02_network | 3 +-
  12. .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 3 +-
  13. target/linux/mediatek/image/filogic.mk | 14 +
  14. 4 files changed, 302 insertions(+), 2 deletions(-)
  15. create mode 100644 target/linux/mediatek/dts/mt7986a-netcore-n60.dts
  16. diff --git a/target/linux/mediatek/dts/mt7986a-netcore-n60.dts b/target/linux/mediatek/dts/mt7986a-netcore-n60.dts
  17. new file mode 100644
  18. index 0000000000000..4cbd9bdf0deb9
  19. --- /dev/null
  20. +++ b/target/linux/mediatek/dts/mt7986a-netcore-n60.dts
  21. @@ -0,0 +1,284 @@
  22. +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  23. +
  24. +/dts-v1/;
  25. +#include <dt-bindings/gpio/gpio.h>
  26. +#include <dt-bindings/input/input.h>
  27. +
  28. +#include "mt7986a.dtsi"
  29. +
  30. +/ {
  31. + model = "Netcore N60";
  32. + compatible = "netcore,n60", "mediatek,mt7986a";
  33. +
  34. + aliases {
  35. + serial0 = &uart0;
  36. + label-mac-device = &gmac0;
  37. + led-boot = &led_status_red;
  38. + led-failsafe = &led_status_red;
  39. + led-running = &led_status_blue;
  40. + led-upgrade = &led_status_blue;
  41. + };
  42. +
  43. + chosen {
  44. + stdout-path = "serial0:115200n8";
  45. + };
  46. +
  47. + memory {
  48. + reg = <0 0x40000000 0 0x10000000>;
  49. + };
  50. +
  51. + keys {
  52. + compatible = "gpio-keys";
  53. +
  54. + reset {
  55. + label = "reset";
  56. + linux,code = <KEY_RESTART>;
  57. + gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  58. + };
  59. +
  60. + mesh {
  61. + label = "mesh";
  62. + linux,code = <KEY_WPS_BUTTON>;
  63. + gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  64. + };
  65. + };
  66. +
  67. + leds {
  68. + compatible = "gpio-leds";
  69. +
  70. + led_status_red: status_red {
  71. + label = "red:status";
  72. + gpios = <&pio 29 GPIO_ACTIVE_LOW>;
  73. + };
  74. +
  75. + led_status_blue: status_blue {
  76. + label = "blue:status";
  77. + gpios = <&pio 32 GPIO_ACTIVE_LOW>;
  78. + };
  79. + };
  80. +};
  81. +
  82. +&crypto {
  83. + status = "okay";
  84. +};
  85. +
  86. +&eth {
  87. + status = "okay";
  88. +
  89. + gmac0: mac@0 {
  90. + compatible = "mediatek,eth-mac";
  91. + reg = <0>;
  92. + phy-mode = "2500base-x";
  93. +
  94. + nvmem-cells = <&macaddr_lan>;
  95. + nvmem-cell-names = "mac-address";
  96. +
  97. + fixed-link {
  98. + speed = <2500>;
  99. + full-duplex;
  100. + pause;
  101. + };
  102. + };
  103. +
  104. + gmac1: mac@1 {
  105. + compatible = "mediatek,eth-mac";
  106. + reg = <1>;
  107. + phy-handle = <&phy6>;
  108. + phy-mode = "2500base-x";
  109. +
  110. + nvmem-cells = <&macaddr_wan>;
  111. + nvmem-cell-names = "mac-address";
  112. + };
  113. +
  114. + mdio: mdio-bus {
  115. + #address-cells = <1>;
  116. + #size-cells = <0>;
  117. + };
  118. +};
  119. +
  120. +&mdio {
  121. + reset-delay-us = <600>;
  122. + reset-post-delay-us = <20000>;
  123. + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
  124. +
  125. + phy6: phy@6 {
  126. + compatible = "ethernet-phy-ieee802.3-c45";
  127. + reg = <6>;
  128. + mxl,led-config = <0x0 0x0 0x0 0x3f0>;
  129. + };
  130. +
  131. + switch: switch@0 {
  132. + compatible = "mediatek,mt7531";
  133. + reg = <31>;
  134. + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  135. + interrupt-controller;
  136. + #interrupt-cells = <1>;
  137. + interrupt-parent = <&pio>;
  138. + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  139. + };
  140. +};
  141. +
  142. +&switch {
  143. + ports {
  144. + #address-cells = <1>;
  145. + #size-cells = <0>;
  146. +
  147. + port@0 {
  148. + reg = <0>;
  149. + label = "lan1";
  150. + };
  151. +
  152. + port@1 {
  153. + reg = <1>;
  154. + label = "lan2";
  155. + };
  156. +
  157. + port@3 {
  158. + reg = <3>;
  159. + label = "lan3";
  160. + };
  161. +
  162. + port@4 {
  163. + reg = <4>;
  164. + label = "lan4";
  165. + };
  166. +
  167. + port@6 {
  168. + reg = <6>;
  169. + label = "cpu";
  170. + ethernet = <&gmac0>;
  171. + phy-mode = "2500base-x";
  172. +
  173. + fixed-link {
  174. + speed = <2500>;
  175. + full-duplex;
  176. + pause;
  177. + };
  178. + };
  179. + };
  180. +};
  181. +
  182. +&spi0 {
  183. + pinctrl-names = "default";
  184. + pinctrl-0 = <&spi_flash_pins>;
  185. + status = "okay";
  186. +
  187. + flash@0 {
  188. + compatible = "spi-nand";
  189. + #address-cells = <1>;
  190. + #size-cells = <1>;
  191. + reg = <0>;
  192. +
  193. + spi-max-frequency = <20000000>;
  194. + spi-tx-bus-width = <4>;
  195. + spi-rx-bus-width = <4>;
  196. +
  197. + mediatek,nmbm;
  198. + mediatek,bmt-max-ratio = <1>;
  199. + mediatek,bmt-max-reserved-blocks = <64>;
  200. +
  201. + partitions {
  202. + compatible = "fixed-partitions";
  203. + #address-cells = <1>;
  204. + #size-cells = <1>;
  205. +
  206. + partition@0 {
  207. + label = "BL2";
  208. + reg = <0x0000000 0x0100000>;
  209. + read-only;
  210. + };
  211. +
  212. + partition@100000 {
  213. + label = "u-boot-env";
  214. + reg = <0x0100000 0x0080000>;
  215. + };
  216. +
  217. + factory: partition@180000 {
  218. + label = "Factory";
  219. + reg = <0x0180000 0x0200000>;
  220. + read-only;
  221. + };
  222. +
  223. + partition@380000 {
  224. + label = "FIP";
  225. + reg = <0x0380000 0x0200000>;
  226. + read-only;
  227. + };
  228. +
  229. + partition@580000 {
  230. + label = "ubi";
  231. + reg = <0x0580000 0x7280000>;
  232. + };
  233. + };
  234. + };
  235. +};
  236. +
  237. +&pio {
  238. + spi_flash_pins: spi-flash-pins-33-to-38 {
  239. + mux {
  240. + function = "spi";
  241. + groups = "spi0", "spi0_wp_hold";
  242. + };
  243. + conf-pu {
  244. + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  245. + drive-strength = <8>;
  246. + mediatek,pull-up-adv = <0>; /* bias-disable */
  247. + };
  248. + conf-pd {
  249. + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  250. + drive-strength = <8>;
  251. + mediatek,pull-down-adv = <0>; /* bias-disable */
  252. + };
  253. + };
  254. +
  255. + wf_2g_5g_pins: wf_2g_5g-pins {
  256. + mux {
  257. + function = "wifi";
  258. + groups = "wf_2g", "wf_5g";
  259. + };
  260. + conf {
  261. + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  262. + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  263. + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  264. + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  265. + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  266. + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  267. + "WF1_TOP_CLK", "WF1_TOP_DATA";
  268. + drive-strength = <4>;
  269. + };
  270. + };
  271. +};
  272. +
  273. +&trng {
  274. + status = "okay";
  275. +};
  276. +
  277. +&uart0 {
  278. + status = "okay";
  279. +};
  280. +
  281. +&watchdog {
  282. + status = "okay";
  283. +};
  284. +
  285. +&wifi {
  286. + status = "okay";
  287. + pinctrl-names = "default";
  288. + pinctrl-0 = <&wf_2g_5g_pins>;
  289. +
  290. + mediatek,mtd-eeprom = <&factory 0x0>;
  291. +};
  292. +
  293. +&factory {
  294. + compatible = "nvmem-cells";
  295. + #address-cells = <1>;
  296. + #size-cells = <1>;
  297. +
  298. + macaddr_lan: macaddr@1fef20 {
  299. + reg = <0x1fef20 0x6>;
  300. + };
  301. +
  302. + macaddr_wan: macaddr@1fef26 {
  303. + reg = <0x1fef26 0x6>;
  304. + };
  305. +};
  306. diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
  307. index 6fa3a9218c629..b8ac6337bd15f 100644
  308. --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
  309. +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
  310. @@ -26,6 +26,7 @@
  311. asus,tuf-ax4200|\
  312. jdcloud,re-cp-03|\
  313. mediatek,mt7981-rfb|\
  314. + netcore,n60|\
  315. ruijie,rg-x60-pro|\
  316. unielec,u7981-01*|\
  317. zbtlink,zbt-z8102ax)
  318. diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
  319. index 7f97e55f1f973..9e35c61434be3 100644
  320. --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
  321. +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
  322. @@ -34,7 +34,8 @@ case "$board" in
  323. [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
  324. [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
  325. ;;
  326. - jcg,q30-pro)
  327. + jcg,q30-pro|\
  328. + netcore,n60)
  329. # Originally, phy1 is phy0 mac with LA bit set. However, this would conflict
  330. # addresses on multiple VIFs with the other radio. Use label mac to set LA bit.
  331. [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(get_mac_label) > /sys${DEVPATH}/macaddress
  332. diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk
  333. index ee29b1b5c6660..9cfd720e138df 100644
  334. --- a/target/linux/mediatek/image/filogic.mk
  335. +++ b/target/linux/mediatek/image/filogic.mk
  336. @@ -273,6 +273,20 @@ define Device/mediatek_mt7986b-rfb
  337. endef
  338. TARGET_DEVICES += mediatek_mt7986b-rfb
  339. +define Device/netcore_n60
  340. + DEVICE_VENDOR := Netcore
  341. + DEVICE_MODEL := N60
  342. + DEVICE_DTS := mt7986a-netcore-n60
  343. + DEVICE_DTS_DIR := ../dts
  344. + UBINIZE_OPTS := -E 5
  345. + BLOCKSIZE := 128k
  346. + PAGESIZE := 2048
  347. + KERNEL_IN_UBI := 1
  348. + DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
  349. + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
  350. +endef
  351. +TARGET_DEVICES += netcore_n60
  352. +
  353. define Device/qihoo_360t7
  354. DEVICE_VENDOR := Qihoo
  355. DEVICE_MODEL := 360T7