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@@ -0,0 +1,74 @@
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+From 0cf731f9ebb5bf6f252055bebf4463a5c0bd490b Mon Sep 17 00:00:00 2001
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+From: Lorenzo Bianconi <[email protected]>
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+Date: Tue, 23 Aug 2022 14:24:07 +0200
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+Subject: [PATCH] net: ethernet: mtk_eth_soc: fix hw hash reporting for
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+ MTK_NETSYS_V2
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+
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+Properly report hw rx hash for mt7986 chipset accroding to the new dma
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+descriptor layout.
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+
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+Fixes: 197c9e9b17b11 ("net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset")
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+Signed-off-by: Lorenzo Bianconi <[email protected]>
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+Link: https://lore.kernel.org/r/091394ea4e705fbb35f828011d98d0ba33808f69.1661257293.git.lorenzo@kernel.org
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+Signed-off-by: Paolo Abeni <[email protected]>
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+---
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+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 22 +++++++++++----------
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+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +++++
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+ 2 files changed, 17 insertions(+), 10 deletions(-)
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+
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+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+@@ -1469,10 +1469,19 @@ static int mtk_poll_rx(struct napi_struc
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+ skb->dev = netdev;
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+ skb_put(skb, pktlen);
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+
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+- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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++ hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
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++ if (hash != MTK_RXD5_FOE_ENTRY)
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++ skb_set_hash(skb, jhash_1word(hash, 0),
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++ PKT_HASH_TYPE_L4);
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+ rxdcsum = &trxd.rxd3;
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+- else
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++ } else {
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++ hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
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++ if (hash != MTK_RXD4_FOE_ENTRY)
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++ skb_set_hash(skb, jhash_1word(hash, 0),
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++ PKT_HASH_TYPE_L4);
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+ rxdcsum = &trxd.rxd4;
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++ }
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+
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+ if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
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+ skb->ip_summed = CHECKSUM_UNNECESSARY;
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+@@ -1481,16 +1490,9 @@ static int mtk_poll_rx(struct napi_struc
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+ skb->protocol = eth_type_trans(skb, netdev);
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+ bytes += pktlen;
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+
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+- hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
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+- if (hash != MTK_RXD4_FOE_ENTRY) {
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+- hash = jhash_1word(hash, 0);
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+- skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
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+- }
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+-
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+ reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
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+ if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
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+- mtk_ppe_check_skb(eth->ppe, skb,
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+- trxd.rxd4 & MTK_RXD4_FOE_ENTRY);
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++ mtk_ppe_check_skb(eth->ppe, skb, hash);
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+
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+ if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+@@ -307,6 +307,11 @@
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+ #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
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+ #define RX_DMA_SPECIAL_TAG BIT(22)
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+
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++/* PDMA descriptor rxd5 */
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++#define MTK_RXD5_FOE_ENTRY GENMASK(14, 0)
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++#define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18)
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++#define MTK_RXD5_SRC_PORT GENMASK(29, 26)
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++
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+ #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0xf)
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+ #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0x7)
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+
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Daniel Golle