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@@ -1,92 +1,90 @@
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From: George Moussalem via B4 Relay
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<[email protected]>
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-Date: Fri, 28 Nov 2025 14:29:14 +0400
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-Subject: [PATCH v19 2/6] pwm: driver for qualcomm ipq6018 pwm block
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+Date: Wed, 04 Feb 2026 15:25:08 +0400
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+Subject: [PATCH v20 2/6] pwm: driver for qualcomm ipq6018 pwm block
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+Message-Id: <20260204-ipq-pwm-v20-2-91733011a3d1@outlook.com>
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+References: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com>
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+In-Reply-To: <20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com>
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To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <[email protected]>,
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Rob Herring <[email protected]>, Krzysztof Kozlowski <[email protected]>,
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Conor Dooley <[email protected]>, Baruch Siach <[email protected]>,
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@@ -98,11 +96,11 @@ Cc: [email protected], [email protected],
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Devi Priya <[email protected]>,
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Baruch Siach <[email protected]>
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[email protected]; s=20250321; h=from:subject:message-id;
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X-Endpoint-Received: by B4 Relay for [email protected]/20250321
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@@ -124,118 +122,6 @@ Signed-off-by: Devi Priya <[email protected]>
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Reviewed-by: Bjorn Andersson <[email protected]>
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Signed-off-by: George Moussalem <[email protected]>
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---
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-v18:
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-
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- Added hardware notes and limitations based on own findings as
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- requested. NOTE: there's no publically available datasheet though.
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-
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- Expanded comment on REG1_UPDATE to indicate that when this bit is set,
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- values for div and pre-div take effect. The hardware automatically
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- unsets it when the change is completed.
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-
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- Added newline between MACRO definition and next comment
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-
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- In config_div_and_duty, used mul_u64_u64_div_u64 to avoid overflow
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-
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- Removed unncessary restriction of pwm_div to MAX_DIV - 1 after testing
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-
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- Constrain pre_div to MAX_DIV is pre_div calculated is > MAX_DIV
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-
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- Use of mul_u64_u64_div_u64 in .apply
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-
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- Skip calculation of period and duty cycle when PWM_ENABLE REG is unset
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-
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- Set duty cycle to period value when calculated duty cycle > period to
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- return a valid config
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-
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- Removed .npwm as it's taken care of in devm_pwmchip_alloc
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-
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- Added call to devm_clk_rate_exclusive_get to lock the clock rate
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-
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- Start all kernel messages with a capital letter and end with \n.
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-
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-v17:
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-
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- Removed unnecessary code comments
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-
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-v16:
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-
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- Simplified code to calculate divs and duty cycle as per Uwe's comments
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-
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- Removed unused pwm_chip struct from ipq_pwm_chip struct
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-
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- Removed unnecessary cast as per Uwe's comment
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-
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- Replaced devm_clk_get & clk_prepare_enable by devm_clk_get_enabled
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-
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- Replaced pwmchip_add by devm_pwmchip_add and removed .remove function
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-
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- Removed .owner from driver struct
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-
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-v15:
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-
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- No change
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-
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-v14:
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-
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- Picked up the R-b tag
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-
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-v13:
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-
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- Updated the file name to match the compatible
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-
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- Sorted the properties and updated the order in the required field
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-
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- Dropped the syscon node from examples
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-
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-v12:
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-
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- Picked up the R-b tag
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-
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-v11:
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-
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- No change
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-
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-v10:
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-
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- No change
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-
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-v9:
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-
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- Add 'ranges' property to example (Rob)
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-
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- Drop label in example (Rob)
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-
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-v8:
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-
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- Add size cell to 'reg' (Rob)
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-
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-v7:
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-
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- Use 'reg' instead of 'offset' (Rob)
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-
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- Drop 'clock-names' and 'assigned-clock*' (Bjorn)
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-
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- Use single cell address/size in example node (Bjorn)
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-
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- Move '#pwm-cells' lower in example node (Bjorn)
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-
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- List 'reg' as required
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-
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-v6:
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-
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- Device node is child of TCSR; remove phandle (Rob Herring)
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-
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- Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)
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-
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-v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn
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- Andersson, Kathiravan T)
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-
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-v4: Update the binding example node as well (Rob Herring's bot)
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-
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-v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)
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-
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-v2: Make #pwm-cells const (Rob Herring)
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---
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drivers/pwm/Kconfig | 12 +++
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drivers/pwm/Makefile | 1 +
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@@ -312,12 +198,6 @@ v2: Make #pwm-cells const (Rob Herring)
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+#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC)
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+
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+/*
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-+ * The max value specified for each field is based on the number of bits
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-+ * in the pwm control register for that field
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-+ */
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-+#define IPQ_PWM_MAX_DIV 0xFFFF
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-+
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-+/*
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+ * Two 32-bit registers for each PWM: REG0, and REG1.
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+ * Base offset for PWM #i is at 8 * #i.
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+ */
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@@ -329,6 +209,12 @@ v2: Make #pwm-cells const (Rob Herring)
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+#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0)
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+
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+/*
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++ * The max value specified for each field is based on the number of bits
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++ * in the pwm control register for that field (16-bit)
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++ */
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++#define IPQ_PWM_MAX_DIV FIELD_MAX(IPQ_PWM_REG0_PWM_DIV)
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++
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++/*
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+ * Enable bit is set to enable output toggling in pwm device.
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+ * Update bit is set to trigger the change and is unset automatically
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+ * to reflect the changed divider and high duration values in register.
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@@ -337,8 +223,8 @@ v2: Make #pwm-cells const (Rob Herring)
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+#define IPQ_PWM_REG1_ENABLE BIT(31)
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+
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+struct ipq_pwm_chip {
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-+ struct clk *clk;
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+ void __iomem *mem;
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++ unsigned long clk_rate;
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+};
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+
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+static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip)
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@@ -363,57 +249,55 @@ v2: Make #pwm-cells const (Rob Herring)
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+ writel(val, ipq_chip->mem + off);
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+}
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+
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-+static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_div,
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-+ unsigned int pwm_div, unsigned long rate, u64 duty_ns,
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-+ bool enable)
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-+{
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-+ unsigned long hi_dur;
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-+ unsigned long val = 0;
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-+
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-+ /*
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-+ * high duration = pwm duty * (pwm div + 1)
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-+ * pwm duty = duty_ns / period_ns
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-+ */
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-+ hi_dur = mul_u64_u64_div_u64(duty_ns, rate, (pre_div + 1) * NSEC_PER_SEC);
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-+
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-+ val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |
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-+ FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);
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-+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val);
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-+
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-+ val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div);
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-+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
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-+
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-+ /* PWM enable toggle needs a separate write to REG1 */
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-+ val |= IPQ_PWM_REG1_UPDATE;
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-+ if (enable)
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-+ val |= IPQ_PWM_REG1_ENABLE;
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-+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
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-+}
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-+
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+static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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+ const struct pwm_state *state)
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+{
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+ struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
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-+ unsigned long rate = clk_get_rate(ipq_chip->clk);
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+ unsigned int pre_div, pwm_div;
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+ u64 period_ns, duty_ns;
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++ unsigned long val = 0;
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++ unsigned long hi_dur;
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+
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+ if (state->polarity != PWM_POLARITY_NORMAL)
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+ return -EINVAL;
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+
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-+ if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate))
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++ if (!ipq_chip->clk_rate)
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++ return -EINVAL;
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++
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++ if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC,
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++ ipq_chip->clk_rate))
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+ return -ERANGE;
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+
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+ period_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS);
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+ duty_ns = min(state->duty_cycle, period_ns);
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+
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-+ pwm_div = IPQ_PWM_MAX_DIV;
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-+ pre_div = mul_u64_u64_div_u64(period_ns, rate, (u64)NSEC_PER_SEC * (pwm_div + 1));
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++ pwm_div = IPQ_PWM_MAX_DIV - 1;
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++ pre_div = mul_u64_u64_div_u64(period_ns, ipq_chip->clk_rate,
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++ (u64)NSEC_PER_SEC * (pwm_div + 1));
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++ pre_div = (pre_div > 0) ? pre_div - 1 : 0;
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+
|
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+ if (pre_div > IPQ_PWM_MAX_DIV)
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+ pre_div = IPQ_PWM_MAX_DIV;
|
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+
|
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|
-+ config_div_and_duty(pwm, pre_div, pwm_div, rate, duty_ns, state->enabled);
|
|
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++ /*
|
|
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++ * high duration = pwm duty * (pwm div + 1)
|
|
|
++ * pwm duty = duty_ns / period_ns
|
|
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++ */
|
|
|
++ hi_dur = mul_u64_u64_div_u64(duty_ns, ipq_chip->clk_rate,
|
|
|
++ (u64)(pre_div + 1) * NSEC_PER_SEC);
|
|
|
++
|
|
|
++ val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |
|
|
|
++ FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);
|
|
|
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val);
|
|
|
++
|
|
|
++ val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div);
|
|
|
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
|
|
|
++
|
|
|
++ /* PWM enable toggle needs a separate write to REG1 */
|
|
|
++ val |= IPQ_PWM_REG1_UPDATE;
|
|
|
++ if (state->enabled)
|
|
|
++ val |= IPQ_PWM_REG1_ENABLE;
|
|
|
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
@@ -422,7 +306,6 @@ v2: Make #pwm-cells const (Rob Herring)
|
|
|
+ struct pwm_state *state)
|
|
|
+{
|
|
|
+ struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
|
|
|
-+ unsigned long rate = clk_get_rate(ipq_chip->clk);
|
|
|
+ unsigned int pre_div, pwm_div, hi_dur;
|
|
|
+ u64 effective_div, hi_div;
|
|
|
+ u32 reg0, reg1;
|
|
|
@@ -441,12 +324,13 @@ v2: Make #pwm-cells const (Rob Herring)
|
|
|
+ hi_dur = FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0);
|
|
|
+ pre_div = FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1);
|
|
|
+
|
|
|
-+ /* No overflow here, both pre_div and pwm_div <= 0xffff */
|
|
|
-+ effective_div = (pre_div + 1) * (pwm_div + 1);
|
|
|
-+ state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate);
|
|
|
++ effective_div = (u64)(pre_div + 1) * (pwm_div + 1);
|
|
|
++ state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC,
|
|
|
++ ipq_chip->clk_rate);
|
|
|
+
|
|
|
+ hi_div = hi_dur * (pre_div + 1);
|
|
|
-+ state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate);
|
|
|
++ state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC,
|
|
|
++ ipq_chip->clk_rate);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * ensure a valid config is passed back to PWM core in case duty_cycle
|
|
|
@@ -467,6 +351,7 @@ v2: Make #pwm-cells const (Rob Herring)
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct ipq_pwm_chip *pwm;
|
|
|
+ struct pwm_chip *chip;
|
|
|
++ struct clk *clk;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ chip = devm_pwmchip_alloc(dev, 4, sizeof(*pwm));
|
|
|
@@ -477,17 +362,18 @@ v2: Make #pwm-cells const (Rob Herring)
|
|
|
+ pwm->mem = devm_platform_ioremap_resource(pdev, 0);
|
|
|
+ if (IS_ERR(pwm->mem))
|
|
|
+ return dev_err_probe(dev, PTR_ERR(pwm->mem),
|
|
|
-+ "Failed to acquire resource\n");
|
|
|
++ "Failed to acquire resource\n");
|
|
|
+
|
|
|
-+ pwm->clk = devm_clk_get_enabled(dev, NULL);
|
|
|
-+ if (IS_ERR(pwm->clk))
|
|
|
-+ return dev_err_probe(dev, PTR_ERR(pwm->clk),
|
|
|
-+ "Failed to get clock\n");
|
|
|
++ clk = devm_clk_get_enabled(dev, NULL);
|
|
|
++ if (IS_ERR(clk))
|
|
|
++ return dev_err_probe(dev, PTR_ERR(clk),
|
|
|
++ "Failed to get clock\n");
|
|
|
+
|
|
|
-+ ret = devm_clk_rate_exclusive_get(dev, pwm->clk);
|
|
|
++ ret = devm_clk_rate_exclusive_get(dev, clk);
|
|
|
+ if (ret)
|
|
|
-+ return dev_err_probe(dev, ret,
|
|
|
-+ "Failed to lock clock rate\n");
|
|
|
++ return dev_err_probe(dev, ret, "Failed to lock clock rate\n");
|
|
|
++
|
|
|
++ pwm->clk_rate = clk_get_rate(clk);
|
|
|
+
|
|
|
+ chip->ops = &ipq_pwm_ops;
|
|
|
+
|
|
|
@@ -495,7 +381,7 @@ v2: Make #pwm-cells const (Rob Herring)
|
|
|
+ if (ret < 0)
|
|
|
+ return dev_err_probe(dev, ret, "Failed to add pwm chip\n");
|
|
|
+
|
|
|
-+ return ret;
|
|
|
++ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct of_device_id pwm_ipq_dt_match[] = {
|
Kenneth Kasilag