qualcommax: ipq50xx: fix GE_PHY and Uniphy resets

Fix the resets of the GE_PHY and Uniphy found on the IPQ5018 SoC.
Bitmasks are used to perform multiple resets simultaneously, including
the RX and TX clocks. This enables the Uniphy to properly shift between
SGMII/1G and SGMII+/2.5G modes.

While at it, properly reorder the patches, and rename some to follow
naming standards.

Signed-off-by: George Moussalem <[email protected]>
Link: https://github.com/openwrt/openwrt/pull/18638
Signed-off-by: Robert Marko <[email protected]>

target/linux/qualcommax/patches-6.6/0721-clk-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch → target/linux/qualcommax/patches-6.6/0715-clk-qcom-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch

@@ -1,7 +1,7 @@
 From f71366e0530db2c5cecbbbb6edfbf7344bd6f83b Mon Sep 17 00:00:00 2001
 From: Ziyang Huang <[email protected]>
 Date: Sun, 8 Sep 2024 16:40:12 +0800
-Subject: [PATCH 1/2] clk: gcc-ipq5018: remove the unsupported clk
+Subject: [PATCH] clk: gcc-ipq5018: remove the unsupported clk
  combination for gmac
 
 Comment out the unsupported clock combination in the frequency table 

target/linux/qualcommax/patches-6.6/0717-clk-qcom-gcc-ipq5018-fix-ge_phy-and-uniphy-resets.patch

@@ -0,0 +1,45 @@
+From: George Moussalem <[email protected]>
+Date: Tue, 29 Apr 2025 17:16:31 +0400
+Subject: [PATCH] clk: qcom: gcc-ipq5018: fix GE_PHY and Uniphy resets
+
+The resets for the GE PHY and Uniphy use bitmasks to assert multiple
+resets simultaneously. These bitmasks are missing and the reset is only
+performed partially against BIT(x) where x is the bit set in the GCC.
+So let's remove the single bit and replace them by the bitmasks as
+intended.
+
+Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932
+Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/036bdc62aca561e8ff94a29c447fc400de2b7304
+
+Signed-off-by: zhongjia <[email protected]>
+Signed-off-by: George Moussalem <[email protected]>
+---
+--- a/drivers/clk/qcom/gcc-ipq5018.c
++++ b/drivers/clk/qcom/gcc-ipq5018.c
+@@ -3566,7 +3566,7 @@ static const struct qcom_reset_map gcc_i
+ 	[GCC_DDRSS_BCR] = { 0x1e000, 0 },
+ 	[GCC_EDPD_BCR] = { 0x3a000, 0 },
+ 	[GCC_GEPHY_BCR] = { 0x56000, 0 },
+-	[GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
++	[GCC_GEPHY_MDC_SW_ARES] = { 0x56004, .bitmask = 0x3 },
+ 	[GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
+ 	[GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
+ 	[GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
+@@ -3646,7 +3646,7 @@ static const struct qcom_reset_map gcc_i
+ 	[GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
+ 	[GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
+ 	[GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
+-	[GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
++	[GCC_UNIPHY_SOFT_RESET] = {0x56104, .bitmask = 0x32 },
+ 	[GCC_USB0_BCR] = { 0x3e070, 0 },
+ 	[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
+ 	[GCC_WCSS_BCR] = { 0x18000, 0 },
+@@ -3659,7 +3659,7 @@ static const struct qcom_reset_map gcc_i
+ 	[GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
+ 	[GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
+ 	[GCC_WCSSAON_RESET] = { 0x59010, 0},
+-	[GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
++	[GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = 0xf },
+ };
+ 
+ static const struct of_device_id gcc_ipq5018_match_table[] = {

target/linux/qualcommax/patches-6.6/0713-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch → target/linux/qualcommax/patches-6.6/0718-arm64-dts-qcom-ipq5018-add-ge_phy-node.patch

@@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <[email protected]>
 
 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -202,6 +202,21 @@
+@@ -202,6 +202,19 @@
  			clock-names = "gcc_mdio_ahb_clk";
  
  			status = "disabled";
@@ -21,21 +21,19 @@ Signed-off-by: George Moussalem <[email protected]>
 +			ge_phy: ethernet-phy@7 {
 +				compatible = "ethernet-phy-id004d.d0c0";
 +				reg = <7>;
++
 +				clocks = <&gcc GCC_GEPHY_RX_CLK>,
 +					 <&gcc GCC_GEPHY_TX_CLK>;
 +
 +				resets = <&gcc GCC_GEPHY_BCR>,
-+					 <&gcc GCC_GEPHY_MDC_SW_ARES>,
-+					 <&gcc GCC_GEPHY_DSP_HW_ARES>,
-+					 <&gcc GCC_GEPHY_RX_ARES>,
-+					 <&gcc GCC_GEPHY_TX_ARES>;
++					 <&gcc GCC_GEPHY_MISC_ARES>;
 +
 +				#clock-cells = <1>;
 +			};
  		};
  
  		mdio1: mdio@90000 {
-@@ -398,8 +413,8 @@
+@@ -398,8 +411,8 @@
  				 <&pcie0_phy>,
  				 <&pcie1_phy>,
  				 <0>,

target/linux/qualcommax/patches-6.6/0816-arm64-dts-qcom-ipq5018-add-wifi-support.patch

@@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <[email protected]>
 ---
 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -699,6 +699,225 @@
+@@ -697,6 +697,225 @@
  			};
  		};