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@@ -152,6 +152,65 @@
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};
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};
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+ thermal-zones {
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+ cpu_thermal: cpu-thermal {
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+ polling-delay-passive = <1000>;
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+ polling-delay = <1000>;
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+ thermal-sensors = <&lvts 0>;
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+ trips {
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+ cpu_trip_crit: crit {
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+ temperature = <125000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+
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+ cpu_trip_hot: hot {
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+ temperature = <120000>;
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+ hysteresis = <2000>;
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+ type = "hot";
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+ };
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+
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+ cpu_trip_active_high: active-high {
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+ temperature = <115000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+
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+ cpu_trip_active_med: active-med {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+
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+ cpu_trip_active_low: active-low {
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+ temperature = <40000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+ };
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+
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+ cooling-maps {
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+ cpu-active-high {
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+ /* active: set fan to cooling level 2 */
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+ cooling-device = <&fan 3 3>;
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+ trip = <&cpu_trip_active_high>;
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+ };
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+
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+ cpu-active-low {
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+ /* active: set fan to cooling level 1 */
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+ cooling-device = <&fan 2 2>;
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+ trip = <&cpu_trip_active_med>;
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+ };
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+
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+ cpu-passive {
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+ /* passive: set fan to cooling level 0 */
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+ cooling-device = <&fan 1 1>;
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+ trip = <&cpu_trip_active_low>;
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+ };
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+ };
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+ };
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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@@ -161,6 +220,24 @@
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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+ reg_1p8v: regulator-1p8v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-1.8V";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-3.3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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@@ -386,6 +463,80 @@
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groups = "uart0";
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};
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};
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+
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+ snfi_pins: snfi-pins {
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+ mux {
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+ function = "flash";
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+ groups = "snfi";
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+ };
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+ };
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+
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+ spi0_pins: spi0-pins {
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+ mux {
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+ function = "spi";
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+ groups = "spi0";
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+ };
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+ };
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+
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+ spi0_flash_pins: spi0-flash-pins {
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+ mux {
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+ function = "spi";
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+ groups = "spi0", "spi0_wp_hold";
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+ };
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+ };
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+
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+ spi1_pins: spi1-pins {
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+ mux {
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+ function = "spi";
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+ groups = "spi1";
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+ };
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+ };
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+
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+ spi2_pins: spi2-pins {
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+ mux {
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+ function = "spi";
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+ groups = "spi2";
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+ };
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+ };
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+
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+ spi2_flash_pins: spi2-flash-pins {
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+ mux {
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+ function = "spi";
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+ groups = "spi2", "spi2_wp_hold";
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+ };
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+ };
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+
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+ pcie0_pins: pcie0-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
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+ "pcie_wake_n0_0";
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+ };
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+ };
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+
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+ pcie1_pins: pcie1-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
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+ "pcie_wake_n1_0";
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+ };
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+ };
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+
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+ pcie2_pins: pcie2-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
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+ "pcie_wake_n2_0";
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+ };
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+ };
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+
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+ pcie3_pins: pcie3-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
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+ "pcie_wake_n3_0";
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+ };
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+ };
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};
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sgmiisys0: syscon@10060000 {
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@@ -420,24 +571,24 @@
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#clock-cells = <1>;
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};
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- xfi_pextp0: xfi_pextp@11f20000 {
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- compatible = "mediatek,mt7988-xfi_pextp",
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- "mediatek,mt7988-xfi_pextp_0",
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+ xfi_pextp0: xfi-pextp@11f20000 {
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+ compatible = "mediatek,mt7988-xfi-pextp",
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+ "mediatek,mt7988-xfi-pextp_0",
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"syscon";
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reg = <0 0x11f20000 0 0x10000>;
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#clock-cells = <1>;
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};
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- xfi_pextp1: xfi_pextp@11f30000 {
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- compatible = "mediatek,mt7988-xfi_pextp",
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- "mediatek,mt7988-xfi_pextp_1",
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+ xfi_pextp1: xfi-pextp@11f30000 {
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+ compatible = "mediatek,mt7988-xfi-pextp",
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+ "mediatek,mt7988-xfi-pextp_1",
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"syscon";
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reg = <0 0x11f30000 0 0x10000>;
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#clock-cells = <1>;
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};
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- xfi_pll: xfi_pll@11f40000 {
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- compatible = "mediatek,mt7988-xfi_pll", "syscon";
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+ xfi_pll: xfi-pll@11f40000 {
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+ compatible = "mediatek,mt7988-xfi-pll", "syscon";
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reg = <0 0x11f40000 0 0x1000>;
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#clock-cells = <1>;
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};
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@@ -470,6 +621,35 @@
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status = "disabled";
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};
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+ snand: spi@11001000 {
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+ compatible = "mediatek,mt7986-snand";
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+ reg = <0 0x11001000 0 0x1000>;
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+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg CLK_INFRA_SPINFI>,
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+ <&infracfg CLK_INFRA_NFI>;
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+ clock-names = "pad_clk", "nfi_clk";
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+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
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+ <&topckgen CLK_TOP_NFI1X_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
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+ <&topckgen CLK_TOP_MPLL_D8>;
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+ nand-ecc-engine = <&bch>;
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+ mediatek,quad-spi;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&snfi_pins>;
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+ status = "disabled";
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+ };
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+
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+ bch: ecc@11002000 {
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+ compatible = "mediatek,mt7686-ecc";
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+ reg = <0 0x11002000 0 0x1000>;
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+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
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+ clock-names = "nfiecc_clk";
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+ status = "disabled";
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+ };
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+
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i2c0: i2c@11003000 {
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compatible = "mediatek,mt7988-i2c",
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"mediatek,mt7981-i2c";
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@@ -525,10 +705,118 @@
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<&infracfg CLK_INFRA_66M_SPI0_HCK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk",
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"spi-hclk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+ spi1: spi@11008000 {
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+ compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
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+ reg = <0 0x11008000 0 0x100>;
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+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
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+ <&topckgen CLK_TOP_SPI_SEL>,
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+ <&infracfg CLK_INFRA_104M_SPI1>,
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+ <&infracfg CLK_INFRA_66M_SPI1_HCK>;
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+ clock-names = "parent-clk", "sel-clk", "spi-clk",
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+ "spi-hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1_pins>;
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+ status = "disabled";
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+ };
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+
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+ spi2: spi@11009000 {
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+ compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
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+ reg = <0 0x11009000 0 0x100>;
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+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
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+ <&topckgen CLK_TOP_SPI_SEL>,
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+ <&infracfg CLK_INFRA_104M_SPI2_BCK>,
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+ <&infracfg CLK_INFRA_66M_SPI2_HCK>;
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+ clock-names = "parent-clk", "sel-clk", "spi-clk",
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+ "spi-hclk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+ pwm: pwm@10048000 {
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+ compatible = "mediatek,mt7988-pwm";
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+ reg = <0 0x10048000 0 0x1000>;
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+ #pwm-cells = <2>;
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+ clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
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+ <&infracfg CLK_INFRA_66M_PWM_HCK>,
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+ <&infracfg CLK_INFRA_66M_PWM_CK1>,
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+ <&infracfg CLK_INFRA_66M_PWM_CK2>,
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+ <&infracfg CLK_INFRA_66M_PWM_CK3>,
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+ <&infracfg CLK_INFRA_66M_PWM_CK4>,
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+ <&infracfg CLK_INFRA_66M_PWM_CK5>,
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+ <&infracfg CLK_INFRA_66M_PWM_CK6>,
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+ <&infracfg CLK_INFRA_66M_PWM_CK7>,
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+ <&infracfg CLK_INFRA_66M_PWM_CK8>;
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+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
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+ "pwm4","pwm5","pwm6","pwm7","pwm8";
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+ status = "disabled";
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+ };
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+
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+ fan: pwm-fan {
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+ compatible = "pwm-fan";
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+ /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
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+ cooling-levels = <0 128 255>;
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+ #cooling-cells = <2>;
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+ #thermal-sensor-cells = <1>;
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+ status = "disabled";
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+ };
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+
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+ lvts: lvts@1100a000 {
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+ compatible = "mediatek,mt7988-lvts";
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+ #thermal-sensor-cells = <1>;
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+ reg = <0 0x1100a000 0 0x1000>;
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+ clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
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+ clock-names = "lvts_clk";
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+ nvmem-cells = <&lvts_calibration>;
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+ nvmem-cell-names = "e_data1";
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+ };
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+
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+ crypto: crypto@15600000 {
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+ compatible = "inside-secure,safexcel-eip197b";
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+ reg = <0 0x15600000 0 0x180000>;
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+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
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+ status = "okay";
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+ };
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+
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+ afe: audio-controller@11210000 {
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+ compatible = "mediatek,mt79xx-audio";
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+ reg = <0 0x11210000 0 0x9000>;
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+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
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+ <&infracfg CLK_INFRA_AUD_26M>,
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+ <&infracfg CLK_INFRA_AUD_L>,
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+ <&infracfg CLK_INFRA_AUD_AUD>,
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+ <&infracfg CLK_INFRA_AUD_EG2>,
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+ <&topckgen CLK_TOP_AUD_SEL>,
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+ <&topckgen CLK_TOP_AUD_I2S_M>;
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+ clock-names = "aud_bus_ck",
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+ "aud_26m_ck",
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+ "aud_l_ck",
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+ "aud_aud_ck",
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+ "aud_eg2_ck",
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+ "aud_sel",
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+ "aud_i2s_m";
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+ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
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+ <&topckgen CLK_TOP_A1SYS_SEL>,
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+ <&topckgen CLK_TOP_AUD_L_SEL>,
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+ <&topckgen CLK_TOP_A_TUNER_SEL>;
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+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
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+ <&topckgen CLK_TOP_APLL2_D4>,
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+ <&apmixedsys CLK_APMIXED_APLL2>,
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+ <&topckgen CLK_TOP_APLL2_D4>;
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status = "disabled";
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};
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@@ -554,6 +842,8 @@
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<&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie2_pins>;
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status = "disabled";
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phys = <&xphyu3port0 PHY_TYPE_PCIE>;
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@@ -594,6 +884,8 @@
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<&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie3_pins>;
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status = "disabled";
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#interrupt-cells = <1>;
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@@ -631,6 +923,8 @@
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<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie0_pins>;
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status = "disabled";
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#interrupt-cells = <1>;
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@@ -668,6 +962,8 @@
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<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie1_pins>;
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status = "disabled";
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#interrupt-cells = <1>;
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@@ -909,7 +1205,7 @@
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mediatek,pio = <&pio>;
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gsw_phy0: ethernet-phy@0 {
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- compatible = "ethernet-phy-id03a2.9481";
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+ compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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phy-mode = "internal";
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nvmem-cells = <&phy_calibration_p0>;
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@@ -934,7 +1230,7 @@
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};
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gsw_phy1: ethernet-phy@1 {
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- compatible = "ethernet-phy-id03a2.9481";
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+ compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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phy-mode = "internal";
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nvmem-cells = <&phy_calibration_p1>;
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@@ -959,7 +1255,7 @@
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};
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gsw_phy2: ethernet-phy@2 {
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- compatible = "ethernet-phy-id03a2.9481";
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|
+ compatible = "ethernet-phy-ieee802.3-c22";
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|
reg = <2>;
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|
|
phy-mode = "internal";
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|
nvmem-cells = <&phy_calibration_p2>;
|
|
@@ -984,7 +1280,7 @@
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|
};
|
|
|
|
|
|
gsw_phy3: ethernet-phy@3 {
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|
- compatible = "ethernet-phy-id03a2.9481";
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|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
reg = <3>;
|
|
|
phy-mode = "internal";
|
|
|
nvmem-cells = <&phy_calibration_p3>;
|
|
@@ -1096,19 +1392,19 @@
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|
|
mediatek,ethsys = <ðsys>;
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|
|
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
|
|
mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
|
|
|
- mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
|
|
|
- mediatek,xfi_pll = <&xfi_pll>;
|
|
|
+ mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
|
|
|
+ mediatek,xfi-pll = <&xfi_pll>;
|
|
|
mediatek,infracfg = <&topmisc>;
|
|
|
mediatek,toprgu = <&watchdog>;
|
|
|
#reset-cells = <1>;
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
- status = "disabled";
|
|
|
|
|
|
gmac0: mac@0 {
|
|
|
compatible = "mediatek,eth-mac";
|
|
|
reg = <0>;
|
|
|
phy-mode = "internal";
|
|
|
+ status = "disabled";
|
|
|
|
|
|
fixed-link {
|
|
|
speed = <10000>;
|
|
@@ -1120,11 +1416,13 @@
|
|
|
gmac1: mac@1 {
|
|
|
compatible = "mediatek,eth-mac";
|
|
|
reg = <1>;
|
|
|
+ status = "disabled";
|
|
|
};
|
|
|
|
|
|
gmac2: mac@2 {
|
|
|
compatible = "mediatek,eth-mac";
|
|
|
reg = <2>;
|
|
|
+ status = "disabled";
|
|
|
};
|
|
|
|
|
|
mdio_bus: mdio-bus {
|