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@@ -482,7 +482,15 @@
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}
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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-@@ -454,7 +454,6 @@ static void ath9k_hw_init_config(struct
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+@@ -17,6 +17,7 @@
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+ #include <linux/io.h>
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+ #include <linux/slab.h>
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+ #include <linux/module.h>
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++#include <linux/time.h>
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+ #include <asm/unaligned.h>
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+
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+ #include "hw.h"
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+@@ -454,7 +455,6 @@ static void ath9k_hw_init_config(struct
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}
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ah->config.rx_intr_mitigation = true;
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@@ -490,6 +498,67 @@
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/*
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* We need this for PCI devices only (Cardbus, PCI, miniPCI)
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+@@ -1502,8 +1502,9 @@ static bool ath9k_hw_channel_change(stru
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+ int r;
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+
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+ if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
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+- band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
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+- mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
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++ u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
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++ band_switch = !!(flags_diff & CHANNEL_5GHZ);
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++ mode_diff = !!(flags_diff & ~CHANNEL_HT);
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+ }
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+
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+ for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
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+@@ -1815,7 +1816,7 @@ static int ath9k_hw_do_fastcc(struct ath
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+ * If cross-band fcc is not supoprted, bail out if channelFlags differ.
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+ */
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+ if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
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+- chan->channelFlags != ah->curchan->channelFlags)
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++ ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
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+ goto fail;
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+
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+ if (!ath9k_hw_check_alive(ah))
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+@@ -1856,10 +1857,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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+ struct ath9k_hw_cal_data *caldata, bool fastcc)
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+ {
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+ struct ath_common *common = ath9k_hw_common(ah);
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++ struct timespec ts;
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+ u32 saveLedState;
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+ u32 saveDefAntenna;
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+ u32 macStaId1;
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+ u64 tsf = 0;
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++ s64 usec = 0;
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+ int r;
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+ bool start_mci_reset = false;
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+ bool save_fullsleep = ah->chip_fullsleep;
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+@@ -1902,10 +1905,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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+
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+ macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
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+
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+- /* For chips on which RTC reset is done, save TSF before it gets cleared */
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+- if (AR_SREV_9100(ah) ||
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+- (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
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+- tsf = ath9k_hw_gettsf64(ah);
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++ /* Save TSF before chip reset, a cold reset clears it */
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++ tsf = ath9k_hw_gettsf64(ah);
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++ getrawmonotonic(&ts);
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++ usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
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+
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+ saveLedState = REG_READ(ah, AR_CFG_LED) &
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+ (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
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+@@ -1938,8 +1941,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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+ }
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+
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+ /* Restore TSF */
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+- if (tsf)
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+- ath9k_hw_settsf64(ah, tsf);
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++ getrawmonotonic(&ts);
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++ usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
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++ ath9k_hw_settsf64(ah, tsf + usec);
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+
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+ if (AR_SREV_9280_20_OR_LATER(ah))
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+ REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
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--- a/drivers/net/wireless/ath/ath9k/hw.h
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+++ b/drivers/net/wireless/ath/ath9k/hw.h
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@@ -283,7 +283,6 @@ struct ath9k_ops_config {
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@@ -4417,7 +4486,24 @@
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--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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-@@ -701,6 +701,54 @@ static int ar9550_hw_get_modes_txgain_in
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+@@ -641,11 +641,12 @@ static void ar9003_hw_override_ini(struc
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+ else
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+ ah->enabled_cals &= ~TX_IQ_CAL;
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+
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+- if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
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+- ah->enabled_cals |= TX_CL_CAL;
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+- else
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+- ah->enabled_cals &= ~TX_CL_CAL;
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+ }
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++
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++ if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
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++ ah->enabled_cals |= TX_CL_CAL;
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++ else
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++ ah->enabled_cals &= ~TX_CL_CAL;
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+ }
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+
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+ static void ar9003_hw_prog_ini(struct ath_hw *ah,
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+@@ -701,6 +702,54 @@ static int ar9550_hw_get_modes_txgain_in
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return ret;
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}
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@@ -4472,7 +4558,7 @@
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static int ar9003_hw_process_ini(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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-@@ -726,6 +774,8 @@ static int ar9003_hw_process_ini(struct
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+@@ -726,6 +775,8 @@ static int ar9003_hw_process_ini(struct
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modesIndex);
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}
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@@ -4527,3 +4613,141 @@
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skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
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}
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}
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+--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
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++++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
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+@@ -1040,8 +1040,8 @@ static void ar9003_hw_cl_cal_post_proc(s
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+ }
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+ }
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+
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+-static bool ar9003_hw_init_cal(struct ath_hw *ah,
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+- struct ath9k_channel *chan)
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++static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
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++ struct ath9k_channel *chan)
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+ {
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+ struct ath_common *common = ath9k_hw_common(ah);
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+ struct ath9k_hw_cal_data *caldata = ah->caldata;
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+@@ -1228,13 +1228,109 @@ skip_tx_iqcal:
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+ return true;
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+ }
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+
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++static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
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++ struct ath9k_channel *chan)
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++{
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++ struct ath_common *common = ath9k_hw_common(ah);
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++ struct ath9k_hw_cal_data *caldata = ah->caldata;
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++ bool txiqcal_done = false;
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++ bool is_reusable = true, status = true;
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++ bool run_agc_cal = false, sep_iq_cal = false;
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++
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++ /* Use chip chainmask only for calibration */
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++ ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
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++
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++ if (ah->enabled_cals & TX_CL_CAL) {
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++ REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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++ run_agc_cal = true;
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++ }
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++
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++ if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
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++ goto skip_tx_iqcal;
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++
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++ /* Do Tx IQ Calibration */
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++ REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
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++ AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
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++ DELPT);
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++
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++ /*
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++ * For AR9485 or later chips, TxIQ cal runs as part of
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++ * AGC calibration. Specifically, AR9550 in SoC chips.
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++ */
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++ if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
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++ txiqcal_done = true;
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++ run_agc_cal = true;
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++ } else {
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++ sep_iq_cal = true;
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++ run_agc_cal = true;
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++ }
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++
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++ /*
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++ * In the SoC family, this will run for AR9300, AR9331 and AR9340.
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++ */
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++ if (sep_iq_cal) {
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++ txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
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++ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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++ udelay(5);
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++ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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++ }
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++
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++skip_tx_iqcal:
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++ if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
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++ /* Calibrate the AGC */
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++ REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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++ REG_READ(ah, AR_PHY_AGC_CONTROL) |
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++ AR_PHY_AGC_CONTROL_CAL);
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++
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++ /* Poll for offset calibration complete */
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++ status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
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++ AR_PHY_AGC_CONTROL_CAL,
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++ 0, AH_WAIT_TIMEOUT);
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++ }
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++
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++ if (!status) {
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++ ath_dbg(common, CALIBRATE,
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++ "offset calibration failed to complete in %d ms; noisy environment?\n",
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++ AH_WAIT_TIMEOUT / 1000);
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++ return false;
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++ }
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++
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++ if (txiqcal_done)
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++ ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
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++
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++ /* Revert chainmask to runtime parameters */
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++ ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
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++
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++ /* Initialize list pointers */
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++ ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
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++
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++ INIT_CAL(&ah->iq_caldata);
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++ INSERT_CAL(ah, &ah->iq_caldata);
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++ ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
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++
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++ /* Initialize current pointer to first element in list */
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++ ah->cal_list_curr = ah->cal_list;
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++
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++ if (ah->cal_list_curr)
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++ ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
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++
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++ if (caldata)
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++ caldata->CalValid = 0;
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++
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++ return true;
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++}
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++
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+ void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
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+ {
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+ struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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+ struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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+
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++ if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
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++ priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
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++ else
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++ priv_ops->init_cal = ar9003_hw_init_cal_soc;
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++
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+ priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
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+- priv_ops->init_cal = ar9003_hw_init_cal;
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+ priv_ops->setup_calibration = ar9003_hw_setup_calibration;
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+
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+ ops->calibrate = ar9003_hw_calibrate;
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+--- a/drivers/net/wireless/ath/ath9k/common.c
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++++ b/drivers/net/wireless/ath/ath9k/common.c
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+@@ -98,10 +98,8 @@ struct ath9k_channel *ath9k_cmn_get_chan
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+ {
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+ struct ieee80211_channel *curchan = chandef->chan;
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+ struct ath9k_channel *channel;
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+- u8 chan_idx;
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+
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+- chan_idx = curchan->hw_value;
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+- channel = &ah->channels[chan_idx];
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++ channel = &ah->channels[curchan->hw_value];
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+ ath9k_cmn_update_ichannel(channel, chandef);
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+
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+ return channel;
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Felix Fietkau