mediatek: mt7988: fix peripheral SPI busses

The clocks for SPI busses were named wrongly which resulted in the
spi-mt65xx driver not requesting them. This has apparently been
worked around by marking the clocks required for SPI0 which is used
for SPI-NOR and SPI-NAND flash chips as critical.
Fix the device tree for all 3 generic SPI host controllers and no
longer mark clocks as critical.

Signed-off-by: Daniel Golle <[email protected]>
(cherry picked from commit 2b173ab730897f53539cab39e87e2b4638cb482a)

target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi

@@ -806,7 +806,7 @@
 				 <&infracfg CLK_INFRA_104M_SPI0>,
 				 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
 			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
+				      "hclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
@@ -817,11 +817,11 @@
 			reg = <0 0x11008000 0 0x100>;
 			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&topckgen CLK_TOP_MPLL_D2>,
-				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
 				 <&infracfg CLK_INFRA_104M_SPI1>,
 				 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
 			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
+				      "hclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			pinctrl-names = "default";
@@ -838,7 +838,7 @@
 				 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
 				 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
 			clock-names = "parent-clk", "sel-clk", "spi-clk",
-				      "spi-hclk";
+				      "hclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";

target/linux/mediatek/patches-6.6/255-clk-mediatek-mt7988-infracfg-SPI0-clocks-are-not-critical.patch

@@ -0,0 +1,65 @@
+From patchwork Fri Nov  1 03:19:39 2024
+Content-Type: text/plain; charset="utf-8"
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+X-Patchwork-Submitter: Daniel Golle <[email protected]>
+X-Patchwork-Id: 13858671
+Return-Path: 
+ <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
+Date: Fri, 1 Nov 2024 03:19:39 +0000
+From: Daniel Golle <[email protected]>
+To: [email protected], [email protected],
+ [email protected], [email protected], Uwe
+	=?iso-8859-1?q?Kleine-K=F6nig?= <[email protected]>,
+ Sam Shih <[email protected]>, Frank Wunderlich <[email protected]>,
+ Daniel Golle <[email protected]>,
+ AngeloGioacchino Del Regno <[email protected]>,
+ Matthias Brugger <[email protected]>, Stephen Boyd <[email protected]>,
+ Michael Turquette <[email protected]>
+Subject: [PATCH] clk: mediatek: mt7988-infracfg: SPI0 clocks are not critical
+Message-ID: <[email protected]>
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+
+SPI0 clocks have wrongly been marked as critical while, probably due
+to the SPI driver not requesting them. This can (and should) be addressed
+in device tree instead.
+Remove CLK_IS_CRITICAL flag from clocks related to SPI0.
+
+Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC")
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[
+ 	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
+ 	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
+ 			  CLK_IS_CRITICAL),
+-	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
+-			  CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12),
+ 	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
+ 	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
+-	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
+-			  CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15),
+ 	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
+ 	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
+ 	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),