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@@ -27,6 +27,7 @@
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#define MT7620A_CDMA_CSG_CFG 0x400
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#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
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+#define MT7621_DMA_VID 0xa8
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#define MT7620A_DMA_2B_OFFSET BIT(31)
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#define MT7620A_RESET_FE BIT(21)
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#define MT7621_RESET_FE BIT(6)
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@@ -76,6 +77,23 @@ static const u32 mt7620_reg_table[FE_REG_COUNT] = {
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[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
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};
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+static const u32 mt7621_reg_table[FE_REG_COUNT] = {
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+ [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
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+ [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
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+ [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
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+ [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
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+ [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
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+ [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
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+ [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
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+ [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
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+ [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
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+ [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
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+ [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
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+ [FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
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+ [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
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+ [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
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+};
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+
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static void mt7620_fe_reset(void)
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{
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u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
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@@ -213,7 +231,7 @@ static struct fe_soc_data mt7621_data = {
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.rx_dma = mt7620_rx_dma,
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.switch_init = mt7620_gsw_probe,
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.switch_config = mt7621_gsw_config,
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- .reg_table = mt7620_reg_table,
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+ .reg_table = mt7621_reg_table,
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.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
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.rx_dly_int = RT5350_RX_DLY_INT,
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.tx_dly_int = RT5350_TX_DLY_INT,
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