|
|
@@ -1,6 +1,6 @@
|
|
|
--- a/arch/mips/include/asm/r4kcache.h
|
|
|
+++ b/arch/mips/include/asm/r4kcache.h
|
|
|
-@@ -27,6 +27,38 @@
|
|
|
+@@ -31,6 +31,38 @@ extern int mips_sc_init(void);
|
|
|
extern void (*r4k_blast_dcache)(void);
|
|
|
extern void (*r4k_blast_icache)(void);
|
|
|
|
|
|
@@ -39,7 +39,7 @@
|
|
|
/*
|
|
|
* This macro return a properly sign-extended address suitable as base address
|
|
|
* for indexed cache operations. Two issues here:
|
|
|
-@@ -60,6 +92,7 @@ static inline void flush_icache_line_ind
|
|
|
+@@ -64,6 +96,7 @@ static inline void flush_icache_line_ind
|
|
|
|
|
|
static inline void flush_dcache_line_indexed(unsigned long addr)
|
|
|
{
|
|
|
@@ -47,7 +47,7 @@
|
|
|
cache_op(Index_Writeback_Inv_D, addr);
|
|
|
}
|
|
|
|
|
|
-@@ -83,11 +116,13 @@ static inline void flush_icache_line(uns
|
|
|
+@@ -87,11 +120,13 @@ static inline void flush_icache_line(uns
|
|
|
|
|
|
static inline void flush_dcache_line(unsigned long addr)
|
|
|
{
|
|
|
@@ -61,7 +61,7 @@
|
|
|
cache_op(Hit_Invalidate_D, addr);
|
|
|
}
|
|
|
|
|
|
-@@ -160,6 +195,7 @@ static inline int protected_flush_icache
|
|
|
+@@ -164,6 +199,7 @@ static inline int protected_flush_icache
|
|
|
return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
|
|
|
|
|
|
default:
|
|
|
@@ -69,7 +69,7 @@
|
|
|
return protected_cache_op(Hit_Invalidate_I, addr);
|
|
|
}
|
|
|
}
|
|
|
-@@ -172,6 +208,7 @@ static inline int protected_flush_icache
|
|
|
+@@ -176,6 +212,7 @@ static inline int protected_flush_icache
|
|
|
*/
|
|
|
static inline int protected_writeback_dcache_line(unsigned long addr)
|
|
|
{
|
|
|
@@ -77,7 +77,7 @@
|
|
|
return protected_cache_op(Hit_Writeback_Inv_D, addr);
|
|
|
}
|
|
|
|
|
|
-@@ -193,8 +230,51 @@ static inline void invalidate_tcache_pag
|
|
|
+@@ -197,8 +234,51 @@ static inline void invalidate_tcache_pag
|
|
|
unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \
|
|
|
} while (0)
|
|
|
|
|
|
@@ -130,7 +130,7 @@
|
|
|
static inline void extra##blast_##pfx##cache##lsize(void) \
|
|
|
{ \
|
|
|
unsigned long start = INDEX_BASE; \
|
|
|
-@@ -204,6 +284,7 @@ static inline void extra##blast_##pfx##c
|
|
|
+@@ -208,6 +288,7 @@ static inline void extra##blast_##pfx##c
|
|
|
current_cpu_data.desc.waybit; \
|
|
|
unsigned long ws, addr; \
|
|
|
\
|
|
|
@@ -138,7 +138,7 @@
|
|
|
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
|
|
for (addr = start; addr < end; addr += lsize * 32) \
|
|
|
cache_unroll(32, kernel_cache, indexop, \
|
|
|
-@@ -215,6 +296,7 @@ static inline void extra##blast_##pfx##c
|
|
|
+@@ -219,6 +300,7 @@ static inline void extra##blast_##pfx##c
|
|
|
unsigned long start = page; \
|
|
|
unsigned long end = page + PAGE_SIZE; \
|
|
|
\
|
|
|
@@ -146,7 +146,7 @@
|
|
|
do { \
|
|
|
cache_unroll(32, kernel_cache, hitop, start, lsize); \
|
|
|
start += lsize * 32; \
|
|
|
-@@ -231,32 +313,33 @@ static inline void extra##blast_##pfx##c
|
|
|
+@@ -235,32 +317,33 @@ static inline void extra##blast_##pfx##c
|
|
|
current_cpu_data.desc.waybit; \
|
|
|
unsigned long ws, addr; \
|
|
|
\
|
|
|
@@ -200,7 +200,7 @@
|
|
|
|
|
|
#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
|
|
|
static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
|
|
|
-@@ -281,65 +364,36 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
|
|
|
+@@ -285,65 +368,36 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
|
|
|
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
|
|
|
|
|
|
/* build blast_xxx_range, protected_blast_xxx_range */
|
|
|
@@ -285,7 +285,7 @@
|
|
|
#define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
|
|
|
--- a/arch/mips/include/asm/stackframe.h
|
|
|
+++ b/arch/mips/include/asm/stackframe.h
|
|
|
-@@ -429,6 +429,10 @@
|
|
|
+@@ -432,6 +432,10 @@
|
|
|
#else
|
|
|
.set push
|
|
|
.set arch=r4000
|
|
|
@@ -380,7 +380,7 @@
|
|
|
if (dc_lsize == 0)
|
|
|
r4k_blast_dcache = (void *)cache_noop;
|
|
|
else if (dc_lsize == 16)
|
|
|
-@@ -1669,6 +1681,17 @@ static void coherency_setup(void)
|
|
|
+@@ -1665,6 +1677,17 @@ static void coherency_setup(void)
|
|
|
* silly idea of putting something else there ...
|
|
|
*/
|
|
|
switch (current_cpu_type()) {
|
|
|
@@ -398,7 +398,7 @@
|
|
|
case CPU_R4000PC:
|
|
|
case CPU_R4000SC:
|
|
|
case CPU_R4000MC:
|
|
|
-@@ -1715,6 +1738,15 @@ void r4k_cache_init(void)
|
|
|
+@@ -1711,6 +1734,15 @@ void r4k_cache_init(void)
|
|
|
extern void build_copy_page(void);
|
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
|
|
|
|
@@ -414,7 +414,7 @@
|
|
|
probe_pcache();
|
|
|
probe_vcache();
|
|
|
setup_scache();
|
|
|
-@@ -1777,7 +1809,15 @@ void r4k_cache_init(void)
|
|
|
+@@ -1773,7 +1805,15 @@ void r4k_cache_init(void)
|
|
|
*/
|
|
|
local_r4k___flush_cache_all(NULL);
|
|
|
|
|
|
@@ -432,7 +432,7 @@
|
|
|
/*
|
|
|
--- a/arch/mips/mm/tlbex.c
|
|
|
+++ b/arch/mips/mm/tlbex.c
|
|
|
-@@ -958,6 +958,9 @@ void build_get_pgde32(u32 **p, unsigned
|
|
|
+@@ -939,6 +939,9 @@ void build_get_pgde32(u32 **p, unsigned
|
|
|
uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
|
|
|
uasm_i_addu(p, ptr, tmp, ptr);
|
|
|
#else
|
|
|
@@ -442,18 +442,18 @@
|
|
|
UASM_i_LA_mostly(p, ptr, pgdc);
|
|
|
#endif
|
|
|
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
|
|
|
-@@ -1304,6 +1307,9 @@ static void build_r4000_tlb_refill_handl
|
|
|
+@@ -1285,6 +1288,9 @@ static void build_r4000_tlb_refill_handl
|
|
|
#ifdef CONFIG_64BIT
|
|
|
- build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
|
|
|
+ build_get_pmde64(&p, &l, &r, GPR_K0, GPR_K1); /* get pmd in GPR_K1 */
|
|
|
#else
|
|
|
-+# ifdef CONFIG_BCM47XX
|
|
|
++#ifdef CONFIG_BCM47XX
|
|
|
+ uasm_i_nop(&p);
|
|
|
-+# endif
|
|
|
- build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
|
|
|
++#endif
|
|
|
+ build_get_pgde32(&p, GPR_K0, GPR_K1); /* get pgd in GPR_K1 */
|
|
|
#endif
|
|
|
|
|
|
-@@ -1315,6 +1321,9 @@ static void build_r4000_tlb_refill_handl
|
|
|
- build_update_entries(&p, K0, K1);
|
|
|
+@@ -1296,6 +1302,9 @@ static void build_r4000_tlb_refill_handl
|
|
|
+ build_update_entries(&p, GPR_K0, GPR_K1);
|
|
|
build_tlb_write_entry(&p, &l, &r, tlb_random);
|
|
|
uasm_l_leave(&l, p);
|
|
|
+#ifdef CONFIG_BCM47XX
|
|
|
@@ -462,7 +462,7 @@
|
|
|
uasm_i_eret(&p); /* return from trap */
|
|
|
}
|
|
|
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
|
|
|
-@@ -2016,6 +2025,9 @@ build_r4000_tlbchange_handler_head(u32 *
|
|
|
+@@ -1998,6 +2007,9 @@ build_r4000_tlbchange_handler_head(u32 *
|
|
|
#ifdef CONFIG_64BIT
|
|
|
build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
|
|
|
#else
|
|
|
@@ -472,7 +472,7 @@
|
|
|
build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
|
|
|
#endif
|
|
|
|
|
|
-@@ -2062,6 +2074,9 @@ build_r4000_tlbchange_handler_tail(u32 *
|
|
|
+@@ -2044,6 +2056,9 @@ build_r4000_tlbchange_handler_tail(u32 *
|
|
|
build_tlb_write_entry(p, l, r, tlb_indexed);
|
|
|
uasm_l_leave(l, *p);
|
|
|
build_restore_work_registers(p);
|