mediatek: drop v4.14 support

Signed-off-by: John Crispin <[email protected]>

target/linux/mediatek/files-4.14/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

@@ -1,574 +0,0 @@
-/*
- * Copyright (c) 2018 MediaTek Inc.
- * Author: Ryder Lee <[email protected]>
- *
- * SPDX-License-Identifier: (GPL-2.0 OR MIT)
- */
-
-/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "mt7622.dtsi"
-#include "mt6380.dtsi"
-
-/ {
-	model = "Bananapi BPI-R64";
-	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-	};
-
-	cpus {
-		cpu@0 {
-			proc-supply = <&mt6380_vcpu_reg>;
-			sram-supply = <&mt6380_vm_reg>;
-		};
-
-		cpu@1 {
-			proc-supply = <&mt6380_vcpu_reg>;
-			sram-supply = <&mt6380_vm_reg>;
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		factory {
-			label = "factory";
-			linux,code = <BTN_0>;
-			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
-		};
-
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		green {
-			label = "bpi-r64:pio:green";
-			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		red {
-			label = "bpi-r64:pio:red";
-			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-	};
-
-	gsw: gsw@0 {
-		compatible = "mediatek,mt753x";
-		mediatek,ethsys = <&ethsys>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&bch {
-	status = "disabled";
-};
-
-&btif {
-	status = "okay";
-};
-
-&cir {
-	pinctrl-names = "default";
-	pinctrl-0 = <&irrx_pins>;
-	status = "okay";
-};
-
-&eth {
-	pinctrl-names = "default";
-	pinctrl-0 = <&eth_pins>;
-	status = "okay";
-
-	gmac1: mac@1 {
-		compatible = "mediatek,eth-mac";
-		reg = <1>;
-		phy-handle = <&phy5>;
-	};
-
-	mdio: mdio-bus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		phy5: ethernet-phy@5 {
-			reg = <5>;
-			phy-mode = "sgmii";
-		};
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-	status = "okay";
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins>;
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&emmc_pins_default>;
-	pinctrl-1 = <&emmc_pins_uhs>;
-	status = "okay";
-	bus-width = <8>;
-	max-frequency = <50000000>;
-	cap-mmc-highspeed;
-	mmc-hs200-1_8v;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
-	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-	non-removable;
-};
-
-&mmc1 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&sd0_pins_default>;
-	pinctrl-1 = <&sd0_pins_uhs>;
-	status = "okay";
-	bus-width = <4>;
-	max-frequency = <50000000>;
-	cap-sd-highspeed;
-	r_smpl = <1>;
-	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_3p3v>;
-	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
-	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-};
-
-&nandc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&parallel_nand_pins>;
-	status = "disabled";
-};
-
-&nor_flash {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_nor_pins>;
-	status = "disabled";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-	};
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-	status = "okay";
-
-	pcie@0,0 {
-		status = "okay";
-	};
-
-	pcie@1,0 {
-		status = "okay";
-	};
-};
-
-&pio {
-	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
-	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
-	 */
-	asm_sel {
-		gpio-hog;
-		gpios = <90 GPIO_ACTIVE_HIGH>;
-		output-high;
-	};
-
-	/* eMMC is shared pin with parallel NAND */
-	emmc_pins_default: emmc-pins-default {
-		mux {
-			function = "emmc", "emmc_rst";
-			groups = "emmc";
-		};
-
-		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
-		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
-		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
-		 */
-		conf-cmd-dat {
-			pins = "NDL0", "NDL1", "NDL2",
-			       "NDL3", "NDL4", "NDL5",
-			       "NDL6", "NDL7", "NRB";
-			input-enable;
-			bias-pull-up;
-		};
-
-		conf-clk {
-			pins = "NCLE";
-			bias-pull-down;
-		};
-	};
-
-	emmc_pins_uhs: emmc-pins-uhs {
-		mux {
-			function = "emmc";
-			groups = "emmc";
-		};
-
-		conf-cmd-dat {
-			pins = "NDL0", "NDL1", "NDL2",
-			       "NDL3", "NDL4", "NDL5",
-			       "NDL6", "NDL7", "NRB";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up;
-		};
-
-		conf-clk {
-			pins = "NCLE";
-			drive-strength = <4>;
-			bias-pull-down;
-		};
-	};
-
-	eth_pins: eth-pins {
-		mux {
-			function = "eth";
-			groups = "mdc_mdio", "rgmii_via_gmac2";
-		};
-	};
-
-	i2c1_pins: i2c1-pins {
-		mux {
-			function = "i2c";
-			groups =  "i2c1_0";
-		};
-	};
-
-	i2c2_pins: i2c2-pins {
-		mux {
-			function = "i2c";
-			groups =  "i2c2_0";
-		};
-	};
-
-	i2s1_pins: i2s1-pins {
-		mux {
-			function = "i2s";
-			groups =  "i2s_out_mclk_bclk_ws",
-				  "i2s1_in_data",
-				  "i2s1_out_data";
-		};
-
-		conf {
-			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
-			       "I2S_WS", "I2S_MCLK";
-			drive-strength = <12>;
-			bias-pull-down;
-		};
-	};
-
-	irrx_pins: irrx-pins {
-		mux {
-			function = "ir";
-			groups =  "ir_1_rx";
-		};
-	};
-
-	irtx_pins: irtx-pins {
-		mux {
-			function = "ir";
-			groups =  "ir_1_tx";
-		};
-	};
-
-	/* Parallel nand is shared pin with eMMC */
-	parallel_nand_pins: parallel-nand-pins {
-		mux {
-			function = "flash";
-			groups = "par_nand";
-		};
-	};
-
-	pcie0_pins: pcie0-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie0_pad_perst",
-				 "pcie0_1_waken",
-				 "pcie0_1_clkreq";
-		};
-	};
-
-	pcie1_pins: pcie1-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie1_pad_perst",
-				 "pcie1_0_waken",
-				 "pcie1_0_clkreq";
-		};
-	};
-
-	pmic_bus_pins: pmic-bus-pins {
-		mux {
-			function = "pmic";
-			groups = "pmic_bus";
-		};
-	};
-
-	pwm7_pins: pwm1-2-pins {
-		mux {
-			function = "pwm";
-			groups = "pwm_ch7_2";
-		};
-	};
-
-	wled_pins: wled-pins {
-		mux {
-			function = "led";
-			groups = "wled";
-		};
-	};
-
-	sd0_pins_default: sd0-pins-default {
-		mux {
-			function = "sd";
-			groups = "sd_0";
-		};
-
-		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
-		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
-		 *  DAT2, DAT3, CMD, CLK for SD respectively.
-		 */
-		conf-cmd-data {
-			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
-			       "I2S2_IN","I2S4_OUT";
-			input-enable;
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-		conf-clk {
-			pins = "I2S3_OUT";
-			drive-strength = <12>;
-			bias-pull-down;
-		};
-		conf-cd {
-			pins = "TXD3";
-			bias-pull-up;
-		};
-	};
-
-	sd0_pins_uhs: sd0-pins-uhs {
-		mux {
-			function = "sd";
-			groups = "sd_0";
-		};
-
-		conf-cmd-data {
-			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
-			       "I2S2_IN","I2S4_OUT";
-			input-enable;
-			bias-pull-up;
-		};
-
-		conf-clk {
-			pins = "I2S3_OUT";
-			bias-pull-down;
-		};
-	};
-
-	/* Serial NAND is shared pin with SPI-NOR */
-	serial_nand_pins: serial-nand-pins {
-		mux {
-			function = "flash";
-			groups = "snfi";
-		};
-	};
-
-	spic0_pins: spic0-pins {
-		mux {
-			function = "spi";
-			groups = "spic0_0";
-		};
-	};
-
-	spic1_pins: spic1-pins {
-		mux {
-			function = "spi";
-			groups = "spic1_0";
-		};
-	};
-
-	/* SPI-NOR is shared pin with serial NAND */
-	spi_nor_pins: spi-nor-pins {
-		mux {
-			function = "flash";
-			groups = "spi_nor";
-		};
-	};
-
-	/* serial NAND is shared pin with SPI-NOR */
-	serial_nand_pins: serial-nand-pins {
-		mux {
-			function = "flash";
-			groups = "snfi";
-		};
-	};
-
-	uart0_pins: uart0-pins {
-		mux {
-			function = "uart";
-			groups = "uart0_0_tx_rx" ;
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2_1_tx_rx" ;
-		};
-	};
-
-	watchdog_pins: watchdog-pins {
-		mux {
-			function = "watchdog";
-			groups = "watchdog";
-		};
-	};
-};
-
-&pwm {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pwm7_pins>;
-	status = "okay";
-};
-
-&pwrap {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pmic_bus_pins>;
-
-	status = "okay";
-};
-
-&sata {
-	status = "disable";
-};
-
-&sata_phy {
-	status = "disable";
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic0_pins>;
-	status = "okay";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic1_pins>;
-	status = "okay";
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&u3phy {
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&watchdog {
-	pinctrl-names = "default";
-	pinctrl-0 = <&watchdog_pins>;
-	status = "okay";
-};
-
-&gsw {
-	mediatek,mdio = <&mdio>;
-	mediatek,portmap = "llllw";
-	mediatek,mdio_master_pinmux = <0>;
-	reset-gpios = <&pio 54 0>;
-	interrupt-parent = <&pio>;
-	interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
-	status = "okay";
-
-	port5: port@5 {
-		compatible = "mediatek,mt753x-port";
-		reg = <5>;
-		phy-mode = "rgmii";
-		fixed-link {
-			speed = <1000>;
-			full-duplex;
-		};
-	};
-
-	port6: port@6 {
-		compatible = "mediatek,mt753x-port";
-		reg = <6>;
-		phy-mode = "sgmii";
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-		};
-	};
-};
-
-

target/linux/mediatek/files-4.14/arch/arm64/boot/dts/mediatek/mt7622-lynx-rfb1.dts

@@ -1,549 +0,0 @@
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: Ming Huang <[email protected]>
- *	   Sean Wang <[email protected]>
- *
- * SPDX-License-Identifier: (GPL-2.0 OR MIT)
- */
-
-/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "mt7622.dtsi"
-#include "mt6380.dtsi"
-
-/ {
-	model = "MediaTek MT7622 RFB1 board";
-	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-	};
-
-	cpus {
-		cpu@0 {
-			proc-supply = <&mt6380_vcpu_reg>;
-			sram-supply = <&mt6380_vm_reg>;
-		};
-
-		cpu@1 {
-			proc-supply = <&mt6380_vcpu_reg>;
-			sram-supply = <&mt6380_vm_reg>;
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		poll-interval = <100>;
-
-		factory {
-			label = "factory";
-			linux,code = <BTN_0>;
-			gpios = <&pio 0 0>;
-		};
-
-		wps {
-			label = "wps";
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&pio 102 0>;
-		};
-	};
-
-	gsw: gsw@0 {
-		compatible = "mediatek,mt753x";
-		mediatek,ethsys = <&ethsys>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	memory {
-		reg = <0 0x40000000 0 0x3F000000>;
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_5v: regulator-5v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-5V";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&pcie {
-	pinctrl-names = "default", "pcie1_pins";
-	pinctrl-0 = <&pcie0_pins>;
-	pinctrl-1 = <&pcie1_pins>;
-	status = "okay";
-
-	pcie@0,0 {
-		status = "okay";
-	};
-
-	pcie@1,0 {
-		status = "okay";
-	};
-
-};
-
-&pio {
-	/* eMMC is shared pin with parallel NAND */
-	emmc_pins_default: emmc-pins-default {
-		mux {
-			function = "emmc", "emmc_rst";
-			groups = "emmc";
-		};
-
-		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
-		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
-		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
-		 */
-		conf-cmd-dat {
-			pins = "NDL0", "NDL1", "NDL2",
-			       "NDL3", "NDL4", "NDL5",
-			       "NDL6", "NDL7", "NRB";
-			input-enable;
-			bias-pull-up;
-		};
-
-		conf-clk {
-			pins = "NCLE";
-			bias-pull-down;
-		};
-	};
-
-	emmc_pins_uhs: emmc-pins-uhs {
-		mux {
-			function = "emmc";
-			groups = "emmc";
-		};
-
-		conf-cmd-dat {
-			pins = "NDL0", "NDL1", "NDL2",
-			       "NDL3", "NDL4", "NDL5",
-			       "NDL6", "NDL7", "NRB";
-			input-enable;
-			drive-strength = <4>;
-			bias-pull-up;
-		};
-
-		conf-clk {
-			pins = "NCLE";
-			drive-strength = <4>;
-			bias-pull-down;
-		};
-	};
-
-	eth_pins: eth-pins {
-		mux {
-			function = "eth";
-			groups = "mdc_mdio", "rgmii_via_gmac2";
-		};
-	};
-
-	i2c1_pins: i2c1-pins {
-		mux {
-			function = "i2c";
-			groups =  "i2c1_0";
-		};
-	};
-
-	i2c2_pins: i2c2-pins {
-		mux {
-			function = "i2c";
-			groups =  "i2c2_0";
-		};
-	};
-
-	i2s1_pins: i2s1-pins {
-		mux {
-			function = "i2s";
-			groups =  "i2s_out_mclk_bclk_ws",
-				  "i2s1_in_data",
-				  "i2s1_out_data";
-		};
-
-		conf {
-			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
-			       "I2S_WS", "I2S_MCLK";
-			drive-strength = <12>;
-			bias-pull-down;
-		};
-	};
-
-	irrx_pins: irrx-pins {
-		mux {
-			function = "ir";
-			groups =  "ir_1_rx";
-		};
-	};
-
-	irtx_pins: irtx-pins {
-		mux {
-			function = "ir";
-			groups =  "ir_1_tx";
-		};
-	};
-
-	/* Parallel nand is shared pin with eMMC */
-	parallel_nand_pins: parallel-nand-pins {
-		mux {
-			function = "flash";
-			groups = "par_nand";
-		};
-	};
-
-	pcie0_pins: pcie0-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie0_pad_perst",
-				 "pcie0_1_waken",
-				 "pcie0_1_clkreq";
-		};
-	};
-
-	pcie1_pins: pcie1-pins {
-		mux {
-			function = "pcie";
-			groups = "pcie1_pad_perst",
-				 "pcie1_0_waken",
-				 "pcie1_0_clkreq";
-		};
-	};
-
-	pmic_bus_pins: pmic-bus-pins {
-		mux {
-			function = "pmic";
-			groups = "pmic_bus";
-		};
-	};
-
-	pwm7_pins: pwm1-2-pins {
-		mux {
-			function = "pwm";
-			groups = "pwm_ch7_2";
-		};
-	};
-
-	wled_pins: wled-pins {
-		mux {
-			function = "led";
-			groups = "wled";
-		};
-	};
-
-	sd0_pins_default: sd0-pins-default {
-		mux {
-			function = "sd";
-			groups = "sd_0";
-		};
-
-		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
-		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
-		 *  DAT2, DAT3, CMD, CLK for SD respectively.
-		 */
-		conf-cmd-data {
-			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
-			       "I2S2_IN","I2S4_OUT";
-			input-enable;
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-		conf-clk {
-			pins = "I2S3_OUT";
-			drive-strength = <12>;
-			bias-pull-down;
-		};
-		conf-cd {
-			pins = "TXD3";
-			bias-pull-up;
-		};
-	};
-
-	sd0_pins_uhs: sd0-pins-uhs {
-		mux {
-			function = "sd";
-			groups = "sd_0";
-		};
-
-		conf-cmd-data {
-			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
-			       "I2S2_IN","I2S4_OUT";
-			input-enable;
-			bias-pull-up;
-		};
-
-		conf-clk {
-			pins = "I2S3_OUT";
-			bias-pull-down;
-		};
-	};
-
-	/* Serial NAND is shared pin with SPI-NOR */
-	serial_nand_pins: serial-nand-pins {
-		mux {
-			function = "flash";
-			groups = "snfi";
-		};
-	};
-
-	spic0_pins: spic0-pins {
-		mux {
-			function = "spi";
-			groups = "spic0_0";
-		};
-	};
-
-	spic1_pins: spic1-pins {
-		mux {
-			function = "spi";
-			groups = "spic1_0";
-		};
-	};
-
-	/* SPI-NOR is shared pin with serial NAND */
-	spi_nor_pins: spi-nor-pins {
-		mux {
-			function = "flash";
-			groups = "spi_nor";
-		};
-	};
-
-	/* serial NAND is shared pin with SPI-NOR */
-	serial_nand_pins: serial-nand-pins {
-		mux {
-			function = "flash";
-			groups = "snfi";
-		};
-	};
-
-	uart0_pins: uart0-pins {
-		mux {
-			function = "uart";
-			groups = "uart0_0_tx_rx" ;
-		};
-	};
-
-	uart2_pins: uart2-pins {
-		mux {
-			function = "uart";
-			groups = "uart2_1_tx_rx" ;
-		};
-	};
-
-	watchdog_pins: watchdog-pins {
-		mux {
-			function = "watchdog";
-			groups = "watchdog";
-		};
-	};
-};
-
-&bch {
-	status = "okay";
-};
-
-&btif {
-	status = "okay";
-};
-
-&cir {
-	pinctrl-names = "default";
-	pinctrl-0 = <&irrx_pins>;
-	status = "okay";
-};
-
-&eth {
-	status = "okay";
-	gmac0: mac@0 {
-                compatible = "mediatek,eth-mac";
-                reg = <0>;
-                phy-mode = "sgmii";
-                fixed-link {
-                        speed = <1000>;
-                        full-duplex;
-                        pause;
-                };
-        };
-        gmac1: mac@1 {
-                compatible = "mediatek,eth-mac";
-                reg = <1>;
-                phy-mode = "rgmii";
-                fixed-link {
-                        speed = <1000>;
-                        full-duplex;
-                        pause;
-                };
-        };
-        mdio: mdio-bus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
-};
-
-&gsw {
-	mediatek,mdio = <&mdio>;
-	mediatek,portmap = "llllw";
-	mediatek,mdio_master_pinmux = <0>;
-	reset-gpios = <&pio 54 0>;
-	interrupt-parent = <&pio>;
-	interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
-	status = "okay";
-
-	port5: port@5 {
-		compatible = "mediatek,mt753x-port";
-		reg = <5>;
-		phy-mode = "rgmii";
-		fixed-link {
-			speed = <1000>;
-			full-duplex;
-		};
-	};
-
-	port6: port@6 {
-		compatible = "mediatek,mt753x-port";
-		reg = <6>;
-		phy-mode = "sgmii";
-		fixed-link {
-			speed = <2500>;
-			full-duplex;
-		};
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-	status = "okay";
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins>;
-	status = "okay";
-};
-
-&mmc0 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&emmc_pins_default>;
-	pinctrl-1 = <&emmc_pins_uhs>;
-	status = "okay";
-	bus-width = <8>;
-	max-frequency = <50000000>;
-	cap-mmc-highspeed;
-	mmc-hs200-1_8v;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
-	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-	non-removable;
-};
-
-&mmc1 {
-	pinctrl-names = "default", "state_uhs";
-	pinctrl-0 = <&sd0_pins_default>;
-	pinctrl-1 = <&sd0_pins_uhs>;
-	status = "okay";
-	bus-width = <4>;
-	max-frequency = <50000000>;
-	cap-sd-highspeed;
-	r_smpl = <1>;
-	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_3p3v>;
-	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
-	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-};
-
-&nandc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&parallel_nand_pins>;
-	status = "disabled";
-};
-
-&nor_flash {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi_nor_pins>;
-	status = "disabled";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-	};
-};
-
-&pwm {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pwm7_pins>;
-	status = "okay";
-};
-
-&pwrap {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pmic_bus_pins>;
-
-	status = "okay";
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic0_pins>;
-	status = "okay";
-};
-
-&spi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spic1_pins>;
-	status = "okay";
-};
-
-&ssusb {
-	vusb33-supply = <&reg_3p3v>;
-	vbus-supply = <&reg_5v>;
-	status = "okay";
-};
-
-&u3phy {
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&watchdog {
-	pinctrl-names = "default";
-	pinctrl-0 = <&watchdog_pins>;
-	status = "okay";
-};

target/linux/mediatek/mt7622/config-4.14

@@ -1,446 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_ACPI is not set
-CONFIG_AHCI_MTK=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
-# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
-CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_FRAME_POINTERS=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_ARM64=y
-# CONFIG_ARM64_16K_PAGES is not set
-CONFIG_ARM64_4K_PAGES=y
-# CONFIG_ARM64_64K_PAGES is not set
-CONFIG_ARM64_CONT_SHIFT=4
-# CONFIG_ARM64_CRYPTO is not set
-CONFIG_ARM64_HW_AFDBM=y
-# CONFIG_ARM64_LSE_ATOMICS is not set
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-# CONFIG_ARM64_PMEM is not set
-# CONFIG_ARM64_PTDUMP_CORE is not set
-# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
-# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
-CONFIG_ARM64_SSBD=y
-CONFIG_ARM64_UAO=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-# CONFIG_ARM64_VA_BITS_48 is not set
-CONFIG_ARM64_VHE=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_SCSI_REQUEST=y
-# CONFIG_BOUNCE is not set
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_BT=y
-CONFIG_BT_DEBUGFS=y
-CONFIG_BT_HCIUART=y
-# CONFIG_BT_HCIUART_BCM is not set
-# CONFIG_BT_HCIUART_INTEL is not set
-# CONFIG_BT_HCIUART_NOKIA is not set
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIVHCI=y
-CONFIG_BUILD_BIN2C=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLOCK_THERMAL=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2712=y
-# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
-# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
-# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-CONFIG_COMMON_CLK_MT7622=y
-CONFIG_COMMON_CLK_MT7622_AUDSYS=y
-CONFIG_COMMON_CLK_MT7622_ETHSYS=y
-CONFIG_COMMON_CLK_MT7622_HIFSYS=y
-# CONFIG_COMMON_CLK_MT8173 is not set
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-# CONFIG_CPUFREQ_DT is not set
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_KPP=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEFAULT_IOSCHED="noop"
-CONFIG_DEFAULT_NOOP=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_EDAC_SUPPORT=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB=y
-# CONFIG_GRO_CELLS is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KASAN=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARCH_VMAP_STACK=y
-CONFIG_HAVE_ARM_SMCCC=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_BUGVERBOSE=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_GUP=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_PATA_PLATFORM=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_RCU_TABLE_FREE=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-# CONFIG_HUGETLBFS is not set
-# CONFIG_HW_RANDOM_MTK is not set
-# CONFIG_I2C_MT65XX is not set
-CONFIG_ICPLUS_PHY=y
-CONFIG_IIO=y
-# CONFIG_IIO_BUFFER is not set
-# CONFIG_IIO_TRIGGER is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IOMMU_HELPER=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JUMP_LABEL=y
-CONFIG_LEDS_MT6323=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MEDIATEK_MT6577_AUXADC=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_CORE=y
-CONFIG_MFD_MT6397=y
-CONFIG_MFD_SYSCON=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_MMC=y
-CONFIG_MMC_MTK=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_MT81xx_NOR=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_MTK=y
-# CONFIG_MTD_OF_PARTS is not set
-CONFIG_MTD_SPI_NOR=y
-# CONFIG_MTK_EFUSE is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NET_CADENCE is not set
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-# CONFIG_NUMA is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_PADATA=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_BUS_ADDR_T_64BIT=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MTK_TPHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT6397 is not set
-CONFIG_PINCTRL_MT7622=y
-# CONFIG_PINCTRL_MT8173 is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-# CONFIG_RANDOMIZE_BASE is not set
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6323=y
-CONFIG_REGULATOR_MT6380=y
-# CONFIG_REGULATOR_MT6397 is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_MT6397 is not set
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SCHED_INFO is not set
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SERIAL_DEV_BUS=y
-# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SRCU=y
-CONFIG_SWAP=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_SUPPORTS_HUGETLBFS=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MTK=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y

target/linux/mediatek/mt7623/config-4.14

@@ -1,502 +0,0 @@
-# CONFIG_AIO is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_STACKPROTECTOR=y
-# CONFIG_CC_STACKPROTECTOR_NONE is not set
-CONFIG_CC_STACKPROTECTOR_REGULAR=y
-CONFIG_CLEANCACHE=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2701=y
-CONFIG_COMMON_CLK_MT2701_BDPSYS=y
-CONFIG_COMMON_CLK_MT2701_ETHSYS=y
-CONFIG_COMMON_CLK_MT2701_HIFSYS=y
-CONFIG_COMMON_CLK_MT2701_IMGSYS=y
-CONFIG_COMMON_CLK_MT2701_MMSYS=y
-CONFIG_COMMON_CLK_MT2701_VDECSYS=y
-# CONFIG_COMMON_CLK_MT7622 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-CONFIG_COREDUMP=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-# CONFIG_CPU_THERMAL is not set
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CTR=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_MEDIATEK=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MT6589_UART0=y
-# CONFIG_DEBUG_MT8127_UART0 is not set
-# CONFIG_DEBUG_MT8135_UART3 is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_UART_8250=y
-# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
-CONFIG_DEBUG_UART_8250_SHIFT=2
-# CONFIG_DEBUG_UART_8250_WORD is not set
-CONFIG_DEBUG_UART_PHYS=0x11004000
-CONFIG_DEBUG_UART_VIRT=0xf1004000
-CONFIG_DEBUG_UNCOMPRESS=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-# CONFIG_F2FS_CHECK_FS is not set
-CONFIG_F2FS_FS=y
-# CONFIG_F2FS_FS_SECURITY is not set
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_STAT_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_GRO_CELLS is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_ARM_SMCCC=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IIO=y
-# CONFIG_IIO_BUFFER is not set
-# CONFIG_IIO_TRIGGER is not set
-CONFIG_INITRAMFS_COMPRESSION=""
-CONFIG_INITRAMFS_ROOT_GID=1000
-CONFIG_INITRAMFS_ROOT_UID=1000
-CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-arm_cortex-a7_musl-1.1.14_eabi/root-mediatek /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
-CONFIG_IOMMU_HELPER=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_LEDS_MT6323=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-CONFIG_MACH_MT7623=y
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEDIATEK_MT6577_AUXADC=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_MT6397=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MTK=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_MT81xx_NOR=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTK_EFUSE=y
-# CONFIG_MTK_HSDMA is not set
-CONFIG_MTK_INFRACFG=y
-# CONFIG_MTK_IOMMU is not set
-# CONFIG_MTK_IOMMU_V1 is not set
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_TIMER=y
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_SWITCHDEV=y
-# CONFIG_NET_VENDOR_AURORA is not set
-CONFIG_NET_VENDOR_MEDIATEK=y
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_NLS=y
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHY_MTK_TPHY=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT2701=y
-CONFIG_PINCTRL_MT6397=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-# CONFIG_RCU_EXPERT is not set
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_MT6323=y
-# CONFIG_REGULATOR_MT6380 is not set
-# CONFIG_REGULATOR_MT6397 is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_MT6397 is not set
-# CONFIG_RTC_DRV_MT7622 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SCHED_INFO is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPMI=y
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TASKS_RCU=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MTK=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y

target/linux/mediatek/patches-4.14/0006-reset-mediatek-mt2701-reset-driver.patch

@@ -1,27 +0,0 @@
-From 596c3a7300c0419dba71d58cbd4136e0d1e12a4e Mon Sep 17 00:00:00 2001
-From: Shunli Wang <[email protected]>
-Date: Tue, 5 Jan 2016 14:30:22 +0800
-Subject: [PATCH 06/57] reset: mediatek: mt2701 reset driver
-
-In infrasys and perifsys, there are many reset
-control bits for kinds of modules. These bits are
-used as actual reset controllers to be registered
-into kernel's generic reset controller framework.
-
-Signed-off-by: Shunli Wang <[email protected]>
-Acked-by: Philipp Zabel <[email protected]>
----
- drivers/clk/mediatek/clk-mt2701.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/clk/mediatek/clk-mt2701.c
-+++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -772,6 +772,8 @@ static void mtk_infrasys_init_early(stru
- 	if (r)
- 		pr_err("%s(): could not register clock provider: %d\n",
- 			__func__, r);
-+
-+	mtk_register_reset_controller(node, 2, 0x30);
- }
- CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
- 			mtk_infrasys_init_early);

target/linux/mediatek/patches-4.14/0012-clk-dont-disable-unused-clocks.patch

@@ -1,21 +0,0 @@
-From 0e60d2112968ccb2570535bf19fb5020c9b28c08 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Thu, 7 Apr 2016 07:18:35 +0200
-Subject: [PATCH 12/57] clk: dont disable unused clocks
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/clk/clk.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/clk.c
-+++ b/drivers/clk/clk.c
-@@ -797,7 +797,7 @@ unlock_out:
- 		clk_core_disable_unprepare(core->parent);
- }
- 
--static bool clk_ignore_unused;
-+static bool clk_ignore_unused = true;
- static int __init clk_ignore_unused_setup(char *__unused)
- {
- 	clk_ignore_unused = true;

target/linux/mediatek/patches-4.14/0027-net-next-mediatek-fix-DQL-support.patch

@@ -1,92 +0,0 @@
-From f974e397b806f7b16d11cc1542538616291924f1 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Sat, 23 Apr 2016 11:57:21 +0200
-Subject: [PATCH 27/57] net-next: mediatek: fix DQL support
-
-The MTK ethernet core has 2 MACs both sitting on the same DMA ring. The
-current code will assign the TX traffic of each MAC to its own DQL. This
-results in the amount of data, that DQL says is in the queue incorrect. As
-the data from multiple devices is infact enqueued. This makes any decision
-based on these value non deterministic. Fix this by tracking all TX
-traffic, regardless of the MAC it belongs to in the DQL of all devices
-using the DMA.
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
- 1 file changed, 21 insertions(+), 14 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -779,7 +779,16 @@ static int mtk_tx_map(struct sk_buff *sk
- 	WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
- 				(!nr_frags * TX_DMA_LS0)));
- 
--	netdev_sent_queue(dev, skb->len);
-+	/* we have a single DMA ring so BQL needs to be updated for all devices
-+	 * sitting on this ring
-+	 */
-+	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+		if (!eth->netdev[i])
-+			continue;
-+
-+		netdev_sent_queue(eth->netdev[i], skb->len);
-+	}
-+
- 	skb_tx_timestamp(skb);
- 
- 	ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
-@@ -1076,20 +1085,17 @@ static int mtk_poll_tx(struct mtk_eth *e
- 	struct mtk_tx_dma *desc;
- 	struct sk_buff *skb;
- 	struct mtk_tx_buf *tx_buf;
--	unsigned int done[MTK_MAX_DEVS];
--	unsigned int bytes[MTK_MAX_DEVS];
-+	int total = 0, done = 0;
-+	unsigned int bytes = 0;
- 	u32 cpu, dma;
--	int total = 0, i;
--
--	memset(done, 0, sizeof(done));
--	memset(bytes, 0, sizeof(bytes));
-+	int i;
- 
- 	cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
- 	dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
- 
- 	desc = mtk_qdma_phys_to_virt(ring, cpu);
- 
--	while ((cpu != dma) && budget) {
-+	while ((cpu != dma) && (done < budget)) {
- 		u32 next_cpu = desc->txd2;
- 		int mac = 0;
- 
-@@ -1106,9 +1112,8 @@ static int mtk_poll_tx(struct mtk_eth *e
- 			break;
- 
- 		if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
--			bytes[mac] += skb->len;
--			done[mac]++;
--			budget--;
-+			bytes += skb->len;
-+			done++;
- 		}
- 		mtk_tx_unmap(eth, tx_buf);
- 
-@@ -1120,11 +1125,13 @@ static int mtk_poll_tx(struct mtk_eth *e
- 
- 	mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
- 
-+	/* we have a single DMA ring so BQL needs to be updated for all devices
-+	 * sitting on this ring
-+	 */
- 	for (i = 0; i < MTK_MAC_COUNT; i++) {
--		if (!eth->netdev[i] || !done[i])
-+		if (!eth->netdev[i])
- 			continue;
--		netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
--		total += done[i];
-+		netdev_completed_queue(eth->netdev[i], done, bytes);
- 	}
- 
- 	if (mtk_queue_stopped(eth) &&

target/linux/mediatek/patches-4.14/0032-net-dsa-mediatek-add-support-for-GMAC2-wired-to-ext-.patch

@@ -1,26 +0,0 @@
-From 52e9ce30a2b3c414e0efb20632fefa7cfc5096e6 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Thu, 10 Aug 2017 14:44:18 +0200
-Subject: [PATCH 32/57] net: dsa: mediatek: add support for GMAC2 wired to ext
- phy
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/dsa/mt7530.c                    | 5 +++++
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 +++
- 2 files changed, 8 insertions(+)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -991,6 +991,11 @@ mt7530_setup(struct dsa_switch *ds)
- 	val = mt7530_read(priv, MT7530_MHWTRAP);
- 	val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
- 	val |= MHWTRAP_MANUAL;
-+	if (!dsa_is_cpu_port(ds, 5)) {
-+		val |= MHWTRAP_P5_DIS;
-+		val |= MHWTRAP_P5_MAC_SEL;
-+		val |= MHWTRAP_P5_RGMII_MODE;
-+	}
- 	mt7530_write(priv, MT7530_MHWTRAP, val);
- 
- 	/* Enable and reset MIB counters */

target/linux/mediatek/patches-4.14/0033-dsa-multi-cpu.patch

@@ -1,268 +0,0 @@
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -670,6 +670,9 @@ static int
- mt7530_cpu_port_enable(struct mt7530_priv *priv,
- 		       int port)
- {
-+	u8 port_mask = 0;
-+	int i;
-+
- 	/* Enable Mediatek header mode on the cpu port */
- 	mt7530_write(priv, MT7530_PVC_P(port),
- 		     PORT_SPEC_TAG);
-@@ -686,8 +689,12 @@ mt7530_cpu_port_enable(struct mt7530_pri
- 	/* CPU port gets connected to all user ports of
- 	 * the switch
- 	 */
-+	for (i = 0; i < MT7530_NUM_PORTS; i++)
-+		if ((priv->ds->enabled_port_mask & BIT(i)) &&
-+		    (dsa_port_upstream_port(priv->ds, i) == port))
-+			port_mask |= BIT(i);
- 	mt7530_write(priv, MT7530_PCR_P(port),
--		     PCR_MATRIX(priv->ds->enabled_port_mask));
-+		     PCR_MATRIX(port_mask));
- 
- 	return 0;
- }
-@@ -697,6 +704,7 @@ mt7530_port_enable(struct dsa_switch *ds
- 		   struct phy_device *phy)
- {
- 	struct mt7530_priv *priv = ds->priv;
-+	u8 upstream = dsa_port_upstream_port(ds, port);
- 
- 	mutex_lock(&priv->reg_mutex);
- 
-@@ -707,7 +715,7 @@ mt7530_port_enable(struct dsa_switch *ds
- 	 * restore the port matrix if the port is the member of a certain
- 	 * bridge.
- 	 */
--	priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
-+	priv->ports[port].pm |= PCR_MATRIX(BIT(upstream));
- 	priv->ports[port].enable = true;
- 	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
- 		   priv->ports[port].pm);
-@@ -770,7 +778,8 @@ mt7530_port_bridge_join(struct dsa_switc
- 			struct net_device *bridge)
- {
- 	struct mt7530_priv *priv = ds->priv;
--	u32 port_bitmap = BIT(MT7530_CPU_PORT);
-+	u8 upstream = dsa_port_upstream_port(ds, port);
-+	u32 port_bitmap = BIT(upstream);
- 	int i;
- 
- 	mutex_lock(&priv->reg_mutex);
-@@ -808,6 +817,7 @@ mt7530_port_bridge_leave(struct dsa_swit
- 			 struct net_device *bridge)
- {
- 	struct mt7530_priv *priv = ds->priv;
-+	u8 upstream = dsa_port_upstream_port(ds, port);
- 	int i;
- 
- 	mutex_lock(&priv->reg_mutex);
-@@ -832,8 +842,8 @@ mt7530_port_bridge_leave(struct dsa_swit
- 	 */
- 	if (priv->ports[port].enable)
- 		mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
--			   PCR_MATRIX(BIT(MT7530_CPU_PORT)));
--	priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
-+			   PCR_MATRIX(BIT(upstream)));
-+	priv->ports[port].pm = PCR_MATRIX(BIT(upstream));
- 
- 	mutex_unlock(&priv->reg_mutex);
- }
-@@ -908,15 +918,7 @@ err:
- static enum dsa_tag_protocol
- mtk_get_tag_protocol(struct dsa_switch *ds)
- {
--	struct mt7530_priv *priv = ds->priv;
--
--	if (!dsa_is_cpu_port(ds, MT7530_CPU_PORT)) {
--		dev_warn(priv->dev,
--			 "port not matched with tagging CPU port\n");
--		return DSA_TAG_PROTO_NONE;
--	} else {
--		return DSA_TAG_PROTO_MTK;
--	}
-+	return DSA_TAG_PROTO_MTK;
- }
- 
- static int
-@@ -989,7 +991,7 @@ mt7530_setup(struct dsa_switch *ds)
- 
- 	/* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
- 	val = mt7530_read(priv, MT7530_MHWTRAP);
--	val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
-+	val &= ~MHWTRAP_P5_DIS & ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
- 	val |= MHWTRAP_MANUAL;
- 	if (!dsa_is_cpu_port(ds, 5)) {
- 		val |= MHWTRAP_P5_DIS;
---- a/include/net/dsa.h
-+++ b/include/net/dsa.h
-@@ -185,6 +185,10 @@ struct dsa_port {
- 	u8			stp_state;
- 	struct net_device	*bridge_dev;
- 	struct devlink_port	devlink_port;
-+
-+	struct net_device	*ethernet;
-+	int			upstream;
-+
- 	/*
- 	 * Original copy of the master netdev ethtool_ops
- 	 */
-@@ -266,6 +270,11 @@ static inline bool dsa_is_normal_port(st
- 	return !dsa_is_cpu_port(ds, p) && !dsa_is_dsa_port(ds, p);
- }
- 
-+static inline bool dsa_is_upstream_port(struct dsa_switch *ds, int p)
-+{
-+	return dsa_is_cpu_port(ds, p) || dsa_is_dsa_port(ds, p);
-+}
-+
- static inline u8 dsa_upstream_port(struct dsa_switch *ds)
- {
- 	struct dsa_switch_tree *dst = ds->dst;
-@@ -282,6 +291,18 @@ static inline u8 dsa_upstream_port(struc
- 		return ds->rtable[dst->cpu_dp->ds->index];
- }
- 
-+static inline u8 dsa_port_upstream_port(struct dsa_switch *ds, int port)
-+{
-+	/*
-+	 * If this port has a specific upstream cpu port, use it,
-+	 * otherwise use the switch default.
-+	 */
-+	if (ds->ports[port].upstream)
-+		return ds->ports[port].upstream;
-+	else
-+		return dsa_upstream_port(ds);
-+}
-+
- typedef int dsa_fdb_dump_cb_t(const unsigned char *addr, u16 vid,
- 			      bool is_static, void *data);
- struct dsa_switch_ops {
---- a/net/dsa/dsa2.c
-+++ b/net/dsa/dsa2.c
-@@ -253,6 +253,8 @@ static int dsa_cpu_port_apply(struct dsa
- 	memset(&port->devlink_port, 0, sizeof(port->devlink_port));
- 	err = devlink_port_register(ds->devlink, &port->devlink_port,
- 				    port->index);
-+	if (port->netdev)
-+		port->netdev->dsa_ptr = ds->dst;
- 	return err;
- }
- 
-@@ -262,6 +264,12 @@ static void dsa_cpu_port_unapply(struct
- 	dsa_cpu_dsa_destroy(port);
- 	port->ds->cpu_port_mask &= ~BIT(port->index);
- 
-+	if (port->netdev)
-+		port->netdev->dsa_ptr = NULL;
-+	if (port->ethernet) {
-+		dev_put(port->ethernet);
-+		port->ethernet = NULL;
-+	}
- }
- 
- static int dsa_user_port_apply(struct dsa_port *port)
-@@ -505,10 +513,9 @@ static int dsa_cpu_parse(struct dsa_port
- 		dev_put(ethernet_dev);
- 	}
- 
--	if (!dst->cpu_dp) {
-+	if (!dst->cpu_dp)
- 		dst->cpu_dp = port;
--		dst->cpu_dp->netdev = ethernet_dev;
--	}
-+	port->netdev = ethernet_dev;
- 
- 	/* Initialize cpu_port_mask now for drv->setup()
- 	 * to have access to a correct value, just like what
-@@ -526,6 +533,29 @@ static int dsa_cpu_parse(struct dsa_port
- 
- 	dst->rcv = dst->tag_ops->rcv;
- 
-+	dev_hold(ethernet_dev);
-+	ds->ports[index].ethernet = ethernet_dev;
-+	ds->cpu_port_mask |= BIT(index);
-+
-+	return 0;
-+}
-+
-+static int dsa_user_parse(struct dsa_port *port, u32 index,
-+			  struct dsa_switch *ds)
-+{
-+	struct device_node *cpu_port;
-+	const unsigned int *cpu_port_reg;
-+	int cpu_port_index;
-+
-+	cpu_port = of_parse_phandle(port->dn, "cpu", 0);
-+	if (cpu_port) {
-+		cpu_port_reg = of_get_property(cpu_port, "reg", NULL);
-+		if (!cpu_port_reg)
-+			return -EINVAL;
-+		cpu_port_index = be32_to_cpup(cpu_port_reg);
-+		ds->ports[index].upstream = cpu_port_index;
-+	}
-+
- 	return 0;
- }
- 
-@@ -533,7 +563,7 @@ static int dsa_ds_parse(struct dsa_switc
- {
- 	struct dsa_port *port;
- 	u32 index;
--	int err;
-+	int err = 0;
- 
- 	for (index = 0; index < ds->num_ports; index++) {
- 		port = &ds->ports[index];
-@@ -546,6 +576,9 @@ static int dsa_ds_parse(struct dsa_switc
- 			if (err)
- 				return err;
- 		} else {
-+			err = dsa_user_parse(port, index, ds);
-+			if (err)
-+				return err;
- 			/* Initialize enabled_port_mask now for drv->setup()
- 			 * to have access to a correct value, just like what
- 			 * net/dsa/dsa.c::dsa_switch_setup_one does.
---- a/net/dsa/dsa_priv.h
-+++ b/net/dsa/dsa_priv.h
-@@ -91,6 +91,8 @@ struct dsa_slave_priv {
- 
- 	/* TC context */
- 	struct list_head	mall_tc_list;
-+
-+	struct net_device       *master;
- };
- 
- /* dsa.c */
-@@ -177,6 +179,9 @@ extern const struct dsa_device_ops trail
- 
- static inline struct net_device *dsa_master_netdev(struct dsa_slave_priv *p)
- {
-+	if (p->master)
-+		return p->master;
-+
- 	return p->dp->cpu_dp->netdev;
- }
- 
---- a/net/dsa/slave.c
-+++ b/net/dsa/slave.c
-@@ -1267,7 +1267,7 @@ int dsa_slave_create(struct dsa_port *po
- 	int ret;
- 
- 	cpu_dp = ds->dst->cpu_dp;
--	master = cpu_dp->netdev;
-+	master = ds->ports[port->upstream].ethernet;
- 
- 	if (!ds->num_tx_queues)
- 		ds->num_tx_queues = 1;
-@@ -1305,6 +1305,7 @@ int dsa_slave_create(struct dsa_port *po
- 	p->dp = port;
- 	INIT_LIST_HEAD(&p->mall_tc_list);
- 	p->xmit = dst->tag_ops->xmit;
-+	p->master = master;
- 
- 	p->old_pause = -1;
- 	p->old_link = -1;

target/linux/mediatek/patches-4.14/0035-net-mediatek-disable-RX-VLan-offloading.patch

@@ -1,47 +0,0 @@
-From 35b83b85e752a6660b92f08c0fb912308f25cf6d Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Thu, 10 Aug 2017 15:56:40 +0200
-Subject: [PATCH 35/57] net: mediatek: disable RX VLan offloading
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 ++++++---
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 --
- 2 files changed, 6 insertions(+), 5 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -709,8 +709,8 @@ static int mtk_tx_map(struct sk_buff *sk
- 		txd4 |= TX_DMA_CHKSUM;
- 
- 	/* VLAN header offload */
--	if (skb_vlan_tag_present(skb))
--		txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
-+//	if (skb_vlan_tag_present(skb))
-+//		txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
- 
- 	mapped_addr = dma_map_single(eth->dev, skb->data,
- 				     skb_headlen(skb), DMA_TO_DEVICE);
-@@ -1981,7 +1981,10 @@ static int mtk_hw_init(struct mtk_eth *e
- 	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
- 
- 	/* Enable RX VLan Offloading */
--	mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
-+	if (MTK_HW_FEATURES & NETIF_F_HW_VLAN_CTAG_RX)
-+		mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
-+	else
-+		mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
- 
- 	/* enable interrupt delay for RX */
- 	mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -34,8 +34,6 @@
- 				 NETIF_MSG_TX_ERR)
- #define MTK_HW_FEATURES		(NETIF_F_IP_CSUM | \
- 				 NETIF_F_RXCSUM | \
--				 NETIF_F_HW_VLAN_CTAG_TX | \
--				 NETIF_F_HW_VLAN_CTAG_RX | \
- 				 NETIF_F_SG | NETIF_F_TSO | \
- 				 NETIF_F_TSO6 | \
- 				 NETIF_F_IPV6_CSUM)

target/linux/mediatek/patches-4.14/0042-net-next-mediatek-honour-special-tag-bit-inside-RX-D.patch

@@ -1,50 +0,0 @@
-From a306af3b97c56b9e224a2f9ee04838a2d32ff60b Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Wed, 9 Aug 2017 14:44:07 +0200
-Subject: [PATCH 42/57] net-next: mediatek: honour special tag bit inside RX
- DMA descriptor
-
-For HW NAT/QoS to work the DSA driver needs to turn the special tag bit
-inside the ingress control register on. This has the side effect that
-the code working out which ingress gmac we have breaks. Fix this by
-honouring the special tag bit inside the RX free descriptor.
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 14 ++++++++++----
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  1 +
- 2 files changed, 11 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -999,10 +999,16 @@ static int mtk_poll_rx(struct napi_struc
- 		if (!(trxd.rxd2 & RX_DMA_DONE))
- 			break;
- 
--		/* find out which mac the packet come from. values start at 1 */
--		mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
--		      RX_DMA_FPORT_MASK;
--		mac--;
-+		/* find out which mac the packet comes from. If the special tag is
-+		 * we can assume that the traffic is coming from the builtin mt7530
-+		 * and the DSA driver has loaded. FPORT will be the physical switch
-+		 * port in this case rather than the FE forward port id. */
-+		if (!(trxd.rxd4 & RX_DMA_SP_TAG)) {
-+			/* values start at 1 */
-+			mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
-+			      RX_DMA_FPORT_MASK;
-+			mac--;
-+		}
- 
- 		if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
- 			     !eth->netdev[mac]))
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -287,6 +287,7 @@
- 
- /* QDMA descriptor rxd4 */
- #define RX_DMA_L4_VALID		BIT(24)
-+#define RX_DMA_SP_TAG		BIT(22)
- #define RX_DMA_FPORT_SHIFT	19
- #define RX_DMA_FPORT_MASK	0x7
- 

target/linux/mediatek/patches-4.14/0043-net-next-mediatek-enable-special-tag-indication-for-.patch

@@ -1,41 +0,0 @@
-From 53e3d9af39805a7e1ba81a047a9ab433be0e82f5 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Wed, 9 Aug 2017 14:56:53 +0200
-Subject: [PATCH 43/57] net-next: mediatek: enable special tag indication for
- PDMA
-
-The Ingress special tag indication was only enabled for QDMA and not PDMA.
-Properly initialize the STAG bit. This broke HW NAT and Qos from working
-for traffic coming in via a DSA device. The PPE failed to properly parse
-the traffic as it was not expecting the special tag.
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 ++
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
- 2 files changed, 6 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1985,6 +1985,8 @@ static int mtk_hw_init(struct mtk_eth *e
- 	 */
- 	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
- 	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
-+	val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
-+	mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
- 
- 	/* Enable RX VLan Offloading */
- 	if (MTK_HW_FEATURES & NETIF_F_HW_VLAN_CTAG_RX)
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -72,6 +72,10 @@
- #define MTK_CDMQ_IG_CTRL	0x1400
- #define MTK_CDMQ_STAG_EN	BIT(0)
- 
-+/* CDMP Ingress Control Register */
-+#define MTK_CDMP_IG_CTRL	0x400
-+#define MTK_CDMP_STAG_EN	BIT(0)
-+
- /* CDMP Exgress Control Register */
- #define MTK_CDMP_EG_CTRL	0x404
- 

target/linux/mediatek/patches-4.14/0044-net-next-dsa-mediatek-tell-GDMA-when-we-are-turning-.patch

@@ -1,43 +0,0 @@
-From 6a5932028a4f3217ed7c9d602f269611d95dd8ca Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Wed, 9 Aug 2017 15:13:19 +0200
-Subject: [PATCH 44/57] net-next: dsa: mediatek: tell GDMA when we are turning
- on the special tag
-
-Enabling this bit will make the RX DMA descriptor enable the SP bit for all
-ingress traffic inside the return descriptor. The PPE needs this to know
-that a SP is present.
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/dsa/mt7530.c | 5 +++++
- drivers/net/dsa/mt7530.h | 4 ++++
- 2 files changed, 9 insertions(+)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -677,6 +677,11 @@ mt7530_cpu_port_enable(struct mt7530_pri
- 	mt7530_write(priv, MT7530_PVC_P(port),
- 		     PORT_SPEC_TAG);
- 
-+	/* Enable Mediatek header mode on the GMAC that the cpu port
-+	 * connects to */
-+	regmap_write_bits(priv->ethernet, MTK_GDMA_FWD_CFG(port),
-+			  GDMA_SPEC_TAG, GDMA_SPEC_TAG);
-+
- 	/* Setup the MAC by default for the cpu port */
- 	mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
- 
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -22,6 +22,10 @@
- 
- #define TRGMII_BASE(x)			(0x10000 + (x))
- 
-+/* Registers for GDMA configuration access */
-+#define MTK_GDMA_FWD_CFG(x)		(0x500 + (x * 0x1000))
-+#define GDMA_SPEC_TAG			BIT(24)
-+
- /* Registers to ethsys access */
- #define ETHSYS_CLKCFG0			0x2c
- #define  ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)

target/linux/mediatek/patches-4.14/0045-net-dsa-mediatek-turn-into-platform-driver.patch

@@ -1,79 +0,0 @@
-From 1e33784f665cb95c2af5481d3e776d2d3099921b Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Thu, 10 Aug 2017 15:57:17 +0200
-Subject: [PATCH 45/57] net: dsa: mediatek: turn into platform driver
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/dsa/mt7530.c | 23 +++++++++++++++--------
- 1 file changed, 15 insertions(+), 8 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -1049,10 +1049,10 @@ static const struct dsa_switch_ops mt753
- };
- 
- static int
--mt7530_probe(struct mdio_device *mdiodev)
-+mt7530_probe(struct platform_device *mdiodev)
- {
- 	struct mt7530_priv *priv;
--	struct device_node *dn;
-+	struct device_node *dn, *mdio;
- 
- 	dn = mdiodev->dev.of_node;
- 
-@@ -1100,7 +1100,12 @@ mt7530_probe(struct mdio_device *mdiodev
- 		}
- 	}
- 
--	priv->bus = mdiodev->bus;
-+	mdio = of_parse_phandle(dn, "dsa,mii-bus", 0);
-+	if (!mdio)
-+		return -EINVAL;
-+	priv->bus = of_mdio_find_bus(mdio);
-+	if (!priv->bus)
-+		return -EPROBE_DEFER;
- 	priv->dev = &mdiodev->dev;
- 	priv->ds->priv = priv;
- 	priv->ds->ops = &mt7530_switch_ops;
-@@ -1110,8 +1115,8 @@ mt7530_probe(struct mdio_device *mdiodev
- 	return dsa_register_switch(priv->ds);
- }
- 
--static void
--mt7530_remove(struct mdio_device *mdiodev)
-+static int
-+mt7530_remove(struct platform_device *mdiodev)
- {
- 	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
- 	int ret = 0;
-@@ -1128,6 +1133,8 @@ mt7530_remove(struct mdio_device *mdiode
- 
- 	dsa_unregister_switch(priv->ds);
- 	mutex_destroy(&priv->reg_mutex);
-+
-+	return 0;
- }
- 
- static const struct of_device_id mt7530_of_match[] = {
-@@ -1136,16 +1143,16 @@ static const struct of_device_id mt7530_
- };
- MODULE_DEVICE_TABLE(of, mt7530_of_match);
- 
--static struct mdio_driver mt7530_mdio_driver = {
-+static struct platform_driver mtk_mt7530_driver = {
- 	.probe  = mt7530_probe,
- 	.remove = mt7530_remove,
--	.mdiodrv.driver = {
-+	.driver = {
- 		.name = "mt7530",
- 		.of_match_table = mt7530_of_match,
- 	},
- };
-+module_platform_driver(mtk_mt7530_driver);
- 
--mdio_module_driver(mt7530_mdio_driver);
- 
- MODULE_AUTHOR("Sean Wang <[email protected]>");
- MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");

target/linux/mediatek/patches-4.14/0046-net-mediatek-add-irq-delay.patch

@@ -1,21 +0,0 @@
-From 6e081074df96bf3762c2e6438c383f11a56b0a7e Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Thu, 10 Aug 2017 15:58:04 +0200
-Subject: [PATCH 46/57] net: mediatek: add irq delay
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 ++++++-
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++++-
- 2 files changed, 13 insertions(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1996,6 +1996,7 @@ static int mtk_hw_init(struct mtk_eth *e
- 
- 	/* enable interrupt delay for RX */
- 	mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
-+	//mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_QDMA_DELAY_INT);
- 
- 	/* disable delay and normal interrupt */
- 	mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);

target/linux/mediatek/patches-4.14/0051-net-mediatek-increase-tx_timeout.patch

@@ -1,21 +0,0 @@
-From 5cbf53c7e5eac5bacc409461888789accdaf8eec Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Thu, 10 Aug 2017 16:00:06 +0200
-Subject: [PATCH 51/57] net: mediatek: increase tx_timeout
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2455,7 +2455,7 @@ static int mtk_add_mac(struct mtk_eth *e
- 	mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
- 
- 	SET_NETDEV_DEV(eth->netdev[id], eth->dev);
--	eth->netdev[id]->watchdog_timeo = 5 * HZ;
-+	eth->netdev[id]->watchdog_timeo = 30 * HZ;
- 	eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
- 	eth->netdev[id]->base_addr = (unsigned long)eth->base;
- 

target/linux/mediatek/patches-4.14/0052-net-phy-add-FC.patch

@@ -1,21 +0,0 @@
-From 18b2169d84b47a3414164e5e40f23fb7e875707c Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Thu, 10 Aug 2017 16:00:28 +0200
-Subject: [PATCH 52/57] net: phy: add FC
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/net/phy/phy_device.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/phy/phy_device.c
-+++ b/drivers/net/phy/phy_device.c
-@@ -1944,7 +1944,7 @@ static struct phy_driver genphy_driver =
- 	.config_init	= genphy_config_init,
- 	.features	= PHY_GBIT_FEATURES | SUPPORTED_MII |
- 			  SUPPORTED_AUI | SUPPORTED_FIBRE |
--			  SUPPORTED_BNC,
-+			  SUPPORTED_BNC | SUPPORTED_Pause | SUPPORTED_Asym_Pause,
- 	.config_aneg	= genphy_config_aneg,
- 	.aneg_done	= genphy_aneg_done,
- 	.read_status	= genphy_read_status,

target/linux/mediatek/patches-4.14/0062-mdio-atomic.patch

@@ -1,14 +0,0 @@
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -76,7 +76,10 @@ static int mtk_mdio_busy_wait(struct mtk
- 			return 0;
- 		if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
- 			break;
--		usleep_range(10, 20);
-+		if (in_atomic())
-+			udelay(10);
-+		else
-+			usleep_range(10, 20);
- 	}
- 
- 	dev_err(eth->dev, "mdio: MDIO timeout\n");

target/linux/mediatek/patches-4.14/0063-atomic-sleep.patch

@@ -1,46 +0,0 @@
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -409,6 +409,7 @@ static int mtk_mdio_init(struct mtk_eth
- 
- 	snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
- 	ret = of_mdiobus_register(eth->mii_bus, mii_np);
-+printk("%s:%s[%d]%d %p\n", __FILE__, __func__, __LINE__, ret, eth->mii_bus);
- 
- err_put_node:
- 	of_node_put(mii_np);
-@@ -1472,7 +1473,10 @@ static void mtk_hwlro_rx_uninit(struct m
- 	for (i = 0; i < 10; i++) {
- 		val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
- 		if (val & MTK_LRO_RING_RELINQUISH_DONE) {
--			msleep(20);
-+			if (in_atomic())
-+				mdelay(20);
-+			else
-+				msleep(20);
- 			continue;
- 		}
- 		break;
-@@ -1869,7 +1873,10 @@ static void mtk_stop_dma(struct mtk_eth
- 	for (i = 0; i < 10; i++) {
- 		val = mtk_r32(eth, glo_cfg);
- 		if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
--			msleep(20);
-+			if (in_atomic())
-+				mdelay(20);
-+			else
-+				msleep(20);
- 			continue;
- 		}
- 		break;
-@@ -1907,7 +1914,10 @@ static void ethsys_reset(struct mtk_eth
- 			   reset_bits,
- 			   reset_bits);
- 
--	usleep_range(1000, 1100);
-+	if (in_atomic())
-+		udelay(1000);
-+	else
-+		usleep_range(1000, 1100);
- 	regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
- 			   reset_bits,
- 			   ~reset_bits);

target/linux/mediatek/patches-4.14/0064-dts.patch

@@ -1,127 +0,0 @@
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -21,6 +21,10 @@
- 		stdout-path = "serial2:115200n8";
- 	};
- 
-+	memory {
-+		reg = <0 0x80000000 0 0x20000000>;
-+	};
-+
- 	cpus {
- 		cpu@0 {
- 			proc-supply = <&mt6323_vproc_reg>;
-@@ -103,6 +107,10 @@
- 		device_type = "memory";
- 		reg = <0 0x80000000 0 0x40000000>;
- 	};
-+
-+	mt7530: switch@0 {
-+		compatible = "mediatek,mt7530";
-+	};
- };
- 
- &cir {
-@@ -130,11 +138,24 @@
- 		};
- 	};
- 
-+	gmac1: mac@1 {
-+		compatible = "mediatek,eth-mac";
-+		reg = <1>;
-+		phy-mode = "rgmii";
-+
-+		fixed-link {
-+			speed = <1000>;
-+			full-duplex;
-+			pause;
-+		};
-+	};
-+
- 	mdio: mdio-bus {
- 		#address-cells = <1>;
- 		#size-cells = <0>;
--
--		switch@0 {
-+	};
-+};
-+		&mt7530 {
- 			compatible = "mediatek,mt7530";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
-@@ -144,6 +165,8 @@
- 			core-supply = <&mt6323_vpa_reg>;
- 			io-supply = <&mt6323_vemc3v3_reg>;
- 
-+			dsa,mii-bus = <&mdio>;
-+
- 			ports {
- 				#address-cells = <1>;
- 				#size-cells = <0>;
-@@ -152,29 +175,46 @@
- 				port@0 {
- 					reg = <0>;
- 					label = "wan";
-+					cpu = <&cpu_port1>;
- 				};
- 
- 				port@1 {
- 					reg = <1>;
- 					label = "lan0";
-+					cpu = <&cpu_port0>;
- 				};
- 
- 				port@2 {
- 					reg = <2>;
- 					label = "lan1";
-+					cpu = <&cpu_port0>;
- 				};
- 
- 				port@3 {
- 					reg = <3>;
- 					label = "lan2";
-+					cpu = <&cpu_port0>;
- 				};
- 
- 				port@4 {
- 					reg = <4>;
- 					label = "lan3";
-+					cpu = <&cpu_port0>;
- 				};
- 
--				port@6 {
-+				cpu_port1: port@5 {
-+					reg = <5>;
-+					label = "cpu";
-+					ethernet = <&gmac1>;
-+					phy-mode = "rgmii";
-+
-+					fixed-link {
-+						speed = <1000>;
-+						full-duplex;
-+					};
-+				};
-+
-+				cpu_port0: port@6 {
- 					reg = <6>;
- 					label = "cpu";
- 					ethernet = <&gmac0>;
-@@ -187,8 +227,6 @@
- 				};
- 			};
- 		};
--	};
--};
- 
- &i2c0 {
- 	pinctrl-names = "default";
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -326,6 +326,7 @@
- 			     "syscon";
- 		reg = <0 0x10209000 0 0x1000>;
- 		#clock-cells = <1>;
-+		#reset-cells = <1>;
- 	};
- 
- 	rng: rng@1020f000 {

target/linux/mediatek/patches-4.14/0101-reset-mediatek-add-reset-controller-dt-bindings-requ.patch

@@ -1,114 +0,0 @@
-From 5d6a82632eb7258c8ca49cc96c18b8b4071b6639 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 20 Sep 2017 17:40:16 +0800
-Subject: [PATCH 101/224] reset: mediatek: add reset controller dt-bindings
- required header for MT7622 SoC
-
-Add the reset controller dt-bindings exported from infracfg, pericfg,
-hifsys and ethsys which could be found on MT7622 SoC. So that we can
-reference them from within a device-tree file.
-
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Philipp Zabel <[email protected]>
----
- include/dt-bindings/reset/mt7622-reset.h | 94 ++++++++++++++++++++++++++++++++
- 1 file changed, 94 insertions(+)
- create mode 100644 include/dt-bindings/reset/mt7622-reset.h
-
---- /dev/null
-+++ b/include/dt-bindings/reset/mt7622-reset.h
-@@ -0,0 +1,94 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Sean Wang <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622
-+#define _DT_BINDINGS_RESET_CONTROLLER_MT7622
-+
-+/* INFRACFG resets */
-+#define MT7622_INFRA_EMI_REG_RST		0
-+#define MT7622_INFRA_DRAMC0_A0_RST		1
-+#define MT7622_INFRA_APCIRQ_EINT_RST		3
-+#define MT7622_INFRA_APXGPT_RST			4
-+#define MT7622_INFRA_SCPSYS_RST			5
-+#define MT7622_INFRA_PMIC_WRAP_RST		7
-+#define MT7622_INFRA_IRRX_RST			9
-+#define MT7622_INFRA_EMI_RST			16
-+#define MT7622_INFRA_WED0_RST			17
-+#define MT7622_INFRA_DRAMC_RST			18
-+#define MT7622_INFRA_CCI_INTF_RST		19
-+#define MT7622_INFRA_TRNG_RST			21
-+#define MT7622_INFRA_SYSIRQ_RST			22
-+#define MT7622_INFRA_WED1_RST			25
-+
-+/* PERICFG Subsystem resets */
-+#define MT7622_PERI_UART0_SW_RST		0
-+#define MT7622_PERI_UART1_SW_RST		1
-+#define MT7622_PERI_UART2_SW_RST		2
-+#define MT7622_PERI_UART3_SW_RST		3
-+#define MT7622_PERI_UART4_SW_RST		4
-+#define MT7622_PERI_BTIF_SW_RST			6
-+#define MT7622_PERI_PWM_SW_RST			8
-+#define MT7622_PERI_AUXADC_SW_RST		10
-+#define MT7622_PERI_DMA_SW_RST			11
-+#define MT7622_PERI_IRTX_SW_RST			13
-+#define MT7622_PERI_NFI_SW_RST			14
-+#define MT7622_PERI_THERM_SW_RST		16
-+#define MT7622_PERI_MSDC0_SW_RST		19
-+#define MT7622_PERI_MSDC1_SW_RST		20
-+#define MT7622_PERI_I2C0_SW_RST			22
-+#define MT7622_PERI_I2C1_SW_RST			23
-+#define MT7622_PERI_I2C2_SW_RST			24
-+#define MT7622_PERI_SPI0_SW_RST			33
-+#define MT7622_PERI_SPI1_SW_RST			34
-+#define MT7622_PERI_FLASHIF_SW_RST		36
-+
-+/* TOPRGU resets */
-+#define MT7622_TOPRGU_INFRA_RST			0
-+#define MT7622_TOPRGU_ETHDMA_RST		1
-+#define MT7622_TOPRGU_DDRPHY_RST		6
-+#define MT7622_TOPRGU_INFRA_AO_RST		8
-+#define MT7622_TOPRGU_CONN_RST			9
-+#define MT7622_TOPRGU_APMIXED_RST		10
-+#define MT7622_TOPRGU_CONN_MCU_RST		12
-+
-+/* PCIe/SATA Subsystem resets */
-+#define MT7622_SATA_PHY_REG_RST			12
-+#define MT7622_SATA_PHY_SW_RST			13
-+#define MT7622_SATA_AXI_BUS_RST			15
-+#define MT7622_PCIE1_CORE_RST			19
-+#define MT7622_PCIE1_MMIO_RST			20
-+#define MT7622_PCIE1_HRST			21
-+#define MT7622_PCIE1_USER_RST			22
-+#define MT7622_PCIE1_PIPE_RST			23
-+#define MT7622_PCIE0_CORE_RST			27
-+#define MT7622_PCIE0_MMIO_RST			28
-+#define MT7622_PCIE0_HRST			29
-+#define MT7622_PCIE0_USER_RST			30
-+#define MT7622_PCIE0_PIPE_RST			31
-+
-+/* SSUSB Subsystem resets */
-+#define MT7622_SSUSB_PHY_PWR_RST		3
-+#define MT7622_SSUSB_MAC_PWR_RST		4
-+
-+/* ETHSYS Subsystem resets */
-+#define MT7622_ETHSYS_SYS_RST			0
-+#define MT7622_ETHSYS_MCM_RST			2
-+#define MT7622_ETHSYS_HSDMA_RST			5
-+#define MT7622_ETHSYS_FE_RST			6
-+#define MT7622_ETHSYS_GMAC_RST			23
-+#define MT7622_ETHSYS_EPHY_RST			24
-+#define MT7622_ETHSYS_CRYPTO_RST		29
-+#define MT7622_ETHSYS_PPE_RST			31
-+
-+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */

target/linux/mediatek/patches-4.14/0102-soc-mediatek-pwrap-fixup-warnings-from-coding-style.patch

@@ -1,71 +0,0 @@
-From c7cb4b7e750fc9a23cd80ef34ad4ef8a47f895d5 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Thu, 21 Sep 2017 16:26:57 +0800
-Subject: [PATCH 102/224] soc: mediatek: pwrap: fixup warnings from coding
- style
-
-fixup those warnings such as lines over 80 words and parenthesis
-alignment which would be complained by checkpatch.pl.
-
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- drivers/soc/mediatek/mtk-pmic-wrap.c | 20 +++++++++++++-------
- 1 file changed, 13 insertions(+), 7 deletions(-)
-
---- a/drivers/soc/mediatek/mtk-pmic-wrap.c
-+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -827,7 +827,8 @@ static int pwrap_init_cipher(struct pmic
- 	/* wait for cipher data ready@PMIC */
- 	ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
- 	if (ret) {
--		dev_err(wrp->dev, "timeout waiting for cipher data ready@PMIC\n");
-+		dev_err(wrp->dev,
-+			"timeout waiting for cipher data ready@PMIC\n");
- 		return ret;
- 	}
- 
-@@ -1159,23 +1160,27 @@ static int pwrap_probe(struct platform_d
- 		if (IS_ERR(wrp->bridge_base))
- 			return PTR_ERR(wrp->bridge_base);
- 
--		wrp->rstc_bridge = devm_reset_control_get(wrp->dev, "pwrap-bridge");
-+		wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
-+							  "pwrap-bridge");
- 		if (IS_ERR(wrp->rstc_bridge)) {
- 			ret = PTR_ERR(wrp->rstc_bridge);
--			dev_dbg(wrp->dev, "cannot get pwrap-bridge reset: %d\n", ret);
-+			dev_dbg(wrp->dev,
-+				"cannot get pwrap-bridge reset: %d\n", ret);
- 			return ret;
- 		}
- 	}
- 
- 	wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
- 	if (IS_ERR(wrp->clk_spi)) {
--		dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_spi));
-+		dev_dbg(wrp->dev, "failed to get clock: %ld\n",
-+			PTR_ERR(wrp->clk_spi));
- 		return PTR_ERR(wrp->clk_spi);
- 	}
- 
- 	wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
- 	if (IS_ERR(wrp->clk_wrap)) {
--		dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_wrap));
-+		dev_dbg(wrp->dev, "failed to get clock: %ld\n",
-+			PTR_ERR(wrp->clk_wrap));
- 		return PTR_ERR(wrp->clk_wrap);
- 	}
- 
-@@ -1220,8 +1225,9 @@ static int pwrap_probe(struct platform_d
- 	pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
- 
- 	irq = platform_get_irq(pdev, 0);
--	ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
--			"mt-pmic-pwrap", wrp);
-+	ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
-+			       IRQF_TRIGGER_HIGH,
-+			       "mt-pmic-pwrap", wrp);
- 	if (ret)
- 		goto err_out2;
- 

target/linux/mediatek/patches-4.14/0104-usb-mtu3-support-option-to-disable-usb3-ports.patch

@@ -1,108 +0,0 @@
-From 7a46c3488c48a0fbe313ed25c12af3fb3af48a01 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:38 +0800
-Subject: [PATCH 104/224] usb: mtu3: support option to disable usb3 ports
-
-Add support to disable specific usb3 ports, it's useful when
-usb3 phy is shared with PCIe or SATA, because we should disable
-the corresponding usb3 port if the phy is used by PCIe or SATA.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- drivers/usb/mtu3/mtu3.h      |  3 +++
- drivers/usb/mtu3/mtu3_host.c | 16 +++++++++++++---
- drivers/usb/mtu3/mtu3_plat.c |  8 ++++++--
- 3 files changed, 22 insertions(+), 5 deletions(-)
-
---- a/drivers/usb/mtu3/mtu3.h
-+++ b/drivers/usb/mtu3/mtu3.h
-@@ -210,6 +210,8 @@ struct otg_switch_mtk {
-  *		host only, device only or dual-role mode
-  * @u2_ports: number of usb2.0 host ports
-  * @u3_ports: number of usb3.0 host ports
-+ * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
-+ *		disable u3port0, bit1==1 to disable u3port1,... etc
-  * @dbgfs_root: only used when supports manual dual-role switch via debugfs
-  * @wakeup_en: it's true when supports remote wakeup in host mode
-  * @wk_deb_p0: port0's wakeup debounce clock
-@@ -232,6 +234,7 @@ struct ssusb_mtk {
- 	bool is_host;
- 	int u2_ports;
- 	int u3_ports;
-+	int u3p_dis_msk;
- 	struct dentry *dbgfs_root;
- 	/* usb wakeup for host mode */
- 	bool wakeup_en;
---- a/drivers/usb/mtu3/mtu3_host.c
-+++ b/drivers/usb/mtu3/mtu3_host.c
-@@ -151,6 +151,7 @@ int ssusb_host_enable(struct ssusb_mtk *
- 	void __iomem *ibase = ssusb->ippc_base;
- 	int num_u3p = ssusb->u3_ports;
- 	int num_u2p = ssusb->u2_ports;
-+	int u3_ports_disabed;
- 	u32 check_clk;
- 	u32 value;
- 	int i;
-@@ -158,8 +159,14 @@ int ssusb_host_enable(struct ssusb_mtk *
- 	/* power on host ip */
- 	mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
- 
--	/* power on and enable all u3 ports */
-+	/* power on and enable u3 ports except skipped ones */
-+	u3_ports_disabed = 0;
- 	for (i = 0; i < num_u3p; i++) {
-+		if ((0x1 << i) & ssusb->u3p_dis_msk) {
-+			u3_ports_disabed++;
-+			continue;
-+		}
-+
- 		value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
- 		value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
- 		value |= SSUSB_U3_PORT_HOST_SEL;
-@@ -175,7 +182,7 @@ int ssusb_host_enable(struct ssusb_mtk *
- 	}
- 
- 	check_clk = SSUSB_XHCI_RST_B_STS;
--	if (num_u3p)
-+	if (num_u3p > u3_ports_disabed)
- 		check_clk = SSUSB_U3_MAC_RST_B_STS;
- 
- 	return ssusb_check_clocks(ssusb, check_clk);
-@@ -190,8 +197,11 @@ int ssusb_host_disable(struct ssusb_mtk
- 	int ret;
- 	int i;
- 
--	/* power down and disable all u3 ports */
-+	/* power down and disable u3 ports except skipped ones */
- 	for (i = 0; i < num_u3p; i++) {
-+		if ((0x1 << i) & ssusb->u3p_dis_msk)
-+			continue;
-+
- 		value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
- 		value |= SSUSB_U3_PORT_PDN;
- 		value |= suspend ? 0 : SSUSB_U3_PORT_DIS;
---- a/drivers/usb/mtu3/mtu3_plat.c
-+++ b/drivers/usb/mtu3/mtu3_plat.c
-@@ -276,6 +276,10 @@ static int get_ssusb_rscs(struct platfor
- 	if (ret)
- 		return ret;
- 
-+	/* optional property, ignore the error if it does not exist */
-+	of_property_read_u32(node, "mediatek,u3p-dis-msk",
-+			     &ssusb->u3p_dis_msk);
-+
- 	if (ssusb->dr_mode != USB_DR_MODE_OTG)
- 		return 0;
- 
-@@ -304,8 +308,8 @@ static int get_ssusb_rscs(struct platfor
- 		}
- 	}
- 
--	dev_info(dev, "dr_mode: %d, is_u3_dr: %d\n",
--		ssusb->dr_mode, otg_sx->is_u3_drd);
-+	dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk:%x\n",
-+		ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk);
- 
- 	return 0;
- }

target/linux/mediatek/patches-4.14/0105-usb-mtu3-remove-dummy-wakeup-debounce-clocks.patch

@@ -1,119 +0,0 @@
-From 50005796f146351dc9c34bbf8898b305c562e964 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:39 +0800
-Subject: [PATCH 105/224] usb: mtu3: remove dummy wakeup debounce clocks
-
-The wakeup debounce clocks for each ports in fact are not
-needed, so remove them.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- drivers/usb/mtu3/mtu3.h      |  4 ----
- drivers/usb/mtu3/mtu3_host.c | 57 ++++----------------------------------------
- 2 files changed, 4 insertions(+), 57 deletions(-)
-
---- a/drivers/usb/mtu3/mtu3.h
-+++ b/drivers/usb/mtu3/mtu3.h
-@@ -214,8 +214,6 @@ struct otg_switch_mtk {
-  *		disable u3port0, bit1==1 to disable u3port1,... etc
-  * @dbgfs_root: only used when supports manual dual-role switch via debugfs
-  * @wakeup_en: it's true when supports remote wakeup in host mode
-- * @wk_deb_p0: port0's wakeup debounce clock
-- * @wk_deb_p1: it's optional, and depends on port1 is supported or not
-  */
- struct ssusb_mtk {
- 	struct device *dev;
-@@ -238,8 +236,6 @@ struct ssusb_mtk {
- 	struct dentry *dbgfs_root;
- 	/* usb wakeup for host mode */
- 	bool wakeup_en;
--	struct clk *wk_deb_p0;
--	struct clk *wk_deb_p1;
- 	struct regmap *pericfg;
- };
- 
---- a/drivers/usb/mtu3/mtu3_host.c
-+++ b/drivers/usb/mtu3/mtu3_host.c
-@@ -79,20 +79,6 @@ int ssusb_wakeup_of_property_parse(struc
- 	if (!ssusb->wakeup_en)
- 		return 0;
- 
--	ssusb->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
--	if (IS_ERR(ssusb->wk_deb_p0)) {
--		dev_err(dev, "fail to get wakeup_deb_p0\n");
--		return PTR_ERR(ssusb->wk_deb_p0);
--	}
--
--	if (of_property_read_bool(dn, "wakeup_deb_p1")) {
--		ssusb->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
--		if (IS_ERR(ssusb->wk_deb_p1)) {
--			dev_err(dev, "fail to get wakeup_deb_p1\n");
--			return PTR_ERR(ssusb->wk_deb_p1);
--		}
--	}
--
- 	ssusb->pericfg = syscon_regmap_lookup_by_phandle(dn,
- 						"mediatek,syscon-wakeup");
- 	if (IS_ERR(ssusb->pericfg)) {
-@@ -103,36 +89,6 @@ int ssusb_wakeup_of_property_parse(struc
- 	return 0;
- }
- 
--static int ssusb_wakeup_clks_enable(struct ssusb_mtk *ssusb)
--{
--	int ret;
--
--	ret = clk_prepare_enable(ssusb->wk_deb_p0);
--	if (ret) {
--		dev_err(ssusb->dev, "failed to enable wk_deb_p0\n");
--		goto usb_p0_err;
--	}
--
--	ret = clk_prepare_enable(ssusb->wk_deb_p1);
--	if (ret) {
--		dev_err(ssusb->dev, "failed to enable wk_deb_p1\n");
--		goto usb_p1_err;
--	}
--
--	return 0;
--
--usb_p1_err:
--	clk_disable_unprepare(ssusb->wk_deb_p0);
--usb_p0_err:
--	return -EINVAL;
--}
--
--static void ssusb_wakeup_clks_disable(struct ssusb_mtk *ssusb)
--{
--	clk_disable_unprepare(ssusb->wk_deb_p1);
--	clk_disable_unprepare(ssusb->wk_deb_p0);
--}
--
- static void host_ports_num_get(struct ssusb_mtk *ssusb)
- {
- 	u32 xhci_cap;
-@@ -286,19 +242,14 @@ void ssusb_host_exit(struct ssusb_mtk *s
- 
- int ssusb_wakeup_enable(struct ssusb_mtk *ssusb)
- {
--	int ret = 0;
--
--	if (ssusb->wakeup_en) {
--		ret = ssusb_wakeup_clks_enable(ssusb);
-+	if (ssusb->wakeup_en)
- 		ssusb_wakeup_ip_sleep_en(ssusb);
--	}
--	return ret;
-+
-+	return 0;
- }
- 
- void ssusb_wakeup_disable(struct ssusb_mtk *ssusb)
- {
--	if (ssusb->wakeup_en) {
-+	if (ssusb->wakeup_en)
- 		ssusb_wakeup_ip_sleep_dis(ssusb);
--		ssusb_wakeup_clks_disable(ssusb);
--	}
- }

target/linux/mediatek/patches-4.14/0106-usb-mtu3-add-optional-mcu-and-dma-bus-clocks.patch

@@ -1,227 +0,0 @@
-From 677805f6d83524717b46b3cde74aa455dbf6299f Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:40 +0800
-Subject: [PATCH 106/224] usb: mtu3: add optional mcu and dma bus clocks
-
-There are mcu_bus and dma_bus clocks needed to be turned on/off by
-driver on some SoCs, so add them as optional ones
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- drivers/usb/mtu3/mtu3.h      |   5 ++
- drivers/usb/mtu3/mtu3_plat.c | 121 +++++++++++++++++++++++++++++--------------
- 2 files changed, 86 insertions(+), 40 deletions(-)
-
---- a/drivers/usb/mtu3/mtu3.h
-+++ b/drivers/usb/mtu3/mtu3.h
-@@ -206,6 +206,9 @@ struct otg_switch_mtk {
-  * @ippc_base: register base address of IP Power and Clock interface (IPPC)
-  * @vusb33: usb3.3V shared by device/host IP
-  * @sys_clk: system clock of mtu3, shared by device/host IP
-+ * @ref_clk: reference clock
-+ * @mcu_clk: mcu_bus_ck clock for AHB bus etc
-+ * @dma_clk: dma_bus_ck clock for AXI bus etc
-  * @dr_mode: works in which mode:
-  *		host only, device only or dual-role mode
-  * @u2_ports: number of usb2.0 host ports
-@@ -226,6 +229,8 @@ struct ssusb_mtk {
- 	struct regulator *vusb33;
- 	struct clk *sys_clk;
- 	struct clk *ref_clk;
-+	struct clk *mcu_clk;
-+	struct clk *dma_clk;
- 	/* otg */
- 	struct otg_switch_mtk otg_switch;
- 	enum usb_dr_mode dr_mode;
---- a/drivers/usb/mtu3/mtu3_plat.c
-+++ b/drivers/usb/mtu3/mtu3_plat.c
-@@ -110,15 +110,9 @@ static void ssusb_phy_power_off(struct s
- 		phy_power_off(ssusb->phys[i]);
- }
- 
--static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
-+static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
- {
--	int ret = 0;
--
--	ret = regulator_enable(ssusb->vusb33);
--	if (ret) {
--		dev_err(ssusb->dev, "failed to enable vusb33\n");
--		goto vusb33_err;
--	}
-+	int ret;
- 
- 	ret = clk_prepare_enable(ssusb->sys_clk);
- 	if (ret) {
-@@ -132,6 +126,52 @@ static int ssusb_rscs_init(struct ssusb_
- 		goto ref_clk_err;
- 	}
- 
-+	ret = clk_prepare_enable(ssusb->mcu_clk);
-+	if (ret) {
-+		dev_err(ssusb->dev, "failed to enable mcu_clk\n");
-+		goto mcu_clk_err;
-+	}
-+
-+	ret = clk_prepare_enable(ssusb->dma_clk);
-+	if (ret) {
-+		dev_err(ssusb->dev, "failed to enable dma_clk\n");
-+		goto dma_clk_err;
-+	}
-+
-+	return 0;
-+
-+dma_clk_err:
-+	clk_disable_unprepare(ssusb->mcu_clk);
-+mcu_clk_err:
-+	clk_disable_unprepare(ssusb->ref_clk);
-+ref_clk_err:
-+	clk_disable_unprepare(ssusb->sys_clk);
-+sys_clk_err:
-+	return ret;
-+}
-+
-+static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
-+{
-+	clk_disable_unprepare(ssusb->dma_clk);
-+	clk_disable_unprepare(ssusb->mcu_clk);
-+	clk_disable_unprepare(ssusb->ref_clk);
-+	clk_disable_unprepare(ssusb->sys_clk);
-+}
-+
-+static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
-+{
-+	int ret = 0;
-+
-+	ret = regulator_enable(ssusb->vusb33);
-+	if (ret) {
-+		dev_err(ssusb->dev, "failed to enable vusb33\n");
-+		goto vusb33_err;
-+	}
-+
-+	ret = ssusb_clks_enable(ssusb);
-+	if (ret)
-+		goto clks_err;
-+
- 	ret = ssusb_phy_init(ssusb);
- 	if (ret) {
- 		dev_err(ssusb->dev, "failed to init phy\n");
-@@ -149,20 +189,16 @@ static int ssusb_rscs_init(struct ssusb_
- phy_err:
- 	ssusb_phy_exit(ssusb);
- phy_init_err:
--	clk_disable_unprepare(ssusb->ref_clk);
--ref_clk_err:
--	clk_disable_unprepare(ssusb->sys_clk);
--sys_clk_err:
-+	ssusb_clks_disable(ssusb);
-+clks_err:
- 	regulator_disable(ssusb->vusb33);
- vusb33_err:
--
- 	return ret;
- }
- 
- static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
- {
--	clk_disable_unprepare(ssusb->sys_clk);
--	clk_disable_unprepare(ssusb->ref_clk);
-+	ssusb_clks_disable(ssusb);
- 	regulator_disable(ssusb->vusb33);
- 	ssusb_phy_power_off(ssusb);
- 	ssusb_phy_exit(ssusb);
-@@ -203,6 +239,19 @@ static int get_iddig_pinctrl(struct ssus
- 	return 0;
- }
- 
-+/* ignore the error if the clock does not exist */
-+static struct clk *get_optional_clk(struct device *dev, const char *id)
-+{
-+	struct clk *opt_clk;
-+
-+	opt_clk = devm_clk_get(dev, id);
-+	/* ignore error number except EPROBE_DEFER */
-+	if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
-+		opt_clk = NULL;
-+
-+	return opt_clk;
-+}
-+
- static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
- {
- 	struct device_node *node = pdev->dev.of_node;
-@@ -225,18 +274,17 @@ static int get_ssusb_rscs(struct platfor
- 		return PTR_ERR(ssusb->sys_clk);
- 	}
- 
--	/*
--	 * reference clock is usually a "fixed-clock", make it optional
--	 * for backward compatibility and ignore the error if it does
--	 * not exist.
--	 */
--	ssusb->ref_clk = devm_clk_get(dev, "ref_ck");
--	if (IS_ERR(ssusb->ref_clk)) {
--		if (PTR_ERR(ssusb->ref_clk) == -EPROBE_DEFER)
--			return -EPROBE_DEFER;
--
--		ssusb->ref_clk = NULL;
--	}
-+	ssusb->ref_clk = get_optional_clk(dev, "ref_ck");
-+	if (IS_ERR(ssusb->ref_clk))
-+		return PTR_ERR(ssusb->ref_clk);
-+
-+	ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck");
-+	if (IS_ERR(ssusb->mcu_clk))
-+		return PTR_ERR(ssusb->mcu_clk);
-+
-+	ssusb->dma_clk = get_optional_clk(dev, "dma_ck");
-+	if (IS_ERR(ssusb->dma_clk))
-+		return PTR_ERR(ssusb->dma_clk);
- 
- 	ssusb->num_phys = of_count_phandle_with_args(node,
- 			"phys", "#phy-cells");
-@@ -451,8 +499,7 @@ static int __maybe_unused mtu3_suspend(s
- 
- 	ssusb_host_disable(ssusb, true);
- 	ssusb_phy_power_off(ssusb);
--	clk_disable_unprepare(ssusb->sys_clk);
--	clk_disable_unprepare(ssusb->ref_clk);
-+	ssusb_clks_disable(ssusb);
- 	ssusb_wakeup_enable(ssusb);
- 
- 	return 0;
-@@ -470,27 +517,21 @@ static int __maybe_unused mtu3_resume(st
- 		return 0;
- 
- 	ssusb_wakeup_disable(ssusb);
--	ret = clk_prepare_enable(ssusb->sys_clk);
--	if (ret)
--		goto err_sys_clk;
--
--	ret = clk_prepare_enable(ssusb->ref_clk);
-+	ret = ssusb_clks_enable(ssusb);
- 	if (ret)
--		goto err_ref_clk;
-+		goto clks_err;
- 
- 	ret = ssusb_phy_power_on(ssusb);
- 	if (ret)
--		goto err_power_on;
-+		goto phy_err;
- 
- 	ssusb_host_enable(ssusb);
- 
- 	return 0;
- 
--err_power_on:
--	clk_disable_unprepare(ssusb->ref_clk);
--err_ref_clk:
--	clk_disable_unprepare(ssusb->sys_clk);
--err_sys_clk:
-+phy_err:
-+	ssusb_clks_disable(ssusb);
-+clks_err:
- 	return ret;
- }
- 

target/linux/mediatek/patches-4.14/0107-usb-mtu3-support-36-bit-DMA-address.patch

@@ -1,362 +0,0 @@
-From d366bf086a61b7a895d8819a3c1349b9c6b8e40f Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:41 +0800
-Subject: [PATCH 107/224] usb: mtu3: support 36-bit DMA address
-
-add support for 36-bit DMA address
-
-[ Felipe Balbi: fix printk format for dma_addr_t ]
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- drivers/usb/mtu3/mtu3.h         |  17 ++++++-
- drivers/usb/mtu3/mtu3_core.c    |  34 +++++++++++++-
- drivers/usb/mtu3/mtu3_hw_regs.h |  10 ++++
- drivers/usb/mtu3/mtu3_qmu.c     | 102 +++++++++++++++++++++++++++++++++-------
- 4 files changed, 142 insertions(+), 21 deletions(-)
-
---- a/drivers/usb/mtu3/mtu3.h
-+++ b/drivers/usb/mtu3/mtu3.h
-@@ -46,6 +46,9 @@ struct mtu3_request;
- #define	MU3D_EP_RXCR1(epnum)	(U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
- #define	MU3D_EP_RXCR2(epnum)	(U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
- 
-+#define USB_QMU_TQHIAR(epnum)	(U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
-+#define USB_QMU_RQHIAR(epnum)	(U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
-+
- #define USB_QMU_RQCSR(epnum)	(U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
- #define USB_QMU_RQSAR(epnum)	(U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
- #define USB_QMU_RQCPR(epnum)	(U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
-@@ -138,23 +141,33 @@ struct mtu3_fifo_info {
-  *	Checksum value is calculated over the 16 bytes of the GPD by default;
-  * @data_buf_len (RX ONLY): This value indicates the length of
-  *	the assigned data buffer
-+ * @tx_ext_addr (TX ONLY): [3:0] are 4 extension bits of @buffer,
-+ *	[7:4] are 4 extension bits of @next_gpd
-  * @next_gpd: Physical address of the next GPD
-  * @buffer: Physical address of the data buffer
-  * @buf_len:
-  *	(TX): This value indicates the length of the assigned data buffer
-  *	(RX): The total length of data received
-  * @ext_len: reserved
-+ * @rx_ext_addr(RX ONLY): [3:0] are 4 extension bits of @buffer,
-+ *	[7:4] are 4 extension bits of @next_gpd
-  * @ext_flag:
-  *	bit5 (TX ONLY): Zero Length Packet (ZLP),
-  */
- struct qmu_gpd {
- 	__u8 flag;
- 	__u8 chksum;
--	__le16 data_buf_len;
-+	union {
-+		__le16 data_buf_len;
-+		__le16 tx_ext_addr;
-+	};
- 	__le32 next_gpd;
- 	__le32 buffer;
- 	__le16 buf_len;
--	__u8 ext_len;
-+	union {
-+		__u8 ext_len;
-+		__u8 rx_ext_addr;
-+	};
- 	__u8 ext_flag;
- } __packed;
- 
---- a/drivers/usb/mtu3/mtu3_core.c
-+++ b/drivers/usb/mtu3/mtu3_core.c
-@@ -17,6 +17,7 @@
-  *
-  */
- 
-+#include <linux/dma-mapping.h>
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/of_address.h>
-@@ -761,7 +762,31 @@ static void mtu3_hw_exit(struct mtu3 *mt
- 	mtu3_mem_free(mtu);
- }
- 
--/*-------------------------------------------------------------------------*/
-+/**
-+ * we set 32-bit DMA mask by default, here check whether the controller
-+ * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
-+ */
-+static int mtu3_set_dma_mask(struct mtu3 *mtu)
-+{
-+	struct device *dev = mtu->dev;
-+	bool is_36bit = false;
-+	int ret = 0;
-+	u32 value;
-+
-+	value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
-+	if (value & DMA_ADDR_36BIT) {
-+		is_36bit = true;
-+		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
-+		/* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
-+		if (ret) {
-+			is_36bit = false;
-+			ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
-+		}
-+	}
-+	dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
-+
-+	return ret;
-+}
- 
- int ssusb_gadget_init(struct ssusb_mtk *ssusb)
- {
-@@ -822,6 +847,12 @@ int ssusb_gadget_init(struct ssusb_mtk *
- 		return ret;
- 	}
- 
-+	ret = mtu3_set_dma_mask(mtu);
-+	if (ret) {
-+		dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
-+		goto dma_mask_err;
-+	}
-+
- 	ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
- 	if (ret) {
- 		dev_err(dev, "request irq %d failed!\n", mtu->irq);
-@@ -847,6 +878,7 @@ int ssusb_gadget_init(struct ssusb_mtk *
- gadget_err:
- 	device_init_wakeup(dev, false);
- 
-+dma_mask_err:
- irq_err:
- 	mtu3_hw_exit(mtu);
- 	ssusb->u3d = NULL;
---- a/drivers/usb/mtu3/mtu3_hw_regs.h
-+++ b/drivers/usb/mtu3/mtu3_hw_regs.h
-@@ -58,6 +58,8 @@
- #define U3D_QCR1		(SSUSB_DEV_BASE + 0x0404)
- #define U3D_QCR2		(SSUSB_DEV_BASE + 0x0408)
- #define U3D_QCR3		(SSUSB_DEV_BASE + 0x040C)
-+#define U3D_TXQHIAR1		(SSUSB_DEV_BASE + 0x0484)
-+#define U3D_RXQHIAR1		(SSUSB_DEV_BASE + 0x04C4)
- 
- #define U3D_TXQCSR1		(SSUSB_DEV_BASE + 0x0510)
- #define U3D_TXQSAR1		(SSUSB_DEV_BASE + 0x0514)
-@@ -189,6 +191,13 @@
- #define QMU_RX_COZ(x)		(BIT(16) << (x))
- #define QMU_RX_ZLP(x)		(BIT(0) << (x))
- 
-+/* U3D_TXQHIAR1 */
-+/* U3D_RXQHIAR1 */
-+#define QMU_LAST_DONE_PTR_HI(x)	(((x) >> 16) & 0xf)
-+#define QMU_CUR_GPD_ADDR_HI(x)	(((x) >> 8) & 0xf)
-+#define QMU_START_ADDR_HI_MSK	GENMASK(3, 0)
-+#define QMU_START_ADDR_HI(x)	(((x) & 0xf) << 0)
-+
- /* U3D_TXQCSR1 */
- /* U3D_RXQCSR1 */
- #define QMU_Q_ACTIVE		BIT(15)
-@@ -225,6 +234,7 @@
- #define CAP_TX_EP_NUM(x)	((x) & 0x1f)
- 
- /* U3D_MISC_CTRL */
-+#define DMA_ADDR_36BIT		BIT(31)
- #define VBUS_ON			BIT(1)
- #define VBUS_FRC_EN		BIT(0)
- 
---- a/drivers/usb/mtu3/mtu3_qmu.c
-+++ b/drivers/usb/mtu3/mtu3_qmu.c
-@@ -40,7 +40,58 @@
- #define GPD_FLAGS_IOC	BIT(7)
- 
- #define GPD_EXT_FLAG_ZLP	BIT(5)
-+#define GPD_EXT_NGP(x)		(((x) & 0xf) << 4)
-+#define GPD_EXT_BUF(x)		(((x) & 0xf) << 0)
- 
-+#define HILO_GEN64(hi, lo) (((u64)(hi) << 32) + (lo))
-+#define HILO_DMA(hi, lo)	\
-+	((dma_addr_t)HILO_GEN64((le32_to_cpu(hi)), (le32_to_cpu(lo))))
-+
-+static dma_addr_t read_txq_cur_addr(void __iomem *mbase, u8 epnum)
-+{
-+	u32 txcpr;
-+	u32 txhiar;
-+
-+	txcpr = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
-+	txhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
-+
-+	return HILO_DMA(QMU_CUR_GPD_ADDR_HI(txhiar), txcpr);
-+}
-+
-+static dma_addr_t read_rxq_cur_addr(void __iomem *mbase, u8 epnum)
-+{
-+	u32 rxcpr;
-+	u32 rxhiar;
-+
-+	rxcpr = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
-+	rxhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
-+
-+	return HILO_DMA(QMU_CUR_GPD_ADDR_HI(rxhiar), rxcpr);
-+}
-+
-+static void write_txq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
-+{
-+	u32 tqhiar;
-+
-+	mtu3_writel(mbase, USB_QMU_TQSAR(epnum),
-+		    cpu_to_le32(lower_32_bits(dma)));
-+	tqhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
-+	tqhiar &= ~QMU_START_ADDR_HI_MSK;
-+	tqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
-+	mtu3_writel(mbase, USB_QMU_TQHIAR(epnum), tqhiar);
-+}
-+
-+static void write_rxq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
-+{
-+	u32 rqhiar;
-+
-+	mtu3_writel(mbase, USB_QMU_RQSAR(epnum),
-+		    cpu_to_le32(lower_32_bits(dma)));
-+	rqhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
-+	rqhiar &= ~QMU_START_ADDR_HI_MSK;
-+	rqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
-+	mtu3_writel(mbase, USB_QMU_RQHIAR(epnum), rqhiar);
-+}
- 
- static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring,
- 		dma_addr_t dma_addr)
-@@ -193,21 +244,27 @@ static int mtu3_prepare_tx_gpd(struct mt
- 	struct mtu3_gpd_ring *ring = &mep->gpd_ring;
- 	struct qmu_gpd *gpd = ring->enqueue;
- 	struct usb_request *req = &mreq->request;
-+	dma_addr_t enq_dma;
-+	u16 ext_addr;
- 
- 	/* set all fields to zero as default value */
- 	memset(gpd, 0, sizeof(*gpd));
- 
--	gpd->buffer = cpu_to_le32((u32)req->dma);
-+	gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
-+	ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma));
- 	gpd->buf_len = cpu_to_le16(req->length);
- 	gpd->flag |= GPD_FLAGS_IOC;
- 
- 	/* get the next GPD */
- 	enq = advance_enq_gpd(ring);
--	dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p\n",
--		mep->epnum, gpd, enq);
-+	enq_dma = gpd_virt_to_dma(ring, enq);
-+	dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
-+		mep->epnum, gpd, enq, enq_dma);
- 
- 	enq->flag &= ~GPD_FLAGS_HWO;
--	gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
-+	gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
-+	ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma));
-+	gpd->tx_ext_addr = cpu_to_le16(ext_addr);
- 
- 	if (req->zero)
- 		gpd->ext_flag |= GPD_EXT_FLAG_ZLP;
-@@ -226,21 +283,27 @@ static int mtu3_prepare_rx_gpd(struct mt
- 	struct mtu3_gpd_ring *ring = &mep->gpd_ring;
- 	struct qmu_gpd *gpd = ring->enqueue;
- 	struct usb_request *req = &mreq->request;
-+	dma_addr_t enq_dma;
-+	u16 ext_addr;
- 
- 	/* set all fields to zero as default value */
- 	memset(gpd, 0, sizeof(*gpd));
- 
--	gpd->buffer = cpu_to_le32((u32)req->dma);
-+	gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
-+	ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma));
- 	gpd->data_buf_len = cpu_to_le16(req->length);
- 	gpd->flag |= GPD_FLAGS_IOC;
- 
- 	/* get the next GPD */
- 	enq = advance_enq_gpd(ring);
--	dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p\n",
--		mep->epnum, gpd, enq);
-+	enq_dma = gpd_virt_to_dma(ring, enq);
-+	dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
-+		mep->epnum, gpd, enq, enq_dma);
- 
- 	enq->flag &= ~GPD_FLAGS_HWO;
--	gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
-+	gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
-+	ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma));
-+	gpd->rx_ext_addr = cpu_to_le16(ext_addr);
- 	gpd->chksum = qmu_calc_checksum((u8 *)gpd);
- 	gpd->flag |= GPD_FLAGS_HWO;
- 
-@@ -267,8 +330,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep)
- 
- 	if (mep->is_in) {
- 		/* set QMU start address */
--		mtu3_writel(mbase, USB_QMU_TQSAR(mep->epnum), ring->dma);
--		mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
-+		write_txq_start_addr(mbase, epnum, ring->dma);
-+		mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN);
- 		mtu3_setbits(mbase, U3D_QCR0, QMU_TX_CS_EN(epnum));
- 		/* send zero length packet according to ZLP flag in GPD */
- 		mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum));
-@@ -282,8 +345,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep)
- 		mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START);
- 
- 	} else {
--		mtu3_writel(mbase, USB_QMU_RQSAR(mep->epnum), ring->dma);
--		mtu3_setbits(mbase, MU3D_EP_RXCR0(mep->epnum), RX_DMAREQEN);
-+		write_rxq_start_addr(mbase, epnum, ring->dma);
-+		mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN);
- 		mtu3_setbits(mbase, U3D_QCR0, QMU_RX_CS_EN(epnum));
- 		/* don't expect ZLP */
- 		mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum));
-@@ -353,9 +416,9 @@ static void qmu_tx_zlp_error_handler(str
- 	struct mtu3_gpd_ring *ring = &mep->gpd_ring;
- 	void __iomem *mbase = mtu->mac_base;
- 	struct qmu_gpd *gpd_current = NULL;
--	dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
- 	struct usb_request *req = NULL;
- 	struct mtu3_request *mreq;
-+	dma_addr_t cur_gpd_dma;
- 	u32 txcsr = 0;
- 	int ret;
- 
-@@ -365,7 +428,8 @@ static void qmu_tx_zlp_error_handler(str
- 	else
- 		return;
- 
--	gpd_current = gpd_dma_to_virt(ring, gpd_dma);
-+	cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
-+	gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
- 
- 	if (le16_to_cpu(gpd_current->buf_len) != 0) {
- 		dev_err(mtu->dev, "TX EP%d buffer length error(!=0)\n", epnum);
-@@ -408,12 +472,13 @@ static void qmu_done_tx(struct mtu3 *mtu
- 	void __iomem *mbase = mtu->mac_base;
- 	struct qmu_gpd *gpd = ring->dequeue;
- 	struct qmu_gpd *gpd_current = NULL;
--	dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
- 	struct usb_request *request = NULL;
- 	struct mtu3_request *mreq;
-+	dma_addr_t cur_gpd_dma;
- 
- 	/*transfer phy address got from QMU register to virtual address */
--	gpd_current = gpd_dma_to_virt(ring, gpd_dma);
-+	cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
-+	gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
- 
- 	dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
- 		__func__, epnum, gpd, gpd_current, ring->enqueue);
-@@ -446,11 +511,12 @@ static void qmu_done_rx(struct mtu3 *mtu
- 	void __iomem *mbase = mtu->mac_base;
- 	struct qmu_gpd *gpd = ring->dequeue;
- 	struct qmu_gpd *gpd_current = NULL;
--	dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
- 	struct usb_request *req = NULL;
- 	struct mtu3_request *mreq;
-+	dma_addr_t cur_gpd_dma;
- 
--	gpd_current = gpd_dma_to_virt(ring, gpd_dma);
-+	cur_gpd_dma = read_rxq_cur_addr(mbase, epnum);
-+	gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
- 
- 	dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
- 		__func__, epnum, gpd, gpd_current, ring->enqueue);

target/linux/mediatek/patches-4.14/0108-usb-mtu3-use-FORCE-RG_IDDIG-to-implement-manual-DRD-.patch

@@ -1,274 +0,0 @@
-From 6c4995c9a8ba8841ba640201636954c84f494587 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:42 +0800
-Subject: [PATCH 108/224] usb: mtu3: use FORCE/RG_IDDIG to implement manual DRD
- switch
-
-In order to keep manual DRD switch independent on IDDIG interrupt,
-make use of FORCE/RG_IDDIG instead of IDDIG EINT interrupt to
-implement manual DRD switch function.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- drivers/usb/mtu3/mtu3.h         | 18 ++++++++----
- drivers/usb/mtu3/mtu3_dr.c      | 61 ++++++++++++++++++++++++++++++-----------
- drivers/usb/mtu3/mtu3_dr.h      |  6 ++++
- drivers/usb/mtu3/mtu3_host.c    |  5 ++++
- drivers/usb/mtu3/mtu3_hw_regs.h |  2 ++
- drivers/usb/mtu3/mtu3_plat.c    | 38 ++-----------------------
- 6 files changed, 74 insertions(+), 56 deletions(-)
-
---- a/drivers/usb/mtu3/mtu3.h
-+++ b/drivers/usb/mtu3/mtu3.h
-@@ -115,6 +115,19 @@ enum mtu3_g_ep0_state {
- };
- 
- /**
-+ * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode
-+ *		by IDPIN signal.
-+ * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
-+ *		IDPIN signal.
-+ * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
-+ */
-+enum mtu3_dr_force_mode {
-+	MTU3_DR_FORCE_NONE = 0,
-+	MTU3_DR_FORCE_HOST,
-+	MTU3_DR_FORCE_DEVICE,
-+};
-+
-+/**
-  * @base: the base address of fifo
-  * @limit: the bitmap size in bits
-  * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
-@@ -196,7 +209,6 @@ struct mtu3_gpd_ring {
- *		xHCI driver initialization, it's necessary for system bootup
- *		as device.
- * @is_u3_drd: whether port0 supports usb3.0 dual-role device or not
--* @id_*: used to maually switch between host and device modes by idpin
- * @manual_drd_enabled: it's true when supports dual-role device by debugfs
- *		to switch host/device modes depending on user input.
- */
-@@ -207,10 +219,6 @@ struct otg_switch_mtk {
- 	struct notifier_block id_nb;
- 	struct delayed_work extcon_reg_dwork;
- 	bool is_u3_drd;
--	/* dual-role switch by debugfs */
--	struct pinctrl *id_pinctrl;
--	struct pinctrl_state *id_float;
--	struct pinctrl_state *id_ground;
- 	bool manual_drd_enabled;
- };
- 
---- a/drivers/usb/mtu3/mtu3_dr.c
-+++ b/drivers/usb/mtu3/mtu3_dr.c
-@@ -261,21 +261,22 @@ static void extcon_register_dwork(struct
-  * depending on user input.
-  * This is useful in special cases, such as uses TYPE-A receptacle but also
-  * wants to support dual-role mode.
-- * It generates cable state changes by pulling up/down IDPIN and
-- * notifies driver to switch mode by "extcon-usb-gpio".
-- * NOTE: when use MICRO receptacle, should not enable this interface.
-  */
- static void ssusb_mode_manual_switch(struct ssusb_mtk *ssusb, int to_host)
- {
- 	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
- 
--	if (to_host)
--		pinctrl_select_state(otg_sx->id_pinctrl, otg_sx->id_ground);
--	else
--		pinctrl_select_state(otg_sx->id_pinctrl, otg_sx->id_float);
-+	if (to_host) {
-+		ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
-+		ssusb_set_mailbox(otg_sx, MTU3_VBUS_OFF);
-+		ssusb_set_mailbox(otg_sx, MTU3_ID_GROUND);
-+	} else {
-+		ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_DEVICE);
-+		ssusb_set_mailbox(otg_sx, MTU3_ID_FLOAT);
-+		ssusb_set_mailbox(otg_sx, MTU3_VBUS_VALID);
-+	}
- }
- 
--
- static int ssusb_mode_show(struct seq_file *sf, void *unused)
- {
- 	struct ssusb_mtk *ssusb = sf->private;
-@@ -388,17 +389,45 @@ static void ssusb_debugfs_exit(struct ss
- 	debugfs_remove_recursive(ssusb->dbgfs_root);
- }
- 
-+void ssusb_set_force_mode(struct ssusb_mtk *ssusb,
-+			  enum mtu3_dr_force_mode mode)
-+{
-+	u32 value;
-+
-+	value = mtu3_readl(ssusb->ippc_base, SSUSB_U2_CTRL(0));
-+	switch (mode) {
-+	case MTU3_DR_FORCE_DEVICE:
-+		value |= SSUSB_U2_PORT_FORCE_IDDIG | SSUSB_U2_PORT_RG_IDDIG;
-+		break;
-+	case MTU3_DR_FORCE_HOST:
-+		value |= SSUSB_U2_PORT_FORCE_IDDIG;
-+		value &= ~SSUSB_U2_PORT_RG_IDDIG;
-+		break;
-+	case MTU3_DR_FORCE_NONE:
-+		value &= ~(SSUSB_U2_PORT_FORCE_IDDIG | SSUSB_U2_PORT_RG_IDDIG);
-+		break;
-+	default:
-+		return;
-+	}
-+	mtu3_writel(ssusb->ippc_base, SSUSB_U2_CTRL(0), value);
-+}
-+
- int ssusb_otg_switch_init(struct ssusb_mtk *ssusb)
- {
- 	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
- 
--	INIT_DELAYED_WORK(&otg_sx->extcon_reg_dwork, extcon_register_dwork);
--
--	if (otg_sx->manual_drd_enabled)
-+	if (otg_sx->manual_drd_enabled) {
- 		ssusb_debugfs_init(ssusb);
-+	} else {
-+		INIT_DELAYED_WORK(&otg_sx->extcon_reg_dwork,
-+				  extcon_register_dwork);
- 
--	/* It is enough to delay 1s for waiting for host initialization */
--	schedule_delayed_work(&otg_sx->extcon_reg_dwork, HZ);
-+		/*
-+		 * It is enough to delay 1s for waiting for
-+		 * host initialization
-+		 */
-+		schedule_delayed_work(&otg_sx->extcon_reg_dwork, HZ);
-+	}
- 
- 	return 0;
- }
-@@ -407,8 +436,8 @@ void ssusb_otg_switch_exit(struct ssusb_
- {
- 	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
- 
--	cancel_delayed_work(&otg_sx->extcon_reg_dwork);
--
- 	if (otg_sx->manual_drd_enabled)
- 		ssusb_debugfs_exit(ssusb);
-+	else
-+		cancel_delayed_work(&otg_sx->extcon_reg_dwork);
- }
---- a/drivers/usb/mtu3/mtu3_dr.h
-+++ b/drivers/usb/mtu3/mtu3_dr.h
-@@ -87,6 +87,8 @@ static inline void ssusb_gadget_exit(str
- int ssusb_otg_switch_init(struct ssusb_mtk *ssusb);
- void ssusb_otg_switch_exit(struct ssusb_mtk *ssusb);
- int ssusb_set_vbus(struct otg_switch_mtk *otg_sx, int is_on);
-+void ssusb_set_force_mode(struct ssusb_mtk *ssusb,
-+			  enum mtu3_dr_force_mode mode);
- 
- #else
- 
-@@ -103,6 +105,10 @@ static inline int ssusb_set_vbus(struct
- 	return 0;
- }
- 
-+static inline void
-+ssusb_set_force_mode(struct ssusb_mtk *ssusb, enum mtu3_dr_force_mode mode)
-+{}
-+
- #endif
- 
- #endif		/* _MTU3_DR_H_ */
---- a/drivers/usb/mtu3/mtu3_host.c
-+++ b/drivers/usb/mtu3/mtu3_host.c
-@@ -189,6 +189,8 @@ int ssusb_host_disable(struct ssusb_mtk
- 
- static void ssusb_host_setup(struct ssusb_mtk *ssusb)
- {
-+	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
-+
- 	host_ports_num_get(ssusb);
- 
- 	/*
-@@ -197,6 +199,9 @@ static void ssusb_host_setup(struct ssus
- 	 */
- 	ssusb_host_enable(ssusb);
- 
-+	if (otg_sx->manual_drd_enabled)
-+		ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
-+
- 	/* if port0 supports dual-role, works as host mode by default */
- 	ssusb_set_vbus(&ssusb->otg_switch, 1);
- }
---- a/drivers/usb/mtu3/mtu3_hw_regs.h
-+++ b/drivers/usb/mtu3/mtu3_hw_regs.h
-@@ -472,6 +472,8 @@
- #define SSUSB_U3_PORT_DIS		BIT(0)
- 
- /* U3D_SSUSB_U2_CTRL_0P */
-+#define SSUSB_U2_PORT_RG_IDDIG		BIT(12)
-+#define SSUSB_U2_PORT_FORCE_IDDIG	BIT(11)
- #define SSUSB_U2_PORT_VBUSVALID	BIT(9)
- #define SSUSB_U2_PORT_OTG_SEL		BIT(7)
- #define SSUSB_U2_PORT_HOST		BIT(2)
---- a/drivers/usb/mtu3/mtu3_plat.c
-+++ b/drivers/usb/mtu3/mtu3_plat.c
-@@ -21,7 +21,6 @@
- #include <linux/module.h>
- #include <linux/of_address.h>
- #include <linux/of_irq.h>
--#include <linux/pinctrl/consumer.h>
- #include <linux/platform_device.h>
- 
- #include "mtu3.h"
-@@ -212,33 +211,6 @@ static void ssusb_ip_sw_reset(struct ssu
- 	mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
- }
- 
--static int get_iddig_pinctrl(struct ssusb_mtk *ssusb)
--{
--	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
--
--	otg_sx->id_pinctrl = devm_pinctrl_get(ssusb->dev);
--	if (IS_ERR(otg_sx->id_pinctrl)) {
--		dev_err(ssusb->dev, "Cannot find id pinctrl!\n");
--		return PTR_ERR(otg_sx->id_pinctrl);
--	}
--
--	otg_sx->id_float =
--		pinctrl_lookup_state(otg_sx->id_pinctrl, "id_float");
--	if (IS_ERR(otg_sx->id_float)) {
--		dev_err(ssusb->dev, "Cannot find pinctrl id_float!\n");
--		return PTR_ERR(otg_sx->id_float);
--	}
--
--	otg_sx->id_ground =
--		pinctrl_lookup_state(otg_sx->id_pinctrl, "id_ground");
--	if (IS_ERR(otg_sx->id_ground)) {
--		dev_err(ssusb->dev, "Cannot find pinctrl id_ground!\n");
--		return PTR_ERR(otg_sx->id_ground);
--	}
--
--	return 0;
--}
--
- /* ignore the error if the clock does not exist */
- static struct clk *get_optional_clk(struct device *dev, const char *id)
- {
-@@ -349,15 +321,11 @@ static int get_ssusb_rscs(struct platfor
- 			dev_err(ssusb->dev, "couldn't get extcon device\n");
- 			return -EPROBE_DEFER;
- 		}
--		if (otg_sx->manual_drd_enabled) {
--			ret = get_iddig_pinctrl(ssusb);
--			if (ret)
--				return ret;
--		}
- 	}
- 
--	dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk:%x\n",
--		ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk);
-+	dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
-+		ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
-+		otg_sx->manual_drd_enabled ? "manual" : "auto");
- 
- 	return 0;
- }

target/linux/mediatek/patches-4.14/0109-usb-mtu3-add-support-for-usb3.1-IP.patch

@@ -1,152 +0,0 @@
-From 8f444887e23b9f0ea31aaae74fbc18171714d8d2 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:43 +0800
-Subject: [PATCH 109/224] usb: mtu3: add support for usb3.1 IP
-
-Support SuperSpeedPlus for usb3.1 device IP
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- drivers/usb/mtu3/mtu3.h            |  1 +
- drivers/usb/mtu3/mtu3_core.c       | 14 +++++++++++---
- drivers/usb/mtu3/mtu3_gadget.c     |  3 ++-
- drivers/usb/mtu3/mtu3_gadget_ep0.c | 16 ++++++++--------
- drivers/usb/mtu3/mtu3_hw_regs.h    |  1 +
- 5 files changed, 23 insertions(+), 12 deletions(-)
-
---- a/drivers/usb/mtu3/mtu3.h
-+++ b/drivers/usb/mtu3/mtu3.h
-@@ -94,6 +94,7 @@ enum mtu3_speed {
- 	MTU3_SPEED_FULL = 1,
- 	MTU3_SPEED_HIGH = 3,
- 	MTU3_SPEED_SUPER = 4,
-+	MTU3_SPEED_SUPER_PLUS = 5,
- };
- 
- /**
---- a/drivers/usb/mtu3/mtu3_core.c
-+++ b/drivers/usb/mtu3/mtu3_core.c
-@@ -237,7 +237,7 @@ void mtu3_ep_stall_set(struct mtu3_ep *m
- 
- void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
- {
--	if (mtu->is_u3_ip && (mtu->max_speed == USB_SPEED_SUPER))
-+	if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER)
- 		mtu3_ss_func_set(mtu, is_on);
- 	else
- 		mtu3_hs_softconn_set(mtu, is_on);
-@@ -547,6 +547,9 @@ static void mtu3_set_speed(struct mtu3 *
- 		mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
- 		/* HS/FS detected by HW */
- 		mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
-+	} else if (mtu->max_speed == USB_SPEED_SUPER) {
-+		mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
-+			     SSUSB_U3_PORT_SSP_SPEED);
- 	}
- 
- 	dev_info(mtu->dev, "max_speed: %s\n",
-@@ -626,6 +629,10 @@ static irqreturn_t mtu3_link_isr(struct
- 		udev_speed = USB_SPEED_SUPER;
- 		maxpkt = 512;
- 		break;
-+	case MTU3_SPEED_SUPER_PLUS:
-+		udev_speed = USB_SPEED_SUPER_PLUS;
-+		maxpkt = 512;
-+		break;
- 	default:
- 		udev_speed = USB_SPEED_UNKNOWN;
- 		break;
-@@ -827,14 +834,15 @@ int ssusb_gadget_init(struct ssusb_mtk *
- 	case USB_SPEED_FULL:
- 	case USB_SPEED_HIGH:
- 	case USB_SPEED_SUPER:
-+	case USB_SPEED_SUPER_PLUS:
- 		break;
- 	default:
- 		dev_err(dev, "invalid max_speed: %s\n",
- 			usb_speed_string(mtu->max_speed));
- 		/* fall through */
- 	case USB_SPEED_UNKNOWN:
--		/* default as SS */
--		mtu->max_speed = USB_SPEED_SUPER;
-+		/* default as SSP */
-+		mtu->max_speed = USB_SPEED_SUPER_PLUS;
- 		break;
- 	}
- 
---- a/drivers/usb/mtu3/mtu3_gadget.c
-+++ b/drivers/usb/mtu3/mtu3_gadget.c
-@@ -89,6 +89,7 @@ static int mtu3_ep_enable(struct mtu3_ep
- 
- 	switch (mtu->g.speed) {
- 	case USB_SPEED_SUPER:
-+	case USB_SPEED_SUPER_PLUS:
- 		if (usb_endpoint_xfer_int(desc) ||
- 				usb_endpoint_xfer_isoc(desc)) {
- 			interval = desc->bInterval;
-@@ -456,7 +457,7 @@ static int mtu3_gadget_wakeup(struct usb
- 		return  -EOPNOTSUPP;
- 
- 	spin_lock_irqsave(&mtu->lock, flags);
--	if (mtu->g.speed == USB_SPEED_SUPER) {
-+	if (mtu->g.speed >= USB_SPEED_SUPER) {
- 		mtu3_setbits(mtu->mac_base, U3D_LINK_POWER_CONTROL, UX_EXIT);
- 	} else {
- 		mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, RESUME);
---- a/drivers/usb/mtu3/mtu3_gadget_ep0.c
-+++ b/drivers/usb/mtu3/mtu3_gadget_ep0.c
-@@ -212,8 +212,8 @@ ep0_get_status(struct mtu3 *mtu, const s
- 	case USB_RECIP_DEVICE:
- 		result[0] = mtu->is_self_powered << USB_DEVICE_SELF_POWERED;
- 		result[0] |= mtu->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
--		/* superspeed only */
--		if (mtu->g.speed == USB_SPEED_SUPER) {
-+
-+		if (mtu->g.speed >= USB_SPEED_SUPER) {
- 			result[0] |= mtu->u1_enable << USB_DEV_STAT_U1_ENABLED;
- 			result[0] |= mtu->u2_enable << USB_DEV_STAT_U2_ENABLED;
- 		}
-@@ -329,8 +329,8 @@ static int ep0_handle_feature_dev(struct
- 		handled = handle_test_mode(mtu, setup);
- 		break;
- 	case USB_DEVICE_U1_ENABLE:
--		if (mtu->g.speed != USB_SPEED_SUPER ||
--			mtu->g.state != USB_STATE_CONFIGURED)
-+		if (mtu->g.speed < USB_SPEED_SUPER ||
-+		    mtu->g.state != USB_STATE_CONFIGURED)
- 			break;
- 
- 		lpc = mtu3_readl(mbase, U3D_LINK_POWER_CONTROL);
-@@ -344,8 +344,8 @@ static int ep0_handle_feature_dev(struct
- 		handled = 1;
- 		break;
- 	case USB_DEVICE_U2_ENABLE:
--		if (mtu->g.speed != USB_SPEED_SUPER ||
--			mtu->g.state != USB_STATE_CONFIGURED)
-+		if (mtu->g.speed < USB_SPEED_SUPER ||
-+		    mtu->g.state != USB_STATE_CONFIGURED)
- 			break;
- 
- 		lpc = mtu3_readl(mbase, U3D_LINK_POWER_CONTROL);
-@@ -384,8 +384,8 @@ static int ep0_handle_feature(struct mtu
- 		break;
- 	case USB_RECIP_INTERFACE:
- 		/* superspeed only */
--		if ((value == USB_INTRF_FUNC_SUSPEND)
--			&& (mtu->g.speed == USB_SPEED_SUPER)) {
-+		if (value == USB_INTRF_FUNC_SUSPEND &&
-+		    mtu->g.speed >= USB_SPEED_SUPER) {
- 			/*
- 			 * forward the request because function drivers
- 			 * should handle it
---- a/drivers/usb/mtu3/mtu3_hw_regs.h
-+++ b/drivers/usb/mtu3/mtu3_hw_regs.h
-@@ -467,6 +467,7 @@
- #define SSUSB_VBUS_CHG_INT_B_EN		BIT(6)
- 
- /* U3D_SSUSB_U3_CTRL_0P */
-+#define SSUSB_U3_PORT_SSP_SPEED	BIT(9)
- #define SSUSB_U3_PORT_HOST_SEL		BIT(2)
- #define SSUSB_U3_PORT_PDN		BIT(1)
- #define SSUSB_U3_PORT_DIS		BIT(0)

target/linux/mediatek/patches-4.14/0110-usb-mtu3-get-optional-vbus-for-host-only-mode.patch

@@ -1,40 +0,0 @@
-From b6712b72d1273e792ee8a533048ba731a3709163 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:44 +0800
-Subject: [PATCH 110/224] usb: mtu3: get optional vbus for host only mode
-
-When dr_mode is set as USB_DR_MODE_HOST, it's better to try to
-get optional vbus, this can increase flexibility, although we
-can set vbus as always on for regulator or put it in host driver
-to turn it on.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- drivers/usb/mtu3/mtu3_plat.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/usb/mtu3/mtu3_plat.c
-+++ b/drivers/usb/mtu3/mtu3_plat.c
-@@ -300,10 +300,6 @@ static int get_ssusb_rscs(struct platfor
- 	of_property_read_u32(node, "mediatek,u3p-dis-msk",
- 			     &ssusb->u3p_dis_msk);
- 
--	if (ssusb->dr_mode != USB_DR_MODE_OTG)
--		return 0;
--
--	/* if dual-role mode is supported */
- 	vbus = devm_regulator_get(&pdev->dev, "vbus");
- 	if (IS_ERR(vbus)) {
- 		dev_err(dev, "failed to get vbus\n");
-@@ -311,6 +307,10 @@ static int get_ssusb_rscs(struct platfor
- 	}
- 	otg_sx->vbus = vbus;
- 
-+	if (ssusb->dr_mode == USB_DR_MODE_HOST)
-+		return 0;
-+
-+	/* if dual-role mode is supported */
- 	otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
- 	otg_sx->manual_drd_enabled =
- 		of_property_read_bool(node, "enable-manual-drd");

target/linux/mediatek/patches-4.14/0111-usb-mtu3-set-invalid-dr_mode-as-dual-role-mode.patch

@@ -1,29 +0,0 @@
-From e315036cdbf8dad7cff4df9dfe8bcff2eddf2277 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:45 +0800
-Subject: [PATCH 111/224] usb: mtu3: set invalid dr_mode as dual-role mode
-
-Treat dr_mode of USB_DR_MODE_UNKNOWN as USB_DR_MODE_OTG to
-enhance functional robustness.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- drivers/usb/mtu3/mtu3_plat.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
---- a/drivers/usb/mtu3/mtu3_plat.c
-+++ b/drivers/usb/mtu3/mtu3_plat.c
-@@ -283,10 +283,8 @@ static int get_ssusb_rscs(struct platfor
- 		return PTR_ERR(ssusb->ippc_base);
- 
- 	ssusb->dr_mode = usb_get_dr_mode(dev);
--	if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
--		dev_err(dev, "dr_mode is error\n");
--		return -EINVAL;
--	}
-+	if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
-+		ssusb->dr_mode = USB_DR_MODE_OTG;
- 
- 	if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
- 		return 0;

target/linux/mediatek/patches-4.14/0112-usb-mtu3-set-otg_sel-for-u2port-only-if-works-as-dua.patch

@@ -1,44 +0,0 @@
-From 36f70702b66cd3453b65d46b5c26ea87d8897363 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:46 +0800
-Subject: [PATCH 112/224] usb: mtu3: set otg_sel for u2port only if works as
- dual-role mode
-
-When set otg_sel(SSUSB_U2_PORT_OTG_SEL) for u2port which supports
-dual-role mode, the controller will automatically switch mode
-between host and device according to IDDIG signal. But if the
-u2port only supports device mode, and no IDDIG pin is provided,
-setting otg_sel may cause failure of detection by host.
-So set it only for dual-role mode.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- drivers/usb/mtu3/mtu3_core.c | 9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/drivers/usb/mtu3/mtu3_core.c
-+++ b/drivers/usb/mtu3/mtu3_core.c
-@@ -115,7 +115,9 @@ static int mtu3_device_enable(struct mtu
- 	mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
- 		(SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
- 		SSUSB_U2_PORT_HOST_SEL));
--	mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
-+
-+	if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
-+		mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
- 
- 	return ssusb_check_clocks(mtu->ssusb, check_clk);
- }
-@@ -130,7 +132,10 @@ static void mtu3_device_disable(struct m
- 
- 	mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
- 		SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
--	mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
-+
-+	if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
-+		mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
-+
- 	mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
- }
- 

target/linux/mediatek/patches-4.14/0113-dt-bindings-usb-mtu3-add-a-optional-property-to-disa.patch

@@ -1,25 +0,0 @@
-From 6b6f2c178ee2cd57713993e3cf0afbe4effb2578 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:47 +0800
-Subject: [PATCH 113/224] dt-bindings: usb: mtu3: add a optional property to
- disable u3ports
-
-Add a new optional property to disable u3ports
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
-+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
-@@ -44,6 +44,8 @@ Optional properties:
-  - mediatek,enable-wakeup : supports ip sleep wakeup used by host mode
-  - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup
- 	control register, it depends on "mediatek,enable-wakeup".
-+ - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
-+	bit1 for u3port1, ... etc;
- 
- Sub-nodes:
- The xhci should be added as subnode to mtu3 as shown in the following example

target/linux/mediatek/patches-4.14/0114-dt-bindings-usb-mtu3-remove-dummy-clocks-and-add-opt.patch

@@ -1,41 +0,0 @@
-From 2c90367440a0dbf9962e7a7f701b0e7a320d325a Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:48 +0800
-Subject: [PATCH 114/224] dt-bindings: usb: mtu3: remove dummy clocks and add
- optional ones
-
-Remove dummy clocks for usb wakeup and add optional ones for
-mcu_bus and dma_bus bus.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 10 ++++------
- 1 file changed, 4 insertions(+), 6 deletions(-)
-
---- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
-+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
-@@ -14,9 +14,9 @@ Required properties:
-  - vusb33-supply : regulator of USB avdd3.3v
-  - clocks : a list of phandle + clock-specifier pairs, one for each
- 	entry in clock-names
-- - clock-names : must contain "sys_ck" and "ref_ck" for clock of controller;
--	"wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are
--	depends on "mediatek,enable-wakeup"
-+ - clock-names : must contain "sys_ck" for clock of controller,
-+	the following clocks are optional:
-+	"ref_ck", "mcu_ck" and "dam_ck";
-  - phys : a list of phandle + phy specifier pairs
-  - dr_mode : should be one of "host", "peripheral" or "otg",
- 	refer to usb/generic.txt
-@@ -65,9 +65,7 @@ ssusb: usb@11271000 {
- 	clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
- 		 <&pericfg CLK_PERI_USB0>,
- 		 <&pericfg CLK_PERI_USB1>;
--	clock-names = "sys_ck", "ref_ck",
--		      "wakeup_deb_p0",
--		      "wakeup_deb_p1";
-+	clock-names = "sys_ck", "ref_ck";
- 	vusb33-supply = <&mt6397_vusb_reg>;
- 	vbus-supply = <&usb_p0_vbus>;
- 	extcon = <&extcon_usb>;

target/linux/mediatek/patches-4.14/0115-dt-bindings-usb-mtu3-remove-optional-pinctrls.patch

@@ -1,30 +0,0 @@
-From df2f0d10213798a806c90bc06db6bed501e7bf7d Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 17:10:49 +0800
-Subject: [PATCH 115/224] dt-bindings: usb: mtu3: remove optional pinctrls
-
-Remove optional pinctrls due to using FORCE/RG_IDDIG to implement
-manual switch function.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Felipe Balbi <[email protected]>
----
- Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
-+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
-@@ -30,9 +30,10 @@ Optional properties:
- 	when supports dual-role mode.
-  - vbus-supply : reference to the VBUS regulator, needed when supports
- 	dual-role mode.
-- - pinctl-names : a pinctrl state named "default" must be defined,
--	"id_float" and "id_ground" are optinal which depends on
--	"mediatek,enable-manual-drd"
-+ - pinctrl-names : a pinctrl state named "default" is optional, and need be
-+	defined if auto drd switch is enabled, that means the property dr_mode
-+	is set as "otg", and meanwhile the property "mediatek,enable-manual-drd"
-+	is not set.
-  - pinctrl-0 : pin control group
- 	See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
- 

target/linux/mediatek/patches-4.14/0116-dt-bindings-arm-mediatek-add-MT7622-string-to-the-PM.patch

@@ -1,38 +0,0 @@
-From 1567cde49a0f2304e18c08e2ccd830e0686fc0a7 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 18 Oct 2017 16:28:42 +0800
-Subject: [PATCH 116/224] dt-bindings: arm: mediatek: add MT7622 string to the
- PMIC wrapper doc
-
-Signed-off-by: Chenglin Xu <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Acked-by: Rob Herring <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
-+++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
-@@ -19,6 +19,7 @@ IP Pairing
- Required properties in pwrap device node.
- - compatible:
- 	"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
-+	"mediatek,mt7622-pwrap" for MT7622 SoCs
- 	"mediatek,mt8135-pwrap" for MT8135 SoCs
- 	"mediatek,mt8173-pwrap" for MT8173 SoCs
- - interrupts: IRQ for pwrap in SOC
-@@ -36,9 +37,12 @@ Required properties in pwrap device node
- - clocks: Must contain an entry for each entry in clock-names.
- 
- Optional properities:
--- pmic: Mediatek PMIC MFD is the child device of pwrap
-+- pmic: Using either MediaTek PMIC MFD as the child device of pwrap
-   See the following for child node definitions:
-   Documentation/devicetree/bindings/mfd/mt6397.txt
-+  or the regulator-only device as the child device of pwrap, such as MT6380.
-+  See the following definitions for such kinds of devices.
-+  Documentation/devicetree/bindings/regulator/mt6380-regulator.txt
- 
- Example:
- 	pwrap: pwrap@1000f000 {

target/linux/mediatek/patches-4.14/0117-soc-mediatek-pwrap-add-pwrap_read32-for-reading-in-3.patch

@@ -1,134 +0,0 @@
-From 9c37953bd08daa3ca227098d763e980d1898add3 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 18 Oct 2017 16:28:43 +0800
-Subject: [PATCH 117/224] soc: mediatek: pwrap: add pwrap_read32 for reading in
- 32-bit mode
-
-Some regulators such as MediaTek MT6380 has to be read in 32-bit mode.
-So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16
-and one function pointer is introduced for increasing flexibility allowing
-the determination which mode is used by the pwrap slave detection through
-device tree.
-
-Signed-off-by: Chenglin Xu <[email protected]>
-Signed-off-by: Chen Zhong <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- drivers/soc/mediatek/mtk-pmic-wrap.c | 55 +++++++++++++++++++++++++++++++++++-
- 1 file changed, 54 insertions(+), 1 deletion(-)
-
---- a/drivers/soc/mediatek/mtk-pmic-wrap.c
-+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -487,6 +487,7 @@ static int mt8135_regs[] = {
- 
- enum pmic_type {
- 	PMIC_MT6323,
-+	PMIC_MT6380,
- 	PMIC_MT6397,
- };
- 
-@@ -496,9 +497,16 @@ enum pwrap_type {
- 	PWRAP_MT8173,
- };
- 
-+struct pmic_wrapper;
- struct pwrap_slv_type {
- 	const u32 *dew_regs;
- 	enum pmic_type type;
-+	/*
-+	 * pwrap operations are highly associated with the PMIC types,
-+	 * so the pointers added increases flexibility allowing determination
-+	 * which type is used by the detection through device tree.
-+	 */
-+	int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
- };
- 
- struct pmic_wrapper {
-@@ -609,7 +617,7 @@ static int pwrap_write(struct pmic_wrapp
- 	return 0;
- }
- 
--static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
-+static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
- {
- 	int ret;
- 
-@@ -632,6 +640,39 @@ static int pwrap_read(struct pmic_wrappe
- 	return 0;
- }
- 
-+static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
-+{
-+	int ret, msb;
-+
-+	*rdata = 0;
-+	for (msb = 0; msb < 2; msb++) {
-+		ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
-+		if (ret) {
-+			pwrap_leave_fsm_vldclr(wrp);
-+			return ret;
-+		}
-+
-+		pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
-+			     PWRAP_WACS2_CMD);
-+
-+		ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
-+		if (ret)
-+			return ret;
-+
-+		*rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
-+			   PWRAP_WACS2_RDATA)) << (16 * msb));
-+
-+		pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
-+	}
-+
-+	return 0;
-+}
-+
-+static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
-+{
-+	return wrp->slave->pwrap_read(wrp, adr, rdata);
-+}
-+
- static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
- {
- 	return pwrap_read(context, adr, rdata);
-@@ -752,6 +793,8 @@ static int pwrap_mt2701_init_reg_clock(s
- 		pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
- 		pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
- 		break;
-+	default:
-+		break;
- 	}
- 
- 	return 0;
-@@ -815,6 +858,8 @@ static int pwrap_init_cipher(struct pmic
- 		pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
- 			    0x1);
- 		break;
-+	default:
-+		break;
- 	}
- 
- 	/* wait for cipher data ready@AP */
-@@ -1036,11 +1081,19 @@ static const struct regmap_config pwrap_
- static const struct pwrap_slv_type pmic_mt6323 = {
- 	.dew_regs = mt6323_regs,
- 	.type = PMIC_MT6323,
-+	.pwrap_read = pwrap_read16,
-+};
-+
-+static const struct pwrap_slv_type pmic_mt6380 = {
-+	.dew_regs = NULL,
-+	.type = PMIC_MT6380,
-+	.pwrap_read = pwrap_read32,
- };
- 
- static const struct pwrap_slv_type pmic_mt6397 = {
- 	.dew_regs = mt6397_regs,
- 	.type = PMIC_MT6397,
-+	.pwrap_read = pwrap_read16,
- };
- 
- static const struct of_device_id of_slave_match_tbl[] = {

target/linux/mediatek/patches-4.14/0118-soc-mediatek-pwrap-add-pwrap_write32-for-writing-in-.patch

@@ -1,132 +0,0 @@
-From 635f800995e4ea2a18ce7520d816dab018ce091f Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 18 Oct 2017 16:28:44 +0800
-Subject: [PATCH 118/224] soc: mediatek: pwrap: add pwrap_write32 for writing
- in 32-bit mode
-
-Some regulators such as MediaTek MT6380 also has to be written in
-32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write
-into pwrap_write16 and one additional function pointer is introduced
-for increasing flexibility allowing the determination which mode is
-used by the pwrap slave detection through device tree.
-
-Signed-off-by: Chenglin Xu <[email protected]>
-Signed-off-by: Chen Zhong <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- drivers/soc/mediatek/mtk-pmic-wrap.c | 70 +++++++++++++++++++++++++++---------
- 1 file changed, 54 insertions(+), 16 deletions(-)
-
---- a/drivers/soc/mediatek/mtk-pmic-wrap.c
-+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -507,6 +507,7 @@ struct pwrap_slv_type {
- 	 * which type is used by the detection through device tree.
- 	 */
- 	int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
-+	int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
- };
- 
- struct pmic_wrapper {
-@@ -601,22 +602,6 @@ static int pwrap_wait_for_state(struct p
- 	} while (1);
- }
- 
--static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
--{
--	int ret;
--
--	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
--	if (ret) {
--		pwrap_leave_fsm_vldclr(wrp);
--		return ret;
--	}
--
--	pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
--			PWRAP_WACS2_CMD);
--
--	return 0;
--}
--
- static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
- {
- 	int ret;
-@@ -673,6 +658,56 @@ static int pwrap_read(struct pmic_wrappe
- 	return wrp->slave->pwrap_read(wrp, adr, rdata);
- }
- 
-+static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
-+{
-+	int ret;
-+
-+	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
-+	if (ret) {
-+		pwrap_leave_fsm_vldclr(wrp);
-+		return ret;
-+	}
-+
-+	pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
-+		     PWRAP_WACS2_CMD);
-+
-+	return 0;
-+}
-+
-+static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
-+{
-+	int ret, msb, rdata;
-+
-+	for (msb = 0; msb < 2; msb++) {
-+		ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
-+		if (ret) {
-+			pwrap_leave_fsm_vldclr(wrp);
-+			return ret;
-+		}
-+
-+		pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
-+			     ((wdata >> (msb * 16)) & 0xffff),
-+			     PWRAP_WACS2_CMD);
-+
-+		/*
-+		 * The pwrap_read operation is the requirement of hardware used
-+		 * for the synchronization between two successive 16-bit
-+		 * pwrap_writel operations composing one 32-bit bus writing.
-+		 * Otherwise, we'll find the result fails on the lower 16-bit
-+		 * pwrap writing.
-+		 */
-+		if (!msb)
-+			pwrap_read(wrp, adr, &rdata);
-+	}
-+
-+	return 0;
-+}
-+
-+static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
-+{
-+	return wrp->slave->pwrap_write(wrp, adr, wdata);
-+}
-+
- static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
- {
- 	return pwrap_read(context, adr, rdata);
-@@ -1082,18 +1117,21 @@ static const struct pwrap_slv_type pmic_
- 	.dew_regs = mt6323_regs,
- 	.type = PMIC_MT6323,
- 	.pwrap_read = pwrap_read16,
-+	.pwrap_write = pwrap_write16,
- };
- 
- static const struct pwrap_slv_type pmic_mt6380 = {
- 	.dew_regs = NULL,
- 	.type = PMIC_MT6380,
- 	.pwrap_read = pwrap_read32,
-+	.pwrap_write = pwrap_write32,
- };
- 
- static const struct pwrap_slv_type pmic_mt6397 = {
- 	.dew_regs = mt6397_regs,
- 	.type = PMIC_MT6397,
- 	.pwrap_read = pwrap_read16,
-+	.pwrap_write = pwrap_write16,
- };
- 
- static const struct of_device_id of_slave_match_tbl[] = {

target/linux/mediatek/patches-4.14/0119-soc-mediatek-pwrap-refactor-pwrap_init-for-the-vario.patch

@@ -1,227 +0,0 @@
-From 16bebe4ad52083316907fb7149c797cd331f5948 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 18 Oct 2017 16:28:45 +0800
-Subject: [PATCH 119/224] soc: mediatek: pwrap: refactor pwrap_init for the
- various PMIC types
-
-pwrap initialization is highly associated with the base SoC and the
-target PMICs, so slight refactorization is made here for allowing
-pwrap_init to run on those PMICs with different capability from the
-previous MediaTek PMICs and the determination for the enablement of the
-pwrap capability depending on PMIC type. Apart from this, the patch
-makes the driver more extensible especially when more PMICs join into
-the pwrap driver.
-
-Signed-off-by: Chenglin Xu <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- drivers/soc/mediatek/mtk-pmic-wrap.c | 130 ++++++++++++++++++++++++-----------
- 1 file changed, 90 insertions(+), 40 deletions(-)
-
---- a/drivers/soc/mediatek/mtk-pmic-wrap.c
-+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -70,6 +70,12 @@
- 					  PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
- 					  PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
- 
-+/* Group of bits used for shown slave capability */
-+#define PWRAP_SLV_CAP_SPI	BIT(0)
-+#define PWRAP_SLV_CAP_DUALIO	BIT(1)
-+#define PWRAP_SLV_CAP_SECURITY	BIT(2)
-+#define HAS_CAP(_c, _x)	(((_c) & (_x)) == (_x))
-+
- /* defines for slave device wrapper registers */
- enum dew_regs {
- 	PWRAP_DEW_BASE,
-@@ -501,6 +507,8 @@ struct pmic_wrapper;
- struct pwrap_slv_type {
- 	const u32 *dew_regs;
- 	enum pmic_type type;
-+	/* Flags indicating the capability for the target slave */
-+	u32 caps;
- 	/*
- 	 * pwrap operations are highly associated with the PMIC types,
- 	 * so the pointers added increases flexibility allowing determination
-@@ -787,6 +795,37 @@ static int pwrap_init_sidly(struct pmic_
- 	return 0;
- }
- 
-+static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
-+{
-+	int ret;
-+	u32 rdata;
-+
-+	/* Enable dual IO mode */
-+	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
-+
-+	/* Check IDLE & INIT_DONE in advance */
-+	ret = pwrap_wait_for_state(wrp,
-+				   pwrap_is_fsm_idle_and_sync_idle);
-+	if (ret) {
-+		dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
-+		return ret;
-+	}
-+
-+	pwrap_writel(wrp, 1, PWRAP_DIO_EN);
-+
-+	/* Read Test */
-+	pwrap_read(wrp,
-+		   wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
-+	if (rdata != PWRAP_DEW_READ_TEST_VAL) {
-+		dev_err(wrp->dev,
-+			"Read failed on DIO mode: 0x%04x!=0x%04x\n",
-+			PWRAP_DEW_READ_TEST_VAL, rdata);
-+		return -EFAULT;
-+	}
-+
-+	return 0;
-+}
-+
- static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp)
- {
- 	pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
-@@ -935,6 +974,30 @@ static int pwrap_init_cipher(struct pmic
- 	return 0;
- }
- 
-+static int pwrap_init_security(struct pmic_wrapper *wrp)
-+{
-+	int ret;
-+
-+	/* Enable encryption */
-+	ret = pwrap_init_cipher(wrp);
-+	if (ret)
-+		return ret;
-+
-+	/* Signature checking - using CRC */
-+	if (pwrap_write(wrp,
-+			wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
-+		return -EFAULT;
-+
-+	pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
-+	pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
-+	pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
-+		     PWRAP_SIG_ADR);
-+	pwrap_writel(wrp,
-+		     wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
-+
-+	return 0;
-+}
-+
- static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
- {
- 	/* enable pwrap events and pwrap bridge in AP side */
-@@ -995,7 +1058,6 @@ static int pwrap_mt2701_init_soc_specifi
- static int pwrap_init(struct pmic_wrapper *wrp)
- {
- 	int ret;
--	u32 rdata;
- 
- 	reset_control_reset(wrp->rstc);
- 	if (wrp->rstc_bridge)
-@@ -1007,10 +1069,12 @@ static int pwrap_init(struct pmic_wrappe
- 		pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
- 	}
- 
--	/* Reset SPI slave */
--	ret = pwrap_reset_spislave(wrp);
--	if (ret)
--		return ret;
-+	if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
-+		/* Reset SPI slave */
-+		ret = pwrap_reset_spislave(wrp);
-+		if (ret)
-+			return ret;
-+	}
- 
- 	pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
- 
-@@ -1022,45 +1086,26 @@ static int pwrap_init(struct pmic_wrappe
- 	if (ret)
- 		return ret;
- 
--	/* Setup serial input delay */
--	ret = pwrap_init_sidly(wrp);
--	if (ret)
--		return ret;
--
--	/* Enable dual IO mode */
--	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
--
--	/* Check IDLE & INIT_DONE in advance */
--	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
--	if (ret) {
--		dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
--		return ret;
-+	if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
-+		/* Setup serial input delay */
-+		ret = pwrap_init_sidly(wrp);
-+		if (ret)
-+			return ret;
- 	}
- 
--	pwrap_writel(wrp, 1, PWRAP_DIO_EN);
--
--	/* Read Test */
--	pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
--	if (rdata != PWRAP_DEW_READ_TEST_VAL) {
--		dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
--				PWRAP_DEW_READ_TEST_VAL, rdata);
--		return -EFAULT;
-+	if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
-+		/* Enable dual I/O mode */
-+		ret = pwrap_init_dual_io(wrp);
-+		if (ret)
-+			return ret;
- 	}
- 
--	/* Enable encryption */
--	ret = pwrap_init_cipher(wrp);
--	if (ret)
--		return ret;
--
--	/* Signature checking - using CRC */
--	if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
--		return -EFAULT;
--
--	pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
--	pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
--	pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
--		     PWRAP_SIG_ADR);
--	pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
-+	if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
-+		/* Enable security on bus */
-+		ret = pwrap_init_security(wrp);
-+		if (ret)
-+			return ret;
-+	}
- 
- 	if (wrp->master->type == PWRAP_MT8135)
- 		pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
-@@ -1116,6 +1161,8 @@ static const struct regmap_config pwrap_
- static const struct pwrap_slv_type pmic_mt6323 = {
- 	.dew_regs = mt6323_regs,
- 	.type = PMIC_MT6323,
-+	.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
-+		PWRAP_SLV_CAP_SECURITY,
- 	.pwrap_read = pwrap_read16,
- 	.pwrap_write = pwrap_write16,
- };
-@@ -1123,6 +1170,7 @@ static const struct pwrap_slv_type pmic_
- static const struct pwrap_slv_type pmic_mt6380 = {
- 	.dew_regs = NULL,
- 	.type = PMIC_MT6380,
-+	.caps = 0,
- 	.pwrap_read = pwrap_read32,
- 	.pwrap_write = pwrap_write32,
- };
-@@ -1130,6 +1178,8 @@ static const struct pwrap_slv_type pmic_
- static const struct pwrap_slv_type pmic_mt6397 = {
- 	.dew_regs = mt6397_regs,
- 	.type = PMIC_MT6397,
-+	.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
-+		PWRAP_SLV_CAP_SECURITY,
- 	.pwrap_read = pwrap_read16,
- 	.pwrap_write = pwrap_write16,
- };

target/linux/mediatek/patches-4.14/0120-soc-mediatek-pwrap-add-MediaTek-MT6380-as-one-slave-.patch

@@ -1,98 +0,0 @@
-From 81c54afc5bc918ea3ed65cc356236b302b1f21ca Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 18 Oct 2017 16:28:46 +0800
-Subject: [PATCH 120/224] soc: mediatek: pwrap: add MediaTek MT6380 as one
- slave of pwrap
-
-Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave
-and also add extra new regmap_config of 32-bit mode for MT6380
-since old regmap_config of 16-bit mode can't be fit into the need.
-
-Signed-off-by: Chenglin Xu <[email protected]>
-Signed-off-by: Chen Zhong <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- drivers/soc/mediatek/mtk-pmic-wrap.c | 24 +++++++++++++++++++++---
- 1 file changed, 21 insertions(+), 3 deletions(-)
-
---- a/drivers/soc/mediatek/mtk-pmic-wrap.c
-+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -507,6 +507,7 @@ struct pmic_wrapper;
- struct pwrap_slv_type {
- 	const u32 *dew_regs;
- 	enum pmic_type type;
-+	const struct regmap_config *regmap;
- 	/* Flags indicating the capability for the target slave */
- 	u32 caps;
- 	/*
-@@ -1149,7 +1150,7 @@ static irqreturn_t pwrap_interrupt(int i
- 	return IRQ_HANDLED;
- }
- 
--static const struct regmap_config pwrap_regmap_config = {
-+static const struct regmap_config pwrap_regmap_config16 = {
- 	.reg_bits = 16,
- 	.val_bits = 16,
- 	.reg_stride = 2,
-@@ -1158,9 +1159,19 @@ static const struct regmap_config pwrap_
- 	.max_register = 0xffff,
- };
- 
-+static const struct regmap_config pwrap_regmap_config32 = {
-+	.reg_bits = 32,
-+	.val_bits = 32,
-+	.reg_stride = 4,
-+	.reg_read = pwrap_regmap_read,
-+	.reg_write = pwrap_regmap_write,
-+	.max_register = 0xffff,
-+};
-+
- static const struct pwrap_slv_type pmic_mt6323 = {
- 	.dew_regs = mt6323_regs,
- 	.type = PMIC_MT6323,
-+	.regmap = &pwrap_regmap_config16,
- 	.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
- 		PWRAP_SLV_CAP_SECURITY,
- 	.pwrap_read = pwrap_read16,
-@@ -1170,6 +1181,7 @@ static const struct pwrap_slv_type pmic_
- static const struct pwrap_slv_type pmic_mt6380 = {
- 	.dew_regs = NULL,
- 	.type = PMIC_MT6380,
-+	.regmap = &pwrap_regmap_config32,
- 	.caps = 0,
- 	.pwrap_read = pwrap_read32,
- 	.pwrap_write = pwrap_write32,
-@@ -1178,6 +1190,7 @@ static const struct pwrap_slv_type pmic_
- static const struct pwrap_slv_type pmic_mt6397 = {
- 	.dew_regs = mt6397_regs,
- 	.type = PMIC_MT6397,
-+	.regmap = &pwrap_regmap_config16,
- 	.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
- 		PWRAP_SLV_CAP_SECURITY,
- 	.pwrap_read = pwrap_read16,
-@@ -1189,9 +1202,14 @@ static const struct of_device_id of_slav
- 		.compatible = "mediatek,mt6323",
- 		.data = &pmic_mt6323,
- 	}, {
-+		/* The MT6380 PMIC only implements a regulator, so we bind it
-+		 * directly instead of using a MFD.
-+		 */
-+		.compatible = "mediatek,mt6380-regulator",
-+		.data = &pmic_mt6380,
-+	}, {
- 		.compatible = "mediatek,mt6397",
- 		.data = &pmic_mt6397,
--	}, {
- 		/* sentinel */
- 	}
- };
-@@ -1372,7 +1390,7 @@ static int pwrap_probe(struct platform_d
- 	if (ret)
- 		goto err_out2;
- 
--	wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config);
-+	wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
- 	if (IS_ERR(wrp->regmap)) {
- 		ret = PTR_ERR(wrp->regmap);
- 		goto err_out2;

target/linux/mediatek/patches-4.14/0121-soc-mediatek-pwrap-add-common-way-for-setup-CS-timin.patch

@@ -1,121 +0,0 @@
-From 442c890727e0f585154662b0908fbe3a7986052a Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 18 Oct 2017 16:28:47 +0800
-Subject: [PATCH 121/224] soc: mediatek: pwrap: add common way for setup CS
- timing extenstion
-
-Multiple platforms would always use their own way handling CS timing
-extension on the bus which leads to a little bit code duplication.
-Therefore, the patch groups the similar logic to handle CS timing
-extension into the common function which allows the following SoCs
-have more reusability for configing CS timing.
-
-Signed-off-by: Chenglin Xu <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- drivers/soc/mediatek/mtk-pmic-wrap.c | 59 ++++++++++++++++++++++--------------
- 1 file changed, 37 insertions(+), 22 deletions(-)
-
---- a/drivers/soc/mediatek/mtk-pmic-wrap.c
-+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -827,23 +827,44 @@ static int pwrap_init_dual_io(struct pmi
- 	return 0;
- }
- 
--static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp)
--{
--	pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
--	pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
--	pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
--	pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
--	pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
--
--	return 0;
-+/*
-+ * pwrap_init_chip_select_ext is used to configure CS extension time for each
-+ * phase during data transactions on the pwrap bus.
-+ */
-+static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
-+				       u8 hext_read, u8 lext_start,
-+				       u8 lext_end)
-+{
-+	/*
-+	 * After finishing a write and read transaction, extends CS high time
-+	 * to be at least xT of BUS CLK as hext_write and hext_read specifies
-+	 * respectively.
-+	 */
-+	pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
-+	pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
-+
-+	/*
-+	 * Extends CS low time after CSL and before CSH command to be at
-+	 * least xT of BUS CLK as lext_start and lext_end specifies
-+	 * respectively.
-+	 */
-+	pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
-+	pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
- }
- 
--static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
-+static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
- {
--	pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
--	pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
--	pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
--	pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
-+	switch (wrp->master->type) {
-+	case PWRAP_MT8173:
-+		pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
-+		break;
-+	case PWRAP_MT8135:
-+		pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
-+		pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
-+		break;
-+	default:
-+		break;
-+	}
- 
- 	return 0;
- }
-@@ -853,20 +874,14 @@ static int pwrap_mt2701_init_reg_clock(s
- 	switch (wrp->slave->type) {
- 	case PMIC_MT6397:
- 		pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
--		pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
--		pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
--		pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
--		pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
-+		pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
- 		break;
- 
- 	case PMIC_MT6323:
- 		pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
- 		pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
- 			    0x8);
--		pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
--		pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
--		pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
--		pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
-+		pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
- 		break;
- 	default:
- 		break;
-@@ -1235,7 +1250,7 @@ static const struct pmic_wrapper_type pw
- 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
- 	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
- 	.has_bridge = 1,
--	.init_reg_clock = pwrap_mt8135_init_reg_clock,
-+	.init_reg_clock = pwrap_common_init_reg_clock,
- 	.init_soc_specific = pwrap_mt8135_init_soc_specific,
- };
- 
-@@ -1247,7 +1262,7 @@ static const struct pmic_wrapper_type pw
- 	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
- 	.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
- 	.has_bridge = 0,
--	.init_reg_clock = pwrap_mt8173_init_reg_clock,
-+	.init_reg_clock = pwrap_common_init_reg_clock,
- 	.init_soc_specific = pwrap_mt8173_init_soc_specific,
- };
- 

target/linux/mediatek/patches-4.14/0122-soc-mediatek-pwrap-add-support-for-MT7622-SoC.patch

@@ -1,237 +0,0 @@
-From 87996dabef0d83bbd2ed5264b83b01224bc42968 Mon Sep 17 00:00:00 2001
-From: Chenglin Xu <[email protected]>
-Date: Wed, 18 Oct 2017 16:28:48 +0800
-Subject: [PATCH 122/224] soc: mediatek: pwrap: add support for MT7622 SoC
-
-Add the registers, callbacks and data structures required to make the
-PMIC wrapper work on MT7622.
-
-Signed-off-by: Chenglin Xu <[email protected]>
-Signed-off-by: Chen Zhong <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- drivers/soc/mediatek/mtk-pmic-wrap.c | 170 +++++++++++++++++++++++++++++++++++
- 1 file changed, 170 insertions(+)
-
---- a/drivers/soc/mediatek/mtk-pmic-wrap.c
-+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -214,6 +214,36 @@ enum pwrap_regs {
- 	PWRAP_ADC_RDATA_ADDR1,
- 	PWRAP_ADC_RDATA_ADDR2,
- 
-+	/* MT7622 only regs */
-+	PWRAP_EINT_STA0_ADR,
-+	PWRAP_EINT_STA1_ADR,
-+	PWRAP_STA,
-+	PWRAP_CLR,
-+	PWRAP_DVFS_ADR8,
-+	PWRAP_DVFS_WDATA8,
-+	PWRAP_DVFS_ADR9,
-+	PWRAP_DVFS_WDATA9,
-+	PWRAP_DVFS_ADR10,
-+	PWRAP_DVFS_WDATA10,
-+	PWRAP_DVFS_ADR11,
-+	PWRAP_DVFS_WDATA11,
-+	PWRAP_DVFS_ADR12,
-+	PWRAP_DVFS_WDATA12,
-+	PWRAP_DVFS_ADR13,
-+	PWRAP_DVFS_WDATA13,
-+	PWRAP_DVFS_ADR14,
-+	PWRAP_DVFS_WDATA14,
-+	PWRAP_DVFS_ADR15,
-+	PWRAP_DVFS_WDATA15,
-+	PWRAP_EXT_CK,
-+	PWRAP_ADC_RDATA_ADDR,
-+	PWRAP_GPS_STA,
-+	PWRAP_SW_RST,
-+	PWRAP_DVFS_STEP_CTRL0,
-+	PWRAP_DVFS_STEP_CTRL1,
-+	PWRAP_DVFS_STEP_CTRL2,
-+	PWRAP_SPI2_CTRL,
-+
- 	/* MT8135 only regs */
- 	PWRAP_CSHEXT,
- 	PWRAP_EVENT_IN_EN,
-@@ -336,6 +366,118 @@ static int mt2701_regs[] = {
- 	[PWRAP_ADC_RDATA_ADDR2] =	0x154,
- };
- 
-+static int mt7622_regs[] = {
-+	[PWRAP_MUX_SEL] =		0x0,
-+	[PWRAP_WRAP_EN] =		0x4,
-+	[PWRAP_DIO_EN] =		0x8,
-+	[PWRAP_SIDLY] =			0xC,
-+	[PWRAP_RDDMY] =			0x10,
-+	[PWRAP_SI_CK_CON] =		0x14,
-+	[PWRAP_CSHEXT_WRITE] =		0x18,
-+	[PWRAP_CSHEXT_READ] =		0x1C,
-+	[PWRAP_CSLEXT_START] =		0x20,
-+	[PWRAP_CSLEXT_END] =		0x24,
-+	[PWRAP_STAUPD_PRD] =		0x28,
-+	[PWRAP_STAUPD_GRPEN] =		0x2C,
-+	[PWRAP_EINT_STA0_ADR] =		0x30,
-+	[PWRAP_EINT_STA1_ADR] =		0x34,
-+	[PWRAP_STA] =			0x38,
-+	[PWRAP_CLR] =			0x3C,
-+	[PWRAP_STAUPD_MAN_TRIG] =	0x40,
-+	[PWRAP_STAUPD_STA] =		0x44,
-+	[PWRAP_WRAP_STA] =		0x48,
-+	[PWRAP_HARB_INIT] =		0x4C,
-+	[PWRAP_HARB_HPRIO] =		0x50,
-+	[PWRAP_HIPRIO_ARB_EN] =		0x54,
-+	[PWRAP_HARB_STA0] =		0x58,
-+	[PWRAP_HARB_STA1] =		0x5C,
-+	[PWRAP_MAN_EN] =		0x60,
-+	[PWRAP_MAN_CMD] =		0x64,
-+	[PWRAP_MAN_RDATA] =		0x68,
-+	[PWRAP_MAN_VLDCLR] =		0x6C,
-+	[PWRAP_WACS0_EN] =		0x70,
-+	[PWRAP_INIT_DONE0] =		0x74,
-+	[PWRAP_WACS0_CMD] =		0x78,
-+	[PWRAP_WACS0_RDATA] =		0x7C,
-+	[PWRAP_WACS0_VLDCLR] =		0x80,
-+	[PWRAP_WACS1_EN] =		0x84,
-+	[PWRAP_INIT_DONE1] =		0x88,
-+	[PWRAP_WACS1_CMD] =		0x8C,
-+	[PWRAP_WACS1_RDATA] =		0x90,
-+	[PWRAP_WACS1_VLDCLR] =		0x94,
-+	[PWRAP_WACS2_EN] =		0x98,
-+	[PWRAP_INIT_DONE2] =		0x9C,
-+	[PWRAP_WACS2_CMD] =		0xA0,
-+	[PWRAP_WACS2_RDATA] =		0xA4,
-+	[PWRAP_WACS2_VLDCLR] =		0xA8,
-+	[PWRAP_INT_EN] =		0xAC,
-+	[PWRAP_INT_FLG_RAW] =		0xB0,
-+	[PWRAP_INT_FLG] =		0xB4,
-+	[PWRAP_INT_CLR] =		0xB8,
-+	[PWRAP_SIG_ADR] =		0xBC,
-+	[PWRAP_SIG_MODE] =		0xC0,
-+	[PWRAP_SIG_VALUE] =		0xC4,
-+	[PWRAP_SIG_ERRVAL] =		0xC8,
-+	[PWRAP_CRC_EN] =		0xCC,
-+	[PWRAP_TIMER_EN] =		0xD0,
-+	[PWRAP_TIMER_STA] =		0xD4,
-+	[PWRAP_WDT_UNIT] =		0xD8,
-+	[PWRAP_WDT_SRC_EN] =		0xDC,
-+	[PWRAP_WDT_FLG] =		0xE0,
-+	[PWRAP_DEBUG_INT_SEL] =		0xE4,
-+	[PWRAP_DVFS_ADR0] =		0xE8,
-+	[PWRAP_DVFS_WDATA0] =		0xEC,
-+	[PWRAP_DVFS_ADR1] =		0xF0,
-+	[PWRAP_DVFS_WDATA1] =		0xF4,
-+	[PWRAP_DVFS_ADR2] =		0xF8,
-+	[PWRAP_DVFS_WDATA2] =		0xFC,
-+	[PWRAP_DVFS_ADR3] =		0x100,
-+	[PWRAP_DVFS_WDATA3] =		0x104,
-+	[PWRAP_DVFS_ADR4] =		0x108,
-+	[PWRAP_DVFS_WDATA4] =		0x10C,
-+	[PWRAP_DVFS_ADR5] =		0x110,
-+	[PWRAP_DVFS_WDATA5] =		0x114,
-+	[PWRAP_DVFS_ADR6] =		0x118,
-+	[PWRAP_DVFS_WDATA6] =		0x11C,
-+	[PWRAP_DVFS_ADR7] =		0x120,
-+	[PWRAP_DVFS_WDATA7] =		0x124,
-+	[PWRAP_DVFS_ADR8] =		0x128,
-+	[PWRAP_DVFS_WDATA8] =		0x12C,
-+	[PWRAP_DVFS_ADR9] =		0x130,
-+	[PWRAP_DVFS_WDATA9] =		0x134,
-+	[PWRAP_DVFS_ADR10] =		0x138,
-+	[PWRAP_DVFS_WDATA10] =		0x13C,
-+	[PWRAP_DVFS_ADR11] =		0x140,
-+	[PWRAP_DVFS_WDATA11] =		0x144,
-+	[PWRAP_DVFS_ADR12] =		0x148,
-+	[PWRAP_DVFS_WDATA12] =		0x14C,
-+	[PWRAP_DVFS_ADR13] =		0x150,
-+	[PWRAP_DVFS_WDATA13] =		0x154,
-+	[PWRAP_DVFS_ADR14] =		0x158,
-+	[PWRAP_DVFS_WDATA14] =		0x15C,
-+	[PWRAP_DVFS_ADR15] =		0x160,
-+	[PWRAP_DVFS_WDATA15] =		0x164,
-+	[PWRAP_SPMINF_STA] =		0x168,
-+	[PWRAP_CIPHER_KEY_SEL] =	0x16C,
-+	[PWRAP_CIPHER_IV_SEL] =		0x170,
-+	[PWRAP_CIPHER_EN] =		0x174,
-+	[PWRAP_CIPHER_RDY] =		0x178,
-+	[PWRAP_CIPHER_MODE] =		0x17C,
-+	[PWRAP_CIPHER_SWRST] =		0x180,
-+	[PWRAP_DCM_EN] =		0x184,
-+	[PWRAP_DCM_DBC_PRD] =		0x188,
-+	[PWRAP_EXT_CK] =		0x18C,
-+	[PWRAP_ADC_CMD_ADDR] =		0x190,
-+	[PWRAP_PWRAP_ADC_CMD] =		0x194,
-+	[PWRAP_ADC_RDATA_ADDR] =	0x198,
-+	[PWRAP_GPS_STA] =		0x19C,
-+	[PWRAP_SW_RST] =		0x1A0,
-+	[PWRAP_DVFS_STEP_CTRL0] =	0x238,
-+	[PWRAP_DVFS_STEP_CTRL1] =	0x23C,
-+	[PWRAP_DVFS_STEP_CTRL2] =	0x240,
-+	[PWRAP_SPI2_CTRL] =		0x244,
-+};
-+
- static int mt8173_regs[] = {
- 	[PWRAP_MUX_SEL] =		0x0,
- 	[PWRAP_WRAP_EN] =		0x4,
-@@ -499,6 +641,7 @@ enum pmic_type {
- 
- enum pwrap_type {
- 	PWRAP_MT2701,
-+	PWRAP_MT7622,
- 	PWRAP_MT8135,
- 	PWRAP_MT8173,
- };
-@@ -927,6 +1070,9 @@ static int pwrap_init_cipher(struct pmic
- 	case PWRAP_MT8173:
- 		pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
- 		break;
-+	case PWRAP_MT7622:
-+		pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
-+		break;
- 	}
- 
- 	/* Config cipher mode @PMIC */
-@@ -1071,6 +1217,15 @@ static int pwrap_mt2701_init_soc_specifi
- 	return 0;
- }
- 
-+static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
-+{
-+	pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
-+	/* enable 2wire SPI master */
-+	pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
-+
-+	return 0;
-+}
-+
- static int pwrap_init(struct pmic_wrapper *wrp)
- {
- 	int ret;
-@@ -1242,6 +1397,18 @@ static const struct pmic_wrapper_type pw
- 	.init_soc_specific = pwrap_mt2701_init_soc_specific,
- };
- 
-+static const struct pmic_wrapper_type pwrap_mt7622 = {
-+	.regs = mt7622_regs,
-+	.type = PWRAP_MT7622,
-+	.arb_en_all = 0xff,
-+	.int_en_all = ~(u32)BIT(31),
-+	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
-+	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
-+	.has_bridge = 0,
-+	.init_reg_clock = pwrap_common_init_reg_clock,
-+	.init_soc_specific = pwrap_mt7622_init_soc_specific,
-+};
-+
- static const struct pmic_wrapper_type pwrap_mt8135 = {
- 	.regs = mt8135_regs,
- 	.type = PWRAP_MT8135,
-@@ -1271,6 +1438,9 @@ static const struct of_device_id of_pwra
- 		.compatible = "mediatek,mt2701-pwrap",
- 		.data = &pwrap_mt2701,
- 	}, {
-+		.compatible = "mediatek,mt7622-pwrap",
-+		.data = &pwrap_mt7622,
-+	}, {
- 		.compatible = "mediatek,mt8135-pwrap",
- 		.data = &pwrap_mt8135,
- 	}, {

target/linux/mediatek/patches-4.14/0123-soc-mediatek-place-Kconfig-for-all-SoC-drivers-under.patch

@@ -1,57 +0,0 @@
-From 21501b17e017cb10f1a64a73e62e3e2e91a52efa Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Thu, 5 Oct 2017 11:17:49 +0800
-Subject: [PATCH 123/224] soc: mediatek: place Kconfig for all SoC drivers
- under menu
-
-Add cleanup for placing all Kconfig for all MediaTek SoC drivers under
-the independent menu as other SoCs vendor usually did. Since the menu
-would be shown depending on "ARCH_MEDIATEK || COMPILE_TEST" selected and
-MTK_PMIC_WRAP is still safe compiling with the case of "COMPILE_TEST"
-only, the superfluous dependency for those items under the menu also is
-also being removed for the sake of simplicity.
-
-Signed-off-by: Sean Wang <[email protected]>
-Reviewed-by: Jean Delvare <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- drivers/soc/mediatek/Kconfig | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/soc/mediatek/Kconfig
-+++ b/drivers/soc/mediatek/Kconfig
-@@ -1,9 +1,11 @@
- #
- # MediaTek SoC drivers
- #
-+menu "MediaTek SoC drivers"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+
- config MTK_INFRACFG
- 	bool "MediaTek INFRACFG Support"
--	depends on ARCH_MEDIATEK || COMPILE_TEST
- 	select REGMAP
- 	help
- 	  Say yes here to add support for the MediaTek INFRACFG controller. The
-@@ -12,7 +14,6 @@ config MTK_INFRACFG
- 
- config MTK_PMIC_WRAP
- 	tristate "MediaTek PMIC Wrapper Support"
--	depends on ARCH_MEDIATEK
- 	depends on RESET_CONTROLLER
- 	select REGMAP
- 	help
-@@ -22,7 +23,6 @@ config MTK_PMIC_WRAP
- 
- config MTK_SCPSYS
- 	bool "MediaTek SCPSYS Support"
--	depends on ARCH_MEDIATEK || COMPILE_TEST
- 	default ARCH_MEDIATEK
- 	select REGMAP
- 	select MTK_INFRACFG
-@@ -30,3 +30,5 @@ config MTK_SCPSYS
- 	help
- 	  Say yes here to add support for the MediaTek SCPSYS power domain
- 	  driver.
-+
-+endmenu

target/linux/mediatek/patches-4.14/0124-arm64-mediatek-cleanup-message-for-platform-selectio.patch

@@ -1,34 +0,0 @@
-From f9bea440dd8dbf1eda8644e4b1d76503053f17b6 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Thu, 19 Oct 2017 17:52:54 +0800
-Subject: [PATCH 124/224] arm64: mediatek: cleanup message for platform
- selection
-
-The latest kernel tree already can support more MediaTek platforms such as
-MT2712 and MT7622, so additional descriptions for those platforms are added
-and certain cleanups are also being made here.
-
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Matthias Brugger <[email protected]>
----
- arch/arm64/Kconfig.platforms | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/Kconfig.platforms
-+++ b/arch/arm64/Kconfig.platforms
-@@ -91,12 +91,13 @@ config ARCH_HISI
- 	  This enables support for Hisilicon ARMv8 SoC family
- 
- config ARCH_MEDIATEK
--	bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
-+	bool "MediaTek SoC Family"
- 	select ARM_GIC
- 	select PINCTRL
- 	select MTK_TIMER
- 	help
--	  Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
-+	  This enables support for MediaTek MT27xx, MT65xx, MT76xx
-+	  & MT81xx ARMv8 SoCs
- 
- config ARCH_MESON
- 	bool "Amlogic Platforms"

target/linux/mediatek/patches-4.14/0125-phy-phy-mtk-tphy-add-set_mode-callback.patch

@@ -1,86 +0,0 @@
-From d42ebed1aa669c5a897ec0aa5e1ede8d9069894a Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Thu, 21 Sep 2017 18:31:49 +0800
-Subject: [PATCH 125/224] phy: phy-mtk-tphy: add set_mode callback
-
-This is used to force PHY with USB OTG function to enter a specific
-mode, and override OTG IDPIN(or IDDIG) signal.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Kishon Vijay Abraham I <[email protected]>
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 39 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -96,9 +96,11 @@
- 
- #define U3P_U2PHYDTM1		0x06C
- #define P2C_RG_UART_EN			BIT(16)
-+#define P2C_FORCE_IDDIG		BIT(9)
- #define P2C_RG_VBUSVALID		BIT(5)
- #define P2C_RG_SESSEND			BIT(4)
- #define P2C_RG_AVALID			BIT(2)
-+#define P2C_RG_IDDIG			BIT(1)
- 
- #define U3P_U3_CHIP_GPIO_CTLD		0x0c
- #define P3C_REG_IP_SW_RST		BIT(31)
-@@ -580,6 +582,31 @@ static void u2_phy_instance_exit(struct
- 	}
- }
- 
-+static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
-+				     struct mtk_phy_instance *instance,
-+				     enum phy_mode mode)
-+{
-+	struct u2phy_banks *u2_banks = &instance->u2_banks;
-+	u32 tmp;
-+
-+	tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
-+	switch (mode) {
-+	case PHY_MODE_USB_DEVICE:
-+		tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
-+		break;
-+	case PHY_MODE_USB_HOST:
-+		tmp |= P2C_FORCE_IDDIG;
-+		tmp &= ~P2C_RG_IDDIG;
-+		break;
-+	case PHY_MODE_USB_OTG:
-+		tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
-+		break;
-+	default:
-+		return;
-+	}
-+	writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
-+}
-+
- static void pcie_phy_instance_init(struct mtk_tphy *tphy,
- 	struct mtk_phy_instance *instance)
- {
-@@ -876,6 +903,17 @@ static int mtk_phy_exit(struct phy *phy)
- 	return 0;
- }
- 
-+static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode)
-+{
-+	struct mtk_phy_instance *instance = phy_get_drvdata(phy);
-+	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
-+
-+	if (instance->type == PHY_TYPE_USB2)
-+		u2_phy_instance_set_mode(tphy, instance, mode);
-+
-+	return 0;
-+}
-+
- static struct phy *mtk_phy_xlate(struct device *dev,
- 					struct of_phandle_args *args)
- {
-@@ -926,6 +964,7 @@ static const struct phy_ops mtk_tphy_ops
- 	.exit		= mtk_phy_exit,
- 	.power_on	= mtk_phy_power_on,
- 	.power_off	= mtk_phy_power_off,
-+	.set_mode	= mtk_phy_set_mode,
- 	.owner		= THIS_MODULE,
- };
- 

target/linux/mediatek/patches-4.14/0126-usb-xhci-mtk-use-dma_set_mask_and_coherent-in-probe-.patch

@@ -1,35 +0,0 @@
-From 9f617ce19c5dab429a539d411204ae220b5b8cd6 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 16:26:33 +0800
-Subject: [PATCH 126/224] usb: xhci-mtk: use dma_set_mask_and_coherent() in
- probe function
-
-This patch uses the simpler dma_set_mask_and_coherent() instead of
-doing these as separate steps
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Acked-by: Mathias Nyman <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- drivers/usb/host/xhci-mtk.c | 7 +------
- 1 file changed, 1 insertion(+), 6 deletions(-)
-
---- a/drivers/usb/host/xhci-mtk.c
-+++ b/drivers/usb/host/xhci-mtk.c
-@@ -606,15 +606,10 @@ static int xhci_mtk_probe(struct platfor
- 	}
- 
- 	/* Initialize dma_mask and coherent_dma_mask to 32-bits */
--	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
-+	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
- 	if (ret)
- 		goto disable_clk;
- 
--	if (!dev->dma_mask)
--		dev->dma_mask = &dev->coherent_dma_mask;
--	else
--		dma_set_mask(dev, DMA_BIT_MASK(32));
--
- 	hcd = usb_create_hcd(driver, dev, dev_name(dev));
- 	if (!hcd) {
- 		ret = -ENOMEM;

target/linux/mediatek/patches-4.14/0127-usb-xhci-mtk-use-ports-count-from-xhci-in-xhci_mtk_s.patch

@@ -1,53 +0,0 @@
-From f97aa71fe34135e7fc8da6231e61ee06f79d739d Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 16:26:34 +0800
-Subject: [PATCH 127/224] usb: xhci-mtk: use ports count from xhci in
- xhci_mtk_sch_init()
-
-Make use of ports count from xhci but not from ippc in
-xhci_mtk_sch_init()
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Acked-by: Mathias Nyman <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- drivers/usb/host/xhci-mtk-sch.c | 3 ++-
- drivers/usb/host/xhci-mtk.c     | 3 ---
- 2 files changed, 2 insertions(+), 4 deletions(-)
-
---- a/drivers/usb/host/xhci-mtk-sch.c
-+++ b/drivers/usb/host/xhci-mtk-sch.c
-@@ -289,12 +289,13 @@ static bool need_bw_sch(struct usb_host_
- 
- int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk)
- {
-+	struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
- 	struct mu3h_sch_bw_info *sch_array;
- 	int num_usb_bus;
- 	int i;
- 
- 	/* ss IN and OUT are separated */
--	num_usb_bus = mtk->num_u3_ports * 2 + mtk->num_u2_ports;
-+	num_usb_bus = xhci->num_usb3_ports * 2 + xhci->num_usb2_ports;
- 
- 	sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL);
- 	if (sch_array == NULL)
---- a/drivers/usb/host/xhci-mtk.c
-+++ b/drivers/usb/host/xhci-mtk.c
-@@ -492,7 +492,6 @@ static void xhci_mtk_quirks(struct devic
- /* called during probe() after chip reset completes */
- static int xhci_mtk_setup(struct usb_hcd *hcd)
- {
--	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
- 	struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
- 	int ret;
- 
-@@ -507,8 +506,6 @@ static int xhci_mtk_setup(struct usb_hcd
- 		return ret;
- 
- 	if (usb_hcd_is_primary_hcd(hcd)) {
--		mtk->num_u3_ports = xhci->num_usb3_ports;
--		mtk->num_u2_ports = xhci->num_usb2_ports;
- 		ret = xhci_mtk_sch_init(mtk);
- 		if (ret)
- 			return ret;

target/linux/mediatek/patches-4.14/0128-usb-xhci-mtk-check-clock-stability-of-U3_MAC.patch

@@ -1,36 +0,0 @@
-From 4422c4efeed2a8b9fa745c6e529623d89c0be75e Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 16:26:35 +0800
-Subject: [PATCH 128/224] usb: xhci-mtk: check clock stability of U3_MAC
-
-This is useful to find out the root cause when the Super Speed doesn't
-work. Such as when the T-PHY is switched to PCIe or SATA, and affects
-Super Speed function, the check will fail.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Acked-by: Mathias Nyman <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- drivers/usb/host/xhci-mtk.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/usb/host/xhci-mtk.c
-+++ b/drivers/usb/host/xhci-mtk.c
-@@ -43,6 +43,7 @@
- 
- /* ip_pw_sts1 register */
- #define STS1_IP_SLEEP_STS	BIT(30)
-+#define STS1_U3_MAC_RST	BIT(16)
- #define STS1_XHCI_RST		BIT(11)
- #define STS1_SYS125_RST	BIT(10)
- #define STS1_REF_RST		BIT(8)
-@@ -125,6 +126,9 @@ static int xhci_mtk_host_enable(struct x
- 	check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
- 			STS1_SYS125_RST | STS1_XHCI_RST;
- 
-+	if (mtk->num_u3_ports)
-+		check_val |= STS1_U3_MAC_RST;
-+
- 	ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
- 			  (check_val == (value & check_val)), 100, 20000);
- 	if (ret) {

target/linux/mediatek/patches-4.14/0129-usb-xhci-mtk-support-option-to-disable-usb3-ports.patch

@@ -1,85 +0,0 @@
-From 13a1b2e927893cbb046a1ec5a55ec3516873a3f6 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 16:26:36 +0800
-Subject: [PATCH 129/224] usb: xhci-mtk: support option to disable usb3 ports
-
-Add support to disable specific usb3 ports, it's useful when
-usb3 phy is shared with PCIe or SATA, because we should disable
-the corresponding usb3 port if the phy is used by PCIe or SATA.
-Sometimes it's helpful to analyse and solve problems.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Acked-by: Mathias Nyman <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- drivers/usb/host/xhci-mtk.c | 18 +++++++++++++++---
- drivers/usb/host/xhci-mtk.h |  1 +
- 2 files changed, 16 insertions(+), 3 deletions(-)
-
---- a/drivers/usb/host/xhci-mtk.c
-+++ b/drivers/usb/host/xhci-mtk.c
-@@ -92,6 +92,7 @@ static int xhci_mtk_host_enable(struct x
- {
- 	struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
- 	u32 value, check_val;
-+	int u3_ports_disabed = 0;
- 	int ret;
- 	int i;
- 
-@@ -103,8 +104,13 @@ static int xhci_mtk_host_enable(struct x
- 	value &= ~CTRL1_IP_HOST_PDN;
- 	writel(value, &ippc->ip_pw_ctr1);
- 
--	/* power on and enable all u3 ports */
-+	/* power on and enable u3 ports except skipped ones */
- 	for (i = 0; i < mtk->num_u3_ports; i++) {
-+		if ((0x1 << i) & mtk->u3p_dis_msk) {
-+			u3_ports_disabed++;
-+			continue;
-+		}
-+
- 		value = readl(&ippc->u3_ctrl_p[i]);
- 		value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
- 		value |= CTRL_U3_PORT_HOST_SEL;
-@@ -126,7 +132,7 @@ static int xhci_mtk_host_enable(struct x
- 	check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
- 			STS1_SYS125_RST | STS1_XHCI_RST;
- 
--	if (mtk->num_u3_ports)
-+	if (mtk->num_u3_ports > u3_ports_disabed)
- 		check_val |= STS1_U3_MAC_RST;
- 
- 	ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
-@@ -149,8 +155,11 @@ static int xhci_mtk_host_disable(struct
- 	if (!mtk->has_ippc)
- 		return 0;
- 
--	/* power down all u3 ports */
-+	/* power down u3 ports except skipped ones */
- 	for (i = 0; i < mtk->num_u3_ports; i++) {
-+		if ((0x1 << i) & mtk->u3p_dis_msk)
-+			continue;
-+
- 		value = readl(&ippc->u3_ctrl_p[i]);
- 		value |= CTRL_U3_PORT_PDN;
- 		writel(value, &ippc->u3_ctrl_p[i]);
-@@ -573,6 +582,9 @@ static int xhci_mtk_probe(struct platfor
- 	}
- 
- 	mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
-+	/* optional property, ignore the error if it does not exist */
-+	of_property_read_u32(node, "mediatek,u3p-dis-msk",
-+			     &mtk->u3p_dis_msk);
- 
- 	ret = usb_wakeup_of_property_parse(mtk, node);
- 	if (ret)
---- a/drivers/usb/host/xhci-mtk.h
-+++ b/drivers/usb/host/xhci-mtk.h
-@@ -121,6 +121,7 @@ struct xhci_hcd_mtk {
- 	bool has_ippc;
- 	int num_u2_ports;
- 	int num_u3_ports;
-+	int u3p_dis_msk;
- 	struct regulator *vusb33;
- 	struct regulator *vbus;
- 	struct clk *sys_clk;	/* sys and mac clock */

target/linux/mediatek/patches-4.14/0130-usb-xhci-mtk-remove-dummy-wakeup-debounce-clocks.patch

@@ -1,86 +0,0 @@
-From 25adaf94e0fcbf6c1b47cb610edb7f5c23c53139 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 16:26:37 +0800
-Subject: [PATCH 130/224] usb: xhci-mtk: remove dummy wakeup debounce clocks
-
-The wakeup debounce clocks for each ports in fact are not
-needed, so remove them.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Acked-by: Mathias Nyman <[email protected]>
-Reviewed-by: Matthias Brugger <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- drivers/usb/host/xhci-mtk.c | 33 ---------------------------------
- drivers/usb/host/xhci-mtk.h |  2 --
- 2 files changed, 35 deletions(-)
-
---- a/drivers/usb/host/xhci-mtk.c
-+++ b/drivers/usb/host/xhci-mtk.c
-@@ -237,25 +237,8 @@ static int xhci_mtk_clks_enable(struct x
- 		goto sys_clk_err;
- 	}
- 
--	if (mtk->wakeup_src) {
--		ret = clk_prepare_enable(mtk->wk_deb_p0);
--		if (ret) {
--			dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
--			goto usb_p0_err;
--		}
--
--		ret = clk_prepare_enable(mtk->wk_deb_p1);
--		if (ret) {
--			dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
--			goto usb_p1_err;
--		}
--	}
- 	return 0;
- 
--usb_p1_err:
--	clk_disable_unprepare(mtk->wk_deb_p0);
--usb_p0_err:
--	clk_disable_unprepare(mtk->sys_clk);
- sys_clk_err:
- 	clk_disable_unprepare(mtk->ref_clk);
- ref_clk_err:
-@@ -264,10 +247,6 @@ ref_clk_err:
- 
- static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
- {
--	if (mtk->wakeup_src) {
--		clk_disable_unprepare(mtk->wk_deb_p1);
--		clk_disable_unprepare(mtk->wk_deb_p0);
--	}
- 	clk_disable_unprepare(mtk->sys_clk);
- 	clk_disable_unprepare(mtk->ref_clk);
- }
-@@ -371,18 +350,6 @@ static int usb_wakeup_of_property_parse(
- 	if (!mtk->wakeup_src)
- 		return 0;
- 
--	mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
--	if (IS_ERR(mtk->wk_deb_p0)) {
--		dev_err(dev, "fail to get wakeup_deb_p0\n");
--		return PTR_ERR(mtk->wk_deb_p0);
--	}
--
--	mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
--	if (IS_ERR(mtk->wk_deb_p1)) {
--		dev_err(dev, "fail to get wakeup_deb_p1\n");
--		return PTR_ERR(mtk->wk_deb_p1);
--	}
--
- 	mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
- 						"mediatek,syscon-wakeup");
- 	if (IS_ERR(mtk->pericfg)) {
---- a/drivers/usb/host/xhci-mtk.h
-+++ b/drivers/usb/host/xhci-mtk.h
-@@ -126,8 +126,6 @@ struct xhci_hcd_mtk {
- 	struct regulator *vbus;
- 	struct clk *sys_clk;	/* sys and mac clock */
- 	struct clk *ref_clk;
--	struct clk *wk_deb_p0;	/* port0's wakeup debounce clock */
--	struct clk *wk_deb_p1;
- 	struct regmap *pericfg;
- 	struct phy **phys;
- 	int num_phys;

target/linux/mediatek/patches-4.14/0131-usb-xhci-mtk-add-optional-mcu-and-dma-bus-clocks.patch

@@ -1,139 +0,0 @@
-From 9dce908d64ffb8b0ab71cb3a4b79db398d2e6dc3 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 16:26:38 +0800
-Subject: [PATCH 131/224] usb: xhci-mtk: add optional mcu and dma bus clocks
-
-There are mcu_bus and dma_bus clocks needed to be controlled by
-driver on some SoCs, so add them as optional ones
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Acked-by: Mathias Nyman <[email protected]>
-Reviewed-by: Matthias Brugger <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- drivers/usb/host/xhci-mtk.c | 79 ++++++++++++++++++++++++++++++++++-----------
- drivers/usb/host/xhci-mtk.h |  2 ++
- 2 files changed, 62 insertions(+), 19 deletions(-)
-
---- a/drivers/usb/host/xhci-mtk.c
-+++ b/drivers/usb/host/xhci-mtk.c
-@@ -221,6 +221,44 @@ static int xhci_mtk_ssusb_config(struct
- 	return xhci_mtk_host_enable(mtk);
- }
- 
-+/* ignore the error if the clock does not exist */
-+static struct clk *optional_clk_get(struct device *dev, const char *id)
-+{
-+	struct clk *opt_clk;
-+
-+	opt_clk = devm_clk_get(dev, id);
-+	/* ignore error number except EPROBE_DEFER */
-+	if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
-+		opt_clk = NULL;
-+
-+	return opt_clk;
-+}
-+
-+static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
-+{
-+	struct device *dev = mtk->dev;
-+
-+	mtk->sys_clk = devm_clk_get(dev, "sys_ck");
-+	if (IS_ERR(mtk->sys_clk)) {
-+		dev_err(dev, "fail to get sys_ck\n");
-+		return PTR_ERR(mtk->sys_clk);
-+	}
-+
-+	mtk->ref_clk = optional_clk_get(dev, "ref_ck");
-+	if (IS_ERR(mtk->ref_clk))
-+		return PTR_ERR(mtk->ref_clk);
-+
-+	mtk->mcu_clk = optional_clk_get(dev, "mcu_ck");
-+	if (IS_ERR(mtk->mcu_clk))
-+		return PTR_ERR(mtk->mcu_clk);
-+
-+	mtk->dma_clk = optional_clk_get(dev, "dma_ck");
-+	if (IS_ERR(mtk->dma_clk))
-+		return PTR_ERR(mtk->dma_clk);
-+
-+	return 0;
-+}
-+
- static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
- {
- 	int ret;
-@@ -237,16 +275,34 @@ static int xhci_mtk_clks_enable(struct x
- 		goto sys_clk_err;
- 	}
- 
-+	ret = clk_prepare_enable(mtk->mcu_clk);
-+	if (ret) {
-+		dev_err(mtk->dev, "failed to enable mcu_clk\n");
-+		goto mcu_clk_err;
-+	}
-+
-+	ret = clk_prepare_enable(mtk->dma_clk);
-+	if (ret) {
-+		dev_err(mtk->dev, "failed to enable dma_clk\n");
-+		goto dma_clk_err;
-+	}
-+
- 	return 0;
- 
-+dma_clk_err:
-+	clk_disable_unprepare(mtk->mcu_clk);
-+mcu_clk_err:
-+	clk_disable_unprepare(mtk->sys_clk);
- sys_clk_err:
- 	clk_disable_unprepare(mtk->ref_clk);
- ref_clk_err:
--	return -EINVAL;
-+	return ret;
- }
- 
- static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
- {
-+	clk_disable_unprepare(mtk->dma_clk);
-+	clk_disable_unprepare(mtk->mcu_clk);
- 	clk_disable_unprepare(mtk->sys_clk);
- 	clk_disable_unprepare(mtk->ref_clk);
- }
-@@ -529,24 +585,9 @@ static int xhci_mtk_probe(struct platfor
- 		return PTR_ERR(mtk->vusb33);
- 	}
- 
--	mtk->sys_clk = devm_clk_get(dev, "sys_ck");
--	if (IS_ERR(mtk->sys_clk)) {
--		dev_err(dev, "fail to get sys_ck\n");
--		return PTR_ERR(mtk->sys_clk);
--	}
--
--	/*
--	 * reference clock is usually a "fixed-clock", make it optional
--	 * for backward compatibility and ignore the error if it does
--	 * not exist.
--	 */
--	mtk->ref_clk = devm_clk_get(dev, "ref_ck");
--	if (IS_ERR(mtk->ref_clk)) {
--		if (PTR_ERR(mtk->ref_clk) == -EPROBE_DEFER)
--			return -EPROBE_DEFER;
--
--		mtk->ref_clk = NULL;
--	}
-+	ret = xhci_mtk_clks_get(mtk);
-+	if (ret)
-+		return ret;
- 
- 	mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
- 	/* optional property, ignore the error if it does not exist */
---- a/drivers/usb/host/xhci-mtk.h
-+++ b/drivers/usb/host/xhci-mtk.h
-@@ -126,6 +126,8 @@ struct xhci_hcd_mtk {
- 	struct regulator *vbus;
- 	struct clk *sys_clk;	/* sys and mac clock */
- 	struct clk *ref_clk;
-+	struct clk *mcu_clk;
-+	struct clk *dma_clk;
- 	struct regmap *pericfg;
- 	struct phy **phys;
- 	int num_phys;

target/linux/mediatek/patches-4.14/0132-usb-host-modify-description-for-MTK-xHCI-config.patch

@@ -1,32 +0,0 @@
-From d975bd8976c4d19fbfbaafe269dd466e281a2e3e Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 16:26:39 +0800
-Subject: [PATCH 132/224] usb: host: modify description for MTK xHCI config
-
-Due to all MediaTek SoCs with xHCI host controller use this
-driver, remove limitation for specific SoCs
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Acked-by: Mathias Nyman <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- drivers/usb/host/Kconfig | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -45,12 +45,12 @@ config USB_XHCI_PLATFORM
- 	  If unsure, say N.
- 
- config USB_XHCI_MTK
--	tristate "xHCI support for Mediatek MT65xx/MT7621"
-+	tristate "xHCI support for MediaTek SoCs"
- 	select MFD_SYSCON
- 	depends on (MIPS && SOC_MT7621) || ARCH_MEDIATEK || COMPILE_TEST
- 	---help---
- 	  Say 'Y' to enable the support for the xHCI host controller
--	  found in Mediatek MT65xx SoCs.
-+	  found in MediaTek SoCs.
- 	  If unsure, say N.
- 
- config USB_XHCI_MVEBU

target/linux/mediatek/patches-4.14/0133-dt-bindings-usb-mtk-xhci-add-a-optional-property-to-.patch

@@ -1,25 +0,0 @@
-From 3a2dce7d84793ec60cff173e17e3669acaade8c9 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 16:26:40 +0800
-Subject: [PATCH 133/224] dt-bindings: usb: mtk-xhci: add a optional property
- to disable u3ports
-
-Add a new optional property to disable u3ports
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
-+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
-@@ -38,6 +38,8 @@ Optional properties:
- 	mode;
-  - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup
- 	control register, it depends on "mediatek,wakeup-src".
-+ - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
-+	bit1 for u3port1, ... etc;
-  - vbus-supply : reference to the VBUS regulator;
-  - usb3-lpm-capable : supports USB3.0 LPM
-  - pinctrl-names : a pinctrl state named "default" must be defined

target/linux/mediatek/patches-4.14/0134-dt-bindings-usb-mtk-xhci-remove-dummy-clocks-and-add.patch

@@ -1,58 +0,0 @@
-From a96468412cac8abd66667c322fbcda756cc3abc9 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Fri, 13 Oct 2017 16:26:41 +0800
-Subject: [PATCH 134/224] dt-bindings: usb: mtk-xhci: remove dummy clocks and
- add optional ones
-
-Remove dummy clocks for usb wakeup and add optional ones for
-MCU_BUS_CK and DMA_BUS_CK.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Acked-by: Rob Herring <[email protected]>
-Reviewed-by: Matthias Brugger <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- .../devicetree/bindings/usb/mediatek,mtk-xhci.txt      | 18 ++++++++----------
- 1 file changed, 8 insertions(+), 10 deletions(-)
-
---- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
-+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
-@@ -26,10 +26,11 @@ Required properties:
-  - clocks : a list of phandle + clock-specifier pairs, one for each
- 	entry in clock-names
-  - clock-names : must contain
--	"sys_ck": for clock of xHCI MAC
--	"ref_ck": for reference clock of xHCI MAC
--	"wakeup_deb_p0": for USB wakeup debounce clock of port0
--	"wakeup_deb_p1": for USB wakeup debounce clock of port1
-+	"sys_ck": controller clock used by normal mode,
-+	the following ones are optional:
-+	"ref_ck": reference clock used by low power mode etc,
-+	"mcu_ck": mcu_bus clock for register access,
-+	"dma_ck": dma_bus clock for data transfer by DMA
- 
-  - phys : a list of phandle + phy specifier pairs
- 
-@@ -57,9 +58,7 @@ usb30: usb@11270000 {
- 	clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
- 		 <&pericfg CLK_PERI_USB0>,
- 		 <&pericfg CLK_PERI_USB1>;
--	clock-names = "sys_ck", "ref_ck",
--		      "wakeup_deb_p0",
--		      "wakeup_deb_p1";
-+	clock-names = "sys_ck", "ref_ck";
- 	phys = <&phy_port0 PHY_TYPE_USB3>,
- 	       <&phy_port1 PHY_TYPE_USB2>;
- 	vusb33-supply = <&mt6397_vusb_reg>;
-@@ -91,9 +90,8 @@ Required properties:
- 
-  - clocks : a list of phandle + clock-specifier pairs, one for each
- 	entry in clock-names
-- - clock-names : must be
--	"sys_ck": for clock of xHCI MAC
--	"ref_ck": for reference clock of xHCI MAC
-+ - clock-names : must contain "sys_ck", and the following ones are optional:
-+	"ref_ck", "mcu_ck" and "dma_ck"
- 
- Optional properties:
-  - vbus-supply : reference to the VBUS regulator;

target/linux/mediatek/patches-4.14/0135-dt-bindings-mtd-add-new-compatible-strings-and-impro.patch

@@ -1,42 +0,0 @@
-From 2af9a8582cb28e786a8cbd913f41e6db9adcf3dc Mon Sep 17 00:00:00 2001
-From: Guochun Mao <[email protected]>
-Date: Thu, 21 Sep 2017 20:45:05 +0800
-Subject: [PATCH 135/224] dt-bindings: mtd: add new compatible strings and
- improve description
-
-Add "mediatak,mt2712-nor" and "mediatek,mt7622-nor"
-for nor flash node's compatible strings.
-Explicate the fallback compatible.
-
-Acked-by: Rob Herring <[email protected]>
-Signed-off-by: Guochun Mao <[email protected]>
-Signed-off-by: Cyrille Pitchen <[email protected]>
----
- Documentation/devicetree/bindings/mtd/mtk-quadspi.txt | 15 +++++++++------
- 1 file changed, 9 insertions(+), 6 deletions(-)
-
---- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
-+++ b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
-@@ -1,13 +1,16 @@
- * Serial NOR flash controller for MTK MT81xx (and similar)
- 
- Required properties:
--- compatible: 	  The possible values are:
--		  "mediatek,mt2701-nor"
--		  "mediatek,mt7623-nor"
-+- compatible: 	  For mt8173, compatible should be "mediatek,mt8173-nor",
-+		  and it's the fallback compatible for other Soc.
-+		  For every other SoC, should contain both the SoC-specific compatible
-+		  string and "mediatek,mt8173-nor".
-+		  The possible values are:
-+		  "mediatek,mt2701-nor", "mediatek,mt8173-nor"
-+		  "mediatek,mt2712-nor", "mediatek,mt8173-nor"
-+		  "mediatek,mt7622-nor", "mediatek,mt8173-nor"
-+		  "mediatek,mt7623-nor", "mediatek,mt8173-nor"
- 		  "mediatek,mt8173-nor"
--		  For mt8173, compatible should be "mediatek,mt8173-nor".
--		  For every other SoC, should contain both the SoC-specific compatible string
--		  and "mediatek,mt8173-nor".
- - reg: 		  physical base address and length of the controller's register
- - clocks: 	  the phandle of the clocks needed by the nor controller
- - clock-names: 	  the names of the clocks

target/linux/mediatek/patches-4.14/0136-mtd-mtk-nor-add-suspend-resume-support.patch

@@ -1,128 +0,0 @@
-From 8947f8cd407a55db816cd03fc03b59096210978e Mon Sep 17 00:00:00 2001
-From: Guochun Mao <[email protected]>
-Date: Thu, 21 Sep 2017 20:45:06 +0800
-Subject: [PATCH 136/224] mtd: mtk-nor: add suspend/resume support
-
-Abstract functions of clock setting, to avoid duplicated code,
-these functions been used in new feature.
-Implement suspend/resume functions.
-
-Signed-off-by: Guochun Mao <[email protected]>
-Signed-off-by: Cyrille Pitchen <[email protected]>
----
- drivers/mtd/spi-nor/mtk-quadspi.c | 70 ++++++++++++++++++++++++++++++++-------
- 1 file changed, 58 insertions(+), 12 deletions(-)
-
---- a/drivers/mtd/spi-nor/mtk-quadspi.c
-+++ b/drivers/mtd/spi-nor/mtk-quadspi.c
-@@ -404,6 +404,29 @@ static int mt8173_nor_write_reg(struct s
- 	return ret;
- }
- 
-+static void mt8173_nor_disable_clk(struct mt8173_nor *mt8173_nor)
-+{
-+	clk_disable_unprepare(mt8173_nor->spi_clk);
-+	clk_disable_unprepare(mt8173_nor->nor_clk);
-+}
-+
-+static int mt8173_nor_enable_clk(struct mt8173_nor *mt8173_nor)
-+{
-+	int ret;
-+
-+	ret = clk_prepare_enable(mt8173_nor->spi_clk);
-+	if (ret)
-+		return ret;
-+
-+	ret = clk_prepare_enable(mt8173_nor->nor_clk);
-+	if (ret) {
-+		clk_disable_unprepare(mt8173_nor->spi_clk);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
- static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
- 			struct device_node *flash_node)
- {
-@@ -468,15 +491,11 @@ static int mtk_nor_drv_probe(struct plat
- 		return PTR_ERR(mt8173_nor->nor_clk);
- 
- 	mt8173_nor->dev = &pdev->dev;
--	ret = clk_prepare_enable(mt8173_nor->spi_clk);
-+
-+	ret = mt8173_nor_enable_clk(mt8173_nor);
- 	if (ret)
- 		return ret;
- 
--	ret = clk_prepare_enable(mt8173_nor->nor_clk);
--	if (ret) {
--		clk_disable_unprepare(mt8173_nor->spi_clk);
--		return ret;
--	}
- 	/* only support one attached flash */
- 	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
- 	if (!flash_np) {
-@@ -487,10 +506,9 @@ static int mtk_nor_drv_probe(struct plat
- 	ret = mtk_nor_init(mt8173_nor, flash_np);
- 
- nor_free:
--	if (ret) {
--		clk_disable_unprepare(mt8173_nor->spi_clk);
--		clk_disable_unprepare(mt8173_nor->nor_clk);
--	}
-+	if (ret)
-+		mt8173_nor_disable_clk(mt8173_nor);
-+
- 	return ret;
- }
- 
-@@ -498,11 +516,38 @@ static int mtk_nor_drv_remove(struct pla
- {
- 	struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev);
- 
--	clk_disable_unprepare(mt8173_nor->spi_clk);
--	clk_disable_unprepare(mt8173_nor->nor_clk);
-+	mt8173_nor_disable_clk(mt8173_nor);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int mtk_nor_suspend(struct device *dev)
-+{
-+	struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev);
-+
-+	mt8173_nor_disable_clk(mt8173_nor);
-+
- 	return 0;
- }
- 
-+static int mtk_nor_resume(struct device *dev)
-+{
-+	struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev);
-+
-+	return mt8173_nor_enable_clk(mt8173_nor);
-+}
-+
-+static const struct dev_pm_ops mtk_nor_dev_pm_ops = {
-+	.suspend = mtk_nor_suspend,
-+	.resume = mtk_nor_resume,
-+};
-+
-+#define MTK_NOR_DEV_PM_OPS	(&mtk_nor_dev_pm_ops)
-+#else
-+#define MTK_NOR_DEV_PM_OPS	NULL
-+#endif
-+
- static const struct of_device_id mtk_nor_of_ids[] = {
- 	{ .compatible = "mediatek,mt8173-nor"},
- 	{ /* sentinel */ }
-@@ -514,6 +559,7 @@ static struct platform_driver mtk_nor_dr
- 	.remove = mtk_nor_drv_remove,
- 	.driver = {
- 		.name = "mtk-nor",
-+		.pm = MTK_NOR_DEV_PM_OPS,
- 		.of_match_table = mtk_nor_of_ids,
- 	},
- };

target/linux/mediatek/patches-4.14/0137-dt-bindings-rtc-mediatek-add-bindings-for-MediaTek-S.patch

@@ -1,41 +0,0 @@
-From 3254edde244fcbcce3bf4da1ade9db2db558ae28 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Mon, 23 Oct 2017 15:16:44 +0800
-Subject: [PATCH 137/224] dt-bindings: rtc: mediatek: add bindings for MediaTek
- SoC based RTC
-
-Add device-tree binding for MediaTek SoC based RTC
-
-Cc: [email protected]
-Signed-off-by: Sean Wang <[email protected]>
-Acked-by: Rob Herring <[email protected]>
-Signed-off-by: Alexandre Belloni <[email protected]>
----
- .../devicetree/bindings/rtc/rtc-mt7622.txt          | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mt7622.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt
-@@ -0,0 +1,21 @@
-+Device-Tree bindings for MediaTek SoC based RTC
-+
-+Required properties:
-+- compatible	    : Should be
-+			"mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
-+- reg 		    : Specifies base physical address and size of the registers;
-+- interrupts	    : Should contain the interrupt for RTC alarm;
-+- clocks	    : Specifies list of clock specifiers, corresponding to
-+		      entries in clock-names property;
-+- clock-names	    : Should contain "rtc" entries
-+
-+Example:
-+
-+rtc: rtc@10212800 {
-+	compatible = "mediatek,mt7622-rtc",
-+		     "mediatek,soc-rtc";
-+	reg = <0 0x10212800 0 0x200>;
-+	interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
-+	clocks = <&topckgen CLK_TOP_RTC>;
-+	clock-names = "rtc";
-+};

target/linux/mediatek/patches-4.14/0138-rtc-mediatek-add-driver-for-RTC-on-MT7622-SoC.patch

@@ -1,471 +0,0 @@
-From 4cf0b74c175cb5cb751e449223c0baafc2f98499 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Mon, 23 Oct 2017 15:16:45 +0800
-Subject: [PATCH 138/224] rtc: mediatek: add driver for RTC on MT7622 SoC
-
-This patch introduces the driver for the RTC on MT7622 SoC.
-
-Signed-off-by: Sean Wang <[email protected]>
-Reviewed-by: Yingjoe Chen <[email protected]>
-Signed-off-by: Alexandre Belloni <[email protected]>
----
- drivers/rtc/Kconfig      |  10 ++
- drivers/rtc/Makefile     |   1 +
- drivers/rtc/rtc-mt7622.c | 422 +++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 433 insertions(+)
- create mode 100644 drivers/rtc/rtc-mt7622.c
-
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -1715,6 +1715,16 @@ config RTC_DRV_MT6397
- 
- 	  If you want to use Mediatek(R) RTC interface, select Y or M here.
- 
-+config RTC_DRV_MT7622
-+	tristate "MediaTek SoC based RTC"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	help
-+	  This enables support for the real time clock built in the MediaTek
-+	  SoCs.
-+
-+	  This drive can also be built as a module. If so, the module
-+	  will be called rtc-mt7622.
-+
- config RTC_DRV_XGENE
- 	tristate "APM X-Gene RTC"
- 	depends on HAS_IOMEM
---- a/drivers/rtc/Makefile
-+++ b/drivers/rtc/Makefile
-@@ -103,6 +103,7 @@ obj-$(CONFIG_RTC_DRV_MPC5121)	+= rtc-mpc
- obj-$(CONFIG_RTC_DRV_VRTC)	+= rtc-mrst.o
- obj-$(CONFIG_RTC_DRV_MSM6242)	+= rtc-msm6242.o
- obj-$(CONFIG_RTC_DRV_MT6397)	+= rtc-mt6397.o
-+obj-$(CONFIG_RTC_DRV_MT7622)	+= rtc-mt7622.o
- obj-$(CONFIG_RTC_DRV_MV)	+= rtc-mv.o
- obj-$(CONFIG_RTC_DRV_MXC)	+= rtc-mxc.o
- obj-$(CONFIG_RTC_DRV_NUC900)	+= rtc-nuc900.o
---- /dev/null
-+++ b/drivers/rtc/rtc-mt7622.c
-@@ -0,0 +1,422 @@
-+/*
-+ * Driver for MediaTek SoC based RTC
-+ *
-+ * Copyright (C) 2017 Sean Wang <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/rtc.h>
-+
-+#define MTK_RTC_DEV KBUILD_MODNAME
-+
-+#define MTK_RTC_PWRCHK1		0x4
-+#define	RTC_PWRCHK1_MAGIC	0xc6
-+
-+#define MTK_RTC_PWRCHK2		0x8
-+#define	RTC_PWRCHK2_MAGIC	0x9a
-+
-+#define MTK_RTC_KEY		0xc
-+#define	RTC_KEY_MAGIC		0x59
-+
-+#define MTK_RTC_PROT1		0x10
-+#define	RTC_PROT1_MAGIC		0xa3
-+
-+#define MTK_RTC_PROT2		0x14
-+#define	RTC_PROT2_MAGIC		0x57
-+
-+#define MTK_RTC_PROT3		0x18
-+#define	RTC_PROT3_MAGIC		0x67
-+
-+#define MTK_RTC_PROT4		0x1c
-+#define	RTC_PROT4_MAGIC		0xd2
-+
-+#define MTK_RTC_CTL		0x20
-+#define	RTC_RC_STOP		BIT(0)
-+
-+#define MTK_RTC_DEBNCE		0x2c
-+#define	RTC_DEBNCE_MASK		GENMASK(2, 0)
-+
-+#define MTK_RTC_INT		0x30
-+#define RTC_INT_AL_STA		BIT(4)
-+
-+/*
-+ * Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
-+ * day of month, day of week, hour, minute and second.
-+ */
-+#define MTK_RTC_TREG(_t, _f)	(0x40 + (0x4 * (_f)) + ((_t) * 0x20))
-+
-+#define MTK_RTC_AL_CTL		0x7c
-+#define	RTC_AL_EN		BIT(0)
-+#define	RTC_AL_ALL		GENMASK(7, 0)
-+
-+/*
-+ * The offset is used in the translation for the year between in struct
-+ * rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA)
-+ */
-+#define MTK_RTC_TM_YR_OFFSET	100
-+
-+/*
-+ * The lowest value for the valid tm_year. RTC hardware would take incorrectly
-+ * tm_year 100 as not a leap year and thus it is also required being excluded
-+ * from the valid options.
-+ */
-+#define MTK_RTC_TM_YR_L		(MTK_RTC_TM_YR_OFFSET + 1)
-+
-+/*
-+ * The most year the RTC can hold is 99 and the next to 99 in year register
-+ * would be wraparound to 0, for MT7622.
-+ */
-+#define MTK_RTC_HW_YR_LIMIT	99
-+
-+/* The highest value for the valid tm_year */
-+#define MTK_RTC_TM_YR_H		(MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT)
-+
-+/* Simple macro helps to check whether the hardware supports the tm_year */
-+#define MTK_RTC_TM_YR_VALID(_y)	((_y) >= MTK_RTC_TM_YR_L && \
-+				 (_y) <= MTK_RTC_TM_YR_H)
-+
-+/* Types of the function the RTC provides are time counter and alarm. */
-+enum {
-+	MTK_TC,
-+	MTK_AL,
-+};
-+
-+/* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */
-+enum {
-+	MTK_YEA,
-+	MTK_MON,
-+	MTK_DOM,
-+	MTK_DOW,
-+	MTK_HOU,
-+	MTK_MIN,
-+	MTK_SEC
-+};
-+
-+struct mtk_rtc {
-+	struct rtc_device *rtc;
-+	void __iomem *base;
-+	int irq;
-+	struct clk *clk;
-+};
-+
-+static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val)
-+{
-+	writel_relaxed(val, rtc->base + reg);
-+}
-+
-+static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg)
-+{
-+	return readl_relaxed(rtc->base + reg);
-+}
-+
-+static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set)
-+{
-+	u32 val;
-+
-+	val = mtk_r32(rtc, reg);
-+	val &= ~mask;
-+	val |= set;
-+	mtk_w32(rtc, reg, val);
-+}
-+
-+static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val)
-+{
-+	mtk_rmw(rtc, reg, 0, val);
-+}
-+
-+static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val)
-+{
-+	mtk_rmw(rtc, reg, val, 0);
-+}
-+
-+static void mtk_rtc_hw_init(struct mtk_rtc *hw)
-+{
-+	/* The setup of the init sequence is for allowing RTC got to work */
-+	mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
-+	mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
-+	mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
-+	mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
-+	mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
-+	mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
-+	mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
-+	mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0);
-+	mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
-+}
-+
-+static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
-+				      int time_alarm)
-+{
-+	u32 year, mon, mday, wday, hour, min, sec;
-+
-+	/*
-+	 * Read again until the field of the second is not changed which
-+	 * ensures all fields in the consistent state. Note that MTK_SEC must
-+	 * be read first. In this way, it guarantees the others remain not
-+	 * changed when the results for two MTK_SEC consecutive reads are same.
-+	 */
-+	do {
-+		sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
-+		min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
-+		hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
-+		wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
-+		mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
-+		mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
-+		year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
-+	} while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
-+
-+	tm->tm_sec  = sec;
-+	tm->tm_min  = min;
-+	tm->tm_hour = hour;
-+	tm->tm_wday = wday;
-+	tm->tm_mday = mday;
-+	tm->tm_mon  = mon - 1;
-+
-+	/* Rebase to the absolute year which userspace queries */
-+	tm->tm_year = year + MTK_RTC_TM_YR_OFFSET;
-+}
-+
-+static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
-+				      int time_alarm)
-+{
-+	u32 year;
-+
-+	/* Rebase to the relative year which RTC hardware requires */
-+	year = tm->tm_year - MTK_RTC_TM_YR_OFFSET;
-+
-+	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
-+	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
-+	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
-+	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
-+	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
-+	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
-+	mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
-+}
-+
-+static irqreturn_t mtk_rtc_alarmirq(int irq, void *id)
-+{
-+	struct mtk_rtc *hw = (struct mtk_rtc *)id;
-+	u32 irq_sta;
-+
-+	irq_sta = mtk_r32(hw, MTK_RTC_INT);
-+	if (irq_sta & RTC_INT_AL_STA) {
-+		/* Stop alarm also implicitly disables the alarm interrupt */
-+		mtk_w32(hw, MTK_RTC_AL_CTL, 0);
-+		rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF);
-+
-+		/* Ack alarm interrupt status */
-+		mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
-+		return IRQ_HANDLED;
-+	}
-+
-+	return IRQ_NONE;
-+}
-+
-+static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm)
-+{
-+	struct mtk_rtc *hw = dev_get_drvdata(dev);
-+
-+	mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC);
-+
-+	return rtc_valid_tm(tm);
-+}
-+
-+static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm)
-+{
-+	struct mtk_rtc *hw = dev_get_drvdata(dev);
-+
-+	if (!MTK_RTC_TM_YR_VALID(tm->tm_year))
-+		return -EINVAL;
-+
-+	/* Stop time counter before setting a new one*/
-+	mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP);
-+
-+	mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC);
-+
-+	/* Restart the time counter */
-+	mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
-+
-+	return 0;
-+}
-+
-+static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
-+{
-+	struct mtk_rtc *hw = dev_get_drvdata(dev);
-+	struct rtc_time *alrm_tm = &wkalrm->time;
-+
-+	mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL);
-+
-+	wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
-+	wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);
-+
-+	return 0;
-+}
-+
-+static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
-+{
-+	struct mtk_rtc *hw = dev_get_drvdata(dev);
-+	struct rtc_time *alrm_tm = &wkalrm->time;
-+
-+	if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year))
-+		return -EINVAL;
-+
-+	/*
-+	 * Stop the alarm also implicitly including disables interrupt before
-+	 * setting a new one.
-+	 */
-+	mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN);
-+
-+	/*
-+	 * Avoid contention between mtk_rtc_setalarm and IRQ handler so that
-+	 * disabling the interrupt and awaiting for pending IRQ handler to
-+	 * complete.
-+	 */
-+	synchronize_irq(hw->irq);
-+
-+	mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL);
-+
-+	/* Restart the alarm with the new setup */
-+	mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);
-+
-+	return 0;
-+}
-+
-+static const struct rtc_class_ops mtk_rtc_ops = {
-+	.read_time		= mtk_rtc_gettime,
-+	.set_time		= mtk_rtc_settime,
-+	.read_alarm		= mtk_rtc_getalarm,
-+	.set_alarm		= mtk_rtc_setalarm,
-+};
-+
-+static const struct of_device_id mtk_rtc_match[] = {
-+	{ .compatible = "mediatek,mt7622-rtc" },
-+	{ .compatible = "mediatek,soc-rtc" },
-+	{},
-+};
-+
-+static int mtk_rtc_probe(struct platform_device *pdev)
-+{
-+	struct mtk_rtc *hw;
-+	struct resource *res;
-+	int ret;
-+
-+	hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
-+	if (!hw)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, hw);
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	hw->base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(hw->base))
-+		return PTR_ERR(hw->base);
-+
-+	hw->clk = devm_clk_get(&pdev->dev, "rtc");
-+	if (IS_ERR(hw->clk)) {
-+		dev_err(&pdev->dev, "No clock\n");
-+		return PTR_ERR(hw->clk);
-+	}
-+
-+	ret = clk_prepare_enable(hw->clk);
-+	if (ret)
-+		return ret;
-+
-+	hw->irq = platform_get_irq(pdev, 0);
-+	if (hw->irq < 0) {
-+		dev_err(&pdev->dev, "No IRQ resource\n");
-+		ret = hw->irq;
-+		goto err;
-+	}
-+
-+	ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq,
-+			       0, dev_name(&pdev->dev), hw);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Can't request IRQ\n");
-+		goto err;
-+	}
-+
-+	mtk_rtc_hw_init(hw);
-+
-+	device_init_wakeup(&pdev->dev, true);
-+
-+	hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
-+					   &mtk_rtc_ops, THIS_MODULE);
-+	if (IS_ERR(hw->rtc)) {
-+		ret = PTR_ERR(hw->rtc);
-+		dev_err(&pdev->dev, "Unable to register device\n");
-+		goto err;
-+	}
-+
-+	return 0;
-+err:
-+	clk_disable_unprepare(hw->clk);
-+
-+	return ret;
-+}
-+
-+static int mtk_rtc_remove(struct platform_device *pdev)
-+{
-+	struct mtk_rtc *hw = platform_get_drvdata(pdev);
-+
-+	clk_disable_unprepare(hw->clk);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int mtk_rtc_suspend(struct device *dev)
-+{
-+	struct mtk_rtc *hw = dev_get_drvdata(dev);
-+
-+	if (device_may_wakeup(dev))
-+		enable_irq_wake(hw->irq);
-+
-+	return 0;
-+}
-+
-+static int mtk_rtc_resume(struct device *dev)
-+{
-+	struct mtk_rtc *hw = dev_get_drvdata(dev);
-+
-+	if (device_may_wakeup(dev))
-+		disable_irq_wake(hw->irq);
-+
-+	return 0;
-+}
-+
-+static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume);
-+
-+#define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops)
-+#else	/* CONFIG_PM */
-+#define MTK_RTC_PM_OPS NULL
-+#endif	/* CONFIG_PM */
-+
-+static struct platform_driver mtk_rtc_driver = {
-+	.probe	= mtk_rtc_probe,
-+	.remove	= mtk_rtc_remove,
-+	.driver = {
-+		.name = MTK_RTC_DEV,
-+		.of_match_table = mtk_rtc_match,
-+		.pm = MTK_RTC_PM_OPS,
-+	},
-+};
-+
-+module_platform_driver(mtk_rtc_driver);
-+
-+MODULE_DESCRIPTION("MediaTek SoC based RTC Driver");
-+MODULE_AUTHOR("Sean Wang <[email protected]>");
-+MODULE_LICENSE("GPL");

target/linux/mediatek/patches-4.14/0139-rtc-mediatek-enhance-the-description-for-MediaTek-PM.patch

@@ -1,39 +0,0 @@
-From ff4f8c2c894f1e6b5b5551571e22b2f947545bff Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Mon, 23 Oct 2017 15:16:46 +0800
-Subject: [PATCH 139/224] rtc: mediatek: enhance the description for MediaTek
- PMIC based RTC
-
-Give a better description for original MediaTek RTC driver as PMIC based
-RTC in order to distinguish SoC based RTC. Also turning all words with
-Mediatek to MediaTek here.
-
-Cc: Eddie Huang <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Acked-by: Eddie Huang <[email protected]>
-Signed-off-by: Alexandre Belloni <[email protected]>
----
- drivers/rtc/Kconfig | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -1706,14 +1706,14 @@ config RTC_DRV_MOXART
- 	   will be called rtc-moxart
- 
- config RTC_DRV_MT6397
--	tristate "Mediatek Real Time Clock driver"
-+	tristate "MediaTek PMIC based RTC"
- 	depends on MFD_MT6397 || (COMPILE_TEST && IRQ_DOMAIN)
- 	help
--	  This selects the Mediatek(R) RTC driver. RTC is part of Mediatek
-+	  This selects the MediaTek(R) RTC driver. RTC is part of MediaTek
- 	  MT6397 PMIC. You should enable MT6397 PMIC MFD before select
--	  Mediatek(R) RTC driver.
-+	  MediaTek(R) RTC driver.
- 
--	  If you want to use Mediatek(R) RTC interface, select Y or M here.
-+	  If you want to use MediaTek(R) RTC interface, select Y or M here.
- 
- config RTC_DRV_MT7622
- 	tristate "MediaTek SoC based RTC"

target/linux/mediatek/patches-4.14/0140-mtd-nand-mtk-change-the-compile-sequence-of-mtk_nand.patch

@@ -1,31 +0,0 @@
-From 71f568692a6d0a746d72c32d46a1bc09486b9dbb Mon Sep 17 00:00:00 2001
-From: Xiaolei Li <[email protected]>
-Date: Sat, 28 Oct 2017 14:52:23 +0800
-Subject: [PATCH 140/224] mtd: nand: mtk: change the compile sequence of
- mtk_nand.o and mtk_ecc.o
-
-There will get mtk ecc handler during mtk nand probe now.
-If mtk ecc module is not initialized, then mtk nand probe will return
--EPROBE_DEFER, and retry later.
-
-Change the compile sequence of mtk_nand.o and mtk_ecc.o, initialize mtk
-ecc module before mtk nand module. This makes mtk nand module initialized
-as soon as possible.
-
-Signed-off-by: Xiaolei Li <[email protected]>
-Signed-off-by: Boris Brezillon <[email protected]>
----
- drivers/mtd/nand/Makefile | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -59,7 +59,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_n
- obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
- obj-$(CONFIG_MTD_NAND_QCOM)		+= qcom_nandc.o
--obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_nand.o mtk_ecc.o
-+obj-$(CONFIG_MTD_NAND_MTK)		+= mtk_ecc.o mtk_nand.o
- 
- nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
- nand-objs += nand_amd.o

target/linux/mediatek/patches-4.14/0142-mmc-dt-bindings-Add-reg-source_cg-latch-ck-for-Media.patch

@@ -1,60 +0,0 @@
-From 9ff279fef1a47a152993bf23f8d75fd233c27015 Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:28 +0800
-Subject: [PATCH 142/224] mmc: dt-bindings: Add reg/source_cg/latch-ck for
- Mediatek MMC bindings
-
-Change the comptiable for support of multi-platform
-Make compatible explicit, as MMC host of mt8173 has difference with
-mt8135(mt8173 supports hs400 and hs400_tune),so that need separate
-mt8173/mt8135 compatible name.
-Add description for reg
-Add description for source_cg
-Add description for mediatek,latch-ck
-Note that source_cg and mediatek,latch-ck are optional for some projects,
-eg, MT2701 do not have source_cg, and MT2712 do not need
-mediatek,latch-ck
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Acked-by: Rob Herring <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 18 +++++++++++++++---
- 1 file changed, 15 insertions(+), 3 deletions(-)
-
---- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
-+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
-@@ -7,10 +7,18 @@ This file documents differences between
- and the properties used by the msdc driver.
- 
- Required properties:
--- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc"
-+- compatible: value should be either of the following.
-+	"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
-+	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
-+	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
-+	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
-+- reg: physical base address of the controller and length
- - interrupts: Should contain MSDC interrupt number
--- clocks: MSDC source clock, HCLK
--- clock-names: "source", "hclk"
-+- clocks: Should contain phandle for the clock feeding the MMC controller
-+- clock-names: Should contain the following:
-+	"source" - source clock (required)
-+	"hclk" - HCLK which used for host (required)
-+	"source_cg" - independent source clock gate (required for MT2712)
- - pinctrl-names: should be "default", "state_uhs"
- - pinctrl-0: should contain default/high speed pin ctrl
- - pinctrl-1: should contain uhs mode pin ctrl
-@@ -30,6 +38,10 @@ Optional properties:
- - mediatek,hs400-cmd-resp-sel-rising:  HS400 command response sample selection
- 				       If present,HS400 command responses are sampled on rising edges.
- 				       If not present,HS400 command responses are sampled on falling edges.
-+- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
-+		     error caused by stop clock(fifo full)
-+		     Valid range = [0:0x7]. if not present, default value is 0.
-+		     applied to compatible "mediatek,mt2701-mmc".
- 
- Examples:
- mmc0: mmc@11230000 {

target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch

@@ -1,187 +0,0 @@
-From 8119f3e147deaf97a66e953fecf3d2b0edbb07fd Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:29 +0800
-Subject: [PATCH 143/224] mmc: mediatek: add support of mt2701/mt2712
-
-mt2701/mt2712 has 12bit clock div, which is not compatible with
-mt8135/mt8173. and, some additional features will be added in
-mt2701/mt2712, so that need distinguish it by comatibale name.
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 82 +++++++++++++++++++++++++++++++++++++++--------
- 1 file changed, 69 insertions(+), 13 deletions(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -95,6 +95,9 @@
- #define MSDC_CFG_CKDIV          (0xff << 8)	/* RW */
- #define MSDC_CFG_CKMOD          (0x3 << 16)	/* RW */
- #define MSDC_CFG_HS400_CK_MODE  (0x1 << 18)	/* RW */
-+#define MSDC_CFG_HS400_CK_MODE_EXTRA  (0x1 << 22)	/* RW */
-+#define MSDC_CFG_CKDIV_EXTRA    (0xfff << 8)	/* RW */
-+#define MSDC_CFG_CKMOD_EXTRA    (0x3 << 20)	/* RW */
- 
- /* MSDC_IOCON mask */
- #define MSDC_IOCON_SDR104CKS    (0x1 << 0)	/* RW */
-@@ -297,6 +300,10 @@ struct msdc_save_para {
- 	u32 emmc50_cfg0;
- };
- 
-+struct mtk_mmc_compatible {
-+	u8 clk_div_bits;
-+};
-+
- struct msdc_tune_para {
- 	u32 iocon;
- 	u32 pad_tune;
-@@ -311,6 +318,7 @@ struct msdc_delay_phase {
- 
- struct msdc_host {
- 	struct device *dev;
-+	const struct mtk_mmc_compatible *dev_comp;
- 	struct mmc_host *mmc;	/* mmc structure */
- 	int cmd_rsp;
- 
-@@ -352,6 +360,31 @@ struct msdc_host {
- 	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
- };
- 
-+static const struct mtk_mmc_compatible mt8135_compat = {
-+	.clk_div_bits = 8,
-+};
-+
-+static const struct mtk_mmc_compatible mt8173_compat = {
-+	.clk_div_bits = 8,
-+};
-+
-+static const struct mtk_mmc_compatible mt2701_compat = {
-+	.clk_div_bits = 12,
-+};
-+
-+static const struct mtk_mmc_compatible mt2712_compat = {
-+	.clk_div_bits = 12,
-+};
-+
-+static const struct of_device_id msdc_of_ids[] = {
-+	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
-+	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
-+	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
-+	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, msdc_of_ids);
-+
- static void sdr_set_bits(void __iomem *reg, u32 bs)
- {
- 	u32 val = readl(reg);
-@@ -511,7 +544,12 @@ static void msdc_set_timeout(struct msdc
- 		timeout = (ns + clk_ns - 1) / clk_ns + clks;
- 		/* in 1048576 sclk cycle unit */
- 		timeout = (timeout + (0x1 << 20) - 1) >> 20;
--		sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
-+		if (host->dev_comp->clk_div_bits == 8)
-+			sdr_get_field(host->base + MSDC_CFG,
-+				      MSDC_CFG_CKMOD, &mode);
-+		else
-+			sdr_get_field(host->base + MSDC_CFG,
-+				      MSDC_CFG_CKMOD_EXTRA, &mode);
- 		/*DDR mode will double the clk cycles for data timeout */
- 		timeout = mode >= 2 ? timeout * 2 : timeout;
- 		timeout = timeout > 1 ? timeout - 1 : 0;
-@@ -550,7 +588,11 @@ static void msdc_set_mclk(struct msdc_ho
- 
- 	flags = readl(host->base + MSDC_INTEN);
- 	sdr_clr_bits(host->base + MSDC_INTEN, flags);
--	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
-+	if (host->dev_comp->clk_div_bits == 8)
-+		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
-+	else
-+		sdr_clr_bits(host->base + MSDC_CFG,
-+			     MSDC_CFG_HS400_CK_MODE_EXTRA);
- 	if (timing == MMC_TIMING_UHS_DDR50 ||
- 	    timing == MMC_TIMING_MMC_DDR52 ||
- 	    timing == MMC_TIMING_MMC_HS400) {
-@@ -570,8 +612,12 @@ static void msdc_set_mclk(struct msdc_ho
- 
- 		if (timing == MMC_TIMING_MMC_HS400 &&
- 		    hz >= (host->src_clk_freq >> 1)) {
--			sdr_set_bits(host->base + MSDC_CFG,
--				     MSDC_CFG_HS400_CK_MODE);
-+			if (host->dev_comp->clk_div_bits == 8)
-+				sdr_set_bits(host->base + MSDC_CFG,
-+					     MSDC_CFG_HS400_CK_MODE);
-+			else
-+				sdr_set_bits(host->base + MSDC_CFG,
-+					     MSDC_CFG_HS400_CK_MODE_EXTRA);
- 			sclk = host->src_clk_freq >> 1;
- 			div = 0; /* div is ignore when bit18 is set */
- 		}
-@@ -589,8 +635,15 @@ static void msdc_set_mclk(struct msdc_ho
- 			sclk = (host->src_clk_freq >> 2) / div;
- 		}
- 	}
--	sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
--		      (mode << 8) | div);
-+	if (host->dev_comp->clk_div_bits == 8)
-+		sdr_set_field(host->base + MSDC_CFG,
-+			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
-+			      (mode << 8) | div);
-+	else
-+		sdr_set_field(host->base + MSDC_CFG,
-+			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
-+			      (mode << 12) | div);
-+
- 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
- 	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
- 		cpu_relax();
-@@ -1620,12 +1673,17 @@ static int msdc_drv_probe(struct platfor
- 	struct mmc_host *mmc;
- 	struct msdc_host *host;
- 	struct resource *res;
-+	const struct of_device_id *of_id;
- 	int ret;
- 
- 	if (!pdev->dev.of_node) {
- 		dev_err(&pdev->dev, "No DT found\n");
- 		return -EINVAL;
- 	}
-+
-+	of_id = of_match_node(msdc_of_ids, pdev->dev.of_node);
-+	if (!of_id)
-+		return -EINVAL;
- 	/* Allocate MMC host for this device */
- 	mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
- 	if (!mmc)
-@@ -1689,11 +1747,15 @@ static int msdc_drv_probe(struct platfor
- 	msdc_of_property_parse(pdev, host);
- 
- 	host->dev = &pdev->dev;
-+	host->dev_comp = of_id->data;
- 	host->mmc = mmc;
- 	host->src_clk_freq = clk_get_rate(host->src_clk);
- 	/* Set host parameters to mmc */
- 	mmc->ops = &mt_msdc_ops;
--	mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
-+	if (host->dev_comp->clk_div_bits == 8)
-+		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
-+	else
-+		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
- 
- 	mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
- 	/* MMC core transfer sizes tunable parameters */
-@@ -1842,12 +1904,6 @@ static const struct dev_pm_ops msdc_dev_
- 	SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
- };
- 
--static const struct of_device_id msdc_of_ids[] = {
--	{   .compatible = "mediatek,mt8135-mmc", },
--	{}
--};
--MODULE_DEVICE_TABLE(of, msdc_of_ids);
--
- static struct platform_driver mt_msdc_driver = {
- 	.probe = msdc_drv_probe,
- 	.remove = msdc_drv_remove,

target/linux/mediatek/patches-4.14/0144-dt-bindings-ARM-Mediatek-Document-bindings-for-MT271.patch

@@ -1,196 +0,0 @@
-From 815d90faddd22e05f05623086a9c42187fbfb1d8 Mon Sep 17 00:00:00 2001
-From: "[email protected]" <[email protected]>
-Date: Mon, 23 Oct 2017 12:10:32 +0800
-Subject: [PATCH 144/224] dt-bindings: ARM: Mediatek: Document bindings for
- MT2712
-
-This patch adds the binding documentation for apmixedsys, bdpsys,
-imgsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, pericfg, topckgen,
-vdecsys and vencsys for Mediatek MT2712.
-
-Acked-by: Rob Herring <[email protected]>
-Signed-off-by: Weiyi Lu <[email protected]>
-Signed-off-by: Stephen Boyd <[email protected]>
----
- .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  1 +
- .../bindings/arm/mediatek/mediatek,bdpsys.txt      |  1 +
- .../bindings/arm/mediatek/mediatek,imgsys.txt      |  1 +
- .../bindings/arm/mediatek/mediatek,infracfg.txt    |  1 +
- .../bindings/arm/mediatek/mediatek,jpgdecsys.txt   | 22 ++++++++++++++++++++++
- .../bindings/arm/mediatek/mediatek,mcucfg.txt      | 22 ++++++++++++++++++++++
- .../bindings/arm/mediatek/mediatek,mfgcfg.txt      | 22 ++++++++++++++++++++++
- .../bindings/arm/mediatek/mediatek,mmsys.txt       |  1 +
- .../bindings/arm/mediatek/mediatek,pericfg.txt     |  1 +
- .../bindings/arm/mediatek/mediatek,topckgen.txt    |  1 +
- .../bindings/arm/mediatek/mediatek,vdecsys.txt     |  1 +
- .../bindings/arm/mediatek/mediatek,vencsys.txt     |  1 +
- 12 files changed, 75 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt
- create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
- create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
-@@ -7,6 +7,7 @@ Required Properties:
- 
- - compatible: Should be one of:
- 	- "mediatek,mt2701-apmixedsys"
-+	- "mediatek,mt2712-apmixedsys", "syscon"
- 	- "mediatek,mt6797-apmixedsys"
- 	- "mediatek,mt8135-apmixedsys"
- 	- "mediatek,mt8173-apmixedsys"
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
-@@ -7,6 +7,7 @@ Required Properties:
- 
- - compatible: Should be:
- 	- "mediatek,mt2701-bdpsys", "syscon"
-+	- "mediatek,mt2712-bdpsys", "syscon"
- - #clock-cells: Must be 1
- 
- The bdpsys controller uses the common clk binding from
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
-@@ -7,6 +7,7 @@ Required Properties:
- 
- - compatible: Should be one of:
- 	- "mediatek,mt2701-imgsys", "syscon"
-+	- "mediatek,mt2712-imgsys", "syscon"
- 	- "mediatek,mt6797-imgsys", "syscon"
- 	- "mediatek,mt8173-imgsys", "syscon"
- - #clock-cells: Must be 1
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
-@@ -8,6 +8,7 @@ Required Properties:
- 
- - compatible: Should be one of:
- 	- "mediatek,mt2701-infracfg", "syscon"
-+	- "mediatek,mt2712-infracfg", "syscon"
- 	- "mediatek,mt6797-infracfg", "syscon"
- 	- "mediatek,mt8135-infracfg", "syscon"
- 	- "mediatek,mt8173-infracfg", "syscon"
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt
-@@ -0,0 +1,22 @@
-+Mediatek jpgdecsys controller
-+============================
-+
-+The Mediatek jpgdecsys controller provides various clocks to the system.
-+
-+Required Properties:
-+
-+- compatible: Should be:
-+	- "mediatek,mt2712-jpgdecsys", "syscon"
-+- #clock-cells: Must be 1
-+
-+The jpgdecsys controller uses the common clk binding from
-+Documentation/devicetree/bindings/clock/clock-bindings.txt
-+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-+
-+Example:
-+
-+jpgdecsys: syscon@19000000 {
-+	compatible = "mediatek,mt2712-jpgdecsys", "syscon";
-+	reg = <0 0x19000000 0 0x1000>;
-+	#clock-cells = <1>;
-+};
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
-@@ -0,0 +1,22 @@
-+Mediatek mcucfg controller
-+============================
-+
-+The Mediatek mcucfg controller provides various clocks to the system.
-+
-+Required Properties:
-+
-+- compatible: Should be one of:
-+	- "mediatek,mt2712-mcucfg", "syscon"
-+- #clock-cells: Must be 1
-+
-+The mcucfg controller uses the common clk binding from
-+Documentation/devicetree/bindings/clock/clock-bindings.txt
-+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-+
-+Example:
-+
-+mcucfg: syscon@10220000 {
-+	compatible = "mediatek,mt2712-mcucfg", "syscon";
-+	reg = <0 0x10220000 0 0x1000>;
-+	#clock-cells = <1>;
-+};
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
-@@ -0,0 +1,22 @@
-+Mediatek mfgcfg controller
-+============================
-+
-+The Mediatek mfgcfg controller provides various clocks to the system.
-+
-+Required Properties:
-+
-+- compatible: Should be one of:
-+	- "mediatek,mt2712-mfgcfg", "syscon"
-+- #clock-cells: Must be 1
-+
-+The mfgcfg controller uses the common clk binding from
-+Documentation/devicetree/bindings/clock/clock-bindings.txt
-+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-+
-+Example:
-+
-+mfgcfg: syscon@13000000 {
-+	compatible = "mediatek,mt2712-mfgcfg", "syscon";
-+	reg = <0 0x13000000 0 0x1000>;
-+	#clock-cells = <1>;
-+};
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
-@@ -7,6 +7,7 @@ Required Properties:
- 
- - compatible: Should be one of:
- 	- "mediatek,mt2701-mmsys", "syscon"
-+	- "mediatek,mt2712-mmsys", "syscon"
- 	- "mediatek,mt6797-mmsys", "syscon"
- 	- "mediatek,mt8173-mmsys", "syscon"
- - #clock-cells: Must be 1
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
-@@ -8,6 +8,7 @@ Required Properties:
- 
- - compatible: Should be one of:
- 	- "mediatek,mt2701-pericfg", "syscon"
-+	- "mediatek,mt2712-pericfg", "syscon"
- 	- "mediatek,mt8135-pericfg", "syscon"
- 	- "mediatek,mt8173-pericfg", "syscon"
- - #clock-cells: Must be 1
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
-@@ -7,6 +7,7 @@ Required Properties:
- 
- - compatible: Should be one of:
- 	- "mediatek,mt2701-topckgen"
-+	- "mediatek,mt2712-topckgen", "syscon"
- 	- "mediatek,mt6797-topckgen"
- 	- "mediatek,mt8135-topckgen"
- 	- "mediatek,mt8173-topckgen"
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
-@@ -7,6 +7,7 @@ Required Properties:
- 
- - compatible: Should be one of:
- 	- "mediatek,mt2701-vdecsys", "syscon"
-+	- "mediatek,mt2712-vdecsys", "syscon"
- 	- "mediatek,mt6797-vdecsys", "syscon"
- 	- "mediatek,mt8173-vdecsys", "syscon"
- - #clock-cells: Must be 1
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
-@@ -6,6 +6,7 @@ The Mediatek vencsys controller provides
- Required Properties:
- 
- - compatible: Should be one of:
-+	- "mediatek,mt2712-vencsys", "syscon"
- 	- "mediatek,mt6797-vencsys", "syscon"
- 	- "mediatek,mt8173-vencsys", "syscon"
- - #clock-cells: Must be 1

target/linux/mediatek/patches-4.14/0145-clk-mediatek-Add-dt-bindings-for-MT2712-clocks.patch

@@ -1,446 +0,0 @@
-From 8a64bf0c04a4b7670cf56be5b0ae63fe9d6ecd56 Mon Sep 17 00:00:00 2001
-From: "[email protected]" <[email protected]>
-Date: Mon, 23 Oct 2017 12:10:33 +0800
-Subject: [PATCH 145/224] clk: mediatek: Add dt-bindings for MT2712 clocks
-
-Add MT2712 clock dt-bindings, include topckgen, apmixedsys,
-infracfg, pericfg, mcucfg and subsystem clocks.
-
-Signed-off-by: Weiyi Lu <[email protected]>
-Acked-by: Rob Herring <[email protected]>
-Signed-off-by: Stephen Boyd <[email protected]>
----
- include/dt-bindings/clock/mt2712-clk.h | 427 +++++++++++++++++++++++++++++++++
- 1 file changed, 427 insertions(+)
- create mode 100644 include/dt-bindings/clock/mt2712-clk.h
-
---- /dev/null
-+++ b/include/dt-bindings/clock/mt2712-clk.h
-@@ -0,0 +1,427 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Weiyi Lu <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_MT2712_H
-+#define _DT_BINDINGS_CLK_MT2712_H
-+
-+/* APMIXEDSYS */
-+
-+#define CLK_APMIXED_MAINPLL		0
-+#define CLK_APMIXED_UNIVPLL		1
-+#define CLK_APMIXED_VCODECPLL		2
-+#define CLK_APMIXED_VENCPLL		3
-+#define CLK_APMIXED_APLL1		4
-+#define CLK_APMIXED_APLL2		5
-+#define CLK_APMIXED_LVDSPLL		6
-+#define CLK_APMIXED_LVDSPLL2		7
-+#define CLK_APMIXED_MSDCPLL		8
-+#define CLK_APMIXED_MSDCPLL2		9
-+#define CLK_APMIXED_TVDPLL		10
-+#define CLK_APMIXED_MMPLL		11
-+#define CLK_APMIXED_ARMCA35PLL		12
-+#define CLK_APMIXED_ARMCA72PLL		13
-+#define CLK_APMIXED_ETHERPLL		14
-+#define CLK_APMIXED_NR_CLK		15
-+
-+/* TOPCKGEN */
-+
-+#define CLK_TOP_ARMCA35PLL		0
-+#define CLK_TOP_ARMCA35PLL_600M		1
-+#define CLK_TOP_ARMCA35PLL_400M		2
-+#define CLK_TOP_ARMCA72PLL		3
-+#define CLK_TOP_SYSPLL			4
-+#define CLK_TOP_SYSPLL_D2		5
-+#define CLK_TOP_SYSPLL1_D2		6
-+#define CLK_TOP_SYSPLL1_D4		7
-+#define CLK_TOP_SYSPLL1_D8		8
-+#define CLK_TOP_SYSPLL1_D16		9
-+#define CLK_TOP_SYSPLL_D3		10
-+#define CLK_TOP_SYSPLL2_D2		11
-+#define CLK_TOP_SYSPLL2_D4		12
-+#define CLK_TOP_SYSPLL_D5		13
-+#define CLK_TOP_SYSPLL3_D2		14
-+#define CLK_TOP_SYSPLL3_D4		15
-+#define CLK_TOP_SYSPLL_D7		16
-+#define CLK_TOP_SYSPLL4_D2		17
-+#define CLK_TOP_SYSPLL4_D4		18
-+#define CLK_TOP_UNIVPLL			19
-+#define CLK_TOP_UNIVPLL_D7		20
-+#define CLK_TOP_UNIVPLL_D26		21
-+#define CLK_TOP_UNIVPLL_D52		22
-+#define CLK_TOP_UNIVPLL_D104		23
-+#define CLK_TOP_UNIVPLL_D208		24
-+#define CLK_TOP_UNIVPLL_D2		25
-+#define CLK_TOP_UNIVPLL1_D2		26
-+#define CLK_TOP_UNIVPLL1_D4		27
-+#define CLK_TOP_UNIVPLL1_D8		28
-+#define CLK_TOP_UNIVPLL_D3		29
-+#define CLK_TOP_UNIVPLL2_D2		30
-+#define CLK_TOP_UNIVPLL2_D4		31
-+#define CLK_TOP_UNIVPLL2_D8		32
-+#define CLK_TOP_UNIVPLL_D5		33
-+#define CLK_TOP_UNIVPLL3_D2		34
-+#define CLK_TOP_UNIVPLL3_D4		35
-+#define CLK_TOP_UNIVPLL3_D8		36
-+#define CLK_TOP_F_MP0_PLL1		37
-+#define CLK_TOP_F_MP0_PLL2		38
-+#define CLK_TOP_F_BIG_PLL1		39
-+#define CLK_TOP_F_BIG_PLL2		40
-+#define CLK_TOP_F_BUS_PLL1		41
-+#define CLK_TOP_F_BUS_PLL2		42
-+#define CLK_TOP_APLL1			43
-+#define CLK_TOP_APLL1_D2		44
-+#define CLK_TOP_APLL1_D4		45
-+#define CLK_TOP_APLL1_D8		46
-+#define CLK_TOP_APLL1_D16		47
-+#define CLK_TOP_APLL2			48
-+#define CLK_TOP_APLL2_D2		49
-+#define CLK_TOP_APLL2_D4		50
-+#define CLK_TOP_APLL2_D8		51
-+#define CLK_TOP_APLL2_D16		52
-+#define CLK_TOP_LVDSPLL			53
-+#define CLK_TOP_LVDSPLL_D2		54
-+#define CLK_TOP_LVDSPLL_D4		55
-+#define CLK_TOP_LVDSPLL_D8		56
-+#define CLK_TOP_LVDSPLL2		57
-+#define CLK_TOP_LVDSPLL2_D2		58
-+#define CLK_TOP_LVDSPLL2_D4		59
-+#define CLK_TOP_LVDSPLL2_D8		60
-+#define CLK_TOP_ETHERPLL_125M		61
-+#define CLK_TOP_ETHERPLL_50M		62
-+#define CLK_TOP_CVBS			63
-+#define CLK_TOP_CVBS_D2			64
-+#define CLK_TOP_SYS_26M			65
-+#define CLK_TOP_MMPLL			66
-+#define CLK_TOP_MMPLL_D2		67
-+#define CLK_TOP_VENCPLL			68
-+#define CLK_TOP_VENCPLL_D2		69
-+#define CLK_TOP_VCODECPLL		70
-+#define CLK_TOP_VCODECPLL_D2		71
-+#define CLK_TOP_TVDPLL			72
-+#define CLK_TOP_TVDPLL_D2		73
-+#define CLK_TOP_TVDPLL_D4		74
-+#define CLK_TOP_TVDPLL_D8		75
-+#define CLK_TOP_TVDPLL_429M		76
-+#define CLK_TOP_TVDPLL_429M_D2		77
-+#define CLK_TOP_TVDPLL_429M_D4		78
-+#define CLK_TOP_MSDCPLL			79
-+#define CLK_TOP_MSDCPLL_D2		80
-+#define CLK_TOP_MSDCPLL_D4		81
-+#define CLK_TOP_MSDCPLL2		82
-+#define CLK_TOP_MSDCPLL2_D2		83
-+#define CLK_TOP_MSDCPLL2_D4		84
-+#define CLK_TOP_CLK26M_D2		85
-+#define CLK_TOP_D2A_ULCLK_6P5M		86
-+#define CLK_TOP_VPLL3_DPIX		87
-+#define CLK_TOP_VPLL_DPIX		88
-+#define CLK_TOP_LTEPLL_FS26M		89
-+#define CLK_TOP_DMPLL			90
-+#define CLK_TOP_DSI0_LNTC		91
-+#define CLK_TOP_DSI1_LNTC		92
-+#define CLK_TOP_LVDSTX3_CLKDIG_CTS	93
-+#define CLK_TOP_LVDSTX_CLKDIG_CTS	94
-+#define CLK_TOP_CLKRTC_EXT		95
-+#define CLK_TOP_CLKRTC_INT		96
-+#define CLK_TOP_CSI0			97
-+#define CLK_TOP_CVBSPLL			98
-+#define CLK_TOP_AXI_SEL			99
-+#define CLK_TOP_MEM_SEL			100
-+#define CLK_TOP_MM_SEL			101
-+#define CLK_TOP_PWM_SEL			102
-+#define CLK_TOP_VDEC_SEL		103
-+#define CLK_TOP_VENC_SEL		104
-+#define CLK_TOP_MFG_SEL			105
-+#define CLK_TOP_CAMTG_SEL		106
-+#define CLK_TOP_UART_SEL		107
-+#define CLK_TOP_SPI_SEL			108
-+#define CLK_TOP_USB20_SEL		109
-+#define CLK_TOP_USB30_SEL		110
-+#define CLK_TOP_MSDC50_0_HCLK_SEL	111
-+#define CLK_TOP_MSDC50_0_SEL		112
-+#define CLK_TOP_MSDC30_1_SEL		113
-+#define CLK_TOP_MSDC30_2_SEL		114
-+#define CLK_TOP_MSDC30_3_SEL		115
-+#define CLK_TOP_AUDIO_SEL		116
-+#define CLK_TOP_AUD_INTBUS_SEL		117
-+#define CLK_TOP_PMICSPI_SEL		118
-+#define CLK_TOP_DPILVDS1_SEL		119
-+#define CLK_TOP_ATB_SEL			120
-+#define CLK_TOP_NR_SEL			121
-+#define CLK_TOP_NFI2X_SEL		122
-+#define CLK_TOP_IRDA_SEL		123
-+#define CLK_TOP_CCI400_SEL		124
-+#define CLK_TOP_AUD_1_SEL		125
-+#define CLK_TOP_AUD_2_SEL		126
-+#define CLK_TOP_MEM_MFG_IN_AS_SEL	127
-+#define CLK_TOP_AXI_MFG_IN_AS_SEL	128
-+#define CLK_TOP_SCAM_SEL		129
-+#define CLK_TOP_NFIECC_SEL		130
-+#define CLK_TOP_PE2_MAC_P0_SEL		131
-+#define CLK_TOP_PE2_MAC_P1_SEL		132
-+#define CLK_TOP_DPILVDS_SEL		133
-+#define CLK_TOP_MSDC50_3_HCLK_SEL	134
-+#define CLK_TOP_HDCP_SEL		135
-+#define CLK_TOP_HDCP_24M_SEL		136
-+#define CLK_TOP_RTC_SEL			137
-+#define CLK_TOP_SPINOR_SEL		138
-+#define CLK_TOP_APLL_SEL		139
-+#define CLK_TOP_APLL2_SEL		140
-+#define CLK_TOP_A1SYS_HP_SEL		141
-+#define CLK_TOP_A2SYS_HP_SEL		142
-+#define CLK_TOP_ASM_L_SEL		143
-+#define CLK_TOP_ASM_M_SEL		144
-+#define CLK_TOP_ASM_H_SEL		145
-+#define CLK_TOP_I2SO1_SEL		146
-+#define CLK_TOP_I2SO2_SEL		147
-+#define CLK_TOP_I2SO3_SEL		148
-+#define CLK_TOP_TDMO0_SEL		149
-+#define CLK_TOP_TDMO1_SEL		150
-+#define CLK_TOP_I2SI1_SEL		151
-+#define CLK_TOP_I2SI2_SEL		152
-+#define CLK_TOP_I2SI3_SEL		153
-+#define CLK_TOP_ETHER_125M_SEL		154
-+#define CLK_TOP_ETHER_50M_SEL		155
-+#define CLK_TOP_JPGDEC_SEL		156
-+#define CLK_TOP_SPISLV_SEL		157
-+#define CLK_TOP_ETHER_50M_RMII_SEL	158
-+#define CLK_TOP_CAM2TG_SEL		159
-+#define CLK_TOP_DI_SEL			160
-+#define CLK_TOP_TVD_SEL			161
-+#define CLK_TOP_I2C_SEL			162
-+#define CLK_TOP_PWM_INFRA_SEL		163
-+#define CLK_TOP_MSDC0P_AES_SEL		164
-+#define CLK_TOP_CMSYS_SEL		165
-+#define CLK_TOP_GCPU_SEL		166
-+#define CLK_TOP_AUD_APLL1_SEL		167
-+#define CLK_TOP_AUD_APLL2_SEL		168
-+#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL	169
-+#define CLK_TOP_APLL_DIV0		170
-+#define CLK_TOP_APLL_DIV1		171
-+#define CLK_TOP_APLL_DIV2		172
-+#define CLK_TOP_APLL_DIV3		173
-+#define CLK_TOP_APLL_DIV4		174
-+#define CLK_TOP_APLL_DIV5		175
-+#define CLK_TOP_APLL_DIV6		176
-+#define CLK_TOP_APLL_DIV7		177
-+#define CLK_TOP_APLL_DIV_PDN0		178
-+#define CLK_TOP_APLL_DIV_PDN1		179
-+#define CLK_TOP_APLL_DIV_PDN2		180
-+#define CLK_TOP_APLL_DIV_PDN3		181
-+#define CLK_TOP_APLL_DIV_PDN4		182
-+#define CLK_TOP_APLL_DIV_PDN5		183
-+#define CLK_TOP_APLL_DIV_PDN6		184
-+#define CLK_TOP_APLL_DIV_PDN7		185
-+#define CLK_TOP_NR_CLK			186
-+
-+/* INFRACFG */
-+
-+#define CLK_INFRA_DBGCLK		0
-+#define CLK_INFRA_GCE			1
-+#define CLK_INFRA_M4U			2
-+#define CLK_INFRA_KP			3
-+#define CLK_INFRA_AO_SPI0		4
-+#define CLK_INFRA_AO_SPI1		5
-+#define CLK_INFRA_AO_UART5		6
-+#define CLK_INFRA_NR_CLK		7
-+
-+/* PERICFG */
-+
-+#define CLK_PERI_NFI			0
-+#define CLK_PERI_THERM			1
-+#define CLK_PERI_PWM0			2
-+#define CLK_PERI_PWM1			3
-+#define CLK_PERI_PWM2			4
-+#define CLK_PERI_PWM3			5
-+#define CLK_PERI_PWM4			6
-+#define CLK_PERI_PWM5			7
-+#define CLK_PERI_PWM6			8
-+#define CLK_PERI_PWM7			9
-+#define CLK_PERI_PWM			10
-+#define CLK_PERI_AP_DMA			11
-+#define CLK_PERI_MSDC30_0		12
-+#define CLK_PERI_MSDC30_1		13
-+#define CLK_PERI_MSDC30_2		14
-+#define CLK_PERI_MSDC30_3		15
-+#define CLK_PERI_UART0			16
-+#define CLK_PERI_UART1			17
-+#define CLK_PERI_UART2			18
-+#define CLK_PERI_UART3			19
-+#define CLK_PERI_I2C0			20
-+#define CLK_PERI_I2C1			21
-+#define CLK_PERI_I2C2			22
-+#define CLK_PERI_I2C3			23
-+#define CLK_PERI_I2C4			24
-+#define CLK_PERI_AUXADC			25
-+#define CLK_PERI_SPI0			26
-+#define CLK_PERI_SPI			27
-+#define CLK_PERI_I2C5			28
-+#define CLK_PERI_SPI2			29
-+#define CLK_PERI_SPI3			30
-+#define CLK_PERI_SPI5			31
-+#define CLK_PERI_UART4			32
-+#define CLK_PERI_SFLASH			33
-+#define CLK_PERI_GMAC			34
-+#define CLK_PERI_PCIE0			35
-+#define CLK_PERI_PCIE1			36
-+#define CLK_PERI_GMAC_PCLK		37
-+#define CLK_PERI_MSDC50_0_EN		38
-+#define CLK_PERI_MSDC30_1_EN		39
-+#define CLK_PERI_MSDC30_2_EN		40
-+#define CLK_PERI_MSDC30_3_EN		41
-+#define CLK_PERI_MSDC50_0_HCLK_EN	42
-+#define CLK_PERI_MSDC50_3_HCLK_EN	43
-+#define CLK_PERI_NR_CLK			44
-+
-+/* MCUCFG */
-+
-+#define CLK_MCU_MP0_SEL			0
-+#define CLK_MCU_MP2_SEL			1
-+#define CLK_MCU_BUS_SEL			2
-+#define CLK_MCU_NR_CLK			3
-+
-+/* MFGCFG */
-+
-+#define CLK_MFG_BG3D			0
-+#define CLK_MFG_NR_CLK			1
-+
-+/* MMSYS */
-+
-+#define CLK_MM_SMI_COMMON		0
-+#define CLK_MM_SMI_LARB0		1
-+#define CLK_MM_CAM_MDP			2
-+#define CLK_MM_MDP_RDMA0		3
-+#define CLK_MM_MDP_RDMA1		4
-+#define CLK_MM_MDP_RSZ0			5
-+#define CLK_MM_MDP_RSZ1			6
-+#define CLK_MM_MDP_RSZ2			7
-+#define CLK_MM_MDP_TDSHP0		8
-+#define CLK_MM_MDP_TDSHP1		9
-+#define CLK_MM_MDP_CROP			10
-+#define CLK_MM_MDP_WDMA			11
-+#define CLK_MM_MDP_WROT0		12
-+#define CLK_MM_MDP_WROT1		13
-+#define CLK_MM_FAKE_ENG			14
-+#define CLK_MM_MUTEX_32K		15
-+#define CLK_MM_DISP_OVL0		16
-+#define CLK_MM_DISP_OVL1		17
-+#define CLK_MM_DISP_RDMA0		18
-+#define CLK_MM_DISP_RDMA1		19
-+#define CLK_MM_DISP_RDMA2		20
-+#define CLK_MM_DISP_WDMA0		21
-+#define CLK_MM_DISP_WDMA1		22
-+#define CLK_MM_DISP_COLOR0		23
-+#define CLK_MM_DISP_COLOR1		24
-+#define CLK_MM_DISP_AAL			25
-+#define CLK_MM_DISP_GAMMA		26
-+#define CLK_MM_DISP_UFOE		27
-+#define CLK_MM_DISP_SPLIT0		28
-+#define CLK_MM_DISP_OD			29
-+#define CLK_MM_DISP_PWM0_MM		30
-+#define CLK_MM_DISP_PWM0_26M		31
-+#define CLK_MM_DISP_PWM1_MM		32
-+#define CLK_MM_DISP_PWM1_26M		33
-+#define CLK_MM_DSI0_ENGINE		34
-+#define CLK_MM_DSI0_DIGITAL		35
-+#define CLK_MM_DSI1_ENGINE		36
-+#define CLK_MM_DSI1_DIGITAL		37
-+#define CLK_MM_DPI_PIXEL		38
-+#define CLK_MM_DPI_ENGINE		39
-+#define CLK_MM_DPI1_PIXEL		40
-+#define CLK_MM_DPI1_ENGINE		41
-+#define CLK_MM_LVDS_PIXEL		42
-+#define CLK_MM_LVDS_CTS			43
-+#define CLK_MM_SMI_LARB4		44
-+#define CLK_MM_SMI_COMMON1		45
-+#define CLK_MM_SMI_LARB5		46
-+#define CLK_MM_MDP_RDMA2		47
-+#define CLK_MM_MDP_TDSHP2		48
-+#define CLK_MM_DISP_OVL2		49
-+#define CLK_MM_DISP_WDMA2		50
-+#define CLK_MM_DISP_COLOR2		51
-+#define CLK_MM_DISP_AAL1		52
-+#define CLK_MM_DISP_OD1			53
-+#define CLK_MM_LVDS1_PIXEL		54
-+#define CLK_MM_LVDS1_CTS		55
-+#define CLK_MM_SMI_LARB7		56
-+#define CLK_MM_MDP_RDMA3		57
-+#define CLK_MM_MDP_WROT2		58
-+#define CLK_MM_DSI2			59
-+#define CLK_MM_DSI2_DIGITAL		60
-+#define CLK_MM_DSI3			61
-+#define CLK_MM_DSI3_DIGITAL		62
-+#define CLK_MM_NR_CLK			63
-+
-+/* IMGSYS */
-+
-+#define CLK_IMG_SMI_LARB2		0
-+#define CLK_IMG_SENINF_SCAM_EN		1
-+#define CLK_IMG_SENINF_CAM_EN		2
-+#define CLK_IMG_CAM_SV_EN		3
-+#define CLK_IMG_CAM_SV1_EN		4
-+#define CLK_IMG_CAM_SV2_EN		5
-+#define CLK_IMG_NR_CLK			6
-+
-+/* BDPSYS */
-+
-+#define CLK_BDP_BRIDGE_B		0
-+#define CLK_BDP_BRIDGE_DRAM		1
-+#define CLK_BDP_LARB_DRAM		2
-+#define CLK_BDP_WR_CHANNEL_VDI_PXL	3
-+#define CLK_BDP_WR_CHANNEL_VDI_DRAM	4
-+#define CLK_BDP_WR_CHANNEL_VDI_B	5
-+#define CLK_BDP_MT_B			6
-+#define CLK_BDP_DISPFMT_27M		7
-+#define CLK_BDP_DISPFMT_27M_VDOUT	8
-+#define CLK_BDP_DISPFMT_27_74_74	9
-+#define CLK_BDP_DISPFMT_2FS		10
-+#define CLK_BDP_DISPFMT_2FS_2FS74_148	11
-+#define CLK_BDP_DISPFMT_B		12
-+#define CLK_BDP_VDO_DRAM		13
-+#define CLK_BDP_VDO_2FS			14
-+#define CLK_BDP_VDO_B			15
-+#define CLK_BDP_WR_CHANNEL_DI_PXL	16
-+#define CLK_BDP_WR_CHANNEL_DI_DRAM	17
-+#define CLK_BDP_WR_CHANNEL_DI_B		18
-+#define CLK_BDP_NR_AGENT		19
-+#define CLK_BDP_NR_DRAM			20
-+#define CLK_BDP_NR_B			21
-+#define CLK_BDP_BRIDGE_RT_B		22
-+#define CLK_BDP_BRIDGE_RT_DRAM		23
-+#define CLK_BDP_LARB_RT_DRAM		24
-+#define CLK_BDP_TVD_TDC			25
-+#define CLK_BDP_TVD_54			26
-+#define CLK_BDP_TVD_CBUS		27
-+#define CLK_BDP_NR_CLK			28
-+
-+/* VDECSYS */
-+
-+#define CLK_VDEC_CKEN			0
-+#define CLK_VDEC_LARB1_CKEN		1
-+#define CLK_VDEC_IMGRZ_CKEN		2
-+#define CLK_VDEC_NR_CLK			3
-+
-+/* VENCSYS */
-+
-+#define CLK_VENC_SMI_COMMON_CON		0
-+#define CLK_VENC_VENC			1
-+#define CLK_VENC_SMI_LARB6		2
-+#define CLK_VENC_NR_CLK			3
-+
-+/* JPGDECSYS */
-+
-+#define CLK_JPGDEC_JPGDEC1		0
-+#define CLK_JPGDEC_JPGDEC		1
-+#define CLK_JPGDEC_NR_CLK		2
-+
-+#endif /* _DT_BINDINGS_CLK_MT2712_H */

target/linux/mediatek/patches-4.14/0146-clk-mediatek-Add-MT2712-clock-support.patch

@@ -1,2296 +0,0 @@
-From ec5192303a3938d0972fde3b1f2526d8d6dd02d7 Mon Sep 17 00:00:00 2001
-From: "[email protected]" <[email protected]>
-Date: Mon, 23 Oct 2017 12:10:34 +0800
-Subject: [PATCH 146/224] clk: mediatek: Add MT2712 clock support
-
-Add MT2712 clock support, include topckgen, apmixedsys,
-infracfg, pericfg, mcucfg and subsystem clocks.
-
-Signed-off-by: Weiyi Lu <[email protected]>
-[[email protected]: Static on top_clk_data]
-Signed-off-by: Stephen Boyd <[email protected]>
----
- drivers/clk/mediatek/Kconfig             |   50 ++
- drivers/clk/mediatek/Makefile            |    8 +
- drivers/clk/mediatek/clk-mt2712-bdp.c    |  102 +++
- drivers/clk/mediatek/clk-mt2712-img.c    |   80 ++
- drivers/clk/mediatek/clk-mt2712-jpgdec.c |   76 ++
- drivers/clk/mediatek/clk-mt2712-mfg.c    |   75 ++
- drivers/clk/mediatek/clk-mt2712-mm.c     |  170 ++++
- drivers/clk/mediatek/clk-mt2712-vdec.c   |   94 ++
- drivers/clk/mediatek/clk-mt2712-venc.c   |   77 ++
- drivers/clk/mediatek/clk-mt2712.c        | 1435 ++++++++++++++++++++++++++++++
- drivers/clk/mediatek/clk-mtk.h           |    2 +
- drivers/clk/mediatek/clk-pll.c           |   13 +-
- 12 files changed, 2180 insertions(+), 2 deletions(-)
- create mode 100644 drivers/clk/mediatek/clk-mt2712-bdp.c
- create mode 100644 drivers/clk/mediatek/clk-mt2712-img.c
- create mode 100644 drivers/clk/mediatek/clk-mt2712-jpgdec.c
- create mode 100644 drivers/clk/mediatek/clk-mt2712-mfg.c
- create mode 100644 drivers/clk/mediatek/clk-mt2712-mm.c
- create mode 100644 drivers/clk/mediatek/clk-mt2712-vdec.c
- create mode 100644 drivers/clk/mediatek/clk-mt2712-venc.c
- create mode 100644 drivers/clk/mediatek/clk-mt2712.c
-
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -50,6 +50,56 @@ config COMMON_CLK_MT2701_BDPSYS
- 	---help---
- 	  This driver supports Mediatek MT2701 bdpsys clocks.
- 
-+config COMMON_CLK_MT2712
-+	bool "Clock driver for Mediatek MT2712"
-+	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK && ARM64
-+	---help---
-+	  This driver supports Mediatek MT2712 basic clocks.
-+
-+config COMMON_CLK_MT2712_BDPSYS
-+	bool "Clock driver for Mediatek MT2712 bdpsys"
-+	depends on COMMON_CLK_MT2712
-+	---help---
-+	  This driver supports Mediatek MT2712 bdpsys clocks.
-+
-+config COMMON_CLK_MT2712_IMGSYS
-+	bool "Clock driver for Mediatek MT2712 imgsys"
-+	depends on COMMON_CLK_MT2712
-+	---help---
-+	  This driver supports Mediatek MT2712 imgsys clocks.
-+
-+config COMMON_CLK_MT2712_JPGDECSYS
-+	bool "Clock driver for Mediatek MT2712 jpgdecsys"
-+	depends on COMMON_CLK_MT2712
-+	---help---
-+	  This driver supports Mediatek MT2712 jpgdecsys clocks.
-+
-+config COMMON_CLK_MT2712_MFGCFG
-+	bool "Clock driver for Mediatek MT2712 mfgcfg"
-+	depends on COMMON_CLK_MT2712
-+	---help---
-+	  This driver supports Mediatek MT2712 mfgcfg clocks.
-+
-+config COMMON_CLK_MT2712_MMSYS
-+	bool "Clock driver for Mediatek MT2712 mmsys"
-+	depends on COMMON_CLK_MT2712
-+	---help---
-+	  This driver supports Mediatek MT2712 mmsys clocks.
-+
-+config COMMON_CLK_MT2712_VDECSYS
-+	bool "Clock driver for Mediatek MT2712 vdecsys"
-+	depends on COMMON_CLK_MT2712
-+	---help---
-+	  This driver supports Mediatek MT2712 vdecsys clocks.
-+
-+config COMMON_CLK_MT2712_VENCSYS
-+	bool "Clock driver for Mediatek MT2712 vencsys"
-+	depends on COMMON_CLK_MT2712
-+	---help---
-+	  This driver supports Mediatek MT2712 vencsys clocks.
-+
- config COMMON_CLK_MT6797
-        bool "Clock driver for Mediatek MT6797"
-        depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -13,5 +13,13 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) +
- obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
- obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
- obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
-+obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
-+obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
-+obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
-+obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
-+obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
-+obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
-+obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
-+obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt2712-bdp.c
-@@ -0,0 +1,102 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Weiyi Lu <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt2712-clk.h>
-+
-+static const struct mtk_gate_regs bdp_cg_regs = {
-+	.set_ofs = 0x100,
-+	.clr_ofs = 0x100,
-+	.sta_ofs = 0x100,
-+};
-+
-+#define GATE_BDP(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &bdp_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr,	\
-+	}
-+
-+static const struct mtk_gate bdp_clks[] = {
-+	GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
-+	GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
-+	GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
-+	GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
-+	GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
-+	GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
-+	GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
-+	GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
-+	GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
-+	GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
-+	GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
-+	GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
-+	GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
-+	GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
-+	GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
-+	GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
-+	GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
-+	GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
-+	GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
-+	GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
-+	GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
-+	GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
-+	GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
-+	GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
-+	GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
-+	GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
-+	GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
-+	GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
-+};
-+
-+static int clk_mt2712_bdp_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
-+
-+	mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
-+			clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt2712_bdp[] = {
-+	{ .compatible = "mediatek,mt2712-bdpsys", },
-+	{}
-+};
-+
-+static struct platform_driver clk_mt2712_bdp_drv = {
-+	.probe = clk_mt2712_bdp_probe,
-+	.driver = {
-+		.name = "clk-mt2712-bdp",
-+		.of_match_table = of_match_clk_mt2712_bdp,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt2712_bdp_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt2712-img.c
-@@ -0,0 +1,80 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Weiyi Lu <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt2712-clk.h>
-+
-+static const struct mtk_gate_regs img_cg_regs = {
-+	.set_ofs = 0x0,
-+	.clr_ofs = 0x0,
-+	.sta_ofs = 0x0,
-+};
-+
-+#define GATE_IMG(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &img_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr,	\
-+	}
-+
-+static const struct mtk_gate img_clks[] = {
-+	GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
-+	GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
-+	GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
-+	GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
-+	GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
-+	GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
-+};
-+
-+static int clk_mt2712_img_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
-+
-+	mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
-+			clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt2712_img[] = {
-+	{ .compatible = "mediatek,mt2712-imgsys", },
-+	{}
-+};
-+
-+static struct platform_driver clk_mt2712_img_drv = {
-+	.probe = clk_mt2712_img_probe,
-+	.driver = {
-+		.name = "clk-mt2712-img",
-+		.of_match_table = of_match_clk_mt2712_img,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt2712_img_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
-@@ -0,0 +1,76 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Weiyi Lu <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt2712-clk.h>
-+
-+static const struct mtk_gate_regs jpgdec_cg_regs = {
-+	.set_ofs = 0x4,
-+	.clr_ofs = 0x8,
-+	.sta_ofs = 0x0,
-+};
-+
-+#define GATE_JPGDEC(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &jpgdec_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate jpgdec_clks[] = {
-+	GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
-+	GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
-+};
-+
-+static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);
-+
-+	mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
-+			clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
-+	{ .compatible = "mediatek,mt2712-jpgdecsys", },
-+	{}
-+};
-+
-+static struct platform_driver clk_mt2712_jpgdec_drv = {
-+	.probe = clk_mt2712_jpgdec_probe,
-+	.driver = {
-+		.name = "clk-mt2712-jpgdec",
-+		.of_match_table = of_match_clk_mt2712_jpgdec,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt2712_jpgdec_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt2712-mfg.c
-@@ -0,0 +1,75 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Weiyi Lu <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt2712-clk.h>
-+
-+static const struct mtk_gate_regs mfg_cg_regs = {
-+	.set_ofs = 0x4,
-+	.clr_ofs = 0x8,
-+	.sta_ofs = 0x0,
-+};
-+
-+#define GATE_MFG(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &mfg_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr,	\
-+	}
-+
-+static const struct mtk_gate mfg_clks[] = {
-+	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
-+};
-+
-+static int clk_mt2712_mfg_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
-+
-+	mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
-+			clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt2712_mfg[] = {
-+	{ .compatible = "mediatek,mt2712-mfgcfg", },
-+	{}
-+};
-+
-+static struct platform_driver clk_mt2712_mfg_drv = {
-+	.probe = clk_mt2712_mfg_probe,
-+	.driver = {
-+		.name = "clk-mt2712-mfg",
-+		.of_match_table = of_match_clk_mt2712_mfg,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt2712_mfg_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt2712-mm.c
-@@ -0,0 +1,170 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Weiyi Lu <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt2712-clk.h>
-+
-+static const struct mtk_gate_regs mm0_cg_regs = {
-+	.set_ofs = 0x104,
-+	.clr_ofs = 0x108,
-+	.sta_ofs = 0x100,
-+};
-+
-+static const struct mtk_gate_regs mm1_cg_regs = {
-+	.set_ofs = 0x114,
-+	.clr_ofs = 0x118,
-+	.sta_ofs = 0x110,
-+};
-+
-+static const struct mtk_gate_regs mm2_cg_regs = {
-+	.set_ofs = 0x224,
-+	.clr_ofs = 0x228,
-+	.sta_ofs = 0x220,
-+};
-+
-+#define GATE_MM0(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &mm0_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr,	\
-+	}
-+
-+#define GATE_MM1(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &mm1_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr,	\
-+	}
-+
-+#define GATE_MM2(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &mm2_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr,	\
-+	}
-+
-+static const struct mtk_gate mm_clks[] = {
-+	/* MM0 */
-+	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
-+	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
-+	GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
-+	GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
-+	GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
-+	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
-+	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
-+	GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
-+	GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
-+	GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
-+	GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
-+	GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
-+	GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
-+	GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
-+	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
-+	GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
-+	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
-+	GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
-+	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
-+	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
-+	GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
-+	GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
-+	GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
-+	GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
-+	GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
-+	GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
-+	GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
-+	GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
-+	GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
-+	GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
-+	/* MM1 */
-+	GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
-+	GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
-+	GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
-+	GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
-+	GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
-+	GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
-+	GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
-+	GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
-+	GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
-+	GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
-+	GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
-+	GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
-+	GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
-+	GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
-+	GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
-+	GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
-+	GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
-+	GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
-+	GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
-+	GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
-+	GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
-+	GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
-+	GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
-+	GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
-+	GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
-+	GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
-+	/* MM2 */
-+	GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
-+	GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
-+	GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
-+	GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
-+	GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
-+	GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
-+	GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
-+};
-+
-+static int clk_mt2712_mm_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
-+
-+	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
-+			clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt2712_mm[] = {
-+	{ .compatible = "mediatek,mt2712-mmsys", },
-+	{}
-+};
-+
-+static struct platform_driver clk_mt2712_mm_drv = {
-+	.probe = clk_mt2712_mm_probe,
-+	.driver = {
-+		.name = "clk-mt2712-mm",
-+		.of_match_table = of_match_clk_mt2712_mm,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt2712_mm_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt2712-vdec.c
-@@ -0,0 +1,94 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Weiyi Lu <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt2712-clk.h>
-+
-+static const struct mtk_gate_regs vdec0_cg_regs = {
-+	.set_ofs = 0x0,
-+	.clr_ofs = 0x4,
-+	.sta_ofs = 0x0,
-+};
-+
-+static const struct mtk_gate_regs vdec1_cg_regs = {
-+	.set_ofs = 0x8,
-+	.clr_ofs = 0xc,
-+	.sta_ofs = 0x8,
-+};
-+
-+#define GATE_VDEC0(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &vdec0_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-+	}
-+
-+#define GATE_VDEC1(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &vdec1_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate vdec_clks[] = {
-+	/* VDEC0 */
-+	GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
-+	/* VDEC1 */
-+	GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
-+	GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
-+};
-+
-+static int clk_mt2712_vdec_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
-+
-+	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
-+			clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt2712_vdec[] = {
-+	{ .compatible = "mediatek,mt2712-vdecsys", },
-+	{}
-+};
-+
-+static struct platform_driver clk_mt2712_vdec_drv = {
-+	.probe = clk_mt2712_vdec_probe,
-+	.driver = {
-+		.name = "clk-mt2712-vdec",
-+		.of_match_table = of_match_clk_mt2712_vdec,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt2712_vdec_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt2712-venc.c
-@@ -0,0 +1,77 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Weiyi Lu <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt2712-clk.h>
-+
-+static const struct mtk_gate_regs venc_cg_regs = {
-+	.set_ofs = 0x4,
-+	.clr_ofs = 0x8,
-+	.sta_ofs = 0x0,
-+};
-+
-+#define GATE_VENC(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &venc_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate venc_clks[] = {
-+	GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
-+	GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
-+	GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
-+};
-+
-+static int clk_mt2712_venc_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
-+
-+	mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
-+			clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt2712_venc[] = {
-+	{ .compatible = "mediatek,mt2712-vencsys", },
-+	{}
-+};
-+
-+static struct platform_driver clk_mt2712_venc_drv = {
-+	.probe = clk_mt2712_venc_probe,
-+	.driver = {
-+		.name = "clk-mt2712-venc",
-+		.of_match_table = of_match_clk_mt2712_venc,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt2712_venc_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt2712.c
-@@ -0,0 +1,1435 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Weiyi Lu <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt2712-clk.h>
-+
-+static DEFINE_SPINLOCK(mt2712_clk_lock);
-+
-+static const struct mtk_fixed_clk top_fixed_clks[] = {
-+	FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
-+	FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
-+	FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
-+	FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
-+	FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
-+	FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
-+	FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
-+	FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
-+	FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
-+	FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
-+	FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
-+	FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
-+};
-+
-+static const struct mtk_fixed_factor top_early_divs[] = {
-+	FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
-+		1),
-+	FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
-+		2),
-+};
-+
-+static const struct mtk_fixed_factor top_divs[] = {
-+	FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
-+		1),
-+	FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
-+		3),
-+	FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
-+		1),
-+	FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
-+		2),
-+	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
-+		4),
-+	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
-+		8),
-+	FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
-+		16),
-+	FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
-+		3),
-+	FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
-+		2),
-+	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
-+		4),
-+	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
-+		5),
-+	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
-+		2),
-+	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
-+		4),
-+	FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
-+		7),
-+	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
-+		2),
-+	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
-+		4),
-+	FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
-+		7),
-+	FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
-+		26),
-+	FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
-+		52),
-+	FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
-+		104),
-+	FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
-+		208),
-+	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
-+		2),
-+	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
-+		4),
-+	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
-+		8),
-+	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
-+		3),
-+	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
-+		2),
-+	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
-+		4),
-+	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
-+		8),
-+	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
-+		5),
-+	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
-+		2),
-+	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
-+		4),
-+	FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
-+		8),
-+	FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
-+		1),
-+	FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
-+		1),
-+	FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
-+		1),
-+	FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
-+		1),
-+	FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
-+		1),
-+	FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
-+		1),
-+	FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
-+		1),
-+	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
-+		4),
-+	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
-+		8),
-+	FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
-+		16),
-+	FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
-+		1),
-+	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
-+		4),
-+	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
-+		8),
-+	FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
-+		16),
-+	FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
-+		1),
-+	FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
-+		4),
-+	FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
-+		8),
-+	FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
-+		1),
-+	FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
-+		4),
-+	FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
-+		8),
-+	FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
-+		1),
-+	FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
-+		2),
-+	FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
-+		4),
-+	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
-+		8),
-+	FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
-+		2),
-+	FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
-+		4),
-+	FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
-+		1),
-+	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
-+		4),
-+	FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
-+		1),
-+	FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
-+		2),
-+	FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
-+		4),
-+	FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
-+		4),
-+};
-+
-+static const char * const axi_parents[] = {
-+	"clk26m",
-+	"syspll1_d2",
-+	"syspll_d5",
-+	"syspll1_d4",
-+	"univpll_d5",
-+	"univpll2_d2",
-+	"msdcpll2_ck"
-+};
-+
-+static const char * const mem_parents[] = {
-+	"clk26m",
-+	"dmpll_ck"
-+};
-+
-+static const char * const mm_parents[] = {
-+	"clk26m",
-+	"vencpll_ck",
-+	"syspll_d3",
-+	"syspll1_d2",
-+	"syspll_d5",
-+	"syspll1_d4",
-+	"univpll1_d2",
-+	"univpll2_d2"
-+};
-+
-+static const char * const pwm_parents[] = {
-+	"clk26m",
-+	"univpll2_d4",
-+	"univpll3_d2",
-+	"univpll1_d4"
-+};
-+
-+static const char * const vdec_parents[] = {
-+	"clk26m",
-+	"vcodecpll_ck",
-+	"tvdpll_429m",
-+	"univpll_d3",
-+	"vencpll_ck",
-+	"syspll_d3",
-+	"univpll1_d2",
-+	"mmpll_d2",
-+	"syspll3_d2",
-+	"tvdpll_ck"
-+};
-+
-+static const char * const venc_parents[] = {
-+	"clk26m",
-+	"univpll1_d2",
-+	"mmpll_d2",
-+	"tvdpll_d2",
-+	"syspll1_d2",
-+	"univpll_d5",
-+	"vcodecpll_d2",
-+	"univpll2_d2",
-+	"syspll3_d2"
-+};
-+
-+static const char * const mfg_parents[] = {
-+	"clk26m",
-+	"mmpll_ck",
-+	"univpll_d3",
-+	"clk26m",
-+	"clk26m",
-+	"clk26m",
-+	"clk26m",
-+	"clk26m",
-+	"clk26m",
-+	"syspll_d3",
-+	"syspll1_d2",
-+	"syspll_d5",
-+	"univpll_d3",
-+	"univpll1_d2",
-+	"univpll_d5",
-+	"univpll2_d2"
-+};
-+
-+static const char * const camtg_parents[] = {
-+	"clk26m",
-+	"univpll_d52",
-+	"univpll_d208",
-+	"univpll_d104",
-+	"clk26m_d2",
-+	"univpll_d26",
-+	"univpll2_d8",
-+	"syspll3_d4",
-+	"syspll3_d2",
-+	"univpll1_d4",
-+	"univpll2_d2"
-+};
-+
-+static const char * const uart_parents[] = {
-+	"clk26m",
-+	"univpll2_d8"
-+};
-+
-+static const char * const spi_parents[] = {
-+	"clk26m",
-+	"univpll2_d4",
-+	"univpll1_d4",
-+	"univpll2_d2",
-+	"univpll3_d2",
-+	"univpll1_d8"
-+};
-+
-+static const char * const usb20_parents[] = {
-+	"clk26m",
-+	"univpll1_d8",
-+	"univpll3_d4"
-+};
-+
-+static const char * const usb30_parents[] = {
-+	"clk26m",
-+	"univpll3_d2",
-+	"univpll3_d4",
-+	"univpll2_d4"
-+};
-+
-+static const char * const msdc50_0_h_parents[] = {
-+	"clk26m",
-+	"syspll1_d2",
-+	"syspll2_d2",
-+	"syspll4_d2",
-+	"univpll_d5",
-+	"univpll1_d4"
-+};
-+
-+static const char * const msdc50_0_parents[] = {
-+	"clk26m",
-+	"msdcpll_ck",
-+	"msdcpll_d2",
-+	"univpll1_d4",
-+	"syspll2_d2",
-+	"msdcpll_d4",
-+	"vencpll_d2",
-+	"univpll1_d2",
-+	"msdcpll2_ck",
-+	"msdcpll2_d2",
-+	"msdcpll2_d4"
-+};
-+
-+static const char * const msdc30_1_parents[] = {
-+	"clk26m",
-+	"univpll2_d2",
-+	"msdcpll_d2",
-+	"univpll1_d4",
-+	"syspll2_d2",
-+	"univpll_d7",
-+	"vencpll_d2"
-+};
-+
-+static const char * const msdc30_3_parents[] = {
-+	"clk26m",
-+	"msdcpll2_ck",
-+	"msdcpll2_d2",
-+	"univpll2_d2",
-+	"msdcpll2_d4",
-+	"univpll1_d4",
-+	"syspll2_d2",
-+	"syspll_d7",
-+	"univpll_d7",
-+	"vencpll_d2",
-+	"msdcpll_ck",
-+	"msdcpll_d2",
-+	"msdcpll_d4"
-+};
-+
-+static const char * const audio_parents[] = {
-+	"clk26m",
-+	"syspll3_d4",
-+	"syspll4_d4",
-+	"syspll1_d16"
-+};
-+
-+static const char * const aud_intbus_parents[] = {
-+	"clk26m",
-+	"syspll1_d4",
-+	"syspll4_d2",
-+	"univpll3_d2",
-+	"univpll2_d8",
-+	"syspll3_d2",
-+	"syspll3_d4"
-+};
-+
-+static const char * const pmicspi_parents[] = {
-+	"clk26m",
-+	"syspll1_d8",
-+	"syspll3_d4",
-+	"syspll1_d16",
-+	"univpll3_d4",
-+	"univpll_d26",
-+	"syspll3_d4"
-+};
-+
-+static const char * const dpilvds1_parents[] = {
-+	"clk26m",
-+	"lvdspll2_ck",
-+	"lvdspll2_d2",
-+	"lvdspll2_d4",
-+	"lvdspll2_d8",
-+	"clkfpc"
-+};
-+
-+static const char * const atb_parents[] = {
-+	"clk26m",
-+	"syspll1_d2",
-+	"univpll_d5",
-+	"syspll_d5"
-+};
-+
-+static const char * const nr_parents[] = {
-+	"clk26m",
-+	"univpll1_d4",
-+	"syspll2_d2",
-+	"syspll1_d4",
-+	"univpll1_d8",
-+	"univpll3_d2",
-+	"univpll2_d2",
-+	"syspll_d5"
-+};
-+
-+static const char * const nfi2x_parents[] = {
-+	"clk26m",
-+	"syspll4_d4",
-+	"univpll3_d4",
-+	"univpll1_d8",
-+	"syspll2_d4",
-+	"univpll3_d2",
-+	"syspll_d7",
-+	"syspll2_d2",
-+	"univpll2_d2",
-+	"syspll_d5",
-+	"syspll1_d2"
-+};
-+
-+static const char * const irda_parents[] = {
-+	"clk26m",
-+	"univpll2_d4",
-+	"syspll2_d4",
-+	"univpll2_d8"
-+};
-+
-+static const char * const cci400_parents[] = {
-+	"clk26m",
-+	"vencpll_ck",
-+	"armca35pll_600m",
-+	"armca35pll_400m",
-+	"univpll_d2",
-+	"syspll_d2",
-+	"msdcpll_ck",
-+	"univpll_d3"
-+};
-+
-+static const char * const aud_1_parents[] = {
-+	"clk26m",
-+	"apll1_ck",
-+	"univpll2_d4",
-+	"univpll2_d8"
-+};
-+
-+static const char * const aud_2_parents[] = {
-+	"clk26m",
-+	"apll2_ck",
-+	"univpll2_d4",
-+	"univpll2_d8"
-+};
-+
-+static const char * const mem_mfg_parents[] = {
-+	"clk26m",
-+	"mmpll_ck",
-+	"univpll_d3"
-+};
-+
-+static const char * const axi_mfg_parents[] = {
-+	"clk26m",
-+	"axi_sel",
-+	"univpll_d5"
-+};
-+
-+static const char * const scam_parents[] = {
-+	"clk26m",
-+	"syspll3_d2",
-+	"univpll2_d4",
-+	"syspll2_d4"
-+};
-+
-+static const char * const nfiecc_parents[] = {
-+	"clk26m",
-+	"nfi2x_sel",
-+	"syspll_d7",
-+	"syspll2_d2",
-+	"univpll2_d2",
-+	"univpll_d5",
-+	"syspll1_d2"
-+};
-+
-+static const char * const pe2_mac_p0_parents[] = {
-+	"clk26m",
-+	"syspll1_d8",
-+	"syspll4_d2",
-+	"syspll2_d4",
-+	"univpll2_d4",
-+	"syspll3_d2"
-+};
-+
-+static const char * const dpilvds_parents[] = {
-+	"clk26m",
-+	"lvdspll_ck",
-+	"lvdspll_d2",
-+	"lvdspll_d4",
-+	"lvdspll_d8",
-+	"clkfpc"
-+};
-+
-+static const char * const hdcp_parents[] = {
-+	"clk26m",
-+	"syspll4_d2",
-+	"syspll3_d4",
-+	"univpll2_d4"
-+};
-+
-+static const char * const hdcp_24m_parents[] = {
-+	"clk26m",
-+	"univpll_d26",
-+	"univpll_d52",
-+	"univpll2_d8"
-+};
-+
-+static const char * const rtc_parents[] = {
-+	"clkrtc_int",
-+	"clkrtc_ext",
-+	"clk26m",
-+	"univpll3_d8"
-+};
-+
-+static const char * const spinor_parents[] = {
-+	"clk26m",
-+	"clk26m_d2",
-+	"syspll4_d4",
-+	"univpll2_d8",
-+	"univpll3_d4",
-+	"syspll4_d2",
-+	"syspll2_d4",
-+	"univpll2_d4",
-+	"etherpll_125m",
-+	"syspll1_d4"
-+};
-+
-+static const char * const apll_parents[] = {
-+	"clk26m",
-+	"apll1_ck",
-+	"apll1_d2",
-+	"apll1_d4",
-+	"apll1_d8",
-+	"apll1_d16",
-+	"apll2_ck",
-+	"apll2_d2",
-+	"apll2_d4",
-+	"apll2_d8",
-+	"apll2_d16",
-+	"clk26m",
-+	"clk26m"
-+};
-+
-+static const char * const a1sys_hp_parents[] = {
-+	"clk26m",
-+	"apll1_ck",
-+	"apll1_d2",
-+	"apll1_d4",
-+	"apll1_d8"
-+};
-+
-+static const char * const a2sys_hp_parents[] = {
-+	"clk26m",
-+	"apll2_ck",
-+	"apll2_d2",
-+	"apll2_d4",
-+	"apll2_d8"
-+};
-+
-+static const char * const asm_l_parents[] = {
-+	"clk26m",
-+	"univpll2_d4",
-+	"univpll2_d2",
-+	"syspll_d5"
-+};
-+
-+static const char * const i2so1_parents[] = {
-+	"clk26m",
-+	"apll1_ck",
-+	"apll2_ck"
-+};
-+
-+static const char * const ether_125m_parents[] = {
-+	"clk26m",
-+	"etherpll_125m",
-+	"univpll3_d2"
-+};
-+
-+static const char * const ether_50m_parents[] = {
-+	"clk26m",
-+	"etherpll_50m",
-+	"univpll_d26",
-+	"univpll3_d4"
-+};
-+
-+static const char * const jpgdec_parents[] = {
-+	"clk26m",
-+	"univpll_d3",
-+	"tvdpll_429m",
-+	"vencpll_ck",
-+	"syspll_d3",
-+	"vcodecpll_ck",
-+	"univpll1_d2",
-+	"armca35pll_400m",
-+	"tvdpll_429m_d2",
-+	"tvdpll_429m_d4"
-+};
-+
-+static const char * const spislv_parents[] = {
-+	"clk26m",
-+	"univpll2_d4",
-+	"univpll1_d4",
-+	"univpll2_d2",
-+	"univpll3_d2",
-+	"univpll1_d8",
-+	"univpll1_d2",
-+	"univpll_d5"
-+};
-+
-+static const char * const ether_parents[] = {
-+	"clk26m",
-+	"etherpll_50m",
-+	"univpll_d26"
-+};
-+
-+static const char * const di_parents[] = {
-+	"clk26m",
-+	"tvdpll_d2",
-+	"tvdpll_d4",
-+	"tvdpll_d8",
-+	"vencpll_ck",
-+	"vencpll_d2",
-+	"cvbs",
-+	"cvbs_d2"
-+};
-+
-+static const char * const tvd_parents[] = {
-+	"clk26m",
-+	"cvbs_d2",
-+	"univpll2_d8"
-+};
-+
-+static const char * const i2c_parents[] = {
-+	"clk26m",
-+	"univpll_d26",
-+	"univpll2_d4",
-+	"univpll3_d2",
-+	"univpll1_d4"
-+};
-+
-+static const char * const msdc0p_aes_parents[] = {
-+	"clk26m",
-+	"msdcpll_ck",
-+	"univpll_d3",
-+	"vcodecpll_ck"
-+};
-+
-+static const char * const cmsys_parents[] = {
-+	"clk26m",
-+	"univpll_d3",
-+	"syspll_d3",
-+	"syspll1_d2",
-+	"syspll2_d2"
-+};
-+
-+static const char * const gcpu_parents[] = {
-+	"clk26m",
-+	"syspll_d3",
-+	"syspll1_d2",
-+	"univpll1_d2",
-+	"univpll_d5",
-+	"univpll3_d2",
-+	"univpll_d3"
-+};
-+
-+static const char * const aud_apll1_parents[] = {
-+	"apll1",
-+	"clkaud_ext_i_1"
-+};
-+
-+static const char * const aud_apll2_parents[] = {
-+	"apll2",
-+	"clkaud_ext_i_2"
-+};
-+
-+static const char * const audull_vtx_parents[] = {
-+	"d2a_ulclk_6p5m",
-+	"clkaud_ext_i_0"
-+};
-+
-+static struct mtk_composite top_muxes[] = {
-+	/* CLK_CFG_0 */
-+	MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
-+		7, CLK_IS_CRITICAL),
-+	MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
-+		15, CLK_IS_CRITICAL),
-+	MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
-+		mm_parents, 0x040, 24, 3, 31),
-+	/* CLK_CFG_1 */
-+	MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
-+		pwm_parents, 0x050, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
-+		vdec_parents, 0x050, 8, 4, 15),
-+	MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
-+		venc_parents, 0x050, 16, 4, 23),
-+	MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
-+		mfg_parents, 0x050, 24, 4, 31),
-+	/* CLK_CFG_2 */
-+	MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
-+		camtg_parents, 0x060, 0, 4, 7),
-+	MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
-+		uart_parents, 0x060, 8, 1, 15),
-+	MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
-+		spi_parents, 0x060, 16, 3, 23),
-+	MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
-+		usb20_parents, 0x060, 24, 2, 31),
-+	/* CLK_CFG_3 */
-+	MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
-+		usb30_parents, 0x070, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
-+		msdc50_0_h_parents, 0x070, 8, 3, 15),
-+	MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
-+		msdc50_0_parents, 0x070, 16, 4, 23),
-+	MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
-+		msdc30_1_parents, 0x070, 24, 3, 31),
-+	/* CLK_CFG_4 */
-+	MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
-+		msdc30_1_parents, 0x080, 0, 3, 7),
-+	MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
-+		msdc30_3_parents, 0x080, 8, 4, 15),
-+	MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
-+		audio_parents, 0x080, 16, 2, 23),
-+	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
-+		aud_intbus_parents, 0x080, 24, 3, 31),
-+	/* CLK_CFG_5 */
-+	MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
-+		pmicspi_parents, 0x090, 0, 3, 7),
-+	MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
-+		dpilvds1_parents, 0x090, 8, 3, 15),
-+	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
-+		atb_parents, 0x090, 16, 2, 23),
-+	MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
-+		nr_parents, 0x090, 24, 3, 31),
-+	/* CLK_CFG_6 */
-+	MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
-+		nfi2x_parents, 0x0a0, 0, 4, 7),
-+	MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
-+		irda_parents, 0x0a0, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
-+		cci400_parents, 0x0a0, 16, 3, 23),
-+	MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
-+		aud_1_parents, 0x0a0, 24, 2, 31),
-+	/* CLK_CFG_7 */
-+	MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
-+		aud_2_parents, 0x0b0, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
-+		mem_mfg_parents, 0x0b0, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
-+		axi_mfg_parents, 0x0b0, 16, 2, 23),
-+	MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
-+		scam_parents, 0x0b0, 24, 2, 31),
-+	/* CLK_CFG_8 */
-+	MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
-+		nfiecc_parents, 0x0c0, 0, 3, 7),
-+	MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
-+		pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
-+	MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
-+		pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
-+	MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
-+		dpilvds_parents, 0x0c0, 24, 3, 31),
-+	/* CLK_CFG_9 */
-+	MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
-+		msdc50_0_h_parents, 0x0d0, 0, 3, 7),
-+	MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
-+		hdcp_parents, 0x0d0, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
-+		hdcp_24m_parents, 0x0d0, 16, 2, 23),
-+	MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
-+		31, CLK_IS_CRITICAL),
-+	/* CLK_CFG_10 */
-+	MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
-+		spinor_parents, 0x500, 0, 4, 7),
-+	MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
-+		apll_parents, 0x500, 8, 4, 15),
-+	MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
-+		apll_parents, 0x500, 16, 4, 23),
-+	MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
-+		a1sys_hp_parents, 0x500, 24, 3, 31),
-+	/* CLK_CFG_11 */
-+	MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
-+		a2sys_hp_parents, 0x510, 0, 3, 7),
-+	MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
-+		asm_l_parents, 0x510, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
-+		asm_l_parents, 0x510, 16, 2, 23),
-+	MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
-+		asm_l_parents, 0x510, 24, 2, 31),
-+	/* CLK_CFG_12 */
-+	MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
-+		i2so1_parents, 0x520, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
-+		i2so1_parents, 0x520, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
-+		i2so1_parents, 0x520, 16, 2, 23),
-+	MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
-+		i2so1_parents, 0x520, 24, 2, 31),
-+	/* CLK_CFG_13 */
-+	MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
-+		i2so1_parents, 0x530, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
-+		i2so1_parents, 0x530, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
-+		i2so1_parents, 0x530, 16, 2, 23),
-+	MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
-+		i2so1_parents, 0x530, 24, 2, 31),
-+	/* CLK_CFG_14 */
-+	MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
-+		ether_125m_parents, 0x540, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
-+		ether_50m_parents, 0x540, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
-+		jpgdec_parents, 0x540, 16, 4, 23),
-+	MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
-+		spislv_parents, 0x540, 24, 3, 31),
-+	/* CLK_CFG_15 */
-+	MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
-+		ether_parents, 0x550, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
-+		camtg_parents, 0x550, 8, 4, 15),
-+	MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
-+		di_parents, 0x550, 16, 3, 23),
-+	MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
-+		tvd_parents, 0x550, 24, 2, 31),
-+	/* CLK_CFG_16 */
-+	MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
-+		i2c_parents, 0x560, 0, 3, 7),
-+	MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
-+		pwm_parents, 0x560, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
-+		msdc0p_aes_parents, 0x560, 16, 2, 23),
-+	MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
-+		cmsys_parents, 0x560, 24, 3, 31),
-+	/* CLK_CFG_17 */
-+	MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
-+		gcpu_parents, 0x570, 0, 3, 7),
-+	/* CLK_AUDDIV_4 */
-+	MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
-+		aud_apll1_parents, 0x134, 0, 1),
-+	MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
-+		aud_apll2_parents, 0x134, 1, 1),
-+	MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
-+		audull_vtx_parents, 0x134, 31, 1),
-+};
-+
-+static const char * const mcu_mp0_parents[] = {
-+	"clk26m",
-+	"armca35pll_ck",
-+	"f_mp0_pll1_ck",
-+	"f_mp0_pll2_ck"
-+};
-+
-+static const char * const mcu_mp2_parents[] = {
-+	"clk26m",
-+	"armca72pll_ck",
-+	"f_big_pll1_ck",
-+	"f_big_pll2_ck"
-+};
-+
-+static const char * const mcu_bus_parents[] = {
-+	"clk26m",
-+	"cci400_sel",
-+	"f_bus_pll1_ck",
-+	"f_bus_pll2_ck"
-+};
-+
-+static struct mtk_composite mcu_muxes[] = {
-+	/* mp0_pll_divider_cfg */
-+	MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
-+		9, 2, -1, CLK_IS_CRITICAL),
-+	/* mp2_pll_divider_cfg */
-+	MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
-+		9, 2, -1, CLK_IS_CRITICAL),
-+	/* bus_pll_divider_cfg */
-+	MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
-+		9, 2, -1, CLK_IS_CRITICAL),
-+};
-+
-+static const struct mtk_clk_divider top_adj_divs[] = {
-+	DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
-+	DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
-+	DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
-+	DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
-+	DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
-+	DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
-+	DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
-+	DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
-+};
-+
-+static const struct mtk_gate_regs top_cg_regs = {
-+	.set_ofs = 0x120,
-+	.clr_ofs = 0x120,
-+	.sta_ofs = 0x120,
-+};
-+
-+#define GATE_TOP(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &top_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr,	\
-+	}
-+
-+static const struct mtk_gate top_clks[] = {
-+	GATE_TOP(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
-+	GATE_TOP(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
-+	GATE_TOP(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
-+	GATE_TOP(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
-+	GATE_TOP(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
-+	GATE_TOP(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
-+	GATE_TOP(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
-+	GATE_TOP(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
-+};
-+
-+static const struct mtk_gate_regs infra_cg_regs = {
-+	.set_ofs = 0x40,
-+	.clr_ofs = 0x44,
-+	.sta_ofs = 0x40,
-+};
-+
-+#define GATE_INFRA(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &infra_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr,	\
-+	}
-+
-+static const struct mtk_gate infra_clks[] = {
-+	GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
-+	GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
-+	GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
-+	GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
-+	GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
-+	GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
-+	GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
-+};
-+
-+static const struct mtk_gate_regs peri0_cg_regs = {
-+	.set_ofs = 0x8,
-+	.clr_ofs = 0x10,
-+	.sta_ofs = 0x18,
-+};
-+
-+static const struct mtk_gate_regs peri1_cg_regs = {
-+	.set_ofs = 0xc,
-+	.clr_ofs = 0x14,
-+	.sta_ofs = 0x1c,
-+};
-+
-+static const struct mtk_gate_regs peri2_cg_regs = {
-+	.set_ofs = 0x42c,
-+	.clr_ofs = 0x42c,
-+	.sta_ofs = 0x42c,
-+};
-+
-+#define GATE_PERI0(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &peri0_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr,	\
-+	}
-+
-+#define GATE_PERI1(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &peri1_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_setclr,	\
-+	}
-+
-+#define GATE_PERI2(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &peri2_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate peri_clks[] = {
-+	/* PERI0 */
-+	GATE_PERI0(CLK_PERI_NFI, "per_nfi",
-+		"axi_sel", 0),
-+	GATE_PERI0(CLK_PERI_THERM, "per_therm",
-+		"axi_sel", 1),
-+	GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
-+		"pwm_sel", 2),
-+	GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
-+		"pwm_sel", 3),
-+	GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
-+		"pwm_sel", 4),
-+	GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
-+		"pwm_sel", 5),
-+	GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
-+		"pwm_sel", 6),
-+	GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
-+		"pwm_sel", 7),
-+	GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
-+		"pwm_sel", 8),
-+	GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
-+		"pwm_sel", 9),
-+	GATE_PERI0(CLK_PERI_PWM, "per_pwm",
-+		"pwm_sel", 10),
-+	GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
-+		"axi_sel", 13),
-+	GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
-+		"msdc50_0_sel", 14),
-+	GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
-+		"msdc30_1_sel", 15),
-+	GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
-+		"msdc30_2_sel", 16),
-+	GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
-+		"msdc30_3_sel", 17),
-+	GATE_PERI0(CLK_PERI_UART0, "per_uart0",
-+		"uart_sel", 20),
-+	GATE_PERI0(CLK_PERI_UART1, "per_uart1",
-+		"uart_sel", 21),
-+	GATE_PERI0(CLK_PERI_UART2, "per_uart2",
-+		"uart_sel", 22),
-+	GATE_PERI0(CLK_PERI_UART3, "per_uart3",
-+		"uart_sel", 23),
-+	GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
-+		"axi_sel", 24),
-+	GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
-+		"axi_sel", 25),
-+	GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
-+		"axi_sel", 26),
-+	GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
-+		"axi_sel", 27),
-+	GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
-+		"axi_sel", 28),
-+	GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
-+		"ltepll_fs26m", 29),
-+	GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
-+		"spi_sel", 30),
-+	/* PERI1 */
-+	GATE_PERI1(CLK_PERI_SPI, "per_spi",
-+		"spinor_sel", 1),
-+	GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
-+		"axi_sel", 3),
-+	GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
-+		"spi_sel", 5),
-+	GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
-+		"spi_sel", 6),
-+	GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
-+		"spi_sel", 8),
-+	GATE_PERI1(CLK_PERI_UART4, "per_uart4",
-+		"uart_sel", 9),
-+	GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
-+		"uart_sel", 11),
-+	GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
-+		"uart_sel", 12),
-+	GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
-+		"uart_sel", 14),
-+	GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
-+		"uart_sel", 15),
-+	GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
-+		"uart_sel", 16),
-+	/* PERI2 */
-+	GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
-+		"msdc50_0_sel", 0),
-+	GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
-+		"msdc30_1_sel", 1),
-+	GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
-+		"msdc30_2_sel", 2),
-+	GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
-+		"msdc30_3_sel", 3),
-+	GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
-+		"msdc50_0_h_sel", 4),
-+	GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
-+		"msdc50_3_h_sel", 5),
-+};
-+
-+#define MT2712_PLL_FMAX		(3000UL * MHZ)
-+
-+#define CON0_MT2712_RST_BAR	BIT(24)
-+
-+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
-+			_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,	\
-+			_tuner_en_bit, _pcw_reg, _pcw_shift,		\
-+			_div_table) {					\
-+		.id = _id,						\
-+		.name = _name,						\
-+		.reg = _reg,						\
-+		.pwr_reg = _pwr_reg,					\
-+		.en_mask = _en_mask,					\
-+		.flags = _flags,					\
-+		.rst_bar_mask = CON0_MT2712_RST_BAR,			\
-+		.fmax = MT2712_PLL_FMAX,				\
-+		.pcwbits = _pcwbits,					\
-+		.pd_reg = _pd_reg,					\
-+		.pd_shift = _pd_shift,					\
-+		.tuner_reg = _tuner_reg,				\
-+		.tuner_en_reg = _tuner_en_reg,				\
-+		.tuner_en_bit = _tuner_en_bit,				\
-+		.pcw_reg = _pcw_reg,					\
-+		.pcw_shift = _pcw_shift,				\
-+		.div_table = _div_table,				\
-+	}
-+
-+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
-+			_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,	\
-+			_tuner_en_bit, _pcw_reg, _pcw_shift)		\
-+		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,	\
-+			_pcwbits, _pd_reg, _pd_shift, _tuner_reg,	\
-+			_tuner_en_reg, _tuner_en_bit, _pcw_reg,		\
-+			_pcw_shift, NULL)
-+
-+static const struct mtk_pll_div_table armca35pll_div_table[] = {
-+	{ .div = 0, .freq = MT2712_PLL_FMAX },
-+	{ .div = 1, .freq = 1202500000 },
-+	{ .div = 2, .freq = 500500000 },
-+	{ .div = 3, .freq = 315250000 },
-+	{ .div = 4, .freq = 157625000 },
-+	{ } /* sentinel */
-+};
-+
-+static const struct mtk_pll_div_table armca72pll_div_table[] = {
-+	{ .div = 0, .freq = MT2712_PLL_FMAX },
-+	{ .div = 1, .freq = 994500000 },
-+	{ .div = 2, .freq = 520000000 },
-+	{ .div = 3, .freq = 315250000 },
-+	{ .div = 4, .freq = 157625000 },
-+	{ } /* sentinel */
-+};
-+
-+static const struct mtk_pll_div_table mmpll_div_table[] = {
-+	{ .div = 0, .freq = MT2712_PLL_FMAX },
-+	{ .div = 1, .freq = 1001000000 },
-+	{ .div = 2, .freq = 601250000 },
-+	{ .div = 3, .freq = 250250000 },
-+	{ .div = 4, .freq = 125125000 },
-+	{ } /* sentinel */
-+};
-+
-+static const struct mtk_pll_data plls[] = {
-+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
-+		HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
-+	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
-+		HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
-+	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
-+		0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
-+	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
-+		0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
-+	PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
-+		0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
-+	PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
-+		0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
-+	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
-+		0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
-+	PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
-+		0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
-+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
-+		0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
-+	PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
-+		0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
-+	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
-+		0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
-+	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
-+		0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
-+		mmpll_div_table),
-+	PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
-+		HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
-+		armca35pll_div_table),
-+	PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
-+		0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
-+		armca72pll_div_table),
-+	PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
-+		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
-+};
-+
-+static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
-+
-+	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static struct clk_onecell_data *top_clk_data;
-+
-+static void clk_mt2712_top_init_early(struct device_node *node)
-+{
-+	int r, i;
-+
-+	if (!top_clk_data) {
-+		top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
-+
-+		for (i = 0; i < CLK_TOP_NR_CLK; i++)
-+			top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
-+	}
-+
-+	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
-+			top_clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
-+	if (r)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+}
-+
-+CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
-+			clk_mt2712_top_init_early);
-+
-+static int clk_mt2712_top_probe(struct platform_device *pdev)
-+{
-+	int r, i;
-+	struct device_node *node = pdev->dev.of_node;
-+	void __iomem *base;
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+	base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(base)) {
-+		pr_err("%s(): ioremap failed\n", __func__);
-+		return PTR_ERR(base);
-+	}
-+
-+	if (!top_clk_data) {
-+		top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
-+	} else {
-+		for (i = 0; i < CLK_TOP_NR_CLK; i++) {
-+			if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
-+				top_clk_data->clks[i] = ERR_PTR(-ENOENT);
-+		}
-+	}
-+
-+	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-+			top_clk_data);
-+	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
-+			top_clk_data);
-+	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
-+	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
-+			&mt2712_clk_lock, top_clk_data);
-+	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
-+			&mt2712_clk_lock, top_clk_data);
-+	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
-+			top_clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static int clk_mt2712_infra_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
-+
-+	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-+			clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	mtk_register_reset_controller(node, 2, 0x30);
-+
-+	return r;
-+}
-+
-+static int clk_mt2712_peri_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
-+
-+	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
-+			clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	mtk_register_reset_controller(node, 2, 0);
-+
-+	return r;
-+}
-+
-+static int clk_mt2712_mcu_probe(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+	void __iomem *base;
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+	base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(base)) {
-+		pr_err("%s(): ioremap failed\n", __func__);
-+		return PTR_ERR(base);
-+	}
-+
-+	clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
-+
-+	mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
-+			&mt2712_clk_lock, clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+
-+	if (r != 0)
-+		pr_err("%s(): could not register clock provider: %d\n",
-+			__func__, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt2712[] = {
-+	{
-+		.compatible = "mediatek,mt2712-apmixedsys",
-+		.data = clk_mt2712_apmixed_probe,
-+	}, {
-+		.compatible = "mediatek,mt2712-topckgen",
-+		.data = clk_mt2712_top_probe,
-+	}, {
-+		.compatible = "mediatek,mt2712-infracfg",
-+		.data = clk_mt2712_infra_probe,
-+	}, {
-+		.compatible = "mediatek,mt2712-pericfg",
-+		.data = clk_mt2712_peri_probe,
-+	}, {
-+		.compatible = "mediatek,mt2712-mcucfg",
-+		.data = clk_mt2712_mcu_probe,
-+	}, {
-+		/* sentinel */
-+	}
-+};
-+
-+static int clk_mt2712_probe(struct platform_device *pdev)
-+{
-+	int (*clk_probe)(struct platform_device *);
-+	int r;
-+
-+	clk_probe = of_device_get_match_data(&pdev->dev);
-+	if (!clk_probe)
-+		return -EINVAL;
-+
-+	r = clk_probe(pdev);
-+	if (r != 0)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	return r;
-+}
-+
-+static struct platform_driver clk_mt2712_drv = {
-+	.probe = clk_mt2712_probe,
-+	.driver = {
-+		.name = "clk-mt2712",
-+		.owner = THIS_MODULE,
-+		.of_match_table = of_match_clk_mt2712,
-+	},
-+};
-+
-+static int __init clk_mt2712_init(void)
-+{
-+	return platform_driver_register(&clk_mt2712_drv);
-+}
-+
-+arch_initcall(clk_mt2712_init);
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -207,6 +207,8 @@ struct mtk_pll_data {
- 	uint32_t en_mask;
- 	uint32_t pd_reg;
- 	uint32_t tuner_reg;
-+	uint32_t tuner_en_reg;
-+	uint8_t tuner_en_bit;
- 	int pd_shift;
- 	unsigned int flags;
- 	const struct clk_ops *ops;
---- a/drivers/clk/mediatek/clk-pll.c
-+++ b/drivers/clk/mediatek/clk-pll.c
-@@ -47,6 +47,7 @@ struct mtk_clk_pll {
- 	void __iomem	*pd_addr;
- 	void __iomem	*pwr_addr;
- 	void __iomem	*tuner_addr;
-+	void __iomem	*tuner_en_addr;
- 	void __iomem	*pcw_addr;
- 	const struct mtk_pll_data *data;
- };
-@@ -227,7 +228,10 @@ static int mtk_pll_prepare(struct clk_hw
- 	r |= pll->data->en_mask;
- 	writel(r, pll->base_addr + REG_CON0);
- 
--	if (pll->tuner_addr) {
-+	if (pll->tuner_en_addr) {
-+		r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
-+		writel(r, pll->tuner_en_addr);
-+	} else if (pll->tuner_addr) {
- 		r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
- 		writel(r, pll->tuner_addr);
- 	}
-@@ -254,7 +258,10 @@ static void mtk_pll_unprepare(struct clk
- 		writel(r, pll->base_addr + REG_CON0);
- 	}
- 
--	if (pll->tuner_addr) {
-+	if (pll->tuner_en_addr) {
-+		r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
-+		writel(r, pll->tuner_en_addr);
-+	} else if (pll->tuner_addr) {
- 		r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
- 		writel(r, pll->tuner_addr);
- 	}
-@@ -297,6 +304,8 @@ static struct clk *mtk_clk_register_pll(
- 	pll->pcw_addr = base + data->pcw_reg;
- 	if (data->tuner_reg)
- 		pll->tuner_addr = base + data->tuner_reg;
-+	if (data->tuner_en_reg)
-+		pll->tuner_en_addr = base + data->tuner_en_reg;
- 	pll->hw.init = &init;
- 	pll->data = data;
- 

target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch

@@ -1,190 +0,0 @@
-From acfa4eba7a4391d443b33a3d90a07eae0ef2ebca Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Thu, 5 Oct 2017 11:50:22 +0800
-Subject: [PATCH 147/224] dt-bindings: clock: mediatek: document clk bindings
- for MediaTek MT7622 SoC
-
-This patch adds the binding documentation for apmixedsys, ethsys, hifsys,
-infracfg, pericfg, topckgen and audsys for MT7622.
-
-Signed-off-by: Chen Zhong <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Acked-by: Rob Herring <[email protected]>
-Signed-off-by: Stephen Boyd <[email protected]>
----
- .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  1 +
- .../bindings/arm/mediatek/mediatek,audsys.txt      | 22 ++++++++++++++++++++++
- .../bindings/arm/mediatek/mediatek,ethsys.txt      |  1 +
- .../bindings/arm/mediatek/mediatek,hifsys.txt      |  1 +
- .../bindings/arm/mediatek/mediatek,infracfg.txt    |  1 +
- .../bindings/arm/mediatek/mediatek,pciesys.txt     | 22 ++++++++++++++++++++++
- .../bindings/arm/mediatek/mediatek,pericfg.txt     |  1 +
- .../bindings/arm/mediatek/mediatek,sgmiisys.txt    | 22 ++++++++++++++++++++++
- .../bindings/arm/mediatek/mediatek,ssusbsys.txt    | 22 ++++++++++++++++++++++
- .../bindings/arm/mediatek/mediatek,topckgen.txt    |  1 +
- 10 files changed, 94 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
- create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
- create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
- create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
-@@ -9,6 +9,7 @@ Required Properties:
- 	- "mediatek,mt2701-apmixedsys"
- 	- "mediatek,mt2712-apmixedsys", "syscon"
- 	- "mediatek,mt6797-apmixedsys"
-+	- "mediatek,mt7622-apmixedsys"
- 	- "mediatek,mt8135-apmixedsys"
- 	- "mediatek,mt8173-apmixedsys"
- - #clock-cells: Must be 1
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
-@@ -0,0 +1,22 @@
-+MediaTek AUDSYS controller
-+============================
-+
-+The MediaTek AUDSYS controller provides various clocks to the system.
-+
-+Required Properties:
-+
-+- compatible: Should be one of:
-+	- "mediatek,mt7622-audsys", "syscon"
-+- #clock-cells: Must be 1
-+
-+The AUDSYS controller uses the common clk binding from
-+Documentation/devicetree/bindings/clock/clock-bindings.txt
-+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-+
-+Example:
-+
-+audsys: audsys@11220000 {
-+	compatible = "mediatek,mt7622-audsys", "syscon";
-+	reg = <0 0x11220000 0 0x1000>;
-+	#clock-cells = <1>;
-+};
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
-@@ -7,6 +7,7 @@ Required Properties:
- 
- - compatible: Should be:
- 	- "mediatek,mt2701-ethsys", "syscon"
-+	- "mediatek,mt7622-ethsys", "syscon"
- - #clock-cells: Must be 1
- 
- The ethsys controller uses the common clk binding from
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
-@@ -8,6 +8,7 @@ Required Properties:
- 
- - compatible: Should be:
- 	- "mediatek,mt2701-hifsys", "syscon"
-+	- "mediatek,mt7622-hifsys", "syscon"
- - #clock-cells: Must be 1
- 
- The hifsys controller uses the common clk binding from
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
-@@ -10,6 +10,7 @@ Required Properties:
- 	- "mediatek,mt2701-infracfg", "syscon"
- 	- "mediatek,mt2712-infracfg", "syscon"
- 	- "mediatek,mt6797-infracfg", "syscon"
-+	- "mediatek,mt7622-infracfg", "syscon"
- 	- "mediatek,mt8135-infracfg", "syscon"
- 	- "mediatek,mt8173-infracfg", "syscon"
- - #clock-cells: Must be 1
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
-@@ -0,0 +1,22 @@
-+MediaTek PCIESYS controller
-+============================
-+
-+The MediaTek PCIESYS controller provides various clocks to the system.
-+
-+Required Properties:
-+
-+- compatible: Should be:
-+	- "mediatek,mt7622-pciesys", "syscon"
-+- #clock-cells: Must be 1
-+
-+The PCIESYS controller uses the common clk binding from
-+Documentation/devicetree/bindings/clock/clock-bindings.txt
-+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-+
-+Example:
-+
-+pciesys: pciesys@1a100800 {
-+	compatible = "mediatek,mt7622-pciesys", "syscon";
-+	reg = <0 0x1a100800 0 0x1000>;
-+	#clock-cells = <1>;
-+};
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
-@@ -9,6 +9,7 @@ Required Properties:
- - compatible: Should be one of:
- 	- "mediatek,mt2701-pericfg", "syscon"
- 	- "mediatek,mt2712-pericfg", "syscon"
-+	- "mediatek,mt7622-pericfg", "syscon"
- 	- "mediatek,mt8135-pericfg", "syscon"
- 	- "mediatek,mt8173-pericfg", "syscon"
- - #clock-cells: Must be 1
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
-@@ -0,0 +1,22 @@
-+MediaTek SGMIISYS controller
-+============================
-+
-+The MediaTek SGMIISYS controller provides various clocks to the system.
-+
-+Required Properties:
-+
-+- compatible: Should be:
-+	- "mediatek,mt7622-sgmiisys", "syscon"
-+- #clock-cells: Must be 1
-+
-+The SGMIISYS controller uses the common clk binding from
-+Documentation/devicetree/bindings/clock/clock-bindings.txt
-+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-+
-+Example:
-+
-+sgmiisys: sgmiisys@1b128000 {
-+	compatible = "mediatek,mt7622-sgmiisys", "syscon";
-+	reg = <0 0x1b128000 0 0x1000>;
-+	#clock-cells = <1>;
-+};
---- /dev/null
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
-@@ -0,0 +1,22 @@
-+MediaTek SSUSBSYS controller
-+============================
-+
-+The MediaTek SSUSBSYS controller provides various clocks to the system.
-+
-+Required Properties:
-+
-+- compatible: Should be:
-+	- "mediatek,mt7622-ssusbsys", "syscon"
-+- #clock-cells: Must be 1
-+
-+The SSUSBSYS controller uses the common clk binding from
-+Documentation/devicetree/bindings/clock/clock-bindings.txt
-+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-+
-+Example:
-+
-+ssusbsys: ssusbsys@1a000000 {
-+	compatible = "mediatek,mt7622-ssusbsys", "syscon";
-+	reg = <0 0x1a000000 0 0x1000>;
-+	#clock-cells = <1>;
-+};
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
-@@ -9,6 +9,7 @@ Required Properties:
- 	- "mediatek,mt2701-topckgen"
- 	- "mediatek,mt2712-topckgen", "syscon"
- 	- "mediatek,mt6797-topckgen"
-+	- "mediatek,mt7622-topckgen"
- 	- "mediatek,mt8135-topckgen"
- 	- "mediatek,mt8173-topckgen"
- - #clock-cells: Must be 1

target/linux/mediatek/patches-4.14/0149-clk-mediatek-add-clocks-dt-bindings-required-header-.patch

@@ -1,310 +0,0 @@
-From ea009d063f7a3d70831788046c7285a4af4ab82d Mon Sep 17 00:00:00 2001
-From: Chen Zhong <[email protected]>
-Date: Thu, 5 Oct 2017 11:50:25 +0800
-Subject: [PATCH 149/224] clk: mediatek: add clocks dt-bindings required header
- for MT7622 SoC
-
-Add the required header for the entire clocks dt-bindings exported
-from topckgen, apmixedsys, infracfg, pericfg, ethsys, pciesys, ssusbsys
-and audsys which could be found on MT7622 SoC.
-
-Signed-off-by: Chen Zhong <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Stephen Boyd <[email protected]>
----
- include/dt-bindings/clock/mt7622-clk.h | 289 +++++++++++++++++++++++++++++++++
- 1 file changed, 289 insertions(+)
- create mode 100644 include/dt-bindings/clock/mt7622-clk.h
-
---- /dev/null
-+++ b/include/dt-bindings/clock/mt7622-clk.h
-@@ -0,0 +1,289 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Chen Zhong <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_MT7622_H
-+#define _DT_BINDINGS_CLK_MT7622_H
-+
-+/* TOPCKGEN */
-+
-+#define CLK_TOP_TO_U2_PHY		0
-+#define CLK_TOP_TO_U2_PHY_1P		1
-+#define CLK_TOP_PCIE0_PIPE_EN		2
-+#define CLK_TOP_PCIE1_PIPE_EN		3
-+#define CLK_TOP_SSUSB_TX250M		4
-+#define CLK_TOP_SSUSB_EQ_RX250M		5
-+#define CLK_TOP_SSUSB_CDR_REF		6
-+#define CLK_TOP_SSUSB_CDR_FB		7
-+#define CLK_TOP_SATA_ASIC		8
-+#define CLK_TOP_SATA_RBC		9
-+#define CLK_TOP_TO_USB3_SYS		10
-+#define CLK_TOP_P1_1MHZ			11
-+#define CLK_TOP_4MHZ			12
-+#define CLK_TOP_P0_1MHZ			13
-+#define CLK_TOP_TXCLK_SRC_PRE		14
-+#define CLK_TOP_RTC			15
-+#define CLK_TOP_MEMPLL			16
-+#define CLK_TOP_DMPLL			17
-+#define CLK_TOP_SYSPLL_D2		18
-+#define CLK_TOP_SYSPLL1_D2		19
-+#define CLK_TOP_SYSPLL1_D4		20
-+#define CLK_TOP_SYSPLL1_D8		21
-+#define CLK_TOP_SYSPLL2_D4		22
-+#define CLK_TOP_SYSPLL2_D8		23
-+#define CLK_TOP_SYSPLL_D5		24
-+#define CLK_TOP_SYSPLL3_D2		25
-+#define CLK_TOP_SYSPLL3_D4		26
-+#define CLK_TOP_SYSPLL4_D2		27
-+#define CLK_TOP_SYSPLL4_D4		28
-+#define CLK_TOP_SYSPLL4_D16		29
-+#define CLK_TOP_UNIVPLL			30
-+#define CLK_TOP_UNIVPLL_D2		31
-+#define CLK_TOP_UNIVPLL1_D2		32
-+#define CLK_TOP_UNIVPLL1_D4		33
-+#define CLK_TOP_UNIVPLL1_D8		34
-+#define CLK_TOP_UNIVPLL1_D16		35
-+#define CLK_TOP_UNIVPLL2_D2		36
-+#define CLK_TOP_UNIVPLL2_D4		37
-+#define CLK_TOP_UNIVPLL2_D8		38
-+#define CLK_TOP_UNIVPLL2_D16		39
-+#define CLK_TOP_UNIVPLL_D5		40
-+#define CLK_TOP_UNIVPLL3_D2		41
-+#define CLK_TOP_UNIVPLL3_D4		42
-+#define CLK_TOP_UNIVPLL3_D16		43
-+#define CLK_TOP_UNIVPLL_D7		44
-+#define CLK_TOP_UNIVPLL_D80_D4		45
-+#define CLK_TOP_UNIV48M			46
-+#define CLK_TOP_SGMIIPLL		47
-+#define CLK_TOP_SGMIIPLL_D2		48
-+#define CLK_TOP_AUD1PLL			49
-+#define CLK_TOP_AUD2PLL			50
-+#define CLK_TOP_AUD_I2S2_MCK		51
-+#define CLK_TOP_TO_USB3_REF		52
-+#define CLK_TOP_PCIE1_MAC_EN		53
-+#define CLK_TOP_PCIE0_MAC_EN		54
-+#define CLK_TOP_ETH_500M		55
-+#define CLK_TOP_AXI_SEL			56
-+#define CLK_TOP_MEM_SEL			57
-+#define CLK_TOP_DDRPHYCFG_SEL		58
-+#define CLK_TOP_ETH_SEL			59
-+#define CLK_TOP_PWM_SEL			60
-+#define CLK_TOP_F10M_REF_SEL		61
-+#define CLK_TOP_NFI_INFRA_SEL		62
-+#define CLK_TOP_FLASH_SEL		63
-+#define CLK_TOP_UART_SEL		64
-+#define CLK_TOP_SPI0_SEL		65
-+#define CLK_TOP_SPI1_SEL		66
-+#define CLK_TOP_MSDC50_0_SEL		67
-+#define CLK_TOP_MSDC30_0_SEL		68
-+#define CLK_TOP_MSDC30_1_SEL		69
-+#define CLK_TOP_A1SYS_HP_SEL		70
-+#define CLK_TOP_A2SYS_HP_SEL		71
-+#define CLK_TOP_INTDIR_SEL		72
-+#define CLK_TOP_AUD_INTBUS_SEL		73
-+#define CLK_TOP_PMICSPI_SEL		74
-+#define CLK_TOP_SCP_SEL			75
-+#define CLK_TOP_ATB_SEL			76
-+#define CLK_TOP_HIF_SEL			77
-+#define CLK_TOP_AUDIO_SEL		78
-+#define CLK_TOP_U2_SEL			79
-+#define CLK_TOP_AUD1_SEL		80
-+#define CLK_TOP_AUD2_SEL		81
-+#define CLK_TOP_IRRX_SEL		82
-+#define CLK_TOP_IRTX_SEL		83
-+#define CLK_TOP_ASM_L_SEL		84
-+#define CLK_TOP_ASM_M_SEL		85
-+#define CLK_TOP_ASM_H_SEL		86
-+#define CLK_TOP_APLL1_SEL		87
-+#define CLK_TOP_APLL2_SEL		88
-+#define CLK_TOP_I2S0_MCK_SEL		89
-+#define CLK_TOP_I2S1_MCK_SEL		90
-+#define CLK_TOP_I2S2_MCK_SEL		91
-+#define CLK_TOP_I2S3_MCK_SEL		92
-+#define CLK_TOP_APLL1_DIV		93
-+#define CLK_TOP_APLL2_DIV		94
-+#define CLK_TOP_I2S0_MCK_DIV		95
-+#define CLK_TOP_I2S1_MCK_DIV		96
-+#define CLK_TOP_I2S2_MCK_DIV		97
-+#define CLK_TOP_I2S3_MCK_DIV		98
-+#define CLK_TOP_A1SYS_HP_DIV		99
-+#define CLK_TOP_A2SYS_HP_DIV		100
-+#define CLK_TOP_APLL1_DIV_PD		101
-+#define CLK_TOP_APLL2_DIV_PD		102
-+#define CLK_TOP_I2S0_MCK_DIV_PD		103
-+#define CLK_TOP_I2S1_MCK_DIV_PD		104
-+#define CLK_TOP_I2S2_MCK_DIV_PD		105
-+#define CLK_TOP_I2S3_MCK_DIV_PD		106
-+#define CLK_TOP_A1SYS_HP_DIV_PD		107
-+#define CLK_TOP_A2SYS_HP_DIV_PD		108
-+#define CLK_TOP_NR_CLK			109
-+
-+/* INFRACFG */
-+
-+#define CLK_INFRA_MUX1_SEL		0
-+#define CLK_INFRA_DBGCLK_PD		1
-+#define CLK_INFRA_AUDIO_PD		2
-+#define CLK_INFRA_IRRX_PD		3
-+#define CLK_INFRA_APXGPT_PD		4
-+#define CLK_INFRA_PMIC_PD		5
-+#define CLK_INFRA_TRNG			6
-+#define CLK_INFRA_NR_CLK		7
-+
-+/* PERICFG */
-+
-+#define CLK_PERIBUS_SEL			0
-+#define CLK_PERI_THERM_PD		1
-+#define CLK_PERI_PWM1_PD		2
-+#define CLK_PERI_PWM2_PD		3
-+#define CLK_PERI_PWM3_PD		4
-+#define CLK_PERI_PWM4_PD		5
-+#define CLK_PERI_PWM5_PD		6
-+#define CLK_PERI_PWM6_PD		7
-+#define CLK_PERI_PWM7_PD		8
-+#define CLK_PERI_PWM_PD			9
-+#define CLK_PERI_AP_DMA_PD		10
-+#define CLK_PERI_MSDC30_0_PD		11
-+#define CLK_PERI_MSDC30_1_PD		12
-+#define CLK_PERI_UART0_PD		13
-+#define CLK_PERI_UART1_PD		14
-+#define CLK_PERI_UART2_PD		15
-+#define CLK_PERI_UART3_PD		16
-+#define CLK_PERI_UART4_PD		17
-+#define CLK_PERI_BTIF_PD		18
-+#define CLK_PERI_I2C0_PD		19
-+#define CLK_PERI_I2C1_PD		20
-+#define CLK_PERI_I2C2_PD		21
-+#define CLK_PERI_SPI1_PD		22
-+#define CLK_PERI_AUXADC_PD		23
-+#define CLK_PERI_SPI0_PD		24
-+#define CLK_PERI_SNFI_PD		25
-+#define CLK_PERI_NFI_PD			26
-+#define CLK_PERI_NFIECC_PD		27
-+#define CLK_PERI_FLASH_PD		28
-+#define CLK_PERI_IRTX_PD		29
-+#define CLK_PERI_NR_CLK			30
-+
-+/* APMIXEDSYS */
-+
-+#define CLK_APMIXED_ARMPLL		0
-+#define CLK_APMIXED_MAINPLL		1
-+#define CLK_APMIXED_UNIV2PLL		2
-+#define CLK_APMIXED_ETH1PLL		3
-+#define CLK_APMIXED_ETH2PLL		4
-+#define CLK_APMIXED_AUD1PLL		5
-+#define CLK_APMIXED_AUD2PLL		6
-+#define CLK_APMIXED_TRGPLL		7
-+#define CLK_APMIXED_SGMIPLL		8
-+#define CLK_APMIXED_MAIN_CORE_EN	9
-+#define CLK_APMIXED_NR_CLK		10
-+
-+/* AUDIOSYS */
-+
-+#define CLK_AUDIO_AFE			0
-+#define CLK_AUDIO_HDMI			1
-+#define CLK_AUDIO_SPDF			2
-+#define CLK_AUDIO_APLL			3
-+#define CLK_AUDIO_I2SIN1		4
-+#define CLK_AUDIO_I2SIN2		5
-+#define CLK_AUDIO_I2SIN3		6
-+#define CLK_AUDIO_I2SIN4		7
-+#define CLK_AUDIO_I2SO1			8
-+#define CLK_AUDIO_I2SO2			9
-+#define CLK_AUDIO_I2SO3			10
-+#define CLK_AUDIO_I2SO4			11
-+#define CLK_AUDIO_ASRCI1		12
-+#define CLK_AUDIO_ASRCI2		13
-+#define CLK_AUDIO_ASRCO1		14
-+#define CLK_AUDIO_ASRCO2		15
-+#define CLK_AUDIO_INTDIR		16
-+#define CLK_AUDIO_A1SYS			17
-+#define CLK_AUDIO_A2SYS			18
-+#define CLK_AUDIO_UL1			19
-+#define CLK_AUDIO_UL2			20
-+#define CLK_AUDIO_UL3			21
-+#define CLK_AUDIO_UL4			22
-+#define CLK_AUDIO_UL5			23
-+#define CLK_AUDIO_UL6			24
-+#define CLK_AUDIO_DL1			25
-+#define CLK_AUDIO_DL2			26
-+#define CLK_AUDIO_DL3			27
-+#define CLK_AUDIO_DL4			28
-+#define CLK_AUDIO_DL5			29
-+#define CLK_AUDIO_DL6			30
-+#define CLK_AUDIO_DLMCH			31
-+#define CLK_AUDIO_ARB1			32
-+#define CLK_AUDIO_AWB			33
-+#define CLK_AUDIO_AWB2			34
-+#define CLK_AUDIO_DAI			35
-+#define CLK_AUDIO_MOD			36
-+#define CLK_AUDIO_ASRCI3		37
-+#define CLK_AUDIO_ASRCI4		38
-+#define CLK_AUDIO_ASRCO3		39
-+#define CLK_AUDIO_ASRCO4		40
-+#define CLK_AUDIO_MEM_ASRC1		41
-+#define CLK_AUDIO_MEM_ASRC2		42
-+#define CLK_AUDIO_MEM_ASRC3		43
-+#define CLK_AUDIO_MEM_ASRC4		44
-+#define CLK_AUDIO_MEM_ASRC5		45
-+#define CLK_AUDIO_NR_CLK		46
-+
-+/* SSUSBSYS */
-+
-+#define CLK_SSUSB_U2_PHY_1P_EN		0
-+#define CLK_SSUSB_U2_PHY_EN		1
-+#define CLK_SSUSB_REF_EN		2
-+#define CLK_SSUSB_SYS_EN		3
-+#define CLK_SSUSB_MCU_EN		4
-+#define CLK_SSUSB_DMA_EN		5
-+#define CLK_SSUSB_NR_CLK		6
-+
-+/* PCIESYS */
-+
-+#define CLK_PCIE_P1_AUX_EN		0
-+#define CLK_PCIE_P1_OBFF_EN		1
-+#define CLK_PCIE_P1_AHB_EN		2
-+#define CLK_PCIE_P1_AXI_EN		3
-+#define CLK_PCIE_P1_MAC_EN		4
-+#define CLK_PCIE_P1_PIPE_EN		5
-+#define CLK_PCIE_P0_AUX_EN		6
-+#define CLK_PCIE_P0_OBFF_EN		7
-+#define CLK_PCIE_P0_AHB_EN		8
-+#define CLK_PCIE_P0_AXI_EN		9
-+#define CLK_PCIE_P0_MAC_EN		10
-+#define CLK_PCIE_P0_PIPE_EN		11
-+#define CLK_SATA_AHB_EN			12
-+#define CLK_SATA_AXI_EN			13
-+#define CLK_SATA_ASIC_EN		14
-+#define CLK_SATA_RBC_EN			15
-+#define CLK_SATA_PM_EN			16
-+#define CLK_PCIE_NR_CLK			17
-+
-+/* ETHSYS */
-+
-+#define CLK_ETH_HSDMA_EN		0
-+#define CLK_ETH_ESW_EN			1
-+#define CLK_ETH_GP2_EN			2
-+#define CLK_ETH_GP1_EN			3
-+#define CLK_ETH_GP0_EN			4
-+#define CLK_ETH_NR_CLK			5
-+
-+/* SGMIISYS */
-+
-+#define CLK_SGMII_TX250M_EN		0
-+#define CLK_SGMII_RX250M_EN		1
-+#define CLK_SGMII_CDR_REF		2
-+#define CLK_SGMII_CDR_FB		3
-+#define CLK_SGMII_NR_CLK		4
-+
-+#endif /* _DT_BINDINGS_CLK_MT7622_H */
-+

target/linux/mediatek/patches-4.14/0150-clk-mediatek-add-clock-support-for-MT7622-SoC.patch

@@ -1,1388 +0,0 @@
-From b24e830d69f1fa637284c093410645a059b60028 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Thu, 5 Oct 2017 11:50:24 +0800
-Subject: [PATCH 150/224] clk: mediatek: add clock support for MT7622 SoC
-
-Add all supported clocks exported from every susbystem found on MT7622 SoC
-such as topckgen, apmixedsys, infracfg, pericfg , pciessys, ssusbsys,
-ethsys and audsys.
-
-Signed-off-by: Chen Zhong <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Stephen Boyd <[email protected]>
----
- drivers/clk/mediatek/Kconfig          |  30 ++
- drivers/clk/mediatek/Makefile         |   4 +
- drivers/clk/mediatek/clk-mt7622-aud.c | 195 +++++++++
- drivers/clk/mediatek/clk-mt7622-eth.c | 156 +++++++
- drivers/clk/mediatek/clk-mt7622-hif.c | 169 ++++++++
- drivers/clk/mediatek/clk-mt7622.c     | 780 ++++++++++++++++++++++++++++++++++
- 6 files changed, 1334 insertions(+)
- create mode 100644 drivers/clk/mediatek/clk-mt7622-aud.c
- create mode 100644 drivers/clk/mediatek/clk-mt7622-eth.c
- create mode 100644 drivers/clk/mediatek/clk-mt7622-hif.c
- create mode 100644 drivers/clk/mediatek/clk-mt7622.c
-
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -132,6 +132,36 @@ config COMMON_CLK_MT6797_VENCSYS
-        ---help---
-          This driver supports Mediatek MT6797 vencsys clocks.
- 
-+config COMMON_CLK_MT7622
-+	bool "Clock driver for MediaTek MT7622"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+	select COMMON_CLK_MEDIATEK
-+	default ARCH_MEDIATEK
-+	---help---
-+	  This driver supports MediaTek MT7622 basic clocks and clocks
-+	  required for various periperals found on MediaTek.
-+
-+config COMMON_CLK_MT7622_ETHSYS
-+	bool "Clock driver for MediaTek MT7622 ETHSYS"
-+	depends on COMMON_CLK_MT7622
-+	---help---
-+	  This driver add support for clocks for Ethernet and SGMII
-+	  required on MediaTek MT7622 SoC.
-+
-+config COMMON_CLK_MT7622_HIFSYS
-+	bool "Clock driver for MediaTek MT7622 HIFSYS"
-+	depends on COMMON_CLK_MT7622
-+	---help---
-+	  This driver supports MediaTek MT7622 HIFSYS clocks providing
-+	  to PCI-E and USB.
-+
-+config COMMON_CLK_MT7622_AUDSYS
-+	bool "Clock driver for MediaTek MT7622 AUDSYS"
-+	depends on COMMON_CLK_MT7622
-+	---help---
-+	  This driver supports MediaTek MT7622 AUDSYS clocks providing
-+	  to audio consumers such as I2S and TDM.
-+
- config COMMON_CLK_MT8135
- 	bool "Clock driver for Mediatek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -21,5 +21,9 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) +
- obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
- obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
- obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
-+obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o
-+obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
-+obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
-@@ -0,0 +1,195 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Chen Zhong <[email protected]>
-+ *	   Sean Wang <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt7622-clk.h>
-+
-+#define GATE_AUDIO0(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &audio0_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr,	\
-+	}
-+
-+#define GATE_AUDIO1(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &audio1_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr,	\
-+	}
-+
-+#define GATE_AUDIO2(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &audio2_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr,	\
-+	}
-+
-+#define GATE_AUDIO3(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &audio3_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr,	\
-+	}
-+
-+static const struct mtk_gate_regs audio0_cg_regs = {
-+	.set_ofs = 0x0,
-+	.clr_ofs = 0x0,
-+	.sta_ofs = 0x0,
-+};
-+
-+static const struct mtk_gate_regs audio1_cg_regs = {
-+	.set_ofs = 0x10,
-+	.clr_ofs = 0x10,
-+	.sta_ofs = 0x10,
-+};
-+
-+static const struct mtk_gate_regs audio2_cg_regs = {
-+	.set_ofs = 0x14,
-+	.clr_ofs = 0x14,
-+	.sta_ofs = 0x14,
-+};
-+
-+static const struct mtk_gate_regs audio3_cg_regs = {
-+	.set_ofs = 0x634,
-+	.clr_ofs = 0x634,
-+	.sta_ofs = 0x634,
-+};
-+
-+static const struct mtk_gate audio_clks[] = {
-+	/* AUDIO0 */
-+	GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
-+	GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
-+	GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
-+	GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
-+	/* AUDIO1 */
-+	GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
-+	GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
-+	GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
-+	GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
-+	GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
-+	GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
-+	GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
-+	GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
-+	GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
-+	GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
-+	GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
-+	GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
-+	GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
-+	GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
-+	GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
-+	/* AUDIO2 */
-+	GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
-+	GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
-+	GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
-+	GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
-+	GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
-+	GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
-+	GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
-+	GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
-+	GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
-+	GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
-+	GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
-+	GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
-+	GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
-+	GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
-+	GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
-+	GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
-+	GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
-+	GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
-+	/* AUDIO3 */
-+	GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
-+	GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
-+	GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
-+	GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
-+	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
-+	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
-+	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
-+	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
-+	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
-+};
-+
-+static int clk_mt7622_audiosys_init(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	struct device_node *node = pdev->dev.of_node;
-+	int r;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
-+
-+	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
-+			       clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+	if (r)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt7622_aud[] = {
-+	{
-+		.compatible = "mediatek,mt7622-audsys",
-+		.data = clk_mt7622_audiosys_init,
-+	}, {
-+		/* sentinel */
-+	}
-+};
-+
-+static int clk_mt7622_aud_probe(struct platform_device *pdev)
-+{
-+	int (*clk_init)(struct platform_device *);
-+	int r;
-+
-+	clk_init = of_device_get_match_data(&pdev->dev);
-+	if (!clk_init)
-+		return -EINVAL;
-+
-+	r = clk_init(pdev);
-+	if (r)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	return r;
-+}
-+
-+static struct platform_driver clk_mt7622_aud_drv = {
-+	.probe = clk_mt7622_aud_probe,
-+	.driver = {
-+		.name = "clk-mt7622-aud",
-+		.of_match_table = of_match_clk_mt7622_aud,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt7622_aud_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
-@@ -0,0 +1,156 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Chen Zhong <[email protected]>
-+ *	   Sean Wang <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt7622-clk.h>
-+
-+#define GATE_ETH(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &eth_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate_regs eth_cg_regs = {
-+	.set_ofs = 0x30,
-+	.clr_ofs = 0x30,
-+	.sta_ofs = 0x30,
-+};
-+
-+static const struct mtk_gate eth_clks[] = {
-+	GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
-+	GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
-+	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
-+	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
-+	GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
-+};
-+
-+static const struct mtk_gate_regs sgmii_cg_regs = {
-+	.set_ofs = 0xE4,
-+	.clr_ofs = 0xE4,
-+	.sta_ofs = 0xE4,
-+};
-+
-+#define GATE_SGMII(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &sgmii_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate sgmii_clks[] = {
-+	GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
-+		   "ssusb_tx250m", 2),
-+	GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
-+		   "ssusb_eq_rx250m", 3),
-+	GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
-+		   "ssusb_cdr_ref", 4),
-+	GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
-+		   "ssusb_cdr_fb", 5),
-+};
-+
-+static int clk_mt7622_ethsys_init(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	struct device_node *node = pdev->dev.of_node;
-+	int r;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
-+
-+	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
-+			       clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+	if (r)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	mtk_register_reset_controller(node, 1, 0x34);
-+
-+	return r;
-+}
-+
-+static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	struct device_node *node = pdev->dev.of_node;
-+	int r;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
-+
-+	mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
-+			       clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+	if (r)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt7622_eth[] = {
-+	{
-+		.compatible = "mediatek,mt7622-ethsys",
-+		.data = clk_mt7622_ethsys_init,
-+	}, {
-+		.compatible = "mediatek,mt7622-sgmiisys",
-+		.data = clk_mt7622_sgmiisys_init,
-+	}, {
-+		/* sentinel */
-+	}
-+};
-+
-+static int clk_mt7622_eth_probe(struct platform_device *pdev)
-+{
-+	int (*clk_init)(struct platform_device *);
-+	int r;
-+
-+	clk_init = of_device_get_match_data(&pdev->dev);
-+	if (!clk_init)
-+		return -EINVAL;
-+
-+	r = clk_init(pdev);
-+	if (r)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	return r;
-+}
-+
-+static struct platform_driver clk_mt7622_eth_drv = {
-+	.probe = clk_mt7622_eth_probe,
-+	.driver = {
-+		.name = "clk-mt7622-eth",
-+		.of_match_table = of_match_clk_mt7622_eth,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt7622_eth_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
-@@ -0,0 +1,169 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Chen Zhong <[email protected]>
-+ *	   Sean Wang <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mt7622-clk.h>
-+
-+#define GATE_PCIE(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &pcie_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-+	}
-+
-+#define GATE_SSUSB(_id, _name, _parent, _shift) {	\
-+		.id = _id,				\
-+		.name = _name,				\
-+		.parent_name = _parent,			\
-+		.regs = &ssusb_cg_regs,			\
-+		.shift = _shift,			\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
-+	}
-+
-+static const struct mtk_gate_regs pcie_cg_regs = {
-+	.set_ofs = 0x30,
-+	.clr_ofs = 0x30,
-+	.sta_ofs = 0x30,
-+};
-+
-+static const struct mtk_gate_regs ssusb_cg_regs = {
-+	.set_ofs = 0x30,
-+	.clr_ofs = 0x30,
-+	.sta_ofs = 0x30,
-+};
-+
-+static const struct mtk_gate ssusb_clks[] = {
-+	GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
-+		   "to_u2_phy_1p", 0),
-+	GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
-+	GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
-+	GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
-+	GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
-+	GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
-+};
-+
-+static const struct mtk_gate pcie_clks[] = {
-+	GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
-+	GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
-+	GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
-+	GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
-+	GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
-+	GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
-+	GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
-+	GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
-+	GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
-+	GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
-+	GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
-+	GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
-+	GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
-+	GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
-+	GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
-+	GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
-+	GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
-+};
-+
-+static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	struct device_node *node = pdev->dev.of_node;
-+	int r;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
-+
-+	mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
-+			       clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+	if (r)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	mtk_register_reset_controller(node, 1, 0x34);
-+
-+	return r;
-+}
-+
-+static int clk_mt7622_pciesys_init(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	struct device_node *node = pdev->dev.of_node;
-+	int r;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
-+
-+	mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
-+			       clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+	if (r)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	mtk_register_reset_controller(node, 1, 0x34);
-+
-+	return r;
-+}
-+
-+static const struct of_device_id of_match_clk_mt7622_hif[] = {
-+	{
-+		.compatible = "mediatek,mt7622-pciesys",
-+		.data = clk_mt7622_pciesys_init,
-+	}, {
-+		.compatible = "mediatek,mt7622-ssusbsys",
-+		.data = clk_mt7622_ssusbsys_init,
-+	}, {
-+		/* sentinel */
-+	}
-+};
-+
-+static int clk_mt7622_hif_probe(struct platform_device *pdev)
-+{
-+	int (*clk_init)(struct platform_device *);
-+	int r;
-+
-+	clk_init = of_device_get_match_data(&pdev->dev);
-+	if (!clk_init)
-+		return -EINVAL;
-+
-+	r = clk_init(pdev);
-+	if (r)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	return r;
-+}
-+
-+static struct platform_driver clk_mt7622_hif_drv = {
-+	.probe = clk_mt7622_hif_probe,
-+	.driver = {
-+		.name = "clk-mt7622-hif",
-+		.of_match_table = of_match_clk_mt7622_hif,
-+	},
-+};
-+
-+builtin_platform_driver(clk_mt7622_hif_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7622.c
-@@ -0,0 +1,780 @@
-+/*
-+ * Copyright (c) 2017 MediaTek Inc.
-+ * Author: Chen Zhong <[email protected]>
-+ *	   Sean Wang <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-cpumux.h"
-+
-+#include <dt-bindings/clock/mt7622-clk.h>
-+#include <linux/clk.h> /* for consumer */
-+
-+#define MT7622_PLL_FMAX		(2500UL * MHZ)
-+#define CON0_MT7622_RST_BAR	BIT(27)
-+
-+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
-+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
-+			_pcw_shift, _div_table, _parent_name) {		\
-+		.id = _id,						\
-+		.name = _name,						\
-+		.reg = _reg,						\
-+		.pwr_reg = _pwr_reg,					\
-+		.en_mask = _en_mask,					\
-+		.flags = _flags,					\
-+		.rst_bar_mask = CON0_MT7622_RST_BAR,			\
-+		.fmax = MT7622_PLL_FMAX,				\
-+		.pcwbits = _pcwbits,					\
-+		.pd_reg = _pd_reg,					\
-+		.pd_shift = _pd_shift,					\
-+		.tuner_reg = _tuner_reg,				\
-+		.pcw_reg = _pcw_reg,					\
-+		.pcw_shift = _pcw_shift,				\
-+		.div_table = _div_table,				\
-+		.parent_name = _parent_name,				\
-+	}
-+
-+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
-+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
-+			_pcw_shift)					\
-+	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
-+		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,  \
-+		 NULL, "clkxtal")
-+
-+#define GATE_APMIXED(_id, _name, _parent, _shift) {			\
-+		.id = _id,						\
-+		.name = _name,						\
-+		.parent_name = _parent,					\
-+		.regs = &apmixed_cg_regs,				\
-+		.shift = _shift,					\
-+		.ops = &mtk_clk_gate_ops_no_setclr_inv,			\
-+	}
-+
-+#define GATE_INFRA(_id, _name, _parent, _shift) {			\
-+		.id = _id,						\
-+		.name = _name,						\
-+		.parent_name = _parent,					\
-+		.regs = &infra_cg_regs,					\
-+		.shift = _shift,					\
-+		.ops = &mtk_clk_gate_ops_setclr,			\
-+	}
-+
-+#define GATE_TOP0(_id, _name, _parent, _shift) {			\
-+		.id = _id,						\
-+		.name = _name,						\
-+		.parent_name = _parent,					\
-+		.regs = &top0_cg_regs,					\
-+		.shift = _shift,					\
-+		.ops = &mtk_clk_gate_ops_no_setclr,			\
-+	}
-+
-+#define GATE_TOP1(_id, _name, _parent, _shift) {			\
-+		.id = _id,						\
-+		.name = _name,						\
-+		.parent_name = _parent,					\
-+		.regs = &top1_cg_regs,					\
-+		.shift = _shift,					\
-+		.ops = &mtk_clk_gate_ops_no_setclr,			\
-+	}
-+
-+#define GATE_PERI0(_id, _name, _parent, _shift) {			\
-+		.id = _id,						\
-+		.name = _name,						\
-+		.parent_name = _parent,					\
-+		.regs = &peri0_cg_regs,					\
-+		.shift = _shift,					\
-+		.ops = &mtk_clk_gate_ops_setclr,			\
-+	}
-+
-+#define GATE_PERI1(_id, _name, _parent, _shift) {			\
-+		.id = _id,						\
-+		.name = _name,						\
-+		.parent_name = _parent,					\
-+		.regs = &peri1_cg_regs,					\
-+		.shift = _shift,					\
-+		.ops = &mtk_clk_gate_ops_setclr,			\
-+	}
-+
-+static DEFINE_SPINLOCK(mt7622_clk_lock);
-+
-+static const char * const infra_mux1_parents[] = {
-+	"clkxtal",
-+	"armpll",
-+	"main_core_en",
-+	"armpll"
-+};
-+
-+static const char * const axi_parents[] = {
-+	"clkxtal",
-+	"syspll1_d2",
-+	"syspll_d5",
-+	"syspll1_d4",
-+	"univpll_d5",
-+	"univpll2_d2",
-+	"univpll_d7"
-+};
-+
-+static const char * const mem_parents[] = {
-+	"clkxtal",
-+	"dmpll_ck"
-+};
-+
-+static const char * const ddrphycfg_parents[] = {
-+	"clkxtal",
-+	"syspll1_d8"
-+};
-+
-+static const char * const eth_parents[] = {
-+	"clkxtal",
-+	"syspll1_d2",
-+	"univpll1_d2",
-+	"syspll1_d4",
-+	"univpll_d5",
-+	"clk_null",
-+	"univpll_d7"
-+};
-+
-+static const char * const pwm_parents[] = {
-+	"clkxtal",
-+	"univpll2_d4"
-+};
-+
-+static const char * const f10m_ref_parents[] = {
-+	"clkxtal",
-+	"syspll4_d16"
-+};
-+
-+static const char * const nfi_infra_parents[] = {
-+	"clkxtal",
-+	"clkxtal",
-+	"clkxtal",
-+	"clkxtal",
-+	"clkxtal",
-+	"clkxtal",
-+	"clkxtal",
-+	"clkxtal",
-+	"univpll2_d8",
-+	"syspll1_d8",
-+	"univpll1_d8",
-+	"syspll4_d2",
-+	"univpll2_d4",
-+	"univpll3_d2",
-+	"syspll1_d4"
-+};
-+
-+static const char * const flash_parents[] = {
-+	"clkxtal",
-+	"univpll_d80_d4",
-+	"syspll2_d8",
-+	"syspll3_d4",
-+	"univpll3_d4",
-+	"univpll1_d8",
-+	"syspll2_d4",
-+	"univpll2_d4"
-+};
-+
-+static const char * const uart_parents[] = {
-+	"clkxtal",
-+	"univpll2_d8"
-+};
-+
-+static const char * const spi0_parents[] = {
-+	"clkxtal",
-+	"syspll3_d2",
-+	"clkxtal",
-+	"syspll2_d4",
-+	"syspll4_d2",
-+	"univpll2_d4",
-+	"univpll1_d8",
-+	"clkxtal"
-+};
-+
-+static const char * const spi1_parents[] = {
-+	"clkxtal",
-+	"syspll3_d2",
-+	"clkxtal",
-+	"syspll4_d4",
-+	"syspll4_d2",
-+	"univpll2_d4",
-+	"univpll1_d8",
-+	"clkxtal"
-+};
-+
-+static const char * const msdc30_0_parents[] = {
-+	"clkxtal",
-+	"univpll2_d16",
-+	"univ48m"
-+};
-+
-+static const char * const a1sys_hp_parents[] = {
-+	"clkxtal",
-+	"aud1pll_ck",
-+	"aud2pll_ck",
-+	"clkxtal"
-+};
-+
-+static const char * const intdir_parents[] = {
-+	"clkxtal",
-+	"syspll_d2",
-+	"univpll_d2",
-+	"sgmiipll_ck"
-+};
-+
-+static const char * const aud_intbus_parents[] = {
-+	"clkxtal",
-+	"syspll1_d4",
-+	"syspll4_d2",
-+	"syspll3_d2"
-+};
-+
-+static const char * const pmicspi_parents[] = {
-+	"clkxtal",
-+	"clk_null",
-+	"clk_null",
-+	"clk_null",
-+	"clk_null",
-+	"univpll2_d16"
-+};
-+
-+static const char * const atb_parents[] = {
-+	"clkxtal",
-+	"syspll1_d2",
-+	"syspll_d5"
-+};
-+
-+static const char * const audio_parents[] = {
-+	"clkxtal",
-+	"syspll3_d4",
-+	"syspll4_d4",
-+	"univpll1_d16"
-+};
-+
-+static const char * const usb20_parents[] = {
-+	"clkxtal",
-+	"univpll3_d4",
-+	"syspll1_d8",
-+	"clkxtal"
-+};
-+
-+static const char * const aud1_parents[] = {
-+	"clkxtal",
-+	"aud1pll_ck"
-+};
-+
-+static const char * const aud2_parents[] = {
-+	"clkxtal",
-+	"aud2pll_ck"
-+};
-+
-+static const char * const asm_l_parents[] = {
-+	"clkxtal",
-+	"syspll_d5",
-+	"univpll2_d2",
-+	"univpll2_d4"
-+};
-+
-+static const char * const apll1_ck_parents[] = {
-+	"aud1_sel",
-+	"aud2_sel"
-+};
-+
-+static const char * const peribus_ck_parents[] = {
-+	"syspll1_d8",
-+	"syspll1_d4"
-+};
-+
-+static const struct mtk_gate_regs apmixed_cg_regs = {
-+	.set_ofs = 0x8,
-+	.clr_ofs = 0x8,
-+	.sta_ofs = 0x8,
-+};
-+
-+static const struct mtk_gate_regs infra_cg_regs = {
-+	.set_ofs = 0x40,
-+	.clr_ofs = 0x44,
-+	.sta_ofs = 0x48,
-+};
-+
-+static const struct mtk_gate_regs top0_cg_regs = {
-+	.set_ofs = 0x120,
-+	.clr_ofs = 0x120,
-+	.sta_ofs = 0x120,
-+};
-+
-+static const struct mtk_gate_regs top1_cg_regs = {
-+	.set_ofs = 0x128,
-+	.clr_ofs = 0x128,
-+	.sta_ofs = 0x128,
-+};
-+
-+static const struct mtk_gate_regs peri0_cg_regs = {
-+	.set_ofs = 0x8,
-+	.clr_ofs = 0x10,
-+	.sta_ofs = 0x18,
-+};
-+
-+static const struct mtk_gate_regs peri1_cg_regs = {
-+	.set_ofs = 0xC,
-+	.clr_ofs = 0x14,
-+	.sta_ofs = 0x1C,
-+};
-+
-+static const struct mtk_pll_data plls[] = {
-+	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
-+	    PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
-+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
-+	    HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
-+	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
-+	    HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
-+	PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
-+	    0, 21, 0x0300, 1, 0, 0x0304, 0),
-+	PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
-+	    0, 21, 0x0314, 1, 0, 0x0318, 0),
-+	PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
-+	    0, 31, 0x0324, 1, 0, 0x0328, 0),
-+	PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
-+	    0, 31, 0x0334, 1, 0, 0x0338, 0),
-+	PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
-+	    0, 21, 0x0344, 1, 0, 0x0348, 0),
-+	PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
-+	    0, 21, 0x0358, 1, 0, 0x035C, 0),
-+};
-+
-+static const struct mtk_gate apmixed_clks[] = {
-+	GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
-+};
-+
-+static const struct mtk_gate infra_clks[] = {
-+	GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
-+	GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
-+	GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
-+	GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
-+	GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
-+	GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
-+};
-+
-+static const struct mtk_fixed_clk top_fixed_clks[] = {
-+	FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
-+		  31250000),
-+	FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
-+		  31250000),
-+	FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
-+		  125000000),
-+	FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
-+		  125000000),
-+	FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
-+		  250000000),
-+	FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
-+		  250000000),
-+	FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
-+		  33333333),
-+	FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
-+		  50000000),
-+	FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
-+		  50000000),
-+	FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
-+		  50000000),
-+};
-+
-+static const struct mtk_fixed_factor top_divs[] = {
-+	FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
-+	FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
-+	FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
-+	FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
-+	FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
-+	FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
-+	FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
-+	FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
-+	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
-+	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
-+	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
-+	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
-+	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
-+	FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
-+	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
-+	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
-+	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
-+	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
-+	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
-+	FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
-+	FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
-+	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
-+	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
-+	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
-+	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
-+	FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
-+	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
-+	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
-+	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
-+	FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
-+	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
-+	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
-+	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
-+	FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
-+	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
-+	FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
-+	FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
-+	FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
-+	FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
-+	FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
-+	FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
-+	FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
-+	FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
-+	FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
-+	FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
-+	FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
-+};
-+
-+static const struct mtk_gate top_clks[] = {
-+	/* TOP0 */
-+	GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
-+	GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
-+	GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
-+		  2),
-+	GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
-+		  3),
-+	GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
-+		  4),
-+	GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
-+		  5),
-+
-+	/* TOP1 */
-+	GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
-+	GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
-+};
-+
-+static const struct mtk_clk_divider top_adj_divs[] = {
-+	DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
-+		0x120, 24, 3),
-+	DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
-+		0x120, 28, 3),
-+	DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
-+		0x124, 0, 7),
-+	DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
-+		0x124, 8, 7),
-+	DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
-+		0x124, 16, 7),
-+	DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
-+		0x124, 24, 7),
-+	DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
-+		0x128, 8, 7),
-+	DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
-+		0x128, 24, 7),
-+};
-+
-+static const struct mtk_gate peri_clks[] = {
-+	/* PERI0 */
-+	GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
-+	GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
-+	GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
-+	GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
-+	GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
-+	GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
-+	GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
-+	GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
-+	GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
-+	GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
-+	GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
-+	GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
-+	GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
-+	GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
-+	GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
-+	GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
-+	GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
-+	GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
-+	GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
-+	GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
-+	GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
-+	GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
-+	GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
-+	GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
-+	GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
-+	GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
-+	GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
-+
-+	/* PERI1 */
-+	GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
-+	GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
-+};
-+
-+static struct mtk_composite infra_muxes[] __initdata = {
-+	MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
-+	    0x000, 2, 2),
-+};
-+
-+static struct mtk_composite top_muxes[] = {
-+	/* CLK_CFG_0 */
-+	MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
-+		 0x040, 0, 3, 7),
-+	MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
-+		 0x040, 8, 1, 15),
-+	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
-+		 0x040, 16, 1, 23),
-+	MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
-+		 0x040, 24, 3, 31),
-+
-+	/* CLK_CFG_1 */
-+	MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
-+		 0x050, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
-+		 0x050, 8, 1, 15),
-+	MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
-+		 0x050, 16, 4, 23),
-+	MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
-+		 0x050, 24, 3, 31),
-+
-+	/* CLK_CFG_2 */
-+	MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
-+		 0x060, 0, 1, 7),
-+	MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
-+		 0x060, 8, 3, 15),
-+	MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
-+		 0x060, 16, 3, 23),
-+	MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
-+		 0x060, 24, 3, 31),
-+
-+	/* CLK_CFG_3 */
-+	MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
-+		 0x070, 0, 3, 7),
-+	MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
-+		 0x070, 8, 3, 15),
-+	MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
-+		 0x070, 16, 2, 23),
-+	MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
-+		 0x070, 24, 2, 31),
-+
-+	/* CLK_CFG_4 */
-+	MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
-+		 0x080, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
-+		 0x080, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
-+		 0x080, 16, 3, 23),
-+	MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
-+		 0x080, 24, 2, 31),
-+
-+	/* CLK_CFG_5 */
-+	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
-+		 0x090, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
-+		 0x090, 8, 3, 15),
-+	MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
-+		 0x090, 16, 2, 23),
-+	MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
-+		 0x090, 24, 2, 31),
-+
-+	/* CLK_CFG_6 */
-+	MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
-+		 0x0A0, 0, 1, 7),
-+	MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
-+		 0x0A0, 8, 1, 15),
-+	MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
-+		 0x0A0, 16, 1, 23),
-+	MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
-+		 0x0A0, 24, 1, 31),
-+
-+	/* CLK_CFG_7 */
-+	MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
-+		 0x0B0, 0, 2, 7),
-+	MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
-+		 0x0B0, 8, 2, 15),
-+	MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
-+		 0x0B0, 16, 2, 23),
-+
-+	/* CLK_AUDDIV_0 */
-+	MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
-+	    0x120, 6, 1),
-+	MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
-+	    0x120, 7, 1),
-+	MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
-+	    0x120, 8, 1),
-+	MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
-+	    0x120, 9, 1),
-+	MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
-+	    0x120, 10, 1),
-+	MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
-+	    0x120, 11, 1),
-+};
-+
-+static struct mtk_composite peri_muxes[] = {
-+	/* PERI_GLOBALCON_CKSEL */
-+	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
-+};
-+
-+static int mtk_topckgen_init(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	void __iomem *base;
-+	struct device_node *node = pdev->dev.of_node;
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+	base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(base))
-+		return PTR_ERR(base);
-+
-+	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
-+
-+	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-+				    clk_data);
-+
-+	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
-+				 clk_data);
-+
-+	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
-+				    base, &mt7622_clk_lock, clk_data);
-+
-+	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
-+				  base, &mt7622_clk_lock, clk_data);
-+
-+	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
-+			       clk_data);
-+
-+	clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
-+	clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
-+	clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
-+
-+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+}
-+
-+static int __init mtk_infrasys_init(struct platform_device *pdev)
-+{
-+	struct device_node *node = pdev->dev.of_node;
-+	struct clk_onecell_data *clk_data;
-+	int r;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
-+
-+	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-+			       clk_data);
-+
-+	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
-+				  clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get,
-+				clk_data);
-+	if (r)
-+		return r;
-+
-+	mtk_register_reset_controller(node, 1, 0x30);
-+
-+	return 0;
-+}
-+
-+static int mtk_apmixedsys_init(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	struct device_node *node = pdev->dev.of_node;
-+
-+	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
-+	if (!clk_data)
-+		return -ENOMEM;
-+
-+	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
-+			      clk_data);
-+
-+	mtk_clk_register_gates(node, apmixed_clks,
-+			       ARRAY_SIZE(apmixed_clks), clk_data);
-+
-+	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-+	clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
-+
-+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+}
-+
-+static int mtk_pericfg_init(struct platform_device *pdev)
-+{
-+	struct clk_onecell_data *clk_data;
-+	void __iomem *base;
-+	int r;
-+	struct device_node *node = pdev->dev.of_node;
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+	base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(base))
-+		return PTR_ERR(base);
-+
-+	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
-+
-+	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
-+			       clk_data);
-+
-+	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
-+				    &mt7622_clk_lock, clk_data);
-+
-+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-+	if (r)
-+		return r;
-+
-+	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
-+
-+	mtk_register_reset_controller(node, 2, 0x0);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id of_match_clk_mt7622[] = {
-+	{
-+		.compatible = "mediatek,mt7622-apmixedsys",
-+		.data = mtk_apmixedsys_init,
-+	}, {
-+		.compatible = "mediatek,mt7622-infracfg",
-+		.data = mtk_infrasys_init,
-+	}, {
-+		.compatible = "mediatek,mt7622-topckgen",
-+		.data = mtk_topckgen_init,
-+	}, {
-+		.compatible = "mediatek,mt7622-pericfg",
-+		.data = mtk_pericfg_init,
-+	}, {
-+		/* sentinel */
-+	}
-+};
-+
-+static int clk_mt7622_probe(struct platform_device *pdev)
-+{
-+	int (*clk_init)(struct platform_device *);
-+	int r;
-+
-+	clk_init = of_device_get_match_data(&pdev->dev);
-+	if (!clk_init)
-+		return -EINVAL;
-+
-+	r = clk_init(pdev);
-+	if (r)
-+		dev_err(&pdev->dev,
-+			"could not register clock provider: %s: %d\n",
-+			pdev->name, r);
-+
-+	return r;
-+}
-+
-+static struct platform_driver clk_mt7622_drv = {
-+	.probe = clk_mt7622_probe,
-+	.driver = {
-+		.name = "clk-mt7622",
-+		.of_match_table = of_match_clk_mt7622,
-+	},
-+};
-+
-+static int clk_mt7622_init(void)
-+{
-+	return platform_driver_register(&clk_mt7622_drv);
-+}
-+
-+arch_initcall(clk_mt7622_init);

target/linux/mediatek/patches-4.14/0151-arm64-dts-mt8173-remove-mediatek-mt8135-mmc-from-mmc.patch

@@ -1,61 +0,0 @@
-From fa69904d3b7357a5be43771f764e10fd99ebbb11 Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:30 +0800
-Subject: [PATCH 151/224] arm64: dts: mt8173: remove "mediatek, mt8135-mmc"
- from mmc nodes
-
-devicetree bindings has been updated to support multi-platforms,
-so that each platform has its owns compatible name.
-And, this compatible name may used in driver to distinguish with
-other platform.
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
-Acked-by: Matthias Brugger <[email protected]>
----
- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++--------
- 1 file changed, 4 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
-@@ -684,8 +684,7 @@
- 		};
- 
- 		mmc0: mmc@11230000 {
--			compatible = "mediatek,mt8173-mmc",
--				     "mediatek,mt8135-mmc";
-+			compatible = "mediatek,mt8173-mmc";
- 			reg = <0 0x11230000 0 0x1000>;
- 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
- 			clocks = <&pericfg CLK_PERI_MSDC30_0>,
-@@ -695,8 +694,7 @@
- 		};
- 
- 		mmc1: mmc@11240000 {
--			compatible = "mediatek,mt8173-mmc",
--				     "mediatek,mt8135-mmc";
-+			compatible = "mediatek,mt8173-mmc";
- 			reg = <0 0x11240000 0 0x1000>;
- 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
- 			clocks = <&pericfg CLK_PERI_MSDC30_1>,
-@@ -706,8 +704,7 @@
- 		};
- 
- 		mmc2: mmc@11250000 {
--			compatible = "mediatek,mt8173-mmc",
--				     "mediatek,mt8135-mmc";
-+			compatible = "mediatek,mt8173-mmc";
- 			reg = <0 0x11250000 0 0x1000>;
- 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
- 			clocks = <&pericfg CLK_PERI_MSDC30_2>,
-@@ -717,8 +714,7 @@
- 		};
- 
- 		mmc3: mmc@11260000 {
--			compatible = "mediatek,mt8173-mmc",
--				     "mediatek,mt8135-mmc";
-+			compatible = "mediatek,mt8173-mmc";
- 			reg = <0 0x11260000 0 0x1000>;
- 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
- 			clocks = <&pericfg CLK_PERI_MSDC30_3>,

target/linux/mediatek/patches-4.14/0152-mmc-mediatek-make-hs400_tune_response-only-for-mt817.patch

@@ -1,70 +0,0 @@
-From bc70c7f1174b937af2784977281a1567f69dd2b6 Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:31 +0800
-Subject: [PATCH 152/224] mmc: mediatek: make hs400_tune_response only for
- mt8173
-
-the origin design of hs400_tune_response is for mt8173 because of
-mt8173 has a special design. for doing that, we add a new member
-"compatible", by now it's only for mt8173.
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 11 +++++++++--
- 1 file changed, 9 insertions(+), 2 deletions(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -302,6 +302,7 @@ struct msdc_save_para {
- 
- struct mtk_mmc_compatible {
- 	u8 clk_div_bits;
-+	bool hs400_tune; /* only used for MT8173 */
- };
- 
- struct msdc_tune_para {
-@@ -362,18 +363,22 @@ struct msdc_host {
- 
- static const struct mtk_mmc_compatible mt8135_compat = {
- 	.clk_div_bits = 8,
-+	.hs400_tune = false,
- };
- 
- static const struct mtk_mmc_compatible mt8173_compat = {
- 	.clk_div_bits = 8,
-+	.hs400_tune = true,
- };
- 
- static const struct mtk_mmc_compatible mt2701_compat = {
- 	.clk_div_bits = 12,
-+	.hs400_tune = false,
- };
- 
- static const struct mtk_mmc_compatible mt2712_compat = {
- 	.clk_div_bits = 12,
-+	.hs400_tune = false,
- };
- 
- static const struct of_device_id msdc_of_ids[] = {
-@@ -668,7 +673,8 @@ static void msdc_set_mclk(struct msdc_ho
- 		       host->base + PAD_CMD_TUNE);
- 	}
- 
--	if (timing == MMC_TIMING_MMC_HS400)
-+	if (timing == MMC_TIMING_MMC_HS400 &&
-+	    host->dev_comp->hs400_tune)
- 		sdr_set_field(host->base + PAD_CMD_TUNE,
- 			      MSDC_PAD_TUNE_CMDRRDLY,
- 			      host->hs400_cmd_int_delay);
-@@ -1597,7 +1603,8 @@ static int msdc_execute_tuning(struct mm
- 	struct msdc_host *host = mmc_priv(mmc);
- 	int ret;
- 
--	if (host->hs400_mode)
-+	if (host->hs400_mode &&
-+	    host->dev_comp->hs400_tune)
- 		ret = hs400_tune_response(mmc, opcode);
- 	else
- 		ret = msdc_tune_response(mmc, opcode);

target/linux/mediatek/patches-4.14/0153-mmc-mediatek-add-pad_tune0-support.patch

@@ -1,256 +0,0 @@
-From a10349f1710a11239c58da3a7e5b353c6b2070c2 Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:32 +0800
-Subject: [PATCH 153/224] mmc: mediatek: add pad_tune0 support
-
-from mt2701, the register of PAD_TUNE has been phased out,
-while there is a new register of PAD_TUNE0
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 51 ++++++++++++++++++++++++++++++-----------------
- 1 file changed, 33 insertions(+), 18 deletions(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -75,6 +75,7 @@
- #define MSDC_PATCH_BIT   0xb0
- #define MSDC_PATCH_BIT1  0xb4
- #define MSDC_PAD_TUNE    0xec
-+#define MSDC_PAD_TUNE0   0xf0
- #define PAD_DS_TUNE      0x188
- #define PAD_CMD_TUNE     0x18c
- #define EMMC50_CFG0      0x208
-@@ -303,6 +304,7 @@ struct msdc_save_para {
- struct mtk_mmc_compatible {
- 	u8 clk_div_bits;
- 	bool hs400_tune; /* only used for MT8173 */
-+	u32 pad_tune_reg;
- };
- 
- struct msdc_tune_para {
-@@ -364,21 +366,25 @@ struct msdc_host {
- static const struct mtk_mmc_compatible mt8135_compat = {
- 	.clk_div_bits = 8,
- 	.hs400_tune = false,
-+	.pad_tune_reg = MSDC_PAD_TUNE,
- };
- 
- static const struct mtk_mmc_compatible mt8173_compat = {
- 	.clk_div_bits = 8,
- 	.hs400_tune = true,
-+	.pad_tune_reg = MSDC_PAD_TUNE,
- };
- 
- static const struct mtk_mmc_compatible mt2701_compat = {
- 	.clk_div_bits = 12,
- 	.hs400_tune = false,
-+	.pad_tune_reg = MSDC_PAD_TUNE0,
- };
- 
- static const struct mtk_mmc_compatible mt2712_compat = {
- 	.clk_div_bits = 12,
- 	.hs400_tune = false,
-+	.pad_tune_reg = MSDC_PAD_TUNE0,
- };
- 
- static const struct of_device_id msdc_of_ids[] = {
-@@ -583,6 +589,7 @@ static void msdc_set_mclk(struct msdc_ho
- 	u32 flags;
- 	u32 div;
- 	u32 sclk;
-+	u32 tune_reg = host->dev_comp->pad_tune_reg;
- 
- 	if (!hz) {
- 		dev_dbg(host->dev, "set mclk to 0\n");
-@@ -665,10 +672,10 @@ static void msdc_set_mclk(struct msdc_ho
- 	 */
- 	if (host->sclk <= 52000000) {
- 		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
--		writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
-+		writel(host->def_tune_para.pad_tune, host->base + tune_reg);
- 	} else {
- 		writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
--		writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE);
-+		writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
- 		writel(host->saved_tune_para.pad_cmd_tune,
- 		       host->base + PAD_CMD_TUNE);
- 	}
-@@ -1226,6 +1233,7 @@ static irqreturn_t msdc_irq(int irq, voi
- static void msdc_init_hw(struct msdc_host *host)
- {
- 	u32 val;
-+	u32 tune_reg = host->dev_comp->pad_tune_reg;
- 
- 	/* Configure to MMC/SD mode, clock free running */
- 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
-@@ -1241,7 +1249,7 @@ static void msdc_init_hw(struct msdc_hos
- 	val = readl(host->base + MSDC_INT);
- 	writel(val, host->base + MSDC_INT);
- 
--	writel(0, host->base + MSDC_PAD_TUNE);
-+	writel(0, host->base + tune_reg);
- 	writel(0, host->base + MSDC_IOCON);
- 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
- 	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
-@@ -1261,7 +1269,7 @@ static void msdc_init_hw(struct msdc_hos
- 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
- 
- 	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
--	host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
-+	host->def_tune_para.pad_tune = readl(host->base + tune_reg);
- 	dev_dbg(host->dev, "init hardware done!");
- }
- 
-@@ -1404,18 +1412,19 @@ static int msdc_tune_response(struct mmc
- 	struct msdc_delay_phase internal_delay_phase;
- 	u8 final_delay, final_maxlen;
- 	u32 internal_delay = 0;
-+	u32 tune_reg = host->dev_comp->pad_tune_reg;
- 	int cmd_err;
- 	int i, j;
- 
- 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
- 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
--		sdr_set_field(host->base + MSDC_PAD_TUNE,
-+		sdr_set_field(host->base + tune_reg,
- 			      MSDC_PAD_TUNE_CMDRRDLY,
- 			      host->hs200_cmd_int_delay);
- 
- 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
--		sdr_set_field(host->base + MSDC_PAD_TUNE,
-+		sdr_set_field(host->base + tune_reg,
- 			      MSDC_PAD_TUNE_CMDRDLY, i);
- 		/*
- 		 * Using the same parameters, it may sometimes pass the test,
-@@ -1439,7 +1448,7 @@ static int msdc_tune_response(struct mmc
- 
- 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- 	for (i = 0; i < PAD_DELAY_MAX; i++) {
--		sdr_set_field(host->base + MSDC_PAD_TUNE,
-+		sdr_set_field(host->base + tune_reg,
- 			      MSDC_PAD_TUNE_CMDRDLY, i);
- 		/*
- 		 * Using the same parameters, it may sometimes pass the test,
-@@ -1464,12 +1473,12 @@ skip_fall:
- 		final_maxlen = final_fall_delay.maxlen;
- 	if (final_maxlen == final_rise_delay.maxlen) {
- 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
--		sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
-+		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
- 			      final_rise_delay.final_phase);
- 		final_delay = final_rise_delay.final_phase;
- 	} else {
- 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
--		sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
-+		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
- 			      final_fall_delay.final_phase);
- 		final_delay = final_fall_delay.final_phase;
- 	}
-@@ -1477,7 +1486,7 @@ skip_fall:
- 		goto skip_internal;
- 
- 	for (i = 0; i < PAD_DELAY_MAX; i++) {
--		sdr_set_field(host->base + MSDC_PAD_TUNE,
-+		sdr_set_field(host->base + tune_reg,
- 			      MSDC_PAD_TUNE_CMDRRDLY, i);
- 		mmc_send_tuning(mmc, opcode, &cmd_err);
- 		if (!cmd_err)
-@@ -1485,7 +1494,7 @@ skip_fall:
- 	}
- 	dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
- 	internal_delay_phase = get_best_delay(host, internal_delay);
--	sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY,
-+	sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
- 		      internal_delay_phase.final_phase);
- skip_internal:
- 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
-@@ -1548,12 +1557,13 @@ static int msdc_tune_data(struct mmc_hos
- 	u32 rise_delay = 0, fall_delay = 0;
- 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
- 	u8 final_delay, final_maxlen;
-+	u32 tune_reg = host->dev_comp->pad_tune_reg;
- 	int i, ret;
- 
- 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
- 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
- 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
--		sdr_set_field(host->base + MSDC_PAD_TUNE,
-+		sdr_set_field(host->base + tune_reg,
- 			      MSDC_PAD_TUNE_DATRRDLY, i);
- 		ret = mmc_send_tuning(mmc, opcode, NULL);
- 		if (!ret)
-@@ -1568,7 +1578,7 @@ static int msdc_tune_data(struct mmc_hos
- 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
- 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
- 	for (i = 0; i < PAD_DELAY_MAX; i++) {
--		sdr_set_field(host->base + MSDC_PAD_TUNE,
-+		sdr_set_field(host->base + tune_reg,
- 			      MSDC_PAD_TUNE_DATRRDLY, i);
- 		ret = mmc_send_tuning(mmc, opcode, NULL);
- 		if (!ret)
-@@ -1581,14 +1591,14 @@ skip_fall:
- 	if (final_maxlen == final_rise_delay.maxlen) {
- 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
- 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
--		sdr_set_field(host->base + MSDC_PAD_TUNE,
-+		sdr_set_field(host->base + tune_reg,
- 			      MSDC_PAD_TUNE_DATRRDLY,
- 			      final_rise_delay.final_phase);
- 		final_delay = final_rise_delay.final_phase;
- 	} else {
- 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
- 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
--		sdr_set_field(host->base + MSDC_PAD_TUNE,
-+		sdr_set_field(host->base + tune_reg,
- 			      MSDC_PAD_TUNE_DATRRDLY,
- 			      final_fall_delay.final_phase);
- 		final_delay = final_fall_delay.final_phase;
-@@ -1602,6 +1612,7 @@ static int msdc_execute_tuning(struct mm
- {
- 	struct msdc_host *host = mmc_priv(mmc);
- 	int ret;
-+	u32 tune_reg = host->dev_comp->pad_tune_reg;
- 
- 	if (host->hs400_mode &&
- 	    host->dev_comp->hs400_tune)
-@@ -1619,7 +1630,7 @@ static int msdc_execute_tuning(struct mm
- 	}
- 
- 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
--	host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
-+	host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
- 	host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
- 	return ret;
- }
-@@ -1860,10 +1871,12 @@ static int msdc_drv_remove(struct platfo
- #ifdef CONFIG_PM
- static void msdc_save_reg(struct msdc_host *host)
- {
-+	u32 tune_reg = host->dev_comp->pad_tune_reg;
-+
- 	host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
- 	host->save_para.iocon = readl(host->base + MSDC_IOCON);
- 	host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
--	host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
-+	host->save_para.pad_tune = readl(host->base + tune_reg);
- 	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
- 	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
- 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
-@@ -1873,10 +1886,12 @@ static void msdc_save_reg(struct msdc_ho
- 
- static void msdc_restore_reg(struct msdc_host *host)
- {
-+	u32 tune_reg = host->dev_comp->pad_tune_reg;
-+
- 	writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
- 	writel(host->save_para.iocon, host->base + MSDC_IOCON);
- 	writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
--	writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
-+	writel(host->save_para.pad_tune, host->base + tune_reg);
- 	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
- 	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
- 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);

target/linux/mediatek/patches-4.14/0154-mmc-mediatek-add-async-fifo-and-data-tune-support.patch

@@ -1,170 +0,0 @@
-From 830574225e621809600902b69bbdd563e67ef4eb Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:33 +0800
-Subject: [PATCH 154/224] mmc: mediatek: add async fifo and data tune support
-
-mt2701/mt2712 supports async fifo & data tune, which can improve
-host stability.
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 52 +++++++++++++++++++++++++++++++++++++++++++++--
- 1 file changed, 50 insertions(+), 2 deletions(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -74,6 +74,7 @@
- #define MSDC_DMA_CFG     0x9c
- #define MSDC_PATCH_BIT   0xb0
- #define MSDC_PATCH_BIT1  0xb4
-+#define MSDC_PATCH_BIT2  0xb8
- #define MSDC_PAD_TUNE    0xec
- #define MSDC_PAD_TUNE0   0xf0
- #define PAD_DS_TUNE      0x188
-@@ -218,11 +219,20 @@
- 
- #define MSDC_PATCH_BIT1_CMDTA     (0x7 << 3)    /* RW */
- 
-+#define MSDC_PATCH_BIT2_CFGRESP   (0x1 << 15)   /* RW */
-+#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28)   /* RW */
-+#define MSDC_PB2_RESPWAIT         (0x3 << 2)    /* RW */
-+#define MSDC_PB2_RESPSTSENSEL     (0x7 << 16)   /* RW */
-+#define MSDC_PB2_CRCSTSENSEL      (0x7 << 29)   /* RW */
-+
- #define MSDC_PAD_TUNE_DATWRDLY	  (0x1f <<  0)	/* RW */
- #define MSDC_PAD_TUNE_DATRRDLY	  (0x1f <<  8)	/* RW */
- #define MSDC_PAD_TUNE_CMDRDLY	  (0x1f << 16)  /* RW */
- #define MSDC_PAD_TUNE_CMDRRDLY	  (0x1f << 22)	/* RW */
- #define MSDC_PAD_TUNE_CLKTDLY	  (0x1f << 27)  /* RW */
-+#define MSDC_PAD_TUNE_RXDLYSEL	  (0x1 << 15)   /* RW */
-+#define MSDC_PAD_TUNE_RD_SEL	  (0x1 << 13)   /* RW */
-+#define MSDC_PAD_TUNE_CMD_SEL	  (0x1 << 21)   /* RW */
- 
- #define PAD_DS_TUNE_DLY1	  (0x1f << 2)   /* RW */
- #define PAD_DS_TUNE_DLY2	  (0x1f << 7)   /* RW */
-@@ -296,6 +306,7 @@ struct msdc_save_para {
- 	u32 pad_tune;
- 	u32 patch_bit0;
- 	u32 patch_bit1;
-+	u32 patch_bit2;
- 	u32 pad_ds_tune;
- 	u32 pad_cmd_tune;
- 	u32 emmc50_cfg0;
-@@ -305,6 +316,8 @@ struct mtk_mmc_compatible {
- 	u8 clk_div_bits;
- 	bool hs400_tune; /* only used for MT8173 */
- 	u32 pad_tune_reg;
-+	bool async_fifo;
-+	bool data_tune;
- };
- 
- struct msdc_tune_para {
-@@ -367,24 +380,32 @@ static const struct mtk_mmc_compatible m
- 	.clk_div_bits = 8,
- 	.hs400_tune = false,
- 	.pad_tune_reg = MSDC_PAD_TUNE,
-+	.async_fifo = false,
-+	.data_tune = false,
- };
- 
- static const struct mtk_mmc_compatible mt8173_compat = {
- 	.clk_div_bits = 8,
- 	.hs400_tune = true,
- 	.pad_tune_reg = MSDC_PAD_TUNE,
-+	.async_fifo = false,
-+	.data_tune = false,
- };
- 
- static const struct mtk_mmc_compatible mt2701_compat = {
- 	.clk_div_bits = 12,
- 	.hs400_tune = false,
- 	.pad_tune_reg = MSDC_PAD_TUNE0,
-+	.async_fifo = true,
-+	.data_tune = true,
- };
- 
- static const struct mtk_mmc_compatible mt2712_compat = {
- 	.clk_div_bits = 12,
- 	.hs400_tune = false,
- 	.pad_tune_reg = MSDC_PAD_TUNE0,
-+	.async_fifo = true,
-+	.data_tune = true,
- };
- 
- static const struct of_device_id msdc_of_ids[] = {
-@@ -1254,8 +1275,29 @@ static void msdc_init_hw(struct msdc_hos
- 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
- 	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
- 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
--	writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
-+	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
- 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
-+	if (host->dev_comp->async_fifo) {
-+		sdr_set_field(host->base + MSDC_PATCH_BIT2,
-+			      MSDC_PB2_RESPWAIT, 3);
-+		sdr_set_field(host->base + MSDC_PATCH_BIT2,
-+			      MSDC_PB2_RESPSTSENSEL, 2);
-+		sdr_set_field(host->base + MSDC_PATCH_BIT2,
-+			      MSDC_PB2_CRCSTSENSEL, 2);
-+		/* use async fifo, then no need tune internal delay */
-+		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
-+			     MSDC_PATCH_BIT2_CFGRESP);
-+		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
-+			     MSDC_PATCH_BIT2_CFGCRCSTS);
-+	}
-+
-+	if (host->dev_comp->data_tune) {
-+		sdr_set_bits(host->base + tune_reg,
-+			     MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
-+	} else {
-+		/* choose clock tune */
-+		sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
-+	}
- 
- 	/* Configure to enable SDIO mode.
- 	 * it's must otherwise sdio cmd5 failed
-@@ -1270,6 +1312,8 @@ static void msdc_init_hw(struct msdc_hos
- 
- 	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
- 	host->def_tune_para.pad_tune = readl(host->base + tune_reg);
-+	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
-+	host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
- 	dev_dbg(host->dev, "init hardware done!");
- }
- 
-@@ -1482,7 +1526,7 @@ skip_fall:
- 			      final_fall_delay.final_phase);
- 		final_delay = final_fall_delay.final_phase;
- 	}
--	if (host->hs200_cmd_int_delay)
-+	if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
- 		goto skip_internal;
- 
- 	for (i = 0; i < PAD_DELAY_MAX; i++) {
-@@ -1641,6 +1685,8 @@ static int msdc_prepare_hs400_tuning(str
- 	host->hs400_mode = true;
- 
- 	writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
-+	/* hs400 mode must set it to 0 */
-+	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
- 	return 0;
- }
- 
-@@ -1879,6 +1925,7 @@ static void msdc_save_reg(struct msdc_ho
- 	host->save_para.pad_tune = readl(host->base + tune_reg);
- 	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
- 	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
-+	host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
- 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
- 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
- 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
-@@ -1894,6 +1941,7 @@ static void msdc_restore_reg(struct msdc
- 	writel(host->save_para.pad_tune, host->base + tune_reg);
- 	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
- 	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
-+	writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
- 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
- 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
- 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);

target/linux/mediatek/patches-4.14/0155-mmc-mediatek-add-busy_check-support.patch

@@ -1,67 +0,0 @@
-From 788d269aee4c612d5cd97b896ea5d22f19137097 Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:34 +0800
-Subject: [PATCH 155/224] mmc: mediatek: add busy_check support
-
-bit7 of PATCH_BIT1 has different meaning in new design, to
-compatible with previous platform, clear this bit in new
-platform.
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -318,6 +318,7 @@ struct mtk_mmc_compatible {
- 	u32 pad_tune_reg;
- 	bool async_fifo;
- 	bool data_tune;
-+	bool busy_check;
- };
- 
- struct msdc_tune_para {
-@@ -382,6 +383,7 @@ static const struct mtk_mmc_compatible m
- 	.pad_tune_reg = MSDC_PAD_TUNE,
- 	.async_fifo = false,
- 	.data_tune = false,
-+	.busy_check = false,
- };
- 
- static const struct mtk_mmc_compatible mt8173_compat = {
-@@ -390,6 +392,7 @@ static const struct mtk_mmc_compatible m
- 	.pad_tune_reg = MSDC_PAD_TUNE,
- 	.async_fifo = false,
- 	.data_tune = false,
-+	.busy_check = false,
- };
- 
- static const struct mtk_mmc_compatible mt2701_compat = {
-@@ -398,6 +401,7 @@ static const struct mtk_mmc_compatible m
- 	.pad_tune_reg = MSDC_PAD_TUNE0,
- 	.async_fifo = true,
- 	.data_tune = true,
-+	.busy_check = false,
- };
- 
- static const struct mtk_mmc_compatible mt2712_compat = {
-@@ -406,6 +410,7 @@ static const struct mtk_mmc_compatible m
- 	.pad_tune_reg = MSDC_PAD_TUNE0,
- 	.async_fifo = true,
- 	.data_tune = true,
-+	.busy_check = true,
- };
- 
- static const struct of_device_id msdc_of_ids[] = {
-@@ -1277,6 +1282,8 @@ static void msdc_init_hw(struct msdc_hos
- 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
- 	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
- 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
-+	if (host->dev_comp->busy_check)
-+		sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
- 	if (host->dev_comp->async_fifo) {
- 		sdr_set_field(host->base + MSDC_PATCH_BIT2,
- 			      MSDC_PB2_RESPWAIT, 3);

target/linux/mediatek/patches-4.14/0156-mmc-mediatek-add-stop_clk-fix-and-enhance_rx-support.patch

@@ -1,168 +0,0 @@
-From 9257240bcaf8f9ee6878357e00e7ab511ad6d325 Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:35 +0800
-Subject: [PATCH 156/224] mmc: mediatek: add stop_clk fix and enhance_rx
- support
-
-mt2712 supports stop_clk fix and enhance_rx, which can improve
-host stability.
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 47 +++++++++++++++++++++++++++++++++++++++++++----
- 1 file changed, 43 insertions(+), 4 deletions(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -67,6 +67,7 @@
- #define SDC_RESP2        0x48
- #define SDC_RESP3        0x4c
- #define SDC_BLK_NUM      0x50
-+#define SDC_ADV_CFG0     0x64
- #define EMMC_IOCON       0x7c
- #define SDC_ACMD_RESP    0x80
- #define MSDC_DMA_SA      0x90
-@@ -80,6 +81,7 @@
- #define PAD_DS_TUNE      0x188
- #define PAD_CMD_TUNE     0x18c
- #define EMMC50_CFG0      0x208
-+#define SDC_FIFO_CFG     0x228
- 
- /*--------------------------------------------------------------------------*/
- /* Register Mask                                                            */
-@@ -188,6 +190,9 @@
- #define SDC_STS_CMDBUSY         (0x1 << 1)	/* RW */
- #define SDC_STS_SWR_COMPL       (0x1 << 31)	/* RW */
- 
-+/* SDC_ADV_CFG0 mask */
-+#define SDC_RX_ENHANCE_EN	(0x1 << 20)	/* RW */
-+
- /* MSDC_DMA_CTRL mask */
- #define MSDC_DMA_CTRL_START     (0x1 << 0)	/* W */
- #define MSDC_DMA_CTRL_STOP      (0x1 << 1)	/* W */
-@@ -219,6 +224,8 @@
- 
- #define MSDC_PATCH_BIT1_CMDTA     (0x7 << 3)    /* RW */
- 
-+#define MSDC_PATCH_BIT1_STOP_DLY  (0xf << 8)    /* RW */
-+
- #define MSDC_PATCH_BIT2_CFGRESP   (0x1 << 15)   /* RW */
- #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28)   /* RW */
- #define MSDC_PB2_RESPWAIT         (0x3 << 2)    /* RW */
-@@ -244,6 +251,9 @@
- #define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
- #define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
- 
-+#define SDC_FIFO_CFG_WRVALIDSEL   (0x1 << 24)  /* RW */
-+#define SDC_FIFO_CFG_RDVALIDSEL   (0x1 << 25)  /* RW */
-+
- #define REQ_CMD_EIO  (0x1 << 0)
- #define REQ_CMD_TMO  (0x1 << 1)
- #define REQ_DAT_ERR  (0x1 << 2)
-@@ -310,6 +320,7 @@ struct msdc_save_para {
- 	u32 pad_ds_tune;
- 	u32 pad_cmd_tune;
- 	u32 emmc50_cfg0;
-+	u32 sdc_fifo_cfg;
- };
- 
- struct mtk_mmc_compatible {
-@@ -319,6 +330,8 @@ struct mtk_mmc_compatible {
- 	bool async_fifo;
- 	bool data_tune;
- 	bool busy_check;
-+	bool stop_clk_fix;
-+	bool enhance_rx;
- };
- 
- struct msdc_tune_para {
-@@ -384,6 +397,8 @@ static const struct mtk_mmc_compatible m
- 	.async_fifo = false,
- 	.data_tune = false,
- 	.busy_check = false,
-+	.stop_clk_fix = false,
-+	.enhance_rx = false,
- };
- 
- static const struct mtk_mmc_compatible mt8173_compat = {
-@@ -393,6 +408,8 @@ static const struct mtk_mmc_compatible m
- 	.async_fifo = false,
- 	.data_tune = false,
- 	.busy_check = false,
-+	.stop_clk_fix = false,
-+	.enhance_rx = false,
- };
- 
- static const struct mtk_mmc_compatible mt2701_compat = {
-@@ -402,6 +419,8 @@ static const struct mtk_mmc_compatible m
- 	.async_fifo = true,
- 	.data_tune = true,
- 	.busy_check = false,
-+	.stop_clk_fix = false,
-+	.enhance_rx = false,
- };
- 
- static const struct mtk_mmc_compatible mt2712_compat = {
-@@ -411,6 +430,8 @@ static const struct mtk_mmc_compatible m
- 	.async_fifo = true,
- 	.data_tune = true,
- 	.busy_check = true,
-+	.stop_clk_fix = true,
-+	.enhance_rx = true,
- };
- 
- static const struct of_device_id msdc_of_ids[] = {
-@@ -1282,15 +1303,31 @@ static void msdc_init_hw(struct msdc_hos
- 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
- 	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
- 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
-+
-+	if (host->dev_comp->stop_clk_fix) {
-+		sdr_set_field(host->base + MSDC_PATCH_BIT1,
-+			      MSDC_PATCH_BIT1_STOP_DLY, 3);
-+		sdr_clr_bits(host->base + SDC_FIFO_CFG,
-+			     SDC_FIFO_CFG_WRVALIDSEL);
-+		sdr_clr_bits(host->base + SDC_FIFO_CFG,
-+			     SDC_FIFO_CFG_RDVALIDSEL);
-+	}
-+
- 	if (host->dev_comp->busy_check)
- 		sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
-+
- 	if (host->dev_comp->async_fifo) {
- 		sdr_set_field(host->base + MSDC_PATCH_BIT2,
- 			      MSDC_PB2_RESPWAIT, 3);
--		sdr_set_field(host->base + MSDC_PATCH_BIT2,
--			      MSDC_PB2_RESPSTSENSEL, 2);
--		sdr_set_field(host->base + MSDC_PATCH_BIT2,
--			      MSDC_PB2_CRCSTSENSEL, 2);
-+		if (host->dev_comp->enhance_rx) {
-+			sdr_set_bits(host->base + SDC_ADV_CFG0,
-+				     SDC_RX_ENHANCE_EN);
-+		} else {
-+			sdr_set_field(host->base + MSDC_PATCH_BIT2,
-+				      MSDC_PB2_RESPSTSENSEL, 2);
-+			sdr_set_field(host->base + MSDC_PATCH_BIT2,
-+				      MSDC_PB2_CRCSTSENSEL, 2);
-+		}
- 		/* use async fifo, then no need tune internal delay */
- 		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
- 			     MSDC_PATCH_BIT2_CFGRESP);
-@@ -1936,6 +1973,7 @@ static void msdc_save_reg(struct msdc_ho
- 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
- 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
- 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
-+	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
- }
- 
- static void msdc_restore_reg(struct msdc_host *host)
-@@ -1952,6 +1990,7 @@ static void msdc_restore_reg(struct msdc
- 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
- 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
- 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
-+	writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
- }
- 
- static int msdc_runtime_suspend(struct device *dev)

target/linux/mediatek/patches-4.14/0157-mmc-mediatek-add-support-of-source_cg-clock.patch

@@ -1,85 +0,0 @@
-From 3c6b94d7091f0793445f2faf777e584af643e9da Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:36 +0800
-Subject: [PATCH 157/224] mmc: mediatek: add support of source_cg clock
-
-source clock need an independent cg to control, when doing clk mode
-switch, need gate source clock to avoid hw issue(multi-bit sync hw hang)
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -374,6 +374,7 @@ struct msdc_host {
- 
- 	struct clk *src_clk;	/* msdc source clock */
- 	struct clk *h_clk;      /* msdc h_clk */
-+	struct clk *src_clk_cg; /* msdc source clock control gate */
- 	u32 mclk;		/* mmc subsystem clock frequency */
- 	u32 src_clk_freq;	/* source clock frequency */
- 	u32 sclk;		/* SD/MS bus clock frequency */
-@@ -618,6 +619,7 @@ static void msdc_set_timeout(struct msdc
- 
- static void msdc_gate_clock(struct msdc_host *host)
- {
-+	clk_disable_unprepare(host->src_clk_cg);
- 	clk_disable_unprepare(host->src_clk);
- 	clk_disable_unprepare(host->h_clk);
- }
-@@ -626,6 +628,7 @@ static void msdc_ungate_clock(struct msd
- {
- 	clk_prepare_enable(host->h_clk);
- 	clk_prepare_enable(host->src_clk);
-+	clk_prepare_enable(host->src_clk_cg);
- 	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
- 		cpu_relax();
- }
-@@ -694,6 +697,15 @@ static void msdc_set_mclk(struct msdc_ho
- 			sclk = (host->src_clk_freq >> 2) / div;
- 		}
- 	}
-+	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
-+	/*
-+	 * As src_clk/HCLK use the same bit to gate/ungate,
-+	 * So if want to only gate src_clk, need gate its parent(mux).
-+	 */
-+	if (host->src_clk_cg)
-+		clk_disable_unprepare(host->src_clk_cg);
-+	else
-+		clk_disable_unprepare(clk_get_parent(host->src_clk));
- 	if (host->dev_comp->clk_div_bits == 8)
- 		sdr_set_field(host->base + MSDC_CFG,
- 			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
-@@ -702,10 +714,14 @@ static void msdc_set_mclk(struct msdc_ho
- 		sdr_set_field(host->base + MSDC_CFG,
- 			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
- 			      (mode << 12) | div);
-+	if (host->src_clk_cg)
-+		clk_prepare_enable(host->src_clk_cg);
-+	else
-+		clk_prepare_enable(clk_get_parent(host->src_clk));
- 
--	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
- 	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
- 		cpu_relax();
-+	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
- 	host->sclk = sclk;
- 	host->mclk = hz;
- 	host->timing = timing;
-@@ -1825,6 +1841,11 @@ static int msdc_drv_probe(struct platfor
- 		goto host_free;
- 	}
- 
-+	/*source clock control gate is optional clock*/
-+	host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
-+	if (IS_ERR(host->src_clk_cg))
-+		host->src_clk_cg = NULL;
-+
- 	host->irq = platform_get_irq(pdev, 0);
- 	if (host->irq < 0) {
- 		ret = -EINVAL;

target/linux/mediatek/patches-4.14/0158-mmc-mediatek-add-latch-ck-support.patch

@@ -1,45 +0,0 @@
-From de14d1d0dc7ecf5c3e7e2a591b4f14e688fa52e6 Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:37 +0800
-Subject: [PATCH 158/224] mmc: mediatek: add latch-ck support
-
-some platform(eg.mt2701) does not support "stop clk fix", in
-this case, need set correct latch-ck to avoid crc error caused
-by stop clock block-internally.
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -380,6 +380,7 @@ struct msdc_host {
- 	u32 sclk;		/* SD/MS bus clock frequency */
- 	unsigned char timing;
- 	bool vqmmc_enabled;
-+	u32 latch_ck;
- 	u32 hs400_ds_delay;
- 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
- 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
-@@ -1664,6 +1665,8 @@ static int msdc_tune_data(struct mmc_hos
- 	u32 tune_reg = host->dev_comp->pad_tune_reg;
- 	int i, ret;
- 
-+	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
-+		      host->latch_ck);
- 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
- 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
- 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
-@@ -1776,6 +1779,9 @@ static const struct mmc_host_ops mt_msdc
- static void msdc_of_property_parse(struct platform_device *pdev,
- 				   struct msdc_host *host)
- {
-+	of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
-+			     &host->latch_ck);
-+
- 	of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
- 			     &host->hs400_ds_delay);
- 

target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch

@@ -1,68 +0,0 @@
-From 29e154716049310bb8c559f742bf2b460d5b6bbc Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:38 +0800
-Subject: [PATCH 159/224] mmc: mediatek: improve eMMC hs400 mode read
- performance
-
-enlarge outstanding value to improve read performance
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -81,6 +81,7 @@
- #define PAD_DS_TUNE      0x188
- #define PAD_CMD_TUNE     0x18c
- #define EMMC50_CFG0      0x208
-+#define EMMC50_CFG3      0x220
- #define SDC_FIFO_CFG     0x228
- 
- /*--------------------------------------------------------------------------*/
-@@ -251,6 +252,8 @@
- #define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
- #define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
- 
-+#define EMMC50_CFG3_OUTS_WR       (0x1f << 0)  /* RW */
-+
- #define SDC_FIFO_CFG_WRVALIDSEL   (0x1 << 24)  /* RW */
- #define SDC_FIFO_CFG_RDVALIDSEL   (0x1 << 25)  /* RW */
- 
-@@ -320,6 +323,7 @@ struct msdc_save_para {
- 	u32 pad_ds_tune;
- 	u32 pad_cmd_tune;
- 	u32 emmc50_cfg0;
-+	u32 emmc50_cfg3;
- 	u32 sdc_fifo_cfg;
- };
- 
-@@ -1750,6 +1754,9 @@ static int msdc_prepare_hs400_tuning(str
- 	writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
- 	/* hs400 mode must set it to 0 */
- 	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
-+	/* to improve read performance, set outstanding to 2 */
-+	sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
-+
- 	return 0;
- }
- 
-@@ -2000,6 +2007,7 @@ static void msdc_save_reg(struct msdc_ho
- 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
- 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
- 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
-+	host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
- 	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
- }
- 
-@@ -2017,6 +2025,7 @@ static void msdc_restore_reg(struct msdc
- 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
- 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
- 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
-+	writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
- 	writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
- }
- 

target/linux/mediatek/patches-4.14/0160-mmc-mediatek-perfer-to-use-rise-edge-latching-for-cm.patch

@@ -1,28 +0,0 @@
-From 81fdc4983e33ef01935a9bf01187951aad34e2ac Mon Sep 17 00:00:00 2001
-From: Chaotian Jing <[email protected]>
-Date: Mon, 16 Oct 2017 09:46:39 +0800
-Subject: [PATCH 160/224] mmc: mediatek: perfer to use rise edge latching for
- cmd line
-
-data lines have applied to perfer to use rise edge, also need
-apply it to cmd line.
-
-Signed-off-by: Chaotian Jing <[email protected]>
-Tested-by: Sean Wang <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- drivers/mmc/host/mtk-sd.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -1552,7 +1552,8 @@ static int msdc_tune_response(struct mmc
- 	}
- 	final_rise_delay = get_best_delay(host, rise_delay);
- 	/* if rising edge has enough margin, then do not scan falling edge */
--	if (final_rise_delay.maxlen >= 12 && final_rise_delay.start < 4)
-+	if (final_rise_delay.maxlen >= 12 ||
-+	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
- 		goto skip_fall;
- 
- 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);

target/linux/mediatek/patches-4.14/0161-pwm-mediatek-Add-MT2712-MT7622-support.patch

@@ -1,145 +0,0 @@
-From 7cc8226e45b2c6b9f06ce82ba6995b8f911afe25 Mon Sep 17 00:00:00 2001
-From: Zhi Mao <[email protected]>
-Date: Wed, 25 Oct 2017 18:11:01 +0800
-Subject: [PATCH 161/224] pwm: mediatek: Add MT2712/MT7622 support
-
-Add support for MT2712 and MT7622. Due to register offset address of
-pwm7 for MT2712 is not fixed 0x40, add mtk_pwm_reg_offset array for PWM
-register offset.
-
-Reviewed-by: Claudiu Beznea <[email protected]>
-Reviewed-by: Matthias Brugger <[email protected]>
-Signed-off-by: Zhi Mao <[email protected]>
-Signed-off-by: Thierry Reding <[email protected]>
----
- drivers/pwm/pwm-mediatek.c | 53 ++++++++++++++++++++++++++++++++++++++--------
- 1 file changed, 44 insertions(+), 9 deletions(-)
-
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -16,6 +16,7 @@
- #include <linux/module.h>
- #include <linux/clk.h>
- #include <linux/of.h>
-+#include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/pwm.h>
- #include <linux/slab.h>
-@@ -40,11 +41,19 @@ enum {
- 	MTK_CLK_PWM3,
- 	MTK_CLK_PWM4,
- 	MTK_CLK_PWM5,
-+	MTK_CLK_PWM6,
-+	MTK_CLK_PWM7,
-+	MTK_CLK_PWM8,
- 	MTK_CLK_MAX,
- };
- 
--static const char * const mtk_pwm_clk_name[] = {
--	"main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5"
-+static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
-+	"main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7",
-+	"pwm8"
-+};
-+
-+struct mtk_pwm_platform_data {
-+	unsigned int num_pwms;
- };
- 
- /**
-@@ -59,6 +68,10 @@ struct mtk_pwm_chip {
- 	struct clk *clks[MTK_CLK_MAX];
- };
- 
-+static const unsigned int mtk_pwm_reg_offset[] = {
-+	0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
-+};
-+
- static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
- {
- 	return container_of(chip, struct mtk_pwm_chip, chip);
-@@ -103,14 +116,14 @@ static void mtk_pwm_clk_disable(struct p
- static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
- 				unsigned int offset)
- {
--	return readl(chip->regs + 0x10 + (num * 0x40) + offset);
-+	return readl(chip->regs + mtk_pwm_reg_offset[num] + offset);
- }
- 
- static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
- 				  unsigned int num, unsigned int offset,
- 				  u32 value)
- {
--	writel(value, chip->regs + 0x10 + (num * 0x40) + offset);
-+	writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset);
- }
- 
- static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
-@@ -185,6 +198,7 @@ static const struct pwm_ops mtk_pwm_ops
- 
- static int mtk_pwm_probe(struct platform_device *pdev)
- {
-+	const struct mtk_pwm_platform_data *data;
- 	struct mtk_pwm_chip *pc;
- 	struct resource *res;
- 	unsigned int i;
-@@ -194,15 +208,22 @@ static int mtk_pwm_probe(struct platform
- 	if (!pc)
- 		return -ENOMEM;
- 
-+	data = of_device_get_match_data(&pdev->dev);
-+	if (data == NULL)
-+		return -EINVAL;
-+
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	pc->regs = devm_ioremap_resource(&pdev->dev, res);
- 	if (IS_ERR(pc->regs))
- 		return PTR_ERR(pc->regs);
- 
--	for (i = 0; i < MTK_CLK_MAX; i++) {
-+	for (i = 0; i < data->num_pwms + 2; i++) {
- 		pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
--		if (IS_ERR(pc->clks[i]))
-+		if (IS_ERR(pc->clks[i])) {
-+			dev_err(&pdev->dev, "clock: %s fail: %ld\n",
-+				mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i]));
- 			return PTR_ERR(pc->clks[i]);
-+		}
- 	}
- 
- 	platform_set_drvdata(pdev, pc);
-@@ -210,7 +231,7 @@ static int mtk_pwm_probe(struct platform
- 	pc->chip.dev = &pdev->dev;
- 	pc->chip.ops = &mtk_pwm_ops;
- 	pc->chip.base = -1;
--	pc->chip.npwm = 5;
-+	pc->chip.npwm = data->num_pwms;
- 
- 	ret = pwmchip_add(&pc->chip);
- 	if (ret < 0) {
-@@ -228,9 +249,23 @@ static int mtk_pwm_remove(struct platfor
- 	return pwmchip_remove(&pc->chip);
- }
- 
-+static const struct mtk_pwm_platform_data mt2712_pwm_data = {
-+	.num_pwms = 8,
-+};
-+
-+static const struct mtk_pwm_platform_data mt7622_pwm_data = {
-+	.num_pwms = 6,
-+};
-+
-+static const struct mtk_pwm_platform_data mt7623_pwm_data = {
-+	.num_pwms = 5,
-+};
-+
- static const struct of_device_id mtk_pwm_of_match[] = {
--	{ .compatible = "mediatek,mt7623-pwm" },
--	{ }
-+	{ .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
-+	{ .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
-+	{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
-+	{ },
- };
- MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
- 

target/linux/mediatek/patches-4.14/0162-mtd-nand-mtk-use-nand_reset-to-reset-NAND-devices-in.patch

@@ -1,41 +0,0 @@
-From fb607c7c1eaeb47ec2ffed99cab571892cb6af7d Mon Sep 17 00:00:00 2001
-From: Xiaolei Li <[email protected]>
-Date: Thu, 2 Nov 2017 10:05:07 +0800
-Subject: [PATCH 162/224] mtd: nand: mtk: use nand_reset() to reset NAND
- devices in resume function
-
-Previously, we only select chips and then send reset command to a NAND
-device during resuming nand driver. There is a lack of deselecting chips.
-It is advised to reset and initialize a NAND device using nand_reset().
-
-Signed-off-by: Xiaolei Li <[email protected]>
-Reviewed-by: Matthias Brugger <[email protected]>
-Signed-off-by: Boris Brezillon <[email protected]>
----
- drivers/mtd/nand/mtk_nand.c | 8 ++------
- 1 file changed, 2 insertions(+), 6 deletions(-)
-
---- a/drivers/mtd/nand/mtk_nand.c
-+++ b/drivers/mtd/nand/mtk_nand.c
-@@ -1539,7 +1539,6 @@ static int mtk_nfc_resume(struct device
- 	struct mtk_nfc *nfc = dev_get_drvdata(dev);
- 	struct mtk_nfc_nand_chip *chip;
- 	struct nand_chip *nand;
--	struct mtd_info *mtd;
- 	int ret;
- 	u32 i;
- 
-@@ -1552,11 +1551,8 @@ static int mtk_nfc_resume(struct device
- 	/* reset NAND chip if VCC was powered off */
- 	list_for_each_entry(chip, &nfc->chips, node) {
- 		nand = &chip->nand;
--		mtd = nand_to_mtd(nand);
--		for (i = 0; i < chip->nsels; i++) {
--			nand->select_chip(mtd, i);
--			nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
--		}
-+		for (i = 0; i < chip->nsels; i++)
-+			nand_reset(nand, i);
- 	}
- 
- 	return 0;

target/linux/mediatek/patches-4.14/0164-cpufreq-mediatek-add-mt2712-into-compatible-list.patch

@@ -1,24 +0,0 @@
-From f027d8b7248cef5b3d3eb8ac68e1040fba340995 Mon Sep 17 00:00:00 2001
-From: Andrew-sh Cheng <[email protected]>
-Date: Fri, 8 Dec 2017 14:07:55 +0800
-Subject: [PATCH 164/224] cpufreq: mediatek: add mt2712 into compatible list
-
-Support mt2712 in mediatek-cpufreq.c
-
-Signed-off-by: Andrew-sh Cheng <[email protected]>
-Acked-by: Viresh Kumar <[email protected]>
-Signed-off-by: Rafael J. Wysocki <[email protected]>
----
- drivers/cpufreq/mediatek-cpufreq.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -574,6 +574,7 @@ static struct platform_driver mtk_cpufre
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- 	{ .compatible = "mediatek,mt2701", },
-+	{ .compatible = "mediatek,mt2712", },
- 	{ .compatible = "mediatek,mt7622", },
- 	{ .compatible = "mediatek,mt7623", },
- 	{ .compatible = "mediatek,mt817x", },

target/linux/mediatek/patches-4.14/0165-mtd-nand-mtk-update-DT-bindings.patch

@@ -1,41 +0,0 @@
-From 42611c6d9f12d16ce4247d76b16218e54ef5b949 Mon Sep 17 00:00:00 2001
-From: RogerCC Lin <[email protected]>
-Date: Thu, 30 Nov 2017 22:10:43 +0800
-Subject: [PATCH 165/224] mtd: nand: mtk: update DT bindings
-
-Add MT7622 NAND Flash Controller dt bindings documentation.
-
-Signed-off-by: RogerCC Lin <[email protected]>
-Reviewed-by: Matthias Brugger <[email protected]>
-Signed-off-by: Boris Brezillon <[email protected]>
----
- Documentation/devicetree/bindings/mtd/mtk-nand.txt | 11 ++++++++---
- 1 file changed, 8 insertions(+), 3 deletions(-)
-
---- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt
-+++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
-@@ -12,8 +12,10 @@ tree nodes.
- 
- The first part of NFC is NAND Controller Interface (NFI) HW.
- Required NFI properties:
--- compatible:			Should be one of "mediatek,mt2701-nfc",
--				"mediatek,mt2712-nfc".
-+- compatible:			Should be one of
-+				"mediatek,mt2701-nfc",
-+				"mediatek,mt2712-nfc",
-+				"mediatek,mt7622-nfc".
- - reg:				Base physical address and size of NFI.
- - interrupts:			Interrupts of NFI.
- - clocks:			NFI required clocks.
-@@ -142,7 +144,10 @@ Example:
- ==============
- 
- Required BCH properties:
--- compatible:	Should be one of "mediatek,mt2701-ecc", "mediatek,mt2712-ecc".
-+- compatible:	Should be one of
-+		"mediatek,mt2701-ecc",
-+		"mediatek,mt2712-ecc",
-+		"mediatek,mt7622-ecc".
- - reg:		Base physical address and size of ECC.
- - interrupts:	Interrupts of ECC.
- - clocks:	ECC required clocks.

target/linux/mediatek/patches-4.14/0166-mtd-nand-mtk-Support-different-MTK-NAND-flash-contro.patch

@@ -1,380 +0,0 @@
-From fd1a1eabf2473e769b5cafc704e0336d11f61961 Mon Sep 17 00:00:00 2001
-From: RogerCC Lin <[email protected]>
-Date: Thu, 30 Nov 2017 22:10:44 +0800
-Subject: [PATCH 166/224] mtd: nand: mtk: Support different MTK NAND flash
- controller IP
-
-MT7622 uses an MTK's earlier NAND flash controller IP which support
-different sector size, max spare size per sector and paraity bits...,
-some register's offset and definition also been changed in the NAND
-flash controller, this patch is the preparation to support MT7622
-NAND flash controller.
-
-MT7622 NFC and ECC engine are similar to MT2701's, except below
-differences:
-(1)MT7622 NFC's max sector size(ECC data size) is 512 bytes, and
-   MT2701's is 1024, and MT7622's max sector number is 8.
-(2)The parity bit of MT7622 is 13, MT2701 is 14.
-(3)MT7622 ECC supports less ECC strength, max to 16 bit ecc strength.
-(4)MT7622 supports less spare size per sector, max spare size per
-   sector is 28 bytes.
-(5)Some register's offset are different, include ECC_ENCIRQ_EN,
-   ECC_ENCIRQ_STA, ECC_DECDONE, ECC_DECIRQ_EN and ECC_DECIRQ_STA.
-(6)ENC_MODE of ECC_ENCCNFG register is moved from bit 5-6 to bit 4-5.
-
-Signed-off-by: RogerCC Lin <[email protected]>
-Signed-off-by: Boris Brezillon <[email protected]>
----
- drivers/mtd/nand/mtk_ecc.c  | 100 ++++++++++++++++++++++++++++++--------------
- drivers/mtd/nand/mtk_ecc.h  |   3 +-
- drivers/mtd/nand/mtk_nand.c |  27 ++++++++----
- 3 files changed, 89 insertions(+), 41 deletions(-)
-
---- a/drivers/mtd/nand/mtk_ecc.c
-+++ b/drivers/mtd/nand/mtk_ecc.c
-@@ -34,34 +34,28 @@
- 
- #define ECC_ENCCON		(0x00)
- #define ECC_ENCCNFG		(0x04)
--#define		ECC_MODE_SHIFT		(5)
- #define		ECC_MS_SHIFT		(16)
- #define ECC_ENCDIADDR		(0x08)
- #define ECC_ENCIDLE		(0x0C)
--#define ECC_ENCIRQ_EN		(0x80)
--#define ECC_ENCIRQ_STA		(0x84)
- #define ECC_DECCON		(0x100)
- #define ECC_DECCNFG		(0x104)
- #define		DEC_EMPTY_EN		BIT(31)
- #define		DEC_CNFG_CORRECT	(0x3 << 12)
- #define ECC_DECIDLE		(0x10C)
- #define ECC_DECENUM0		(0x114)
--#define ECC_DECDONE		(0x124)
--#define ECC_DECIRQ_EN		(0x200)
--#define ECC_DECIRQ_STA		(0x204)
- 
- #define ECC_TIMEOUT		(500000)
- 
- #define ECC_IDLE_REG(op)	((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
- #define ECC_CTL_REG(op)		((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
--#define ECC_IRQ_REG(op)		((op) == ECC_ENCODE ? \
--					ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
- 
- struct mtk_ecc_caps {
- 	u32 err_mask;
- 	const u8 *ecc_strength;
-+	const u32 *ecc_regs;
- 	u8 num_ecc_strength;
--	u32 encode_parity_reg0;
-+	u8 ecc_mode_shift;
-+	u32 parity_bits;
- 	int pg_irq_sel;
- };
- 
-@@ -89,6 +83,33 @@ static const u8 ecc_strength_mt2712[] =
- 	40, 44, 48, 52, 56, 60, 68, 72, 80
- };
- 
-+enum mtk_ecc_regs {
-+	ECC_ENCPAR00,
-+	ECC_ENCIRQ_EN,
-+	ECC_ENCIRQ_STA,
-+	ECC_DECDONE,
-+	ECC_DECIRQ_EN,
-+	ECC_DECIRQ_STA,
-+};
-+
-+static int mt2701_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
-+static int mt2712_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x300,
-+	[ECC_ENCIRQ_EN] =       0x80,
-+	[ECC_ENCIRQ_STA] =      0x84,
-+	[ECC_DECDONE] =         0x124,
-+	[ECC_DECIRQ_EN] =       0x200,
-+	[ECC_DECIRQ_STA] =      0x204,
-+};
-+
- static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
- 				     enum mtk_ecc_operation op)
- {
-@@ -107,32 +128,30 @@ static inline void mtk_ecc_wait_idle(str
- static irqreturn_t mtk_ecc_irq(int irq, void *id)
- {
- 	struct mtk_ecc *ecc = id;
--	enum mtk_ecc_operation op;
- 	u32 dec, enc;
- 
--	dec = readw(ecc->regs + ECC_DECIRQ_STA) & ECC_IRQ_EN;
-+	dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
-+		    & ECC_IRQ_EN;
- 	if (dec) {
--		op = ECC_DECODE;
--		dec = readw(ecc->regs + ECC_DECDONE);
-+		dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
- 		if (dec & ecc->sectors) {
- 			/*
- 			 * Clear decode IRQ status once again to ensure that
- 			 * there will be no extra IRQ.
- 			 */
--			readw(ecc->regs + ECC_DECIRQ_STA);
-+			readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
- 			ecc->sectors = 0;
- 			complete(&ecc->done);
- 		} else {
- 			return IRQ_HANDLED;
- 		}
- 	} else {
--		enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ECC_IRQ_EN;
--		if (enc) {
--			op = ECC_ENCODE;
-+		enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
-+		      & ECC_IRQ_EN;
-+		if (enc)
- 			complete(&ecc->done);
--		} else {
-+		else
- 			return IRQ_NONE;
--		}
- 	}
- 
- 	return IRQ_HANDLED;
-@@ -160,7 +179,7 @@ static int mtk_ecc_config(struct mtk_ecc
- 		/* configure ECC encoder (in bits) */
- 		enc_sz = config->len << 3;
- 
--		reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
- 		reg |= (enc_sz << ECC_MS_SHIFT);
- 		writel(reg, ecc->regs + ECC_ENCCNFG);
- 
-@@ -171,9 +190,9 @@ static int mtk_ecc_config(struct mtk_ecc
- 	} else {
- 		/* configure ECC decoder (in bits) */
- 		dec_sz = (config->len << 3) +
--					config->strength * ECC_PARITY_BITS;
-+			 config->strength * ecc->caps->parity_bits;
- 
--		reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
-+		reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
- 		reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
- 		reg |= DEC_EMPTY_EN;
- 		writel(reg, ecc->regs + ECC_DECCNFG);
-@@ -291,7 +310,12 @@ int mtk_ecc_enable(struct mtk_ecc *ecc,
- 		 */
- 		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
- 			reg_val |= ECC_PG_IRQ_SEL;
--		writew(reg_val, ecc->regs + ECC_IRQ_REG(op));
-+		if (op == ECC_ENCODE)
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+		else
-+			writew(reg_val, ecc->regs +
-+			       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
- 	}
- 
- 	writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
-@@ -310,13 +334,17 @@ void mtk_ecc_disable(struct mtk_ecc *ecc
- 
- 	/* disable it */
- 	mtk_ecc_wait_idle(ecc, op);
--	if (op == ECC_DECODE)
-+	if (op == ECC_DECODE) {
- 		/*
- 		 * Clear decode IRQ status in case there is a timeout to wait
- 		 * decode IRQ.
- 		 */
--		readw(ecc->regs + ECC_DECIRQ_STA);
--	writew(0, ecc->regs + ECC_IRQ_REG(op));
-+		readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+	} else {
-+		writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+	}
-+
- 	writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
- 
- 	mutex_unlock(&ecc->lock);
-@@ -367,11 +395,11 @@ int mtk_ecc_encode(struct mtk_ecc *ecc,
- 	mtk_ecc_wait_idle(ecc, ECC_ENCODE);
- 
- 	/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
--	len = (config->strength * ECC_PARITY_BITS + 7) >> 3;
-+	len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
- 
- 	/* write the parity bytes generated by the ECC back to temp buffer */
- 	__ioread32_copy(ecc->eccdata,
--			ecc->regs + ecc->caps->encode_parity_reg0,
-+			ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
- 			round_up(len, 4));
- 
- 	/* copy into possibly unaligned OOB region with actual length */
-@@ -404,19 +432,29 @@ void mtk_ecc_adjust_strength(struct mtk_
- }
- EXPORT_SYMBOL(mtk_ecc_adjust_strength);
- 
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
-+{
-+	return ecc->caps->parity_bits;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
-+
- static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
- 	.err_mask = 0x3f,
- 	.ecc_strength = ecc_strength_mt2701,
-+	.ecc_regs = mt2701_ecc_regs,
- 	.num_ecc_strength = 20,
--	.encode_parity_reg0 = 0x10,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
- 	.pg_irq_sel = 0,
- };
- 
- static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
- 	.err_mask = 0x7f,
- 	.ecc_strength = ecc_strength_mt2712,
-+	.ecc_regs = mt2712_ecc_regs,
- 	.num_ecc_strength = 23,
--	.encode_parity_reg0 = 0x300,
-+	.ecc_mode_shift = 5,
-+	.parity_bits = 14,
- 	.pg_irq_sel = 1,
- };
- 
-@@ -452,7 +490,7 @@ static int mtk_ecc_probe(struct platform
- 
- 	max_eccdata_size = ecc->caps->num_ecc_strength - 1;
- 	max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
--	max_eccdata_size = (max_eccdata_size * ECC_PARITY_BITS + 7) >> 3;
-+	max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
- 	max_eccdata_size = round_up(max_eccdata_size, 4);
- 	ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
- 	if (!ecc->eccdata)
---- a/drivers/mtd/nand/mtk_ecc.h
-+++ b/drivers/mtd/nand/mtk_ecc.h
-@@ -14,8 +14,6 @@
- 
- #include <linux/types.h>
- 
--#define ECC_PARITY_BITS		(14)
--
- enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
- enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
- 
-@@ -43,6 +41,7 @@ int mtk_ecc_wait_done(struct mtk_ecc *,
- int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
- void mtk_ecc_disable(struct mtk_ecc *);
- void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
- 
- struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
- void mtk_ecc_release(struct mtk_ecc *);
---- a/drivers/mtd/nand/mtk_nand.c
-+++ b/drivers/mtd/nand/mtk_nand.c
-@@ -97,7 +97,6 @@
- 
- #define MTK_TIMEOUT		(500000)
- #define MTK_RESET_TIMEOUT	(1000000)
--#define MTK_MAX_SECTOR		(16)
- #define MTK_NAND_MAX_NSELS	(2)
- #define MTK_NFC_MIN_SPARE	(16)
- #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \
-@@ -109,6 +108,8 @@ struct mtk_nfc_caps {
- 	u8 num_spare_size;
- 	u8 pageformat_spare_shift;
- 	u8 nfi_clk_div;
-+	u8 max_sector;
-+	u32 max_sector_size;
- };
- 
- struct mtk_nfc_bad_mark_ctl {
-@@ -450,7 +451,7 @@ static inline u8 mtk_nfc_read_byte(struc
- 		 * set to max sector to allow the HW to continue reading over
- 		 * unaligned accesses
- 		 */
--		reg = (MTK_MAX_SECTOR << CON_SEC_SHIFT) | CON_BRD;
-+		reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD;
- 		nfi_writel(nfc, reg, NFI_CON);
- 
- 		/* trigger to fetch data */
-@@ -481,7 +482,7 @@ static void mtk_nfc_write_byte(struct mt
- 		reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
- 		nfi_writew(nfc, reg, NFI_CNFG);
- 
--		reg = MTK_MAX_SECTOR << CON_SEC_SHIFT | CON_BWR;
-+		reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR;
- 		nfi_writel(nfc, reg, NFI_CON);
- 
- 		nfi_writew(nfc, STAR_EN, NFI_STRDATA);
-@@ -1125,9 +1126,11 @@ static void mtk_nfc_set_fdm(struct mtk_n
- {
- 	struct nand_chip *nand = mtd_to_nand(mtd);
- 	struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
-+	struct mtk_nfc *nfc = nand_get_controller_data(nand);
- 	u32 ecc_bytes;
- 
--	ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8);
-+	ecc_bytes = DIV_ROUND_UP(nand->ecc.strength *
-+				 mtk_ecc_get_parity_bits(nfc->ecc), 8);
- 
- 	fdm->reg_size = chip->spare_per_sector - ecc_bytes;
- 	if (fdm->reg_size > NFI_FDM_MAX_SIZE)
-@@ -1207,7 +1210,8 @@ static int mtk_nfc_ecc_init(struct devic
- 		 * this controller only supports 512 and 1024 sizes
- 		 */
- 		if (nand->ecc.size < 1024) {
--			if (mtd->writesize > 512) {
-+			if (mtd->writesize > 512 &&
-+			    nfc->caps->max_sector_size > 512) {
- 				nand->ecc.size = 1024;
- 				nand->ecc.strength <<= 1;
- 			} else {
-@@ -1222,7 +1226,8 @@ static int mtk_nfc_ecc_init(struct devic
- 			return ret;
- 
- 		/* calculate oob bytes except ecc parity data */
--		free = ((nand->ecc.strength * ECC_PARITY_BITS) + 7) >> 3;
-+		free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc)
-+			+ 7) >> 3;
- 		free = spare - free;
- 
- 		/*
-@@ -1232,10 +1237,12 @@ static int mtk_nfc_ecc_init(struct devic
- 		 */
- 		if (free > NFI_FDM_MAX_SIZE) {
- 			spare -= NFI_FDM_MAX_SIZE;
--			nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
-+			nand->ecc.strength = (spare << 3) /
-+					     mtk_ecc_get_parity_bits(nfc->ecc);
- 		} else if (free < 0) {
- 			spare -= NFI_FDM_MIN_SIZE;
--			nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
-+			nand->ecc.strength = (spare << 3) /
-+					     mtk_ecc_get_parity_bits(nfc->ecc);
- 		}
- 	}
- 
-@@ -1388,6 +1395,8 @@ static const struct mtk_nfc_caps mtk_nfc
- 	.num_spare_size = 16,
- 	.pageformat_spare_shift = 4,
- 	.nfi_clk_div = 1,
-+	.max_sector = 16,
-+	.max_sector_size = 1024,
- };
- 
- static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
-@@ -1395,6 +1404,8 @@ static const struct mtk_nfc_caps mtk_nfc
- 	.num_spare_size = 19,
- 	.pageformat_spare_shift = 16,
- 	.nfi_clk_div = 2,
-+	.max_sector = 16,
-+	.max_sector_size = 1024,
- };
- 
- static const struct of_device_id mtk_nfc_id_table[] = {

target/linux/mediatek/patches-4.14/0167-mtd-nand-mtk-Support-MT7622-NAND-flash-controller.patch

@@ -1,109 +0,0 @@
-From f395a149fbbc190afbadbdcf9ce95f85f78da22f Mon Sep 17 00:00:00 2001
-From: RogerCC Lin <[email protected]>
-Date: Thu, 30 Nov 2017 22:10:45 +0800
-Subject: [PATCH 167/224] mtd: nand: mtk: Support MT7622 NAND flash controller.
-
-Add tables to support MT7622 NAND flash controller.
-
-Signed-off-by: RogerCC Lin <[email protected]>
-Signed-off-by: Boris Brezillon <[email protected]>
----
- drivers/mtd/nand/mtk_ecc.c  | 26 ++++++++++++++++++++++++++
- drivers/mtd/nand/mtk_nand.c | 16 ++++++++++++++++
- 2 files changed, 42 insertions(+)
-
---- a/drivers/mtd/nand/mtk_ecc.c
-+++ b/drivers/mtd/nand/mtk_ecc.c
-@@ -83,6 +83,10 @@ static const u8 ecc_strength_mt2712[] =
- 	40, 44, 48, 52, 56, 60, 68, 72, 80
- };
- 
-+static const u8 ecc_strength_mt7622[] = {
-+	4, 6, 8, 10, 12, 14, 16
-+};
-+
- enum mtk_ecc_regs {
- 	ECC_ENCPAR00,
- 	ECC_ENCIRQ_EN,
-@@ -110,6 +114,15 @@ static int mt2712_ecc_regs[] = {
- 	[ECC_DECIRQ_STA] =      0x204,
- };
- 
-+static int mt7622_ecc_regs[] = {
-+	[ECC_ENCPAR00] =        0x10,
-+	[ECC_ENCIRQ_EN] =       0x30,
-+	[ECC_ENCIRQ_STA] =      0x34,
-+	[ECC_DECDONE] =         0x11c,
-+	[ECC_DECIRQ_EN] =       0x140,
-+	[ECC_DECIRQ_STA] =      0x144,
-+};
-+
- static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
- 				     enum mtk_ecc_operation op)
- {
-@@ -458,6 +471,16 @@ static const struct mtk_ecc_caps mtk_ecc
- 	.pg_irq_sel = 1,
- };
- 
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
-+	.err_mask = 0x3f,
-+	.ecc_strength = ecc_strength_mt7622,
-+	.ecc_regs = mt7622_ecc_regs,
-+	.num_ecc_strength = 7,
-+	.ecc_mode_shift = 4,
-+	.parity_bits = 13,
-+	.pg_irq_sel = 0,
-+};
-+
- static const struct of_device_id mtk_ecc_dt_match[] = {
- 	{
- 		.compatible = "mediatek,mt2701-ecc",
-@@ -465,6 +488,9 @@ static const struct of_device_id mtk_ecc
- 	}, {
- 		.compatible = "mediatek,mt2712-ecc",
- 		.data = &mtk_ecc_caps_mt2712,
-+	}, {
-+		.compatible = "mediatek,mt7622-ecc",
-+		.data = &mtk_ecc_caps_mt7622,
- 	},
- 	{},
- };
---- a/drivers/mtd/nand/mtk_nand.c
-+++ b/drivers/mtd/nand/mtk_nand.c
-@@ -174,6 +174,10 @@ static const u8 spare_size_mt2712[] = {
- 	74
- };
- 
-+static const u8 spare_size_mt7622[] = {
-+	16, 26, 27, 28
-+};
-+
- static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
- {
- 	return container_of(nand, struct mtk_nfc_nand_chip, nand);
-@@ -1408,6 +1412,15 @@ static const struct mtk_nfc_caps mtk_nfc
- 	.max_sector_size = 1024,
- };
- 
-+static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
-+	.spare_size = spare_size_mt7622,
-+	.num_spare_size = 4,
-+	.pageformat_spare_shift = 4,
-+	.nfi_clk_div = 1,
-+	.max_sector = 8,
-+	.max_sector_size = 512,
-+};
-+
- static const struct of_device_id mtk_nfc_id_table[] = {
- 	{
- 		.compatible = "mediatek,mt2701-nfc",
-@@ -1415,6 +1428,9 @@ static const struct of_device_id mtk_nfc
- 	}, {
- 		.compatible = "mediatek,mt2712-nfc",
- 		.data = &mtk_nfc_caps_mt2712,
-+	}, {
-+		.compatible = "mediatek,mt7622-nfc",
-+		.data = &mtk_nfc_caps_mt7622,
- 	},
- 	{}
- };

target/linux/mediatek/patches-4.14/0168-mmc-dt-bindings-add-mmc-support-to-MT7623-SoC.patch

@@ -1,26 +0,0 @@
-From bb37b1aa5d1aadfcecd9189a653856099fbed507 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Thu, 7 Dec 2017 14:43:22 +0800
-Subject: [PATCH 168/224] mmc: dt-bindings: add mmc support to MT7623 SoC
-
-Add the devicetree binding for MT7623 SoC using MT2701 as the fallback.
-
-Cc: [email protected]
-Signed-off-by: Sean Wang <[email protected]>
-Acked-by: Rob Herring <[email protected]>
-Signed-off-by: Ulf Hansson <[email protected]>
----
- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
-+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
-@@ -12,6 +12,8 @@ Required properties:
- 	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
- 	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
- 	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
-+	"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
-+
- - reg: physical base address of the controller and length
- - interrupts: Should contain MSDC interrupt number
- - clocks: Should contain phandle for the clock feeding the MMC controller

target/linux/mediatek/patches-4.14/0169-dt-bindings-pinctrl-add-bindings-for-MediaTek-MT7622.patch

@@ -1,371 +0,0 @@
-From 4e4c2d695a5daf6dc55b8713af720ef15b52c0e7 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Tue, 12 Dec 2017 14:24:18 +0800
-Subject: [PATCH 169/224] dt-bindings: pinctrl: add bindings for MediaTek
- MT7622 SoC
-
-Add devicetree bindings for MediaTek MT7622 pinctrl driver.
-
-Signed-off-by: Sean Wang <[email protected]>
-Reviewed-by: Biao Huang <[email protected]>
-Acked-by: Rob Herring <[email protected]>
-Signed-off-by: Linus Walleij <[email protected]>
----
- .../devicetree/bindings/pinctrl/pinctrl-mt7622.txt | 351 +++++++++++++++++++++
- 1 file changed, 351 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
-@@ -0,0 +1,351 @@
-+== MediaTek MT7622 pinctrl controller ==
-+
-+Required properties for the root node:
-+ - compatible: Should be one of the following
-+	       "mediatek,mt7622-pinctrl" for MT7622 SoC
-+ - reg: offset and length of the pinctrl space
-+
-+ - gpio-controller: Marks the device node as a GPIO controller.
-+ - #gpio-cells: Should be two. The first cell is the pin number and the
-+   second is the GPIO flags.
-+
-+Please refer to pinctrl-bindings.txt in this directory for details of the
-+common pinctrl bindings used by client devices, including the meaning of the
-+phrase "pin configuration node".
-+
-+MT7622 pin configuration nodes act as a container for an arbitrary number of
-+subnodes. Each of these subnodes represents some desired configuration for a
-+pin, a group, or a list of pins or groups. This configuration can include the
-+mux function to select on those pin(s)/group(s), and various pin configuration
-+parameters, such as pull-up, slew rate, etc.
-+
-+We support 2 types of configuration nodes. Those nodes can be either pinmux
-+nodes or pinconf nodes. Each configuration node can consist of multiple nodes
-+describing the pinmux and pinconf options.
-+
-+The name of each subnode doesn't matter as long as it is unique; all subnodes
-+should be enumerated and processed purely based on their content.
-+
-+== pinmux nodes content ==
-+
-+The following generic properties as defined in pinctrl-bindings.txt are valid
-+to specify in a pinmux subnode:
-+
-+Required properties are:
-+ - groups: An array of strings. Each string contains the name of a group.
-+  Valid values for these names are listed below.
-+ - function: A string containing the name of the function to mux to the
-+  group. Valid values for function names are listed below.
-+
-+== pinconf nodes content ==
-+
-+The following generic properties as defined in pinctrl-bindings.txt are valid
-+to specify in a pinconf subnode:
-+
-+Required properties are:
-+ - pins: An array of strings. Each string contains the name of a pin.
-+  Valid values for these names are listed below.
-+ - groups: An array of strings. Each string contains the name of a group.
-+  Valid values for these names are listed below.
-+
-+Optional properies are:
-+ bias-disable, bias-pull, bias-pull-down, input-enable,
-+ input-schmitt-enable, input-schmitt-disable, output-enable
-+ output-low, output-high, drive-strength, slew-rate
-+
-+ Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
-+ slower slew rate respectively.
-+ Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
-+
-+The following specific properties as defined are valid to specify in a pinconf
-+subnode:
-+
-+Optional properties are:
-+ - mediatek,tdsel: An integer describing the steps for output level shifter duty
-+   cycle when asserted (high pulse width adjustment). Valid arguments are from 0
-+   to 15.
-+ - mediatek,rdsel: An integer describing the steps for input level shifter duty
-+   cycle when asserted (high pulse width adjustment). Valid arguments are from 0
-+   to 63.
-+
-+== Valid values for pins, function and groups on MT7622 ==
-+
-+Valid values for pins are:
-+pins can be referenced via the pin names as the below table shown and the
-+related physical number is also put ahead of those names which helps cross
-+references to pins between groups to know whether pins assignment conflict
-+happens among devices try to acquire those available pins.
-+
-+	Pin #:  Valid values for pins
-+	-----------------------------
-+	PIN 0: "GPIO_A"
-+	PIN 1: "I2S1_IN"
-+	PIN 2: "I2S1_OUT"
-+	PIN 3: "I2S_BCLK"
-+	PIN 4: "I2S_WS"
-+	PIN 5: "I2S_MCLK"
-+	PIN 6: "TXD0"
-+	PIN 7: "RXD0"
-+	PIN 8: "SPI_WP"
-+	PIN 9: "SPI_HOLD"
-+	PIN 10: "SPI_CLK"
-+	PIN 11: "SPI_MOSI"
-+	PIN 12: "SPI_MISO"
-+	PIN 13: "SPI_CS"
-+	PIN 14: "I2C_SDA"
-+	PIN 15: "I2C_SCL"
-+	PIN 16: "I2S2_IN"
-+	PIN 17: "I2S3_IN"
-+	PIN 18: "I2S4_IN"
-+	PIN 19: "I2S2_OUT"
-+	PIN 20: "I2S3_OUT"
-+	PIN 21: "I2S4_OUT"
-+	PIN 22: "GPIO_B"
-+	PIN 23: "MDC"
-+	PIN 24: "MDIO"
-+	PIN 25: "G2_TXD0"
-+	PIN 26: "G2_TXD1"
-+	PIN 27: "G2_TXD2"
-+	PIN 28: "G2_TXD3"
-+	PIN 29: "G2_TXEN"
-+	PIN 30: "G2_TXC"
-+	PIN 31: "G2_RXD0"
-+	PIN 32: "G2_RXD1"
-+	PIN 33: "G2_RXD2"
-+	PIN 34: "G2_RXD3"
-+	PIN 35: "G2_RXDV"
-+	PIN 36: "G2_RXC"
-+	PIN 37: "NCEB"
-+	PIN 38: "NWEB"
-+	PIN 39: "NREB"
-+	PIN 40: "NDL4"
-+	PIN 41: "NDL5"
-+	PIN 42: "NDL6"
-+	PIN 43: "NDL7"
-+	PIN 44: "NRB"
-+	PIN 45: "NCLE"
-+	PIN 46: "NALE"
-+	PIN 47: "NDL0"
-+	PIN 48: "NDL1"
-+	PIN 49: "NDL2"
-+	PIN 50: "NDL3"
-+	PIN 51: "MDI_TP_P0"
-+	PIN 52: "MDI_TN_P0"
-+	PIN 53: "MDI_RP_P0"
-+	PIN 54: "MDI_RN_P0"
-+	PIN 55: "MDI_TP_P1"
-+	PIN 56: "MDI_TN_P1"
-+	PIN 57: "MDI_RP_P1"
-+	PIN 58: "MDI_RN_P1"
-+	PIN 59: "MDI_RP_P2"
-+	PIN 60: "MDI_RN_P2"
-+	PIN 61: "MDI_TP_P2"
-+	PIN 62: "MDI_TN_P2"
-+	PIN 63: "MDI_TP_P3"
-+	PIN 64: "MDI_TN_P3"
-+	PIN 65: "MDI_RP_P3"
-+	PIN 66: "MDI_RN_P3"
-+	PIN 67: "MDI_RP_P4"
-+	PIN 68: "MDI_RN_P4"
-+	PIN 69: "MDI_TP_P4"
-+	PIN 70: "MDI_TN_P4"
-+	PIN 71: "PMIC_SCL"
-+	PIN 72: "PMIC_SDA"
-+	PIN 73: "SPIC1_CLK"
-+	PIN 74: "SPIC1_MOSI"
-+	PIN 75: "SPIC1_MISO"
-+	PIN 76: "SPIC1_CS"
-+	PIN 77: "GPIO_D"
-+	PIN 78: "WATCHDOG"
-+	PIN 79: "RTS3_N"
-+	PIN 80: "CTS3_N"
-+	PIN 81: "TXD3"
-+	PIN 82: "RXD3"
-+	PIN 83: "PERST0_N"
-+	PIN 84: "PERST1_N"
-+	PIN 85: "WLED_N"
-+	PIN 86: "EPHY_LED0_N"
-+	PIN 87: "AUXIN0"
-+	PIN 88: "AUXIN1"
-+	PIN 89: "AUXIN2"
-+	PIN 90: "AUXIN3"
-+	PIN 91: "TXD4"
-+	PIN 92: "RXD4"
-+	PIN 93: "RTS4_N"
-+	PIN 94: "CST4_N"
-+	PIN 95: "PWM1"
-+	PIN 96: "PWM2"
-+	PIN 97: "PWM3"
-+	PIN 98: "PWM4"
-+	PIN 99: "PWM5"
-+	PIN 100: "PWM6"
-+	PIN 101: "PWM7"
-+	PIN 102: "GPIO_E"
-+
-+Valid values for function are:
-+	"emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie",
-+	"pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
-+
-+Valid values for groups are:
-+additional data is put followingly with valid value allowing us to know which
-+applicable function and which relevant pins (in pin#) are able applied for that
-+group.
-+
-+	Valid value			function	pins (in pin#)
-+	-------------------------------------------------------------------------
-+	"emmc"				"emmc"		40, 41, 42, 43, 44, 45,
-+							47, 48, 49, 50
-+	"emmc_rst"			"emmc"		37
-+	"esw"				"eth"		51, 52, 53, 54, 55, 56,
-+							57, 58, 59, 60, 61, 62,
-+							63, 64, 65, 66, 67, 68,
-+							69, 70
-+	"esw_p0_p1"			"eth"		51, 52, 53, 54, 55, 56,
-+							57, 58
-+	"esw_p2_p3_p4"			"eth"		59, 60, 61, 62, 63, 64,
-+							65, 66, 67, 68, 69, 70
-+	"rgmii_via_esw"			"eth"		59, 60, 61, 62, 63, 64,
-+							65, 66, 67, 68, 69, 70
-+	"rgmii_via_gmac1"		"eth"		59, 60, 61, 62, 63, 64,
-+							65, 66, 67, 68, 69, 70
-+	"rgmii_via_gmac2"		"eth"		25, 26, 27, 28, 29, 30,
-+							31, 32, 33, 34, 35, 36
-+	"mdc_mdio"			"eth"		23, 24
-+	"i2c0"				"i2c"		14, 15
-+	"i2c1_0"			"i2c"		55, 56
-+	"i2c1_1"			"i2c"		73, 74
-+	"i2c1_2"			"i2c"		87, 88
-+	"i2c2_0"			"i2c"		57, 58
-+	"i2c2_1"			"i2c"		75, 76
-+	"i2c2_2"			"i2c"		89, 90
-+	"i2s_in_mclk_bclk_ws"		"i2s"		3, 4, 5
-+	"i2s1_in_data"			"i2s"		1
-+	"i2s2_in_data"			"i2s"		16
-+	"i2s3_in_data"			"i2s"		17
-+	"i2s4_in_data"			"i2s"		18
-+	"i2s_out_mclk_bclk_ws"		"i2s"		3, 4, 5
-+	"i2s1_out_data"			"i2s"		2
-+	"i2s2_out_data"			"i2s"		19
-+	"i2s3_out_data"			"i2s"		20
-+	"i2s4_out_data"			"i2s"		21
-+	"ir_0_tx"			"ir"		16
-+	"ir_1_tx"			"ir"		59
-+	"ir_2_tx"			"ir"		99
-+	"ir_0_rx"			"ir"		17
-+	"ir_1_rx"			"ir"		60
-+	"ir_2_rx"			"ir"		100
-+	"ephy_leds"			"led"		86, 91, 92, 93, 94
-+	"ephy0_led"			"led"		86
-+	"ephy1_led"			"led"		91
-+	"ephy2_led"			"led"		92
-+	"ephy3_led"			"led"		93
-+	"ephy4_led"			"led"		94
-+	"wled"				"led"		85
-+	"par_nand"			"flash"		37, 38, 39, 40, 41, 42,
-+							43, 44, 45, 46, 47, 48,
-+							49, 50
-+	"snfi"				"flash"		8, 9, 10, 11, 12, 13
-+	"spi_nor"			"flash"		8, 9, 10, 11, 12, 13
-+	"pcie0_0_waken"			"pcie"		14
-+	"pcie0_1_waken"			"pcie"		79
-+	"pcie1_0_waken"			"pcie"		14
-+	"pcie0_0_clkreq"		"pcie"		15
-+	"pcie0_1_clkreq"		"pcie"		80
-+	"pcie1_0_clkreq"		"pcie"		15
-+	"pcie0_pad_perst"		"pcie"		83
-+	"pcie1_pad_perst"		"pcie"		84
-+	"pmic_bus"			"pmic"		71, 72
-+	"pwm_ch1_0"			"pwm"		51
-+	"pwm_ch1_1"			"pwm"		73
-+	"pwm_ch1_2"			"pwm"		95
-+	"pwm_ch2_0"			"pwm"		52
-+	"pwm_ch2_1"			"pwm"		74
-+	"pwm_ch2_2"			"pwm"		96
-+	"pwm_ch3_0"			"pwm"		53
-+	"pwm_ch3_1"			"pwm"		75
-+	"pwm_ch3_2"			"pwm"		97
-+	"pwm_ch4_0"			"pwm"		54
-+	"pwm_ch4_1"			"pwm"		67
-+	"pwm_ch4_2"			"pwm"		76
-+	"pwm_ch4_3"			"pwm"		98
-+	"pwm_ch5_0"			"pwm"		68
-+	"pwm_ch5_1"			"pwm"		77
-+	"pwm_ch5_2"			"pwm"		99
-+	"pwm_ch6_0"			"pwm"		69
-+	"pwm_ch6_1"			"pwm"		78
-+	"pwm_ch6_2"			"pwm"		81
-+	"pwm_ch6_3"			"pwm"		100
-+	"pwm_ch7_0"			"pwm"		70
-+	"pwm_ch7_1"			"pwm"		82
-+	"pwm_ch7_2"			"pwm"		101
-+	"sd_0"				"sd"		16, 17, 18, 19, 20, 21
-+	"sd_1"				"sd"		25, 26, 27, 28, 29, 30
-+	"spic0_0"			"spi"		63, 64, 65, 66
-+	"spic0_1"			"spi"		79, 80, 81, 82
-+	"spic1_0"			"spi"		67, 68, 69, 70
-+	"spic1_1"			"spi"		73, 74, 75, 76
-+	"spic2_0_wp_hold"		"spi"		8, 9
-+	"spic2_0"			"spi"		10, 11, 12, 13
-+	"tdm_0_out_mclk_bclk_ws"	"tdm"		8, 9, 10
-+	"tdm_0_in_mclk_bclk_ws"		"tdm"		11, 12, 13
-+	"tdm_0_out_data"		"tdm"		20
-+	"tdm_0_in_data"			"tdm"		21
-+	"tdm_1_out_mclk_bclk_ws"	"tdm"		57, 58, 59
-+	"tdm_1_in_mclk_bclk_ws"		"tdm"		60, 61, 62
-+	"tdm_1_out_data"		"tdm"		55
-+	"tdm_1_in_data"			"tdm"		56
-+	"uart0_0_tx_rx"			"uart"		6, 7
-+	"uart1_0_tx_rx"			"uart"		55, 56
-+	"uart1_0_rts_cts"		"uart"		57, 58
-+	"uart1_1_tx_rx"			"uart"		73, 74
-+	"uart1_1_rts_cts"		"uart"		75, 76
-+	"uart2_0_tx_rx"			"uart"		3, 4
-+	"uart2_0_rts_cts"		"uart"		1, 2
-+	"uart2_1_tx_rx"			"uart"		51, 52
-+	"uart2_1_rts_cts"		"uart"		53, 54
-+	"uart2_2_tx_rx"			"uart"		59, 60
-+	"uart2_2_rts_cts"		"uart"		61, 62
-+	"uart2_3_tx_rx"			"uart"		95, 96
-+	"uart3_0_tx_rx"			"uart"		57, 58
-+	"uart3_1_tx_rx"			"uart"		81, 82
-+	"uart3_1_rts_cts"		"uart"		79, 80
-+	"uart4_0_tx_rx"			"uart"		61, 62
-+	"uart4_1_tx_rx"			"uart"		91, 92
-+	"uart4_1_rts_cts"		"uart"		93, 94
-+	"uart4_2_tx_rx"			"uart"		97, 98
-+	"uart4_2_rts_cts"		"uart"		95, 96
-+	"watchdog"			"watchdog"	78
-+
-+Example:
-+
-+	pio: pinctrl@10211000 {
-+		compatible = "mediatek,mt7622-pinctrl";
-+		reg = <0 0x10211000 0 0x1000>;
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+
-+		pinctrl_eth_default: eth-default {
-+			mux-mdio {
-+				groups = "mdc_mdio";
-+				function = "eth";
-+				drive-strength = <12>;
-+			};
-+
-+			mux-gmac2 {
-+				groups = "gmac2";
-+				function = "eth";
-+				drive-strength = <12>;
-+			};
-+
-+			mux-esw {
-+				groups = "esw";
-+				function = "eth";
-+				drive-strength = <8>;
-+			};
-+
-+			conf-mdio {
-+				pins = "MDC";
-+				bias-pull-up;
-+			};
-+		};
-+	};

target/linux/mediatek/patches-4.14/0170-pinctrl-mediatek-cleanup-for-placing-all-drivers-und.patch

@@ -1,32 +0,0 @@
-From 547700768b2e7a105ed27a3b955fd9b7142987d7 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Tue, 12 Dec 2017 14:24:19 +0800
-Subject: [PATCH 170/224] pinctrl: mediatek: cleanup for placing all drivers
- under the menu
-
-Since lots of MediaTek drivers had been added, it seems slightly better
-for that adding cleanup for placing MediaTek pinctrl drivers under the
-independent menu as other kinds of drivers usually was done.
-
-Signed-off-by: Sean Wang <[email protected]>
-Reviewed-by: Biao Huang <[email protected]>
-Signed-off-by: Linus Walleij <[email protected]>
----
- drivers/pinctrl/mediatek/Kconfig | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -1,4 +1,5 @@
--if ARCH_MEDIATEK || COMPILE_TEST
-+menu "MediaTek pinctrl drivers"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
- 
- config PINCTRL_MTK
- 	bool
-@@ -46,4 +47,4 @@ config PINCTRL_MT6397
- 	default MFD_MT6397
- 	select PINCTRL_MTK
- 
--endif
-+endmenu

target/linux/mediatek/patches-4.14/0171-pinctrl-mediatek-add-pinctrl-driver-for-MT7622-SoC.patch

@@ -1,1675 +0,0 @@
-From 4318e143fe3ac617de20cf72aa32fd9d3ad92ee6 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Tue, 12 Dec 2017 14:24:20 +0800
-Subject: [PATCH 171/224] pinctrl: mediatek: add pinctrl driver for MT7622 SoC
-
-Add support for pinctrl on MT7622 SoC. The IO core found on the SoC has
-the registers for pinctrl, pinconf and gpio mixed up in the same register
-range. However, the IO core for the MT7622 SoC is completely distinct from
-anyone of previous MediaTek SoCs which already had support, such as
-the hardware internal, register address map and register detailed
-definition for each pin.
-
-Therefore, instead, the driver is being newly implemented by reusing
-generic methods provided from the core layer with GENERIC_PINCONF,
-GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code
-simplicity and rid of superfluous code. Where the function of pins
-determined by groups is utilized in this driver which can help developers
-less confused with what combinations of pins effective on the SoC and even
-reducing the mistakes during the integration of those relevant boards.
-
-As the gpio_chip handling is also only a few lines, the driver also
-implements the gpio functionality directly through GPIOLIB.
-
-Signed-off-by: Sean Wang <[email protected]>
-Reviewed-by: Biao Huang <[email protected]>
-Signed-off-by: Linus Walleij <[email protected]>
----
- drivers/pinctrl/Makefile                  |    2 +-
- drivers/pinctrl/mediatek/Kconfig          |   10 +
- drivers/pinctrl/mediatek/Makefile         |    3 +-
- drivers/pinctrl/mediatek/pinctrl-mt7622.c | 1595 +++++++++++++++++++++++++++++
- 4 files changed, 1608 insertions(+), 2 deletions(-)
- create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7622.c
-
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -64,5 +64,5 @@ obj-$(CONFIG_PINCTRL_SUNXI)	+= sunxi/
- obj-y				+= ti/
- obj-$(CONFIG_PINCTRL_UNIPHIER)	+= uniphier/
- obj-$(CONFIG_ARCH_VT8500)	+= vt8500/
--obj-$(CONFIG_PINCTRL_MTK)	+= mediatek/
-+obj-y				+= mediatek/
- obj-$(CONFIG_PINCTRL_ZX)	+= zte/
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -32,6 +32,16 @@ config PINCTRL_MT8127
- 	select PINCTRL_MTK
- 
- # For ARMv8 SoCs
-+config PINCTRL_MT7622
-+	bool "MediaTek MT7622 pin control"
-+	depends on OF
-+	depends on ARM64 || COMPILE_TEST
-+	select GENERIC_PINCONF
-+	select GENERIC_PINCTRL_GROUPS
-+	select GENERIC_PINMUX_FUNCTIONS
-+	select GPIOLIB
-+	select OF_GPIO
-+
- config PINCTRL_MT8173
- 	bool "Mediatek MT8173 pin control"
- 	depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -1,10 +1,11 @@
- # SPDX-License-Identifier: GPL-2.0
- # Core
--obj-y				+= pinctrl-mtk-common.o
-+obj-$(CONFIG_PINCTRL_MTK)	+= pinctrl-mtk-common.o
- 
- # SoC Drivers
- obj-$(CONFIG_PINCTRL_MT2701)	+= pinctrl-mt2701.o
- obj-$(CONFIG_PINCTRL_MT8135)	+= pinctrl-mt8135.o
- obj-$(CONFIG_PINCTRL_MT8127)	+= pinctrl-mt8127.o
-+obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT6397)	+= pinctrl-mt6397.o
---- /dev/null
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-@@ -0,0 +1,1595 @@
-+/*
-+ * MediaTek MT7622 Pinctrl Driver
-+ *
-+ * Copyright (C) 2017 Sean Wang <[email protected]>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/gpio.h>
-+#include <linux/gpio/driver.h>
-+#include <linux/io.h>
-+#include <linux/init.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/pinctrl/pinconf.h>
-+#include <linux/pinctrl/pinconf-generic.h>
-+#include <linux/regmap.h>
-+
-+#include "../core.h"
-+#include "../pinconf.h"
-+#include "../pinmux.h"
-+
-+#define PINCTRL_PINCTRL_DEV		KBUILD_MODNAME
-+#define MTK_RANGE(_a)		{ .range = (_a), .nranges = ARRAY_SIZE(_a), }
-+#define PINCTRL_PIN_GROUP(name, id)			\
-+	{						\
-+		name,					\
-+		id##_pins,				\
-+		ARRAY_SIZE(id##_pins),			\
-+		id##_funcs,				\
-+	}
-+
-+#define MTK_GPIO_MODE	1
-+#define MTK_INPUT	0
-+#define MTK_OUTPUT	1
-+#define MTK_DISABLE	0
-+#define MTK_ENABLE	1
-+
-+/* Custom pinconf parameters */
-+#define MTK_PIN_CONFIG_TDSEL	(PIN_CONFIG_END + 1)
-+#define MTK_PIN_CONFIG_RDSEL	(PIN_CONFIG_END + 2)
-+
-+/* List these attributes which could be modified for the pin */
-+enum {
-+	PINCTRL_PIN_REG_MODE,
-+	PINCTRL_PIN_REG_DIR,
-+	PINCTRL_PIN_REG_DI,
-+	PINCTRL_PIN_REG_DO,
-+	PINCTRL_PIN_REG_SR,
-+	PINCTRL_PIN_REG_SMT,
-+	PINCTRL_PIN_REG_PD,
-+	PINCTRL_PIN_REG_PU,
-+	PINCTRL_PIN_REG_E4,
-+	PINCTRL_PIN_REG_E8,
-+	PINCTRL_PIN_REG_TDSEL,
-+	PINCTRL_PIN_REG_RDSEL,
-+	PINCTRL_PIN_REG_MAX,
-+};
-+
-+/* struct mtk_pin_field - the structure that holds the information of the field
-+ *			  used to describe the attribute for the pin
-+ * @offset:		the register offset relative to the base address
-+ * @mask:		the mask used to filter out the field from the register
-+ * @bitpos:		the start bit relative to the register
-+ * @next:		the indication that the field would be extended to the
-+			next register
-+ */
-+struct mtk_pin_field {
-+	u32 offset;
-+	u32 mask;
-+	u8  bitpos;
-+	u8  next;
-+};
-+
-+/* struct mtk_pin_field_calc - the structure that holds the range providing
-+ *			       the guide used to look up the relevant field
-+ * @s_pin:		the start pin within the range
-+ * @e_pin:		the end pin within the range
-+ * @s_addr:		the start address for the range
-+ * @x_addrs:		the address distance between two consecutive registers
-+ *			within the range
-+ * @s_bit:		the start bit for the first register within the range
-+ * @x_bits:		the bit distance between two consecutive pins within
-+ *			the range
-+ */
-+struct mtk_pin_field_calc {
-+	u16 s_pin;
-+	u16 e_pin;
-+	u32 s_addr;
-+	u8  x_addrs;
-+	u8  s_bit;
-+	u8  x_bits;
-+};
-+
-+/* struct mtk_pin_reg_calc - the structure that holds all ranges used to
-+ *			     determine which register the pin would make use of
-+ *			     for certain pin attribute.
-+ * @range:		     the start address for the range
-+ * @nranges:		     the number of items in the range
-+ */
-+struct mtk_pin_reg_calc {
-+	const struct mtk_pin_field_calc *range;
-+	unsigned int nranges;
-+};
-+
-+/* struct mtk_pin_soc - the structure that holds SoC-specific data */
-+struct mtk_pin_soc {
-+	const struct mtk_pin_reg_calc	*reg_cal;
-+	const struct pinctrl_pin_desc	*pins;
-+	unsigned int			npins;
-+	const struct group_desc		*grps;
-+	unsigned int			ngrps;
-+	const struct function_desc	*funcs;
-+	unsigned int			nfuncs;
-+};
-+
-+struct mtk_pinctrl {
-+	struct pinctrl_dev		*pctrl;
-+	void __iomem			*base;
-+	struct device			*dev;
-+	struct gpio_chip		chip;
-+	const struct mtk_pin_soc	*soc;
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
-+	{0, 0, 0x320, 0x10, 16, 4},
-+	{1, 4, 0x3a0, 0x10,  16, 4},
-+	{5, 5, 0x320, 0x10,  0, 4},
-+	{6, 6, 0x300, 0x10,  4, 4},
-+	{7, 7, 0x300, 0x10,  4, 4},
-+	{8, 9, 0x350, 0x10,  20, 4},
-+	{10, 10, 0x300, 0x10, 8, 4},
-+	{11, 11, 0x300, 0x10, 8, 4},
-+	{12, 12, 0x300, 0x10, 8, 4},
-+	{13, 13, 0x300, 0x10, 8, 4},
-+	{14, 15, 0x320, 0x10, 4, 4},
-+	{16, 17, 0x320, 0x10, 20, 4},
-+	{18, 21, 0x310, 0x10, 16, 4},
-+	{22, 22, 0x380, 0x10, 16, 4},
-+	{23, 23, 0x300,	0x10, 24, 4},
-+	{24, 24, 0x300, 0x10, 24, 4},
-+	{25, 25, 0x300, 0x10, 12, 4},
-+	{25, 25, 0x300, 0x10, 12, 4},
-+	{26, 26, 0x300, 0x10, 12, 4},
-+	{27, 27, 0x300, 0x10, 12, 4},
-+	{28, 28, 0x300, 0x10, 12, 4},
-+	{29, 29, 0x300, 0x10, 12, 4},
-+	{30, 30, 0x300, 0x10, 12, 4},
-+	{31, 31, 0x300, 0x10, 12, 4},
-+	{32, 32, 0x300, 0x10, 12, 4},
-+	{33, 33, 0x300,	0x10, 12, 4},
-+	{34, 34, 0x300,	0x10, 12, 4},
-+	{35, 35, 0x300,	0x10, 12, 4},
-+	{36, 36, 0x300, 0x10, 12, 4},
-+	{37, 37, 0x300, 0x10, 20, 4},
-+	{38, 38, 0x300, 0x10, 20, 4},
-+	{39, 39, 0x300, 0x10, 20, 4},
-+	{40, 40, 0x300, 0x10, 20, 4},
-+	{41, 41, 0x300,	0x10, 20, 4},
-+	{42, 42, 0x300, 0x10, 20, 4},
-+	{43, 43, 0x300,	0x10, 20, 4},
-+	{44, 44, 0x300, 0x10, 20, 4},
-+	{45, 46, 0x300, 0x10, 20, 4},
-+	{47, 47, 0x300,	0x10, 20, 4},
-+	{48, 48, 0x300, 0x10, 20, 4},
-+	{49, 49, 0x300, 0x10, 20, 4},
-+	{50, 50, 0x300, 0x10, 20, 4},
-+	{51, 70, 0x330, 0x10, 4, 4},
-+	{71, 71, 0x300, 0x10, 16, 4},
-+	{72, 72, 0x300, 0x10, 16, 4},
-+	{73, 76, 0x310, 0x10, 0, 4},
-+	{77, 77, 0x320, 0x10, 28, 4},
-+	{78, 78, 0x320, 0x10, 12, 4},
-+	{79, 82, 0x3a0, 0x10, 0, 4},
-+	{83, 83, 0x350,	0x10, 28, 4},
-+	{84, 84, 0x330, 0x10, 0, 4},
-+	{85, 90, 0x360, 0x10, 4, 4},
-+	{91, 94, 0x390, 0x10, 16, 4},
-+	{95, 97, 0x380, 0x10, 20, 4},
-+	{98, 101, 0x390, 0x10, 0, 4},
-+	{102, 102, 0x360, 0x10, 0, 4},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
-+	{0, 102, 0x0, 0x10, 0, 1},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
-+	{0, 102, 0x200, 0x10, 0, 1},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
-+	{0, 102, 0x100, 0x10, 0, 1},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
-+	{0, 31, 0x910, 0x10, 0, 1},
-+	{32, 50, 0xa10, 0x10, 0, 1},
-+	{51, 70, 0x810, 0x10, 0, 1},
-+	{71, 72, 0xb10, 0x10, 0, 1},
-+	{73, 86, 0xb10, 0x10, 4, 1},
-+	{87, 90, 0xc10, 0x10, 0, 1},
-+	{91, 102, 0xb10, 0x10, 18, 1},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
-+	{0, 31, 0x920, 0x10, 0, 1},
-+	{32, 50, 0xa20, 0x10, 0, 1},
-+	{51, 70, 0x820, 0x10, 0, 1},
-+	{71, 72, 0xb20, 0x10, 0, 1},
-+	{73, 86, 0xb20, 0x10, 4, 1},
-+	{87, 90, 0xc20, 0x10, 0, 1},
-+	{91, 102, 0xb20, 0x10, 18, 1},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
-+	{0, 31, 0x930, 0x10, 0, 1},
-+	{32, 50, 0xa30, 0x10, 0, 1},
-+	{51, 70, 0x830, 0x10, 0, 1},
-+	{71, 72, 0xb30, 0x10, 0, 1},
-+	{73, 86, 0xb30, 0x10, 4, 1},
-+	{87, 90, 0xc30, 0x10, 0, 1},
-+	{91, 102, 0xb30, 0x10, 18, 1},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
-+	{0, 31, 0x940, 0x10, 0, 1},
-+	{32, 50, 0xa40, 0x10, 0, 1},
-+	{51, 70, 0x840, 0x10, 0, 1},
-+	{71, 72, 0xb40, 0x10, 0, 1},
-+	{73, 86, 0xb40, 0x10, 4, 1},
-+	{87, 90, 0xc40, 0x10, 0, 1},
-+	{91, 102, 0xb40, 0x10, 18, 1},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
-+	{0, 31, 0x960, 0x10, 0, 1},
-+	{32, 50, 0xa60, 0x10, 0, 1},
-+	{51, 70, 0x860, 0x10, 0, 1},
-+	{71, 72, 0xb60, 0x10, 0, 1},
-+	{73, 86, 0xb60, 0x10, 4, 1},
-+	{87, 90, 0xc60, 0x10, 0, 1},
-+	{91, 102, 0xb60, 0x10, 18, 1},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
-+	{0, 31, 0x970, 0x10, 0, 1},
-+	{32, 50, 0xa70, 0x10, 0, 1},
-+	{51, 70, 0x870, 0x10, 0, 1},
-+	{71, 72, 0xb70, 0x10, 0, 1},
-+	{73, 86, 0xb70, 0x10, 4, 1},
-+	{87, 90, 0xc70, 0x10, 0, 1},
-+	{91, 102, 0xb70, 0x10, 18, 1},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
-+	{0, 31, 0x980, 0x4, 0, 4},
-+	{32, 50, 0xa80, 0x4, 0, 4},
-+	{51, 70, 0x880, 0x4, 0, 4},
-+	{71, 72, 0xb80, 0x4, 0, 4},
-+	{73, 86, 0xb80, 0x4, 16, 4},
-+	{87, 90, 0xc80, 0x4, 0, 4},
-+	{91, 102, 0xb88, 0x4, 8, 4},
-+};
-+
-+static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
-+	{0, 31, 0x990, 0x4, 0, 6},
-+	{32, 50, 0xa90, 0x4, 0, 6},
-+	{51, 58, 0x890, 0x4, 0, 6},
-+	{59, 60, 0x894, 0x4, 28, 6},
-+	{61, 62, 0x894, 0x4, 16, 6},
-+	{63, 66, 0x898, 0x4, 8, 6},
-+	{67, 68, 0x89c, 0x4, 12, 6},
-+	{69, 70, 0x89c, 0x4, 0, 6},
-+	{71, 72, 0xb90, 0x4, 0, 6},
-+	{73, 86, 0xb90, 0x4, 24, 6},
-+	{87, 90, 0xc90, 0x4, 0, 6},
-+	{91, 102, 0xb9c, 0x4, 12, 6},
-+};
-+
-+static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
-+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
-+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
-+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
-+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
-+	[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt7622_pin_sr_range),
-+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
-+	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
-+	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
-+	[PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
-+	[PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
-+	[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7622_pin_tdsel_range),
-+	[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
-+};
-+
-+static const struct pinctrl_pin_desc mt7622_pins[] = {
-+	PINCTRL_PIN(0, "GPIO_A"),
-+	PINCTRL_PIN(1, "I2S1_IN"),
-+	PINCTRL_PIN(2, "I2S1_OUT"),
-+	PINCTRL_PIN(3, "I2S_BCLK"),
-+	PINCTRL_PIN(4, "I2S_WS"),
-+	PINCTRL_PIN(5, "I2S_MCLK"),
-+	PINCTRL_PIN(6, "TXD0"),
-+	PINCTRL_PIN(7, "RXD0"),
-+	PINCTRL_PIN(8, "SPI_WP"),
-+	PINCTRL_PIN(9, "SPI_HOLD"),
-+	PINCTRL_PIN(10, "SPI_CLK"),
-+	PINCTRL_PIN(11, "SPI_MOSI"),
-+	PINCTRL_PIN(12, "SPI_MISO"),
-+	PINCTRL_PIN(13, "SPI_CS"),
-+	PINCTRL_PIN(14, "I2C_SDA"),
-+	PINCTRL_PIN(15, "I2C_SCL"),
-+	PINCTRL_PIN(16, "I2S2_IN"),
-+	PINCTRL_PIN(17, "I2S3_IN"),
-+	PINCTRL_PIN(18, "I2S4_IN"),
-+	PINCTRL_PIN(19, "I2S2_OUT"),
-+	PINCTRL_PIN(20, "I2S3_OUT"),
-+	PINCTRL_PIN(21, "I2S4_OUT"),
-+	PINCTRL_PIN(22, "GPIO_B"),
-+	PINCTRL_PIN(23, "MDC"),
-+	PINCTRL_PIN(24, "MDIO"),
-+	PINCTRL_PIN(25, "G2_TXD0"),
-+	PINCTRL_PIN(26, "G2_TXD1"),
-+	PINCTRL_PIN(27, "G2_TXD2"),
-+	PINCTRL_PIN(28, "G2_TXD3"),
-+	PINCTRL_PIN(29, "G2_TXEN"),
-+	PINCTRL_PIN(30, "G2_TXC"),
-+	PINCTRL_PIN(31, "G2_RXD0"),
-+	PINCTRL_PIN(32, "G2_RXD1"),
-+	PINCTRL_PIN(33, "G2_RXD2"),
-+	PINCTRL_PIN(34, "G2_RXD3"),
-+	PINCTRL_PIN(35, "G2_RXDV"),
-+	PINCTRL_PIN(36, "G2_RXC"),
-+	PINCTRL_PIN(37, "NCEB"),
-+	PINCTRL_PIN(38, "NWEB"),
-+	PINCTRL_PIN(39, "NREB"),
-+	PINCTRL_PIN(40, "NDL4"),
-+	PINCTRL_PIN(41, "NDL5"),
-+	PINCTRL_PIN(42, "NDL6"),
-+	PINCTRL_PIN(43, "NDL7"),
-+	PINCTRL_PIN(44, "NRB"),
-+	PINCTRL_PIN(45, "NCLE"),
-+	PINCTRL_PIN(46, "NALE"),
-+	PINCTRL_PIN(47, "NDL0"),
-+	PINCTRL_PIN(48, "NDL1"),
-+	PINCTRL_PIN(49, "NDL2"),
-+	PINCTRL_PIN(50, "NDL3"),
-+	PINCTRL_PIN(51, "MDI_TP_P0"),
-+	PINCTRL_PIN(52, "MDI_TN_P0"),
-+	PINCTRL_PIN(53, "MDI_RP_P0"),
-+	PINCTRL_PIN(54, "MDI_RN_P0"),
-+	PINCTRL_PIN(55, "MDI_TP_P1"),
-+	PINCTRL_PIN(56, "MDI_TN_P1"),
-+	PINCTRL_PIN(57, "MDI_RP_P1"),
-+	PINCTRL_PIN(58, "MDI_RN_P1"),
-+	PINCTRL_PIN(59, "MDI_RP_P2"),
-+	PINCTRL_PIN(60, "MDI_RN_P2"),
-+	PINCTRL_PIN(61, "MDI_TP_P2"),
-+	PINCTRL_PIN(62, "MDI_TN_P2"),
-+	PINCTRL_PIN(63, "MDI_TP_P3"),
-+	PINCTRL_PIN(64, "MDI_TN_P3"),
-+	PINCTRL_PIN(65, "MDI_RP_P3"),
-+	PINCTRL_PIN(66, "MDI_RN_P3"),
-+	PINCTRL_PIN(67, "MDI_RP_P4"),
-+	PINCTRL_PIN(68, "MDI_RN_P4"),
-+	PINCTRL_PIN(69, "MDI_TP_P4"),
-+	PINCTRL_PIN(70, "MDI_TN_P4"),
-+	PINCTRL_PIN(71, "PMIC_SCL"),
-+	PINCTRL_PIN(72, "PMIC_SDA"),
-+	PINCTRL_PIN(73, "SPIC1_CLK"),
-+	PINCTRL_PIN(74, "SPIC1_MOSI"),
-+	PINCTRL_PIN(75, "SPIC1_MISO"),
-+	PINCTRL_PIN(76, "SPIC1_CS"),
-+	PINCTRL_PIN(77, "GPIO_D"),
-+	PINCTRL_PIN(78, "WATCHDOG"),
-+	PINCTRL_PIN(79, "RTS3_N"),
-+	PINCTRL_PIN(80, "CTS3_N"),
-+	PINCTRL_PIN(81, "TXD3"),
-+	PINCTRL_PIN(82, "RXD3"),
-+	PINCTRL_PIN(83, "PERST0_N"),
-+	PINCTRL_PIN(84, "PERST1_N"),
-+	PINCTRL_PIN(85, "WLED_N"),
-+	PINCTRL_PIN(86, "EPHY_LED0_N"),
-+	PINCTRL_PIN(87, "AUXIN0"),
-+	PINCTRL_PIN(88, "AUXIN1"),
-+	PINCTRL_PIN(89, "AUXIN2"),
-+	PINCTRL_PIN(90, "AUXIN3"),
-+	PINCTRL_PIN(91, "TXD4"),
-+	PINCTRL_PIN(92, "RXD4"),
-+	PINCTRL_PIN(93, "RTS4_N"),
-+	PINCTRL_PIN(94, "CTS4_N"),
-+	PINCTRL_PIN(95, "PWM1"),
-+	PINCTRL_PIN(96, "PWM2"),
-+	PINCTRL_PIN(97, "PWM3"),
-+	PINCTRL_PIN(98, "PWM4"),
-+	PINCTRL_PIN(99, "PWM5"),
-+	PINCTRL_PIN(100, "PWM6"),
-+	PINCTRL_PIN(101, "PWM7"),
-+	PINCTRL_PIN(102, "GPIO_E"),
-+};
-+
-+/* List all groups consisting of these pins dedicated to the enablement of
-+ * certain hardware block and the corresponding mode for all of the pins. The
-+ * hardware probably has multiple combinations of these pinouts.
-+ */
-+
-+/* EMMC */
-+static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
-+static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+
-+static int mt7622_emmc_rst_pins[] = { 37, };
-+static int mt7622_emmc_rst_funcs[] = { 1, };
-+
-+/* LED for EPHY */
-+static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
-+static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
-+static int mt7622_ephy0_led_pins[] = { 86, };
-+static int mt7622_ephy0_led_funcs[] = { 0, };
-+static int mt7622_ephy1_led_pins[] = { 91, };
-+static int mt7622_ephy1_led_funcs[] = { 2, };
-+static int mt7622_ephy2_led_pins[] = { 92, };
-+static int mt7622_ephy2_led_funcs[] = { 2, };
-+static int mt7622_ephy3_led_pins[] = { 93, };
-+static int mt7622_ephy3_led_funcs[] = { 2, };
-+static int mt7622_ephy4_led_pins[] = { 94, };
-+static int mt7622_ephy4_led_funcs[] = { 2, };
-+
-+/* Embedded Switch */
-+static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
-+				 62, 63, 64, 65, 66, 67, 68, 69, 70, };
-+static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+				  0, 0, 0, 0, 0, 0, 0, 0, 0, };
-+static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
-+static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
-+static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
-+					  68, 69, 70, };
-+static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+					   0, 0, 0, };
-+/* RGMII via ESW */
-+static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
-+					   67, 68, 69, 70, };
-+static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+					    0, };
-+
-+/* RGMII via GMAC1 */
-+static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
-+					     67, 68, 69, 70, };
-+static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-+					      2, };
-+
-+/* RGMII via GMAC2 */
-+static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
-+					     33, 34, 35, 36, };
-+static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+					      0, };
-+
-+/* I2C */
-+static int mt7622_i2c0_pins[] = { 14, 15, };
-+static int mt7622_i2c0_funcs[] = { 0, 0, };
-+static int mt7622_i2c1_0_pins[] = { 55, 56, };
-+static int mt7622_i2c1_0_funcs[] = { 0, 0, };
-+static int mt7622_i2c1_1_pins[] = { 73, 74, };
-+static int mt7622_i2c1_1_funcs[] = { 3, 3, };
-+static int mt7622_i2c1_2_pins[] = { 87, 88, };
-+static int mt7622_i2c1_2_funcs[] = { 0, 0, };
-+static int mt7622_i2c2_0_pins[] = { 57, 58, };
-+static int mt7622_i2c2_0_funcs[] = { 0, 0, };
-+static int mt7622_i2c2_1_pins[] = { 75, 76, };
-+static int mt7622_i2c2_1_funcs[] = { 3, 3, };
-+static int mt7622_i2c2_2_pins[] = { 89, 90, };
-+static int mt7622_i2c2_2_funcs[] = { 0, 0, };
-+
-+/* I2S */
-+static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-+static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
-+static int mt7622_i2s1_in_data_pins[] = { 1, };
-+static int mt7622_i2s1_in_data_funcs[] = { 0, };
-+static int mt7622_i2s2_in_data_pins[] = { 16, };
-+static int mt7622_i2s2_in_data_funcs[] = { 0, };
-+static int mt7622_i2s3_in_data_pins[] = { 17, };
-+static int mt7622_i2s3_in_data_funcs[] = { 0, };
-+static int mt7622_i2s4_in_data_pins[] = { 18, };
-+static int mt7622_i2s4_in_data_funcs[] = { 0, };
-+static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
-+static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
-+static int mt7622_i2s1_out_data_pins[] = { 2, };
-+static int mt7622_i2s1_out_data_funcs[] = { 0, };
-+static int mt7622_i2s2_out_data_pins[] = { 19, };
-+static int mt7622_i2s2_out_data_funcs[] = { 0, };
-+static int mt7622_i2s3_out_data_pins[] = { 20, };
-+static int mt7622_i2s3_out_data_funcs[] = { 0, };
-+static int mt7622_i2s4_out_data_pins[] = { 21, };
-+static int mt7622_i2s4_out_data_funcs[] = { 0, };
-+
-+/* IR */
-+static int mt7622_ir_0_tx_pins[] = { 16, };
-+static int mt7622_ir_0_tx_funcs[] = { 4, };
-+static int mt7622_ir_1_tx_pins[] = { 59, };
-+static int mt7622_ir_1_tx_funcs[] = { 5, };
-+static int mt7622_ir_2_tx_pins[] = { 99, };
-+static int mt7622_ir_2_tx_funcs[] = { 3, };
-+static int mt7622_ir_0_rx_pins[] = { 17, };
-+static int mt7622_ir_0_rx_funcs[] = { 4, };
-+static int mt7622_ir_1_rx_pins[] = { 60, };
-+static int mt7622_ir_1_rx_funcs[] = { 5, };
-+static int mt7622_ir_2_rx_pins[] = { 100, };
-+static int mt7622_ir_2_rx_funcs[] = { 3, };
-+
-+/* MDIO */
-+static int mt7622_mdc_mdio_pins[] = { 23, 24, };
-+static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
-+
-+/* PCIE */
-+static int mt7622_pcie0_0_waken_pins[] = { 14, };
-+static int mt7622_pcie0_0_waken_funcs[] = { 2, };
-+static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
-+static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
-+static int mt7622_pcie0_1_waken_pins[] = { 79, };
-+static int mt7622_pcie0_1_waken_funcs[] = { 4, };
-+static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
-+static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
-+static int mt7622_pcie1_0_waken_pins[] = { 14, };
-+static int mt7622_pcie1_0_waken_funcs[] = { 3, };
-+static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
-+static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
-+
-+static int mt7622_pcie0_pad_perst_pins[] = { 83, };
-+static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
-+static int mt7622_pcie1_pad_perst_pins[] = { 84, };
-+static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
-+
-+/* PMIC bus */
-+static int mt7622_pmic_bus_pins[] = { 71, 72, };
-+static int mt7622_pmic_bus_funcs[] = { 0, 0, };
-+
-+/* Parallel NAND */
-+static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
-+				   48, 49, 50, };
-+static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+				    0, };
-+
-+/* PWM */
-+static int mt7622_pwm_ch1_0_pins[] = { 51, };
-+static int mt7622_pwm_ch1_0_funcs[] = { 3, };
-+static int mt7622_pwm_ch1_1_pins[] = { 73, };
-+static int mt7622_pwm_ch1_1_funcs[] = { 4, };
-+static int mt7622_pwm_ch1_2_pins[] = { 95, };
-+static int mt7622_pwm_ch1_2_funcs[] = { 0, };
-+static int mt7622_pwm_ch2_0_pins[] = { 52, };
-+static int mt7622_pwm_ch2_0_funcs[] = { 3, };
-+static int mt7622_pwm_ch2_1_pins[] = { 74, };
-+static int mt7622_pwm_ch2_1_funcs[] = { 4, };
-+static int mt7622_pwm_ch2_2_pins[] = { 96, };
-+static int mt7622_pwm_ch2_2_funcs[] = { 0, };
-+static int mt7622_pwm_ch3_0_pins[] = { 53, };
-+static int mt7622_pwm_ch3_0_funcs[] = { 3, };
-+static int mt7622_pwm_ch3_1_pins[] = { 75, };
-+static int mt7622_pwm_ch3_1_funcs[] = { 4, };
-+static int mt7622_pwm_ch3_2_pins[] = { 97, };
-+static int mt7622_pwm_ch3_2_funcs[] = { 0, };
-+static int mt7622_pwm_ch4_0_pins[] = { 54, };
-+static int mt7622_pwm_ch4_0_funcs[] = { 3, };
-+static int mt7622_pwm_ch4_1_pins[] = { 67, };
-+static int mt7622_pwm_ch4_1_funcs[] = { 3, };
-+static int mt7622_pwm_ch4_2_pins[] = { 76, };
-+static int mt7622_pwm_ch4_2_funcs[] = { 4, };
-+static int mt7622_pwm_ch4_3_pins[] = { 98, };
-+static int mt7622_pwm_ch4_3_funcs[] = { 0, };
-+static int mt7622_pwm_ch5_0_pins[] = { 68, };
-+static int mt7622_pwm_ch5_0_funcs[] = { 3, };
-+static int mt7622_pwm_ch5_1_pins[] = { 77, };
-+static int mt7622_pwm_ch5_1_funcs[] = { 4, };
-+static int mt7622_pwm_ch5_2_pins[] = { 99, };
-+static int mt7622_pwm_ch5_2_funcs[] = { 0, };
-+static int mt7622_pwm_ch6_0_pins[] = { 69, };
-+static int mt7622_pwm_ch6_0_funcs[] = { 3, };
-+static int mt7622_pwm_ch6_1_pins[] = { 78, };
-+static int mt7622_pwm_ch6_1_funcs[] = { 4, };
-+static int mt7622_pwm_ch6_2_pins[] = { 81, };
-+static int mt7622_pwm_ch6_2_funcs[] = { 4, };
-+static int mt7622_pwm_ch6_3_pins[] = { 100, };
-+static int mt7622_pwm_ch6_3_funcs[] = { 0, };
-+static int mt7622_pwm_ch7_0_pins[] = { 70, };
-+static int mt7622_pwm_ch7_0_funcs[] = { 3, };
-+static int mt7622_pwm_ch7_1_pins[] = { 82, };
-+static int mt7622_pwm_ch7_1_funcs[] = { 4, };
-+static int mt7622_pwm_ch7_2_pins[] = { 101, };
-+static int mt7622_pwm_ch7_2_funcs[] = { 0, };
-+
-+/* SD */
-+static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
-+static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
-+static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+
-+/* Serial NAND */
-+static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
-+static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+
-+/* SPI NOR */
-+static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
-+static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
-+
-+/* SPIC */
-+static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
-+static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
-+static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
-+static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
-+static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
-+static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
-+static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
-+static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
-+static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
-+static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
-+static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
-+static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
-+
-+/* TDM */
-+static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
-+static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
-+static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static int mt7622_tdm_0_out_data_pins[] = { 20, };
-+static int mt7622_tdm_0_out_data_funcs[] = { 3, };
-+static int mt7622_tdm_0_in_data_pins[] = { 21, };
-+static int mt7622_tdm_0_in_data_funcs[] = { 3, };
-+static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
-+static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
-+static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
-+static int mt7622_tdm_1_out_data_pins[] = { 55, };
-+static int mt7622_tdm_1_out_data_funcs[] = { 3, };
-+static int mt7622_tdm_1_in_data_pins[] = { 56, };
-+static int mt7622_tdm_1_in_data_funcs[] = { 3, };
-+
-+/* UART */
-+static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
-+static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
-+static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
-+static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
-+static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
-+static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
-+static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
-+static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
-+static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
-+static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
-+static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
-+static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
-+static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
-+static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
-+static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
-+static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
-+static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
-+static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
-+static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
-+static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
-+static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
-+static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
-+static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
-+static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
-+static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
-+static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
-+static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
-+static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
-+static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
-+static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
-+static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
-+static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
-+static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
-+static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
-+static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
-+static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
-+static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
-+static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
-+static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
-+static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
-+
-+/* Watchdog */
-+static int mt7622_watchdog_pins[] = { 78, };
-+static int mt7622_watchdog_funcs[] = { 0, };
-+
-+/* WLAN LED */
-+static int mt7622_wled_pins[] = { 85, };
-+static int mt7622_wled_funcs[] = { 0, };
-+
-+static const struct group_desc mt7622_groups[] = {
-+	PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
-+	PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
-+	PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
-+	PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
-+	PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
-+	PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
-+	PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
-+	PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
-+	PINCTRL_PIN_GROUP("esw", mt7622_esw),
-+	PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
-+	PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
-+	PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
-+	PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
-+	PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
-+	PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
-+	PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
-+	PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
-+	PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
-+	PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
-+	PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
-+	PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
-+	PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
-+	PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
-+	PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
-+	PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
-+	PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
-+	PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
-+	PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
-+	PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
-+	PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
-+	PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
-+	PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
-+	PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
-+	PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
-+	PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
-+	PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
-+	PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
-+	PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
-+	PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
-+	PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
-+	PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
-+	PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
-+	PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
-+	PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
-+	PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
-+	PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
-+	PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
-+	PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
-+	PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
-+	PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
-+	PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
-+	PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
-+	PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
-+	PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
-+	PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
-+	PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
-+	PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
-+	PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
-+	PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
-+	PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
-+	PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
-+	PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
-+	PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
-+	PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
-+	PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
-+	PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
-+	PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
-+	PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
-+	PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
-+	PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
-+	PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
-+	PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
-+	PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
-+	PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
-+	PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
-+	PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
-+	PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
-+	PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
-+	PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
-+	PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
-+	PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
-+	PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
-+			  mt7622_tdm_0_out_mclk_bclk_ws),
-+	PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
-+			  mt7622_tdm_0_in_mclk_bclk_ws),
-+	PINCTRL_PIN_GROUP("tdm_0_out_data",  mt7622_tdm_0_out_data),
-+	PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
-+	PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
-+			  mt7622_tdm_1_out_mclk_bclk_ws),
-+	PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
-+			  mt7622_tdm_1_in_mclk_bclk_ws),
-+	PINCTRL_PIN_GROUP("tdm_1_out_data",  mt7622_tdm_1_out_data),
-+	PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
-+	PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
-+	PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
-+	PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
-+	PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
-+	PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
-+	PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
-+	PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
-+	PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
-+	PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
-+	PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
-+	PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
-+	PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
-+	PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
-+	PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
-+	PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
-+	PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
-+	PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
-+	PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
-+	PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
-+	PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
-+	PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
-+	PINCTRL_PIN_GROUP("wled", mt7622_wled),
-+};
-+
-+/* Joint those groups owning the same capability in user point of view which
-+ * allows that people tend to use through the device tree.
-+ */
-+static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
-+static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
-+						"esw_p2_p3_p4", "mdc_mdio",
-+						"rgmii_via_gmac1",
-+						"rgmii_via_gmac2",
-+						"rgmii_via_esw", };
-+static const char *mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
-+					   "i2c1_2", "i2c2_0", "i2c2_1",
-+					   "i2c2_2", };
-+static const char *mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
-+					   "i2s_in_mclk_bclk_ws",
-+					   "i2s1_in_data", "i2s2_in_data",
-+					   "i2s3_in_data", "i2s4_in_data",
-+					   "i2s1_out_data", "i2s2_out_data",
-+					   "i2s3_out_data", "i2s4_out_data", };
-+static const char *mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
-+					  "ir_0_rx", "ir_1_rx", "ir_2_rx"};
-+static const char *mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
-+					   "ephy1_led", "ephy2_led",
-+					   "ephy3_led", "ephy4_led",
-+					   "wled", };
-+static const char *mt7622_flash_groups[] = { "par_nand", "snfi", "spi_nor"};
-+static const char *mt7622_pcie_groups[] = { "pcie0_0_waken", "pcie0_0_clkreq",
-+					    "pcie0_1_waken", "pcie0_1_clkreq",
-+					    "pcie1_0_waken", "pcie1_0_clkreq",
-+					    "pcie0_pad_perst",
-+					    "pcie1_pad_perst", };
-+static const char *mt7622_pmic_bus_groups[] = { "pmic_bus", };
-+static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
-+					   "pwm_ch1_2", "pwm_ch2_0",
-+					   "pwm_ch2_1", "pwm_ch2_2",
-+					   "pwm_ch3_0", "pwm_ch3_1",
-+					   "pwm_ch3_2", "pwm_ch4_0",
-+					   "pwm_ch4_1", "pwm_ch4_2",
-+					   "pwm_ch4_3", "pwm_ch5_0",
-+					   "pwm_ch5_1", "pwm_ch5_2",
-+					   "pwm_ch6_0", "pwm_ch6_1",
-+					   "pwm_ch6_2", "pwm_ch6_3",
-+					   "pwm_ch7_0", "pwm_ch7_1",
-+					   "pwm_ch7_2", };
-+static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", };
-+static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0",
-+					    "spic1_1", "spic2_0",
-+					    "spic2_0_wp_hold", };
-+static const char *mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
-+					   "tdm_0_in_mclk_bclk_ws",
-+					   "tdm_0_out_data",
-+					   "tdm_0_in_data",
-+					   "tdm_1_out_mclk_bclk_ws",
-+					   "tdm_1_in_mclk_bclk_ws",
-+					   "tdm_1_out_data",
-+					   "tdm_1_in_data", };
-+
-+static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
-+					    "uart1_0_tx_rx", "uart1_0_rts_cts",
-+					    "uart1_1_tx_rx", "uart1_1_rts_cts",
-+					    "uart2_0_tx_rx", "uart2_0_rts_cts",
-+					    "uart2_1_tx_rx", "uart2_1_rts_cts",
-+					    "uart2_2_tx_rx", "uart2_2_rts_cts",
-+					    "uart2_3_tx_rx",
-+					    "uart3_0_tx_rx",
-+					    "uart3_1_tx_rx", "uart3_1_rts_cts",
-+					    "uart4_0_tx_rx",
-+					    "uart4_1_tx_rx", "uart4_1_rts_cts",
-+					    "uart4_2_tx_rx",
-+					    "uart4_2_rts_cts",};
-+static const char *mt7622_wdt_groups[] = { "watchdog", };
-+
-+static const struct function_desc mt7622_functions[] = {
-+	{"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
-+	{"eth",	mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
-+	{"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
-+	{"i2s",	mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
-+	{"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
-+	{"led",	mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
-+	{"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
-+	{"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
-+	{"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
-+	{"pwm",	mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
-+	{"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
-+	{"spi",	mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
-+	{"tdm",	mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
-+	{"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
-+	{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
-+};
-+
-+static const struct pinconf_generic_params mtk_custom_bindings[] = {
-+	{"mediatek,tdsel",	MTK_PIN_CONFIG_TDSEL,		0},
-+	{"mediatek,rdsel",	MTK_PIN_CONFIG_RDSEL,		0},
-+};
-+
-+#ifdef CONFIG_DEBUG_FS
-+static const struct pin_config_item mtk_conf_items[] = {
-+	PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
-+	PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
-+};
-+#endif
-+
-+static const struct mtk_pin_soc mt7622_data = {
-+	.reg_cal = mt7622_reg_cals,
-+	.pins = mt7622_pins,
-+	.npins = ARRAY_SIZE(mt7622_pins),
-+	.grps = mt7622_groups,
-+	.ngrps = ARRAY_SIZE(mt7622_groups),
-+	.funcs = mt7622_functions,
-+	.nfuncs = ARRAY_SIZE(mt7622_functions),
-+};
-+
-+static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val)
-+{
-+	writel_relaxed(val, pctl->base + reg);
-+}
-+
-+static u32 mtk_r32(struct mtk_pinctrl *pctl, u32 reg)
-+{
-+	return readl_relaxed(pctl->base + reg);
-+}
-+
-+static void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set)
-+{
-+	u32 val;
-+
-+	val = mtk_r32(pctl, reg);
-+	val &= ~mask;
-+	val |= set;
-+	mtk_w32(pctl, reg, val);
-+}
-+
-+static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, int pin,
-+				   const struct mtk_pin_reg_calc *rc,
-+				   struct mtk_pin_field *pfd)
-+{
-+	const struct mtk_pin_field_calc *c, *e;
-+	u32 bits;
-+
-+	c = rc->range;
-+	e = c + rc->nranges;
-+
-+	while (c < e) {
-+		if (pin >= c->s_pin && pin <= c->e_pin)
-+			break;
-+		c++;
-+	}
-+
-+	if (c >= e) {
-+		dev_err(hw->dev, "Out of range for pin = %d\n", pin);
-+		return -EINVAL;
-+	}
-+
-+	/* Caculated bits as the overall offset the pin is located at */
-+	bits = c->s_bit + (pin - c->s_pin) * (c->x_bits);
-+
-+	/* Fill pfd from bits and 32-bit register applied is assumed */
-+	pfd->offset = c->s_addr + c->x_addrs * (bits / 32);
-+	pfd->bitpos = bits % 32;
-+	pfd->mask = (1 << c->x_bits) - 1;
-+
-+	/* pfd->next is used for indicating that bit wrapping-around happens
-+	 * which requires the manipulation for bit 0 starting in the next
-+	 * register to form the complete field read/write.
-+	 */
-+	pfd->next = pfd->bitpos + c->x_bits - 1 > 31 ? c->x_addrs : 0;
-+
-+	return 0;
-+}
-+
-+static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, int pin,
-+				int field, struct mtk_pin_field *pfd)
-+{
-+	const struct mtk_pin_reg_calc *rc;
-+
-+	if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
-+		dev_err(hw->dev, "Invalid Field %d\n", field);
-+		return -EINVAL;
-+	}
-+
-+	if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
-+		rc = &hw->soc->reg_cal[field];
-+	} else {
-+		dev_err(hw->dev, "Undefined range for field %d\n", field);
-+		return -EINVAL;
-+	}
-+
-+	return mtk_hw_pin_field_lookup(hw, pin, rc, pfd);
-+}
-+
-+static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
-+{
-+	*l = 32 - pf->bitpos;
-+	*h = get_count_order(pf->mask) - *l;
-+}
-+
-+static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
-+				     struct mtk_pin_field *pf, int value)
-+{
-+	int nbits_l, nbits_h;
-+
-+	mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
-+
-+	mtk_rmw(hw, pf->offset, pf->mask << pf->bitpos,
-+		(value & pf->mask) << pf->bitpos);
-+
-+	mtk_rmw(hw, pf->offset + pf->next, BIT(nbits_h) - 1,
-+		(value & pf->mask) >> nbits_l);
-+}
-+
-+static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
-+				    struct mtk_pin_field *pf, int *value)
-+{
-+	int nbits_l, nbits_h, h, l;
-+
-+	mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
-+
-+	l  = (mtk_r32(hw, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
-+	h  = (mtk_r32(hw, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
-+
-+	*value = (h << nbits_l) | l;
-+}
-+
-+static int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field,
-+			    int value)
-+{
-+	struct mtk_pin_field pf;
-+	int err;
-+
-+	err = mtk_hw_pin_field_get(hw, pin, field, &pf);
-+	if (err)
-+		return err;
-+
-+	if (!pf.next)
-+		mtk_rmw(hw, pf.offset, pf.mask << pf.bitpos,
-+			(value & pf.mask) << pf.bitpos);
-+	else
-+		mtk_hw_write_cross_field(hw, &pf, value);
-+
-+	return 0;
-+}
-+
-+static int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field,
-+			    int *value)
-+{
-+	struct mtk_pin_field pf;
-+	int err;
-+
-+	err = mtk_hw_pin_field_get(hw, pin, field, &pf);
-+	if (err)
-+		return err;
-+
-+	if (!pf.next)
-+		*value = (mtk_r32(hw, pf.offset) >> pf.bitpos) & pf.mask;
-+	else
-+		mtk_hw_read_cross_field(hw, &pf, value);
-+
-+	return 0;
-+}
-+
-+static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
-+			      unsigned int selector, unsigned int group)
-+{
-+	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
-+	struct function_desc *func;
-+	struct group_desc *grp;
-+	int i;
-+
-+	func = pinmux_generic_get_function(pctldev, selector);
-+	if (!func)
-+		return -EINVAL;
-+
-+	grp = pinctrl_generic_get_group(pctldev, group);
-+	if (!grp)
-+		return -EINVAL;
-+
-+	dev_dbg(pctldev->dev, "enable function %s group %s\n",
-+		func->name, grp->name);
-+
-+	for (i = 0; i < grp->num_pins; i++) {
-+		int *pin_modes = grp->data;
-+
-+		mtk_hw_set_value(hw, grp->pins[i], PINCTRL_PIN_REG_MODE,
-+				 pin_modes[i]);
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
-+					  struct pinctrl_gpio_range *range,
-+					  unsigned int pin)
-+{
-+	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
-+
-+	return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_MODE, MTK_GPIO_MODE);
-+}
-+
-+static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
-+					 struct pinctrl_gpio_range *range,
-+					 unsigned int pin, bool input)
-+{
-+	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
-+
-+	/* hardware would take 0 as input direction */
-+	return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, !input);
-+}
-+
-+static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
-+			   unsigned int pin, unsigned long *config)
-+{
-+	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
-+	u32 param = pinconf_to_config_param(*config);
-+	int val, val2, err, reg, ret = 1;
-+
-+	switch (param) {
-+	case PIN_CONFIG_BIAS_DISABLE:
-+		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PU, &val);
-+		if (err)
-+			return err;
-+
-+		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PD, &val2);
-+		if (err)
-+			return err;
-+
-+		if (val || val2)
-+			return -EINVAL;
-+
-+		break;
-+	case PIN_CONFIG_BIAS_PULL_UP:
-+	case PIN_CONFIG_BIAS_PULL_DOWN:
-+	case PIN_CONFIG_SLEW_RATE:
-+		reg = (param == PIN_CONFIG_BIAS_PULL_UP) ?
-+		      PINCTRL_PIN_REG_PU :
-+		      (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
-+		      PINCTRL_PIN_REG_PD : PINCTRL_PIN_REG_SR;
-+
-+		err = mtk_hw_get_value(hw, pin, reg, &val);
-+		if (err)
-+			return err;
-+
-+		if (!val)
-+			return -EINVAL;
-+
-+		break;
-+	case PIN_CONFIG_INPUT_ENABLE:
-+	case PIN_CONFIG_OUTPUT_ENABLE:
-+		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
-+		if (err)
-+			return -EINVAL;
-+
-+		/* HW takes input mode as zero; output mode as non-zero */
-+		if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
-+		    (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
-+			return -EINVAL;
-+
-+		break;
-+	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
-+		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
-+		if (err)
-+			return err;
-+
-+		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_SMT, &val2);
-+		if (err)
-+			return err;
-+
-+		if (val || !val2)
-+			return -EINVAL;
-+
-+		break;
-+	case PIN_CONFIG_DRIVE_STRENGTH:
-+		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E4, &val);
-+		if (err)
-+			return -EINVAL;
-+
-+		err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E8, &val2);
-+		if (err)
-+			return -EINVAL;
-+
-+		/* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
-+		 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
-+		 */
-+		ret = ((val2 << 1) + val + 1) * 4;
-+
-+		break;
-+	case MTK_PIN_CONFIG_TDSEL:
-+	case MTK_PIN_CONFIG_RDSEL:
-+		reg = (param == MTK_PIN_CONFIG_TDSEL) ?
-+		       PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
-+
-+		err = mtk_hw_get_value(hw, pin, reg, &val);
-+		if (err)
-+			return -EINVAL;
-+
-+		ret = val;
-+
-+		break;
-+	default:
-+		return -ENOTSUPP;
-+	}
-+
-+	*config = pinconf_to_config_packed(param, ret);
-+
-+	return 0;
-+}
-+
-+static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
-+			   unsigned long *configs, unsigned int num_configs)
-+{
-+	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
-+	u32 reg, param, arg;
-+	int cfg, err = 0;
-+
-+	for (cfg = 0; cfg < num_configs; cfg++) {
-+		param = pinconf_to_config_param(configs[cfg]);
-+		arg = pinconf_to_config_argument(configs[cfg]);
-+
-+		switch (param) {
-+		case PIN_CONFIG_BIAS_DISABLE:
-+		case PIN_CONFIG_BIAS_PULL_UP:
-+		case PIN_CONFIG_BIAS_PULL_DOWN:
-+			arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
-+			       (param == PIN_CONFIG_BIAS_PULL_UP) ? 1 : 2;
-+
-+			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PU,
-+					       arg & 1);
-+			if (err)
-+				goto err;
-+
-+			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PD,
-+					       !!(arg & 2));
-+			if (err)
-+				goto err;
-+			break;
-+		case PIN_CONFIG_OUTPUT_ENABLE:
-+			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
-+					       MTK_DISABLE);
-+			if (err)
-+				goto err;
-+		case PIN_CONFIG_INPUT_ENABLE:
-+		case PIN_CONFIG_SLEW_RATE:
-+			reg = (param == PIN_CONFIG_SLEW_RATE) ?
-+			       PINCTRL_PIN_REG_SR : PINCTRL_PIN_REG_DIR;
-+
-+			arg = (param == PIN_CONFIG_INPUT_ENABLE) ? 0 :
-+			      (param == PIN_CONFIG_OUTPUT_ENABLE) ? 1 : arg;
-+			err = mtk_hw_set_value(hw, pin, reg, arg);
-+			if (err)
-+				goto err;
-+
-+			break;
-+		case PIN_CONFIG_OUTPUT:
-+			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
-+					       MTK_OUTPUT);
-+			if (err)
-+				goto err;
-+
-+			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DO,
-+					       arg);
-+			if (err)
-+				goto err;
-+			break;
-+		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
-+			/* arg = 1: Input mode & SMT enable ;
-+			 * arg = 0: Output mode & SMT disable
-+			 */
-+			arg = arg ? 2 : 1;
-+			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
-+					       arg & 1);
-+			if (err)
-+				goto err;
-+
-+			err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
-+					       !!(arg & 2));
-+			if (err)
-+				goto err;
-+			break;
-+		case PIN_CONFIG_DRIVE_STRENGTH:
-+			/* 4mA when (e8, e4) = (0, 0);
-+			 * 8mA when (e8, e4) = (0, 1);
-+			 * 12mA when (e8, e4) = (1, 0);
-+			 * 16mA when (e8, e4) = (1, 1)
-+			 */
-+			if (!(arg % 4) && (arg >= 4 && arg <= 16)) {
-+				arg = arg / 4 - 1;
-+				err = mtk_hw_set_value(hw, pin,
-+						       PINCTRL_PIN_REG_E4,
-+						       arg & 0x1);
-+				if (err)
-+					goto err;
-+
-+				err = mtk_hw_set_value(hw, pin,
-+						       PINCTRL_PIN_REG_E8,
-+						       (arg & 0x2) >> 1);
-+				if (err)
-+					goto err;
-+			} else {
-+				err = -ENOTSUPP;
-+			}
-+			break;
-+		case MTK_PIN_CONFIG_TDSEL:
-+		case MTK_PIN_CONFIG_RDSEL:
-+			reg = (param == MTK_PIN_CONFIG_TDSEL) ?
-+			       PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
-+
-+			err = mtk_hw_set_value(hw, pin, reg, arg);
-+			if (err)
-+				goto err;
-+			break;
-+		default:
-+			err = -ENOTSUPP;
-+		}
-+	}
-+err:
-+	return err;
-+}
-+
-+static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
-+				 unsigned int group, unsigned long *config)
-+{
-+	const unsigned int *pins;
-+	unsigned int i, npins, old = 0;
-+	int ret;
-+
-+	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
-+	if (ret)
-+		return ret;
-+
-+	for (i = 0; i < npins; i++) {
-+		if (mtk_pinconf_get(pctldev, pins[i], config))
-+			return -ENOTSUPP;
-+
-+		/* configs do not match between two pins */
-+		if (i && old != *config)
-+			return -ENOTSUPP;
-+
-+		old = *config;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
-+				 unsigned int group, unsigned long *configs,
-+				 unsigned int num_configs)
-+{
-+	const unsigned int *pins;
-+	unsigned int i, npins;
-+	int ret;
-+
-+	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
-+	if (ret)
-+		return ret;
-+
-+	for (i = 0; i < npins; i++) {
-+		ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct pinctrl_ops mtk_pctlops = {
-+	.get_groups_count = pinctrl_generic_get_group_count,
-+	.get_group_name = pinctrl_generic_get_group_name,
-+	.get_group_pins = pinctrl_generic_get_group_pins,
-+	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
-+	.dt_free_map = pinconf_generic_dt_free_map,
-+};
-+
-+static const struct pinmux_ops mtk_pmxops = {
-+	.get_functions_count = pinmux_generic_get_function_count,
-+	.get_function_name = pinmux_generic_get_function_name,
-+	.get_function_groups = pinmux_generic_get_function_groups,
-+	.set_mux = mtk_pinmux_set_mux,
-+	.gpio_request_enable = mtk_pinmux_gpio_request_enable,
-+	.gpio_set_direction = mtk_pinmux_gpio_set_direction,
-+	.strict = true,
-+};
-+
-+static const struct pinconf_ops mtk_confops = {
-+	.is_generic = true,
-+	.pin_config_get = mtk_pinconf_get,
-+	.pin_config_set = mtk_pinconf_set,
-+	.pin_config_group_get = mtk_pinconf_group_get,
-+	.pin_config_group_set = mtk_pinconf_group_set,
-+	.pin_config_config_dbg_show = pinconf_generic_dump_config,
-+};
-+
-+static struct pinctrl_desc mtk_desc = {
-+	.name = PINCTRL_PINCTRL_DEV,
-+	.pctlops = &mtk_pctlops,
-+	.pmxops = &mtk_pmxops,
-+	.confops = &mtk_confops,
-+	.owner = THIS_MODULE,
-+};
-+
-+static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
-+{
-+	struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
-+	int value;
-+
-+	mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value);
-+
-+	return !!value;
-+}
-+
-+static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
-+{
-+	struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
-+
-+	mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value);
-+}
-+
-+static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
-+{
-+	return pinctrl_gpio_direction_input(chip->base + gpio);
-+}
-+
-+static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
-+				     int value)
-+{
-+	mtk_gpio_set(chip, gpio, value);
-+
-+	return pinctrl_gpio_direction_output(chip->base + gpio);
-+}
-+
-+static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
-+{
-+	struct gpio_chip *chip = &hw->chip;
-+	int ret;
-+
-+	chip->label		= PINCTRL_PINCTRL_DEV;
-+	chip->parent		= hw->dev;
-+	chip->request		= gpiochip_generic_request;
-+	chip->free		= gpiochip_generic_free;
-+	chip->direction_input	= mtk_gpio_direction_input;
-+	chip->direction_output	= mtk_gpio_direction_output;
-+	chip->get		= mtk_gpio_get;
-+	chip->set		= mtk_gpio_set;
-+	chip->base		= -1;
-+	chip->ngpio		= hw->soc->npins;
-+	chip->of_node		= np;
-+	chip->of_gpio_n_cells	= 2;
-+
-+	ret = gpiochip_add_data(chip, hw);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
-+				     chip->ngpio);
-+	if (ret < 0) {
-+		gpiochip_remove(chip);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_build_groups(struct mtk_pinctrl *hw)
-+{
-+	int err, i;
-+
-+	for (i = 0; i < hw->soc->ngrps; i++) {
-+		const struct group_desc *group = hw->soc->grps + i;
-+
-+		err = pinctrl_generic_add_group(hw->pctrl, group->name,
-+						group->pins, group->num_pins,
-+						group->data);
-+		if (err) {
-+			dev_err(hw->dev, "Failed to register group %s\n",
-+				group->name);
-+			return err;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_build_functions(struct mtk_pinctrl *hw)
-+{
-+	int i, err;
-+
-+	for (i = 0; i < hw->soc->nfuncs ; i++) {
-+		const struct function_desc *func = hw->soc->funcs + i;
-+
-+		err = pinmux_generic_add_function(hw->pctrl, func->name,
-+						  func->group_names,
-+						  func->num_group_names,
-+						  func->data);
-+		if (err) {
-+			dev_err(hw->dev, "Failed to register function %s\n",
-+				func->name);
-+			return err;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id mtk_pinctrl_of_match[] = {
-+	{ .compatible = "mediatek,mt7622-pinctrl", .data = &mt7622_data},
-+	{ }
-+};
-+
-+static int mtk_pinctrl_probe(struct platform_device *pdev)
-+{
-+	struct resource *res;
-+	struct mtk_pinctrl *hw;
-+	const struct of_device_id *of_id =
-+		of_match_device(mtk_pinctrl_of_match, &pdev->dev);
-+	int err;
-+
-+	hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
-+	if (!hw)
-+		return -ENOMEM;
-+
-+	hw->soc = of_id->data;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res) {
-+		dev_err(&pdev->dev, "missing IO resource\n");
-+		return -ENXIO;
-+	}
-+
-+	hw->dev = &pdev->dev;
-+	hw->base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(hw->base))
-+		return PTR_ERR(hw->base);
-+
-+	/* Setup pins descriptions per SoC types */
-+	mtk_desc.pins = hw->soc->pins;
-+	mtk_desc.npins = hw->soc->npins;
-+	mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
-+	mtk_desc.custom_params = mtk_custom_bindings;
-+#ifdef CONFIG_DEBUG_FS
-+	mtk_desc.custom_conf_items = mtk_conf_items;
-+#endif
-+
-+	hw->pctrl = devm_pinctrl_register(&pdev->dev, &mtk_desc, hw);
-+	if (IS_ERR(hw->pctrl))
-+		return PTR_ERR(hw->pctrl);
-+
-+	/* Setup groups descriptions per SoC types */
-+	err = mtk_build_groups(hw);
-+	if (err) {
-+		dev_err(&pdev->dev, "Failed to build groups\n");
-+		return 0;
-+	}
-+
-+	/* Setup functions descriptions per SoC types */
-+	err = mtk_build_functions(hw);
-+	if (err) {
-+		dev_err(&pdev->dev, "Failed to build functions\n");
-+		return err;
-+	}
-+
-+	err = mtk_build_gpiochip(hw, pdev->dev.of_node);
-+	if (err) {
-+		dev_err(&pdev->dev, "Failed to add gpio_chip\n");
-+		return err;
-+	}
-+
-+	platform_set_drvdata(pdev, hw);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver mtk_pinctrl_driver = {
-+	.driver = {
-+		.name = "mtk-pinctrl",
-+		.of_match_table = mtk_pinctrl_of_match,
-+	},
-+	.probe = mtk_pinctrl_probe,
-+};
-+
-+static int __init mtk_pinctrl_init(void)
-+{
-+	return platform_driver_register(&mtk_pinctrl_driver);
-+}
-+arch_initcall(mtk_pinctrl_init);

target/linux/mediatek/patches-4.14/0172-clk-mediatek-group-drivers-under-indpendent-menu.patch

@@ -1,223 +0,0 @@
-From 13ee94af58240b75550f413fece707987d563193 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 20 Dec 2017 14:42:58 +0800
-Subject: [PATCH 172/224] clk: mediatek: group drivers under indpendent menu
-
-Getting much MediaTek clock driver have been added to CCF, so it's
-better adding the cleanup for grouping drivers under the independent
-menu to simplify configuration selection. In addition, really trivial
-fixups for typos are added in the same patch.
-
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Stephen Boyd <[email protected]>
----
- drivers/clk/mediatek/Kconfig | 96 +++++++++++++++++++++++---------------------
- 1 file changed, 50 insertions(+), 46 deletions(-)
-
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -1,136 +1,139 @@
- #
--# MediaTek SoC drivers
-+# MediaTek Clock Drivers
- #
-+menu "Clock driver for MediaTek SoC"
-+	depends on ARCH_MEDIATEK || COMPILE_TEST
-+
- config COMMON_CLK_MEDIATEK
- 	bool
- 	---help---
--	  Mediatek SoCs' clock support.
-+	  MediaTek SoCs' clock support.
- 
- config COMMON_CLK_MT2701
--	bool "Clock driver for Mediatek MT2701"
-+	bool "Clock driver for MediaTek MT2701"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
- 	select COMMON_CLK_MEDIATEK
- 	default ARCH_MEDIATEK && ARM
- 	---help---
--	  This driver supports Mediatek MT2701 basic clocks.
-+	  This driver supports MediaTek MT2701 basic clocks.
- 
- config COMMON_CLK_MT2701_MMSYS
--	bool "Clock driver for Mediatek MT2701 mmsys"
-+	bool "Clock driver for MediaTek MT2701 mmsys"
- 	depends on COMMON_CLK_MT2701
- 	---help---
--	  This driver supports Mediatek MT2701 mmsys clocks.
-+	  This driver supports MediaTek MT2701 mmsys clocks.
- 
- config COMMON_CLK_MT2701_IMGSYS
--	bool "Clock driver for Mediatek MT2701 imgsys"
-+	bool "Clock driver for MediaTek MT2701 imgsys"
- 	depends on COMMON_CLK_MT2701
- 	---help---
--	  This driver supports Mediatek MT2701 imgsys clocks.
-+	  This driver supports MediaTek MT2701 imgsys clocks.
- 
- config COMMON_CLK_MT2701_VDECSYS
--	bool "Clock driver for Mediatek MT2701 vdecsys"
-+	bool "Clock driver for MediaTek MT2701 vdecsys"
- 	depends on COMMON_CLK_MT2701
- 	---help---
--	  This driver supports Mediatek MT2701 vdecsys clocks.
-+	  This driver supports MediaTek MT2701 vdecsys clocks.
- 
- config COMMON_CLK_MT2701_HIFSYS
--	bool "Clock driver for Mediatek MT2701 hifsys"
-+	bool "Clock driver for MediaTek MT2701 hifsys"
- 	depends on COMMON_CLK_MT2701
- 	---help---
--	  This driver supports Mediatek MT2701 hifsys clocks.
-+	  This driver supports MediaTek MT2701 hifsys clocks.
- 
- config COMMON_CLK_MT2701_ETHSYS
--	bool "Clock driver for Mediatek MT2701 ethsys"
-+	bool "Clock driver for MediaTek MT2701 ethsys"
- 	depends on COMMON_CLK_MT2701
- 	---help---
--	  This driver supports Mediatek MT2701 ethsys clocks.
-+	  This driver supports MediaTek MT2701 ethsys clocks.
- 
- config COMMON_CLK_MT2701_BDPSYS
--	bool "Clock driver for Mediatek MT2701 bdpsys"
-+	bool "Clock driver for MediaTek MT2701 bdpsys"
- 	depends on COMMON_CLK_MT2701
- 	---help---
--	  This driver supports Mediatek MT2701 bdpsys clocks.
-+	  This driver supports MediaTek MT2701 bdpsys clocks.
- 
- config COMMON_CLK_MT2712
--	bool "Clock driver for Mediatek MT2712"
-+	bool "Clock driver for MediaTek MT2712"
- 	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
- 	select COMMON_CLK_MEDIATEK
- 	default ARCH_MEDIATEK && ARM64
- 	---help---
--	  This driver supports Mediatek MT2712 basic clocks.
-+	  This driver supports MediaTek MT2712 basic clocks.
- 
- config COMMON_CLK_MT2712_BDPSYS
--	bool "Clock driver for Mediatek MT2712 bdpsys"
-+	bool "Clock driver for MediaTek MT2712 bdpsys"
- 	depends on COMMON_CLK_MT2712
- 	---help---
--	  This driver supports Mediatek MT2712 bdpsys clocks.
-+	  This driver supports MediaTek MT2712 bdpsys clocks.
- 
- config COMMON_CLK_MT2712_IMGSYS
--	bool "Clock driver for Mediatek MT2712 imgsys"
-+	bool "Clock driver for MediaTek MT2712 imgsys"
- 	depends on COMMON_CLK_MT2712
- 	---help---
--	  This driver supports Mediatek MT2712 imgsys clocks.
-+	  This driver supports MediaTek MT2712 imgsys clocks.
- 
- config COMMON_CLK_MT2712_JPGDECSYS
--	bool "Clock driver for Mediatek MT2712 jpgdecsys"
-+	bool "Clock driver for MediaTek MT2712 jpgdecsys"
- 	depends on COMMON_CLK_MT2712
- 	---help---
--	  This driver supports Mediatek MT2712 jpgdecsys clocks.
-+	  This driver supports MediaTek MT2712 jpgdecsys clocks.
- 
- config COMMON_CLK_MT2712_MFGCFG
--	bool "Clock driver for Mediatek MT2712 mfgcfg"
-+	bool "Clock driver for MediaTek MT2712 mfgcfg"
- 	depends on COMMON_CLK_MT2712
- 	---help---
--	  This driver supports Mediatek MT2712 mfgcfg clocks.
-+	  This driver supports MediaTek MT2712 mfgcfg clocks.
- 
- config COMMON_CLK_MT2712_MMSYS
--	bool "Clock driver for Mediatek MT2712 mmsys"
-+	bool "Clock driver for MediaTek MT2712 mmsys"
- 	depends on COMMON_CLK_MT2712
- 	---help---
--	  This driver supports Mediatek MT2712 mmsys clocks.
-+	  This driver supports MediaTek MT2712 mmsys clocks.
- 
- config COMMON_CLK_MT2712_VDECSYS
--	bool "Clock driver for Mediatek MT2712 vdecsys"
-+	bool "Clock driver for MediaTek MT2712 vdecsys"
- 	depends on COMMON_CLK_MT2712
- 	---help---
--	  This driver supports Mediatek MT2712 vdecsys clocks.
-+	  This driver supports MediaTek MT2712 vdecsys clocks.
- 
- config COMMON_CLK_MT2712_VENCSYS
--	bool "Clock driver for Mediatek MT2712 vencsys"
-+	bool "Clock driver for MediaTek MT2712 vencsys"
- 	depends on COMMON_CLK_MT2712
- 	---help---
--	  This driver supports Mediatek MT2712 vencsys clocks.
-+	  This driver supports MediaTek MT2712 vencsys clocks.
- 
- config COMMON_CLK_MT6797
--       bool "Clock driver for Mediatek MT6797"
-+       bool "Clock driver for MediaTek MT6797"
-        depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-        select COMMON_CLK_MEDIATEK
-        default ARCH_MEDIATEK && ARM64
-        ---help---
--         This driver supports Mediatek MT6797 basic clocks.
-+         This driver supports MediaTek MT6797 basic clocks.
- 
- config COMMON_CLK_MT6797_MMSYS
--       bool "Clock driver for Mediatek MT6797 mmsys"
-+       bool "Clock driver for MediaTek MT6797 mmsys"
-        depends on COMMON_CLK_MT6797
-        ---help---
--         This driver supports Mediatek MT6797 mmsys clocks.
-+         This driver supports MediaTek MT6797 mmsys clocks.
- 
- config COMMON_CLK_MT6797_IMGSYS
--       bool "Clock driver for Mediatek MT6797 imgsys"
-+       bool "Clock driver for MediaTek MT6797 imgsys"
-        depends on COMMON_CLK_MT6797
-        ---help---
--         This driver supports Mediatek MT6797 imgsys clocks.
-+         This driver supports MediaTek MT6797 imgsys clocks.
- 
- config COMMON_CLK_MT6797_VDECSYS
--       bool "Clock driver for Mediatek MT6797 vdecsys"
-+       bool "Clock driver for MediaTek MT6797 vdecsys"
-        depends on COMMON_CLK_MT6797
-        ---help---
--         This driver supports Mediatek MT6797 vdecsys clocks.
-+         This driver supports MediaTek MT6797 vdecsys clocks.
- 
- config COMMON_CLK_MT6797_VENCSYS
--       bool "Clock driver for Mediatek MT6797 vencsys"
-+       bool "Clock driver for MediaTek MT6797 vencsys"
-        depends on COMMON_CLK_MT6797
-        ---help---
--         This driver supports Mediatek MT6797 vencsys clocks.
-+         This driver supports MediaTek MT6797 vencsys clocks.
- 
- config COMMON_CLK_MT7622
- 	bool "Clock driver for MediaTek MT7622"
-@@ -163,17 +166,18 @@ config COMMON_CLK_MT7622_AUDSYS
- 	  to audio consumers such as I2S and TDM.
- 
- config COMMON_CLK_MT8135
--	bool "Clock driver for Mediatek MT8135"
-+	bool "Clock driver for MediaTek MT8135"
- 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
- 	select COMMON_CLK_MEDIATEK
- 	default ARCH_MEDIATEK && ARM
- 	---help---
--	  This driver supports Mediatek MT8135 clocks.
-+	  This driver supports MediaTek MT8135 clocks.
- 
- config COMMON_CLK_MT8173
--	bool "Clock driver for Mediatek MT8173"
-+	bool "Clock driver for MediaTek MT8173"
- 	depends on ARCH_MEDIATEK || COMPILE_TEST
- 	select COMMON_CLK_MEDIATEK
- 	default ARCH_MEDIATEK
- 	---help---
--	  This driver supports Mediatek MT8173 clocks.
-+	  This driver supports MediaTek MT8173 clocks.
-+endmenu

target/linux/mediatek/patches-4.14/0173-clk-mediatek-fixup-test-building-of-MediaTek-clock-d.patch

@@ -1,27 +0,0 @@
-From 3f963310151f6e630f94acf73ff44493619038ff Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 20 Dec 2017 14:42:59 +0800
-Subject: [PATCH 173/224] clk: mediatek: fixup test-building of MediaTek clock
- drivers
-
-Let the build system looking into the directiory where the clock drivers
-resides for the COMPILE_TEST alternative dependency allows test-building
-the drivers.
-
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: Stephen Boyd <[email protected]>
----
- drivers/clk/Makefile | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/Makefile
-+++ b/drivers/clk/Makefile
-@@ -68,7 +68,7 @@ obj-$(CONFIG_MACH_INGENIC)		+= ingenic/
- obj-$(CONFIG_ARCH_K3)			+= keystone/
- obj-$(CONFIG_ARCH_KEYSTONE)		+= keystone/
- obj-$(CONFIG_MACH_LOONGSON32)		+= loongson1/
--obj-$(CONFIG_ARCH_MEDIATEK)		+= mediatek/
-+obj-y					+= mediatek/
- obj-$(CONFIG_COMMON_CLK_AMLOGIC)	+= meson/
- obj-$(CONFIG_MACH_PIC32)		+= microchip/
- ifeq ($(CONFIG_COMMON_CLK), y)

target/linux/mediatek/patches-4.14/0174-dt-bindings-net-mediatek-add-condition-to-property-m.patch

@@ -1,27 +0,0 @@
-From ee687ebf4708fb9e2a64830cdecd8cf992ef9b2b Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 20 Dec 2017 17:47:05 +0800
-Subject: [PATCH 174/224] dt-bindings: net: mediatek: add condition to property
- mediatek, pctl
-
-The property "mediatek,pctl" is only required for SoCs such as MT2701 and
-MT7623, so adding a few words for stating the condition.
-
-Signed-off-by: Sean Wang <[email protected]>
-Reviewed-by: Rob Herring <[email protected]>
-Signed-off-by: David S. Miller <[email protected]>
----
- Documentation/devicetree/bindings/net/mediatek-net.txt | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/net/mediatek-net.txt
-+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
-@@ -28,7 +28,7 @@ Required properties:
- - mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
- 	which is required for those SoCs equipped with SGMII such as MT7622 SoC.
- - mediatek,pctl: phandle to the syscon node that handles the ports slew rate
--	and driver current
-+	and driver current: only for MT2701 and MT7623 SoC
- 
- Optional properties:
- - interrupt-parent: Should be the phandle for the interrupt controller

target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch

@@ -1,102 +0,0 @@
-From d96cf7e724105dc73f623c2019ab5bc78cef036e Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Wed, 20 Dec 2017 17:47:06 +0800
-Subject: [PATCH 175/224] net: mediatek: remove superfluous pin setup for
- MT7622 SoC
-
-Remove superfluous pin setup to get out of accessing invalid I/O pin
-registers because the way for pin configuring tends to be different from
-various SoCs and thus it should be better being managed and controlled by
-the pinctrl driver which MT7622 already can support.
-
-Signed-off-by: Sean Wang <[email protected]>
-Signed-off-by: David S. Miller <[email protected]>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +++
- 2 files changed, 24 insertions(+), 14 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1977,14 +1977,16 @@ static int mtk_hw_init(struct mtk_eth *e
- 	}
- 	regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
- 
--	/* Set GE2 driving and slew rate */
--	regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
-+	if (eth->pctl) {
-+		/* Set GE2 driving and slew rate */
-+		regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
- 
--	/* set GE2 TDSEL */
--	regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
-+		/* set GE2 TDSEL */
-+		regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
- 
--	/* set GE2 TUNE */
--	regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
-+		/* set GE2 TUNE */
-+		regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
-+	}
- 
- 	/* Set linkdown as the default for each GMAC. Its own MCR would be set
- 	 * up with the more appropriate value when mtk_phy_link_adjust call is
-@@ -2569,11 +2571,13 @@ static int mtk_probe(struct platform_dev
- 		}
- 	}
- 
--	eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
--						    "mediatek,pctl");
--	if (IS_ERR(eth->pctl)) {
--		dev_err(&pdev->dev, "no pctl regmap found\n");
--		return PTR_ERR(eth->pctl);
-+	if (eth->soc->required_pctl) {
-+		eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
-+							    "mediatek,pctl");
-+		if (IS_ERR(eth->pctl)) {
-+			dev_err(&pdev->dev, "no pctl regmap found\n");
-+			return PTR_ERR(eth->pctl);
-+		}
- 	}
- 
- 	for (i = 0; i < 3; i++) {
-@@ -2699,17 +2703,20 @@ static int mtk_remove(struct platform_de
- 
- static const struct mtk_soc_data mt2701_data = {
- 	.caps = MTK_GMAC1_TRGMII,
--	.required_clks = MT7623_CLKS_BITMAP
-+	.required_clks = MT7623_CLKS_BITMAP,
-+	.required_pctl = true,
- };
- 
- static const struct mtk_soc_data mt7622_data = {
- 	.caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
--	.required_clks = MT7622_CLKS_BITMAP
-+	.required_clks = MT7622_CLKS_BITMAP,
-+	.required_pctl = false,
- };
- 
- static const struct mtk_soc_data mt7623_data = {
- 	.caps = MTK_GMAC1_TRGMII,
--	.required_clks = MT7623_CLKS_BITMAP
-+	.required_clks = MT7623_CLKS_BITMAP,
-+	.required_pctl = true,
- };
- 
- const struct of_device_id of_mtk_match[] = {
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -574,10 +574,13 @@ struct mtk_rx_ring {
-  * @caps			Flags shown the extra capability for the SoC
-  * @required_clks		Flags shown the bitmap for required clocks on
-  *				the target SoC
-+ * @required_pctl		A bool value to show whether the SoC requires
-+ *				the extra setup for those pins used by GMAC.
-  */
- struct mtk_soc_data {
- 	u32		caps;
- 	u32		required_clks;
-+	bool		required_pctl;
- };
- 
- /* currently no SoC has more than 2 macs */

target/linux/mediatek/patches-4.14/0176-clk-mediatek-Fix-all-warnings-for-missing-struct-clk.patch

@@ -1,68 +0,0 @@
-From f42f141077a12e28fe33c0033f698afb1402ec20 Mon Sep 17 00:00:00 2001
-From: Sean Wang <[email protected]>
-Date: Mon, 25 Dec 2017 16:03:57 +0800
-Subject: [PATCH 176/224] clk: mediatek: Fix all warnings for missing struct
- clk_onecell_data
-
-Even though the header file linux/clk-provider.h is already being properly
-included in clk-mtk.h, the definition of struct clk_onecell_data still
-must depend on CONFIG_COMMON_CLK defined and thus it's possible that
-below build warnings occur when CONFIG_COMMON_CLK is not being selected.
-
-Therefore, these functions which need struct clk_onecell_data without
-declaring that structure first requires simply declaring that this struct
-exists prior to referencing it in clk-mtk.h
-
-Changes from v1->v2:
-enhance v1 based on two useful solutions Jean Delvare kindly suggested.
-
-All warnings (new ones prefixed by >>):
-
-In file included from drivers/clk/mediatek/reset.c:22:0:
->>drivers/clk/mediatek/clk-mtk.h:44:19: warning: 'struct clk_onecell_data'
-declared inside parameter list will not be visible outside of
-this definition or declaration
-  int num, struct clk_onecell_data *clk_data);
-		  ^~~~~~~~~~~~~~~~
-drivers/clk/mediatek/clk-mtk.h:63:19: warning: 'struct clk_onecell_data'
-declared inside parameter list will not be visible outside of
-this definition or declaration
-  int num, struct clk_onecell_data *clk_data);
-		  ^~~~~~~~~~~~~~~~
-drivers/clk/mediatek/clk-mtk.h:145:10: warning: 'struct clk_onecell_data'
-declared inside parameter list will not be visible outside of
-this definition or declaration
-  struct clk_onecell_data *clk_data);
-	 ^~~~~~~~~~~~~~~~
-drivers/clk/mediatek/clk-mtk.h:164:11: warning: 'struct clk_onecell_data'
-declared inside parameter list will not be visible outside of
-this definition or declaration
-   struct clk_onecell_data *clk_data);
-	  ^~~~~~~~~~~~~~~~
-drivers/clk/mediatek/clk-mtk.h:190:12: warning: 'struct clk_onecell_data'
-declared inside parameter list will not be visible outside of this
-definition or declaration
-    struct clk_onecell_data *clk_data);
-	   ^~~~~~~~~~~~~~~~
-
-Reported-by: kbuild test robot <[email protected]>
-Signed-off-by: Sean Wang <[email protected]>
-Cc: [email protected]
-Cc: Stephen Boyd <[email protected]>
-Cc: Jean Delvare <[email protected]>
-Cc: [email protected]
-Signed-off-by: Stephen Boyd <[email protected]>
----
- drivers/clk/mediatek/clk-mtk.h | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -20,6 +20,7 @@
- #include <linux/clk-provider.h>
- 
- struct clk;
-+struct clk_onecell_data;
- 
- #define MAX_MUX_GATE_BIT	31
- #define INVALID_MUX_GATE_BIT	(MAX_MUX_GATE_BIT + 1)

target/linux/mediatek/patches-4.14/0178-phy-phy-mtk-tphy-make-shared-banks-optional-for-V1-T.patch

@@ -1,30 +0,0 @@
-From d7a38584713b00cf9ae97aed89d5e8fb7e3c1bea Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Thu, 7 Dec 2017 19:53:35 +0800
-Subject: [PATCH 178/224] phy: phy-mtk-tphy: make shared banks optional for V1
- TPHY
-
-V1 TPHY for SATA doesn't have shared banks if it isn't shared
-with PCIe or USB, so make it optional.
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Kishon Vijay Abraham I <[email protected]>
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -1023,9 +1023,10 @@ static int mtk_tphy_probe(struct platfor
- 	tphy->dev = dev;
- 	platform_set_drvdata(pdev, tphy);
- 
--	if (tphy->pdata->version == MTK_PHY_V1) {
-+	sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	/* SATA phy of V1 needn't it if not shared with PCIe or USB */
-+	if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
- 		/* get banks shared by multiple phys */
--		sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 		tphy->sif_base = devm_ioremap_resource(dev, sif_res);
- 		if (IS_ERR(tphy->sif_base)) {
- 			dev_err(dev, "failed to remap sif regs\n");

target/linux/mediatek/patches-4.14/0179-phy-phy-mtk-tphy-use-of_device_get_match_data.patch

@@ -1,51 +0,0 @@
-From 3e53007a55e70d5036a527900befecf9a6316d05 Mon Sep 17 00:00:00 2001
-From: Chunfeng Yun <[email protected]>
-Date: Thu, 28 Dec 2017 16:40:36 +0530
-Subject: [PATCH 179/224] phy: phy-mtk-tphy: use of_device_get_match_data()
-
-reduce the boilerplate code to get the specific data
-
-Signed-off-by: Chunfeng Yun <[email protected]>
-Signed-off-by: Kishon Vijay Abraham I <[email protected]>
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 11 +++++------
- 1 file changed, 5 insertions(+), 6 deletions(-)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -20,6 +20,7 @@
- #include <linux/iopoll.h>
- #include <linux/module.h>
- #include <linux/of_address.h>
-+#include <linux/of_device.h>
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- 
-@@ -995,7 +996,6 @@ MODULE_DEVICE_TABLE(of, mtk_tphy_id_tabl
- 
- static int mtk_tphy_probe(struct platform_device *pdev)
- {
--	const struct of_device_id *match;
- 	struct device *dev = &pdev->dev;
- 	struct device_node *np = dev->of_node;
- 	struct device_node *child_np;
-@@ -1005,15 +1005,14 @@ static int mtk_tphy_probe(struct platfor
- 	struct resource res;
- 	int port, retval;
- 
--	match = of_match_node(mtk_tphy_id_table, pdev->dev.of_node);
--	if (!match)
--		return -EINVAL;
--
- 	tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
- 	if (!tphy)
- 		return -ENOMEM;
- 
--	tphy->pdata = match->data;
-+	tphy->pdata = of_device_get_match_data(dev);
-+	if (!tphy->pdata)
-+		return -EINVAL;
-+
- 	tphy->nphys = of_get_child_count(np);
- 	tphy->phys = devm_kcalloc(dev, tphy->nphys,
- 				       sizeof(*tphy->phys), GFP_KERNEL);

target/linux/mediatek/patches-4.14/0180-ASoC-mediatek-fix-error-handling-in-mt2701_afe_pcm_d.patch

@@ -1,81 +0,0 @@
-From 17508c32dd65649d2617c1c52b32b02bdb54b793 Mon Sep 17 00:00:00 2001
-From: Ryder Lee <[email protected]>
-Date: Tue, 2 Jan 2018 19:47:18 +0800
-Subject: [PATCH 180/224] ASoC: mediatek: fix error handling in
- mt2701_afe_pcm_dev_probe()
-
-Fix unbalanced error handling path which will get incorrect counts
-if probe failed. The .remove() should be adjusted accordingly.
-
-Signed-off-by: Ryder Lee <[email protected]>
-Tested-by: Garlic Tseng <[email protected]>
-Signed-off-by: Mark Brown <[email protected]>
----
- sound/soc/mediatek/mt2701/mt2701-afe-pcm.c | 31 ++++++++++++++----------------
- 1 file changed, 14 insertions(+), 17 deletions(-)
-
---- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
-@@ -1590,12 +1590,16 @@ static int mt2701_afe_pcm_dev_probe(stru
- 	}
- 
- 	platform_set_drvdata(pdev, afe);
--	pm_runtime_enable(&pdev->dev);
--	if (!pm_runtime_enabled(&pdev->dev))
--		goto err_pm_disable;
--	pm_runtime_get_sync(&pdev->dev);
- 
--	ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform);
-+	pm_runtime_enable(dev);
-+	if (!pm_runtime_enabled(dev)) {
-+		ret = mt2701_afe_runtime_resume(dev);
-+		if (ret)
-+			goto err_pm_disable;
-+	}
-+	pm_runtime_get_sync(dev);
-+
-+	ret = snd_soc_register_platform(dev, &mtk_afe_pcm_platform);
- 	if (ret) {
- 		dev_warn(dev, "err_platform\n");
- 		goto err_platform;
-@@ -1610,35 +1614,28 @@ static int mt2701_afe_pcm_dev_probe(stru
- 		goto err_dai_component;
- 	}
- 
--	mt2701_afe_runtime_resume(&pdev->dev);
--
- 	return 0;
- 
- err_dai_component:
--	snd_soc_unregister_component(&pdev->dev);
--
-+	snd_soc_unregister_platform(dev);
- err_platform:
--	snd_soc_unregister_platform(&pdev->dev);
--
-+	pm_runtime_put_sync(dev);
- err_pm_disable:
--	pm_runtime_disable(&pdev->dev);
-+	pm_runtime_disable(dev);
- 
- 	return ret;
- }
- 
- static int mt2701_afe_pcm_dev_remove(struct platform_device *pdev)
- {
--	struct mtk_base_afe *afe = platform_get_drvdata(pdev);
--
-+	pm_runtime_put_sync(&pdev->dev);
- 	pm_runtime_disable(&pdev->dev);
- 	if (!pm_runtime_status_suspended(&pdev->dev))
- 		mt2701_afe_runtime_suspend(&pdev->dev);
--	pm_runtime_put_sync(&pdev->dev);
- 
- 	snd_soc_unregister_component(&pdev->dev);
- 	snd_soc_unregister_platform(&pdev->dev);
--	/* disable afe clock */
--	mt2701_afe_disable_clock(afe);
-+
- 	return 0;
- }
- 

target/linux/mediatek/patches-4.14/0181-ASoC-mediatek-rework-clock-functions-for-MT2701.patch

@@ -1,919 +0,0 @@
-From d038da516563d910dd39930777f431d4c65a56cd Mon Sep 17 00:00:00 2001
-From: Ryder Lee <[email protected]>
-Date: Tue, 2 Jan 2018 19:47:19 +0800
-Subject: [PATCH 181/224] ASoC: mediatek: rework clock functions for MT2701
-
-Reworks clock part to make it more reasonable. The current changes are:
-
-- Replace regmap operations by CCF APIs. Doing so, we just need to handle
-  the element clocks and can also get accurate information via CCF.
-
-- Rename clocks to make them more generic so that the future revisions
-  of the IP can adapt gracefully.
-
-- Regroup 'aud_clks[]' by usage - the basic needs and I2S parts:
-
-  The new code just keep the common clocks in array and let SoC self decide
-  I2S numbers - If future chips have different sets of channels we will
-  add a little more abstract here.
-
-  Moreover, this patch moves I2S clocks to the struct mt2701_i2s_data
-  so that we can easily manage them when calls .prepare() and .shutdown().
-
-Signed-off-by: Ryder Lee <[email protected]>
-Tested-by: Garlic Tseng <[email protected]>
-Signed-off-by: Mark Brown <[email protected]>
----
- sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 518 +++++++---------------
- sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h |  15 +-
- sound/soc/mediatek/mt2701/mt2701-afe-common.h     |  64 +--
- sound/soc/mediatek/mt2701/mt2701-afe-pcm.c        |  45 +-
- 4 files changed, 200 insertions(+), 442 deletions(-)
-
---- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
-@@ -21,442 +21,256 @@
- #include "mt2701-afe-common.h"
- #include "mt2701-afe-clock-ctrl.h"
- 
--static const char *aud_clks[MT2701_CLOCK_NUM] = {
--	[MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
--	[MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel",
--	[MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel",
--	[MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div",
--	[MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div",
--	[MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing",
--	[MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing",
--	[MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel",
--	[MT2701_AUD_APLL_SEL] = "top_apll_sel",
--	[MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M",
--	[MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M",
--	[MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M",
--	[MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M",
--	[MT2701_AUD_AUDPLL] = "top_audpll",
--	[MT2701_AUD_AUDPLL_D4] = "top_audpll_d4",
--	[MT2701_AUD_AUDPLL_D8] = "top_audpll_d8",
--	[MT2701_AUD_AUDPLL_D16] = "top_audpll_d16",
--	[MT2701_AUD_AUDPLL_D24] = "top_audpll_d24",
--	[MT2701_AUD_AUDINTBUS] = "top_audintbus_sel",
--	[MT2701_AUD_CLK_26M] = "clk_26m",
--	[MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4",
--	[MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel",
--	[MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel",
--	[MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel",
--	[MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel",
--	[MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel",
--	[MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel",
--	[MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div",
--	[MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div",
--	[MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div",
--	[MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div",
--	[MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div",
--	[MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div",
--	[MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk",
--	[MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk",
--	[MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk",
--	[MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk",
--	[MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk",
--	[MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk",
--	[MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel",
--	[MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel",
--	[MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4",
--	[MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2",
--	[MT2701_AUD_SYSPLL_D5] = "top_syspll_d5",
-+static const char *const base_clks[] = {
-+	[MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
-+	[MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
-+	[MT2701_AUDSYS_AFE] = "audio_afe_pd",
-+	[MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
-+	[MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
-+	[MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
- };
- 
- int mt2701_init_clock(struct mtk_base_afe *afe)
- {
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
--	int i = 0;
-+	int i;
- 
--	for (i = 0; i < MT2701_CLOCK_NUM; i++) {
--		afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
--		if (IS_ERR(afe_priv->clocks[i])) {
--			dev_warn(afe->dev, "%s devm_clk_get %s fail\n",
--				 __func__, aud_clks[i]);
--			return PTR_ERR(aud_clks[i]);
-+	for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
-+		afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
-+		if (IS_ERR(afe_priv->base_ck[i])) {
-+			dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
-+			return PTR_ERR(afe_priv->base_ck[i]);
- 		}
- 	}
- 
--	return 0;
--}
-+	/* Get I2S related clocks */
-+	for (i = 0; i < MT2701_I2S_NUM; i++) {
-+		struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
-+		char name[13];
-+
-+		snprintf(name, sizeof(name), "i2s%d_src_sel", i);
-+		i2s_path->sel_ck = devm_clk_get(afe->dev, name);
-+		if (IS_ERR(i2s_path->sel_ck)) {
-+			dev_err(afe->dev, "failed to get %s\n", name);
-+			return PTR_ERR(i2s_path->sel_ck);
-+		}
- 
--int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
--{
--	int ret = 0;
-+		snprintf(name, sizeof(name), "i2s%d_src_div", i);
-+		i2s_path->div_ck = devm_clk_get(afe->dev, name);
-+		if (IS_ERR(i2s_path->div_ck)) {
-+			dev_err(afe->dev, "failed to get %s\n", name);
-+			return PTR_ERR(i2s_path->div_ck);
-+		}
- 
--	ret = mt2701_turn_on_a1sys_clock(afe);
--	if (ret) {
--		dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n",
--			__func__, ret);
--		return ret;
--	}
-+		snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
-+		i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
-+		if (IS_ERR(i2s_path->mclk_ck)) {
-+			dev_err(afe->dev, "failed to get %s\n", name);
-+			return PTR_ERR(i2s_path->mclk_ck);
-+		}
- 
--	ret = mt2701_turn_on_a2sys_clock(afe);
--	if (ret) {
--		dev_err(afe->dev, "%s turn_on_a2sys_clock fail %d\n",
--			__func__, ret);
--		mt2701_turn_off_a1sys_clock(afe);
--		return ret;
--	}
-+		snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
-+		i2s_path->hop_ck[I2S_OUT] = devm_clk_get(afe->dev, name);
-+		if (IS_ERR(i2s_path->hop_ck[I2S_OUT])) {
-+			dev_err(afe->dev, "failed to get %s\n", name);
-+			return PTR_ERR(i2s_path->hop_ck[I2S_OUT]);
-+		}
- 
--	ret = mt2701_turn_on_afe_clock(afe);
--	if (ret) {
--		dev_err(afe->dev, "%s turn_on_afe_clock fail %d\n",
--			__func__, ret);
--		mt2701_turn_off_a1sys_clock(afe);
--		mt2701_turn_off_a2sys_clock(afe);
--		return ret;
-+		snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
-+		i2s_path->hop_ck[I2S_IN] = devm_clk_get(afe->dev, name);
-+		if (IS_ERR(i2s_path->hop_ck[I2S_IN])) {
-+			dev_err(afe->dev, "failed to get %s\n", name);
-+			return PTR_ERR(i2s_path->hop_ck[I2S_IN]);
-+		}
-+
-+		snprintf(name, sizeof(name), "asrc%d_out_ck", i);
-+		i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
-+		if (IS_ERR(i2s_path->asrco_ck)) {
-+			dev_err(afe->dev, "failed to get %s\n", name);
-+			return PTR_ERR(i2s_path->asrco_ck);
-+		}
- 	}
- 
--	regmap_update_bits(afe->regmap, ASYS_TOP_CON,
--			   AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
--			   AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
--	regmap_update_bits(afe->regmap, AFE_DAC_CON0,
--			   AFE_DAC_CON0_AFE_ON,
--			   AFE_DAC_CON0_AFE_ON);
--	regmap_write(afe->regmap, PWR2_TOP_CON,
--		     PWR2_TOP_CON_INIT_VAL);
--	regmap_write(afe->regmap, PWR1_ASM_CON1,
--		     PWR1_ASM_CON1_INIT_VAL);
--	regmap_write(afe->regmap, PWR2_ASM_CON1,
--		     PWR2_ASM_CON1_INIT_VAL);
-+	/* Some platforms may support BT path */
-+	afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
-+	if (IS_ERR(afe_priv->mrgif_ck)) {
-+		if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
-+			return -EPROBE_DEFER;
- 
--	return 0;
--}
-+		afe_priv->mrgif_ck = NULL;
-+	}
- 
--void mt2701_afe_disable_clock(struct mtk_base_afe *afe)
--{
--	mt2701_turn_off_afe_clock(afe);
--	mt2701_turn_off_a1sys_clock(afe);
--	mt2701_turn_off_a2sys_clock(afe);
--	regmap_update_bits(afe->regmap, ASYS_TOP_CON,
--			   AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
--	regmap_update_bits(afe->regmap, AFE_DAC_CON0,
--			   AFE_DAC_CON0_AFE_ON, 0);
-+	return 0;
- }
- 
--int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe)
-+int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir)
- {
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
--	int ret = 0;
-+	struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
-+	int ret;
- 
--	/* Set Mux */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
-+	ret = clk_prepare_enable(i2s_path->asrco_ck);
- 	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
--		goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
-+		dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
-+		return ret;
- 	}
- 
--	ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL],
--			     afe_priv->clocks[MT2701_AUD_AUD1PLL_98M]);
-+	ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
- 	if (ret) {
--		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
--			aud_clks[MT2701_AUD_AUD_MUX1_SEL],
--			aud_clks[MT2701_AUD_AUD1PLL_98M], ret);
--		goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
-+		dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
-+		goto err_hop_ck;
- 	}
- 
--	/* Set Divider */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__,
--			aud_clks[MT2701_AUD_AUD_MUX1_DIV],
--			ret);
--		goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
--	}
-+	return 0;
- 
--	ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV],
--			   MT2701_AUD_AUD_MUX1_DIV_RATE);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
--			aud_clks[MT2701_AUD_AUD_MUX1_DIV],
--			MT2701_AUD_AUD_MUX1_DIV_RATE, ret);
--		goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
--	}
-+err_hop_ck:
-+	clk_disable_unprepare(i2s_path->asrco_ck);
- 
--	/* Enable clock gate */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_AUD_48K_TIMING], ret);
--		goto A1SYS_CLK_AUD_48K_ERR;
--	}
-+	return ret;
-+}
- 
--	/* Enable infra audio */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
--		goto A1SYS_CLK_INFRA_ERR;
--	}
-+void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir)
-+{
-+	struct mt2701_afe_private *afe_priv = afe->platform_priv;
-+	struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
- 
--	return 0;
-+	clk_disable_unprepare(i2s_path->hop_ck[dir]);
-+	clk_disable_unprepare(i2s_path->asrco_ck);
-+}
- 
--A1SYS_CLK_INFRA_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
--A1SYS_CLK_AUD_48K_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
--A1SYS_CLK_AUD_MUX1_DIV_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
--A1SYS_CLK_AUD_MUX1_SEL_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
-+int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
-+{
-+	struct mt2701_afe_private *afe_priv = afe->platform_priv;
-+	struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
- 
--	return ret;
-+	return clk_prepare_enable(i2s_path->mclk_ck);
- }
- 
--void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe)
-+void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
- {
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
-+	struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
- 
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
-+	clk_disable_unprepare(i2s_path->mclk_ck);
- }
- 
--int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe)
-+int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
- {
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
--	int ret = 0;
- 
--	/* Set Mux */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
--		goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
--	}
-+	return clk_prepare_enable(afe_priv->mrgif_ck);
-+}
- 
--	ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL],
--			     afe_priv->clocks[MT2701_AUD_AUD2PLL_90M]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
--			aud_clks[MT2701_AUD_AUD_MUX2_SEL],
--			aud_clks[MT2701_AUD_AUD2PLL_90M], ret);
--		goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
--	}
-+void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
-+{
-+	struct mt2701_afe_private *afe_priv = afe->platform_priv;
- 
--	/* Set Divider */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_AUD_MUX2_DIV], ret);
--		goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
--	}
-+	clk_disable_unprepare(afe_priv->mrgif_ck);
-+}
- 
--	ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV],
--			   MT2701_AUD_AUD_MUX2_DIV_RATE);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
--			aud_clks[MT2701_AUD_AUD_MUX2_DIV],
--			MT2701_AUD_AUD_MUX2_DIV_RATE, ret);
--		goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
--	}
-+static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
-+{
-+	struct mt2701_afe_private *afe_priv = afe->platform_priv;
-+	int ret;
- 
--	/* Enable clock gate */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_AUD_44K_TIMING], ret);
--		goto A2SYS_CLK_AUD_44K_ERR;
--	}
-+	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
-+	if (ret)
-+		return ret;
- 
--	/* Enable infra audio */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
--		goto A2SYS_CLK_INFRA_ERR;
--	}
-+	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
-+	if (ret)
-+		goto err_audio_a1sys;
-+
-+	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
-+	if (ret)
-+		goto err_audio_a2sys;
-+
-+	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
-+	if (ret)
-+		goto err_afe_conn;
- 
- 	return 0;
- 
--A2SYS_CLK_INFRA_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
--A2SYS_CLK_AUD_44K_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
--A2SYS_CLK_AUD_MUX2_DIV_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
--A2SYS_CLK_AUD_MUX2_SEL_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
-+err_afe_conn:
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
-+err_audio_a2sys:
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
-+err_audio_a1sys:
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
- 
- 	return ret;
- }
- 
--void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe)
-+static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
- {
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
- 
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
- }
- 
--int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe)
-+int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
- {
--	struct mt2701_afe_private *afe_priv = afe->platform_priv;
- 	int ret;
- 
--	/* enable INFRA_SYS */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-+	/* Enable audio system */
-+	ret = mt2701_afe_enable_audsys(afe);
- 	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
--		goto AFE_AUD_INFRA_ERR;
--	}
--
--	/* Set MT2701_AUD_AUDINTBUS to MT2701_AUD_SYSPLL1_D4 */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_AUDINTBUS], ret);
--		goto AFE_AUD_AUDINTBUS_ERR;
--	}
--
--	ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUDINTBUS],
--			     afe_priv->clocks[MT2701_AUD_SYSPLL1_D4]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
--			aud_clks[MT2701_AUD_AUDINTBUS],
--			aud_clks[MT2701_AUD_SYSPLL1_D4], ret);
--		goto AFE_AUD_AUDINTBUS_ERR;
--	}
--
--	/* Set MT2701_AUD_ASM_H_SEL to MT2701_AUD_UNIVPLL2_D2 */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_ASM_H_SEL], ret);
--		goto AFE_AUD_ASM_H_ERR;
--	}
--
--	ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_H_SEL],
--			     afe_priv->clocks[MT2701_AUD_UNIVPLL2_D2]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
--			aud_clks[MT2701_AUD_ASM_H_SEL],
--			aud_clks[MT2701_AUD_UNIVPLL2_D2], ret);
--		goto AFE_AUD_ASM_H_ERR;
--	}
--
--	/* Set MT2701_AUD_ASM_M_SEL to MT2701_AUD_UNIVPLL2_D4 */
--	ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[MT2701_AUD_ASM_M_SEL], ret);
--		goto AFE_AUD_ASM_M_ERR;
-+		dev_err(afe->dev, "failed to enable audio system %d\n", ret);
-+		return ret;
- 	}
- 
--	ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_M_SEL],
--			     afe_priv->clocks[MT2701_AUD_UNIVPLL2_D4]);
--	if (ret) {
--		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
--			aud_clks[MT2701_AUD_ASM_M_SEL],
--			aud_clks[MT2701_AUD_UNIVPLL2_D4], ret);
--		goto AFE_AUD_ASM_M_ERR;
--	}
-+	regmap_update_bits(afe->regmap, ASYS_TOP_CON,
-+			   AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
-+			   AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
-+	regmap_update_bits(afe->regmap, AFE_DAC_CON0,
-+			   AFE_DAC_CON0_AFE_ON,
-+			   AFE_DAC_CON0_AFE_ON);
- 
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
--			   AUDIO_TOP_CON0_PDN_AFE, 0);
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
--			   AUDIO_TOP_CON0_PDN_APLL_CK, 0);
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--			   AUDIO_TOP_CON4_PDN_A1SYS, 0);
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--			   AUDIO_TOP_CON4_PDN_A2SYS, 0);
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--			   AUDIO_TOP_CON4_PDN_AFE_CONN, 0);
-+	/* Configure ASRC */
-+	regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
-+	regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
- 
- 	return 0;
--
--AFE_AUD_ASM_M_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
--AFE_AUD_ASM_H_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
--AFE_AUD_AUDINTBUS_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
--AFE_AUD_INFRA_ERR:
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
--
--	return ret;
- }
- 
--void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe)
-+int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
- {
--	struct mt2701_afe_private *afe_priv = afe->platform_priv;
-+	regmap_update_bits(afe->regmap, ASYS_TOP_CON,
-+			   AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
-+	regmap_update_bits(afe->regmap, AFE_DAC_CON0,
-+			   AFE_DAC_CON0_AFE_ON, 0);
- 
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
-+	mt2701_afe_disable_audsys(afe);
- 
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
--	clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
--
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
--			   AUDIO_TOP_CON0_PDN_AFE, AUDIO_TOP_CON0_PDN_AFE);
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
--			   AUDIO_TOP_CON0_PDN_APLL_CK,
--			   AUDIO_TOP_CON0_PDN_APLL_CK);
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--			   AUDIO_TOP_CON4_PDN_A1SYS,
--			   AUDIO_TOP_CON4_PDN_A1SYS);
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--			   AUDIO_TOP_CON4_PDN_A2SYS,
--			   AUDIO_TOP_CON4_PDN_A2SYS);
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--			   AUDIO_TOP_CON4_PDN_AFE_CONN,
--			   AUDIO_TOP_CON4_PDN_AFE_CONN);
-+	return 0;
- }
- 
- void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
- 			       int mclk)
- {
--	struct mt2701_afe_private *afe_priv = afe->platform_priv;
-+	struct mt2701_afe_private *priv = afe->platform_priv;
-+	struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
- 	int ret;
--	int aud_src_div_id = MT2701_AUD_AUD_K1_SRC_DIV + id;
--	int aud_src_clk_id = MT2701_AUD_AUD_K1_SRC_SEL + id;
- 
--	/* Set MCLK Kx_SRC_SEL(domain) */
--	ret = clk_prepare_enable(afe_priv->clocks[aud_src_clk_id]);
--	if (ret)
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[aud_src_clk_id], ret);
--
--	if (domain == 0) {
--		ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
--				     afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
--		if (ret)
--			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
--				__func__, aud_clks[aud_src_clk_id],
--				aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
--	} else {
--		ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
--				     afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
--		if (ret)
--			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
--				__func__, aud_clks[aud_src_clk_id],
--				aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
--	}
--	clk_disable_unprepare(afe_priv->clocks[aud_src_clk_id]);
-+	/* Set mclk source */
-+	if (domain == 0)
-+		ret = clk_set_parent(i2s_path->sel_ck,
-+				     priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
-+	else
-+		ret = clk_set_parent(i2s_path->sel_ck,
-+				     priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
- 
--	/* Set MCLK Kx_SRC_DIV(divider) */
--	ret = clk_prepare_enable(afe_priv->clocks[aud_src_div_id]);
- 	if (ret)
--		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
--			__func__, aud_clks[aud_src_div_id], ret);
-+		dev_err(afe->dev, "failed to set domain%d mclk source %d\n",
-+			domain, ret);
- 
--	ret = clk_set_rate(afe_priv->clocks[aud_src_div_id], mclk);
-+	/* Set mclk divider */
-+	ret = clk_set_rate(i2s_path->div_ck, mclk);
- 	if (ret)
--		dev_err(afe->dev, "%s clk_set_rate %s-%d fail %d\n", __func__,
--			aud_clks[aud_src_div_id], mclk, ret);
--	clk_disable_unprepare(afe_priv->clocks[aud_src_div_id]);
-+		dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
- }
- 
- MODULE_DESCRIPTION("MT2701 afe clock control");
---- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
-@@ -21,16 +21,15 @@ struct mtk_base_afe;
- 
- int mt2701_init_clock(struct mtk_base_afe *afe);
- int mt2701_afe_enable_clock(struct mtk_base_afe *afe);
--void mt2701_afe_disable_clock(struct mtk_base_afe *afe);
-+int mt2701_afe_disable_clock(struct mtk_base_afe *afe);
- 
--int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe);
--void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe);
-+int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir);
-+void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir);
-+int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id);
-+void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id);
- 
--int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe);
--void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe);
--
--int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe);
--void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe);
-+int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe);
-+void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe);
- 
- void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
- 			       int mclk);
---- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
-@@ -69,53 +69,14 @@ enum {
- 	MT2701_IRQ_ASYS_END,
- };
- 
--/* 2701 clock def */
--enum audio_system_clock_type {
--	MT2701_AUD_INFRA_SYS_AUDIO,
--	MT2701_AUD_AUD_MUX1_SEL,
--	MT2701_AUD_AUD_MUX2_SEL,
--	MT2701_AUD_AUD_MUX1_DIV,
--	MT2701_AUD_AUD_MUX2_DIV,
--	MT2701_AUD_AUD_48K_TIMING,
--	MT2701_AUD_AUD_44K_TIMING,
--	MT2701_AUD_AUDPLL_MUX_SEL,
--	MT2701_AUD_APLL_SEL,
--	MT2701_AUD_AUD1PLL_98M,
--	MT2701_AUD_AUD2PLL_90M,
--	MT2701_AUD_HADDS2PLL_98M,
--	MT2701_AUD_HADDS2PLL_294M,
--	MT2701_AUD_AUDPLL,
--	MT2701_AUD_AUDPLL_D4,
--	MT2701_AUD_AUDPLL_D8,
--	MT2701_AUD_AUDPLL_D16,
--	MT2701_AUD_AUDPLL_D24,
--	MT2701_AUD_AUDINTBUS,
--	MT2701_AUD_CLK_26M,
--	MT2701_AUD_SYSPLL1_D4,
--	MT2701_AUD_AUD_K1_SRC_SEL,
--	MT2701_AUD_AUD_K2_SRC_SEL,
--	MT2701_AUD_AUD_K3_SRC_SEL,
--	MT2701_AUD_AUD_K4_SRC_SEL,
--	MT2701_AUD_AUD_K5_SRC_SEL,
--	MT2701_AUD_AUD_K6_SRC_SEL,
--	MT2701_AUD_AUD_K1_SRC_DIV,
--	MT2701_AUD_AUD_K2_SRC_DIV,
--	MT2701_AUD_AUD_K3_SRC_DIV,
--	MT2701_AUD_AUD_K4_SRC_DIV,
--	MT2701_AUD_AUD_K5_SRC_DIV,
--	MT2701_AUD_AUD_K6_SRC_DIV,
--	MT2701_AUD_AUD_I2S1_MCLK,
--	MT2701_AUD_AUD_I2S2_MCLK,
--	MT2701_AUD_AUD_I2S3_MCLK,
--	MT2701_AUD_AUD_I2S4_MCLK,
--	MT2701_AUD_AUD_I2S5_MCLK,
--	MT2701_AUD_AUD_I2S6_MCLK,
--	MT2701_AUD_ASM_M_SEL,
--	MT2701_AUD_ASM_H_SEL,
--	MT2701_AUD_UNIVPLL2_D4,
--	MT2701_AUD_UNIVPLL2_D2,
--	MT2701_AUD_SYSPLL_D5,
--	MT2701_CLOCK_NUM
-+enum audio_base_clock {
-+	MT2701_TOP_AUD_MCLK_SRC0,
-+	MT2701_TOP_AUD_MCLK_SRC1,
-+	MT2701_AUDSYS_AFE,
-+	MT2701_AUDSYS_AFE_CONN,
-+	MT2701_AUDSYS_A1SYS,
-+	MT2701_AUDSYS_A2SYS,
-+	MT2701_BASE_CLK_NUM,
- };
- 
- static const unsigned int mt2701_afe_backup_list[] = {
-@@ -144,7 +105,6 @@ struct mtk_base_irq_data;
- 
- struct mt2701_i2s_data {
- 	int i2s_ctrl_reg;
--	int i2s_pwn_shift;
- 	int i2s_asrc_fs_shift;
- 	int i2s_asrc_fs_mask;
- };
-@@ -161,11 +121,17 @@ struct mt2701_i2s_path {
- 	int on[I2S_DIR_NUM];
- 	int occupied[I2S_DIR_NUM];
- 	const struct mt2701_i2s_data *i2s_data[2];
-+	struct clk *hop_ck[I2S_DIR_NUM];
-+	struct clk *sel_ck;
-+	struct clk *div_ck;
-+	struct clk *mclk_ck;
-+	struct clk *asrco_ck;
- };
- 
- struct mt2701_afe_private {
--	struct clk *clocks[MT2701_CLOCK_NUM];
- 	struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM];
-+	struct clk *base_ck[MT2701_BASE_CLK_NUM];
-+	struct clk *mrgif_ck;
- 	bool mrg_enable[MT2701_STREAM_DIR_NUM];
- };
- 
---- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
-@@ -97,21 +97,12 @@ static int mt2701_afe_i2s_startup(struct
- {
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
- 	struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
--	struct mt2701_afe_private *afe_priv = afe->platform_priv;
- 	int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
--	int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
--	int ret = 0;
- 
- 	if (i2s_num < 0)
- 		return i2s_num;
- 
--	/* enable mclk */
--	ret = clk_prepare_enable(afe_priv->clocks[clk_num]);
--	if (ret)
--		dev_err(afe->dev, "Failed to enable mclk for I2S: %d\n",
--			i2s_num);
--
--	return ret;
-+	return mt2701_afe_enable_mclk(afe, i2s_num);
- }
- 
- static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
-@@ -151,9 +142,9 @@ static int mt2701_afe_i2s_path_shutdown(
- 	/* disable i2s */
- 	regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
- 			   ASYS_I2S_CON_I2S_EN, 0);
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--			   1 << i2s_data->i2s_pwn_shift,
--			   1 << i2s_data->i2s_pwn_shift);
-+
-+	mt2701_afe_disable_i2s(afe, i2s_num, stream_dir);
-+
- 	return 0;
- }
- 
-@@ -165,7 +156,6 @@ static void mt2701_afe_i2s_shutdown(stru
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
- 	int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
- 	struct mt2701_i2s_path *i2s_path;
--	int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
- 
- 	if (i2s_num < 0)
- 		return;
-@@ -185,7 +175,7 @@ static void mt2701_afe_i2s_shutdown(stru
- 
- I2S_UNSTART:
- 	/* disable mclk */
--	clk_disable_unprepare(afe_priv->clocks[clk_num]);
-+	mt2701_afe_disable_mclk(afe, i2s_num);
- }
- 
- static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
-@@ -251,9 +241,7 @@ static int mt2701_i2s_path_prepare_enabl
- 			   fs << i2s_data->i2s_asrc_fs_shift);
- 
- 	/* enable i2s */
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--			   1 << i2s_data->i2s_pwn_shift,
--			   0 << i2s_data->i2s_pwn_shift);
-+	mt2701_afe_enable_i2s(afe, i2s_num, stream_dir);
- 
- 	/* reset i2s hw status before enable */
- 	regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
-@@ -339,9 +327,11 @@ static int mt2701_btmrg_startup(struct s
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
- 	struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
-+	int ret;
- 
--	regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--			   AUDIO_TOP_CON4_PDN_MRGIF, 0);
-+	ret = mt2701_enable_btmrg_clk(afe);
-+	if (ret)
-+		return ret;
- 
- 	afe_priv->mrg_enable[substream->stream] = 1;
- 	return 0;
-@@ -406,9 +396,7 @@ static void mt2701_btmrg_shutdown(struct
- 				   AFE_MRGIF_CON_MRG_EN, 0);
- 		regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
- 				   AFE_MRGIF_CON_MRG_I2S_EN, 0);
--		regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
--				   AUDIO_TOP_CON4_PDN_MRGIF,
--				   AUDIO_TOP_CON4_PDN_MRGIF);
-+		mt2701_disable_btmrg_clk(afe);
- 	}
- 	afe_priv->mrg_enable[substream->stream] = 0;
- }
-@@ -1386,14 +1374,12 @@ static const struct mt2701_i2s_data mt27
- 	{
- 		{
- 			.i2s_ctrl_reg = ASYS_I2SO1_CON,
--			.i2s_pwn_shift = 6,
- 			.i2s_asrc_fs_shift = 0,
- 			.i2s_asrc_fs_mask = 0x1f,
- 
- 		},
- 		{
- 			.i2s_ctrl_reg = ASYS_I2SIN1_CON,
--			.i2s_pwn_shift = 0,
- 			.i2s_asrc_fs_shift = 0,
- 			.i2s_asrc_fs_mask = 0x1f,
- 
-@@ -1402,14 +1388,12 @@ static const struct mt2701_i2s_data mt27
- 	{
- 		{
- 			.i2s_ctrl_reg = ASYS_I2SO2_CON,
--			.i2s_pwn_shift = 7,
- 			.i2s_asrc_fs_shift = 5,
- 			.i2s_asrc_fs_mask = 0x1f,
- 
- 		},
- 		{
- 			.i2s_ctrl_reg = ASYS_I2SIN2_CON,
--			.i2s_pwn_shift = 1,
- 			.i2s_asrc_fs_shift = 5,
- 			.i2s_asrc_fs_mask = 0x1f,
- 
-@@ -1418,14 +1402,12 @@ static const struct mt2701_i2s_data mt27
- 	{
- 		{
- 			.i2s_ctrl_reg = ASYS_I2SO3_CON,
--			.i2s_pwn_shift = 8,
- 			.i2s_asrc_fs_shift = 10,
- 			.i2s_asrc_fs_mask = 0x1f,
- 
- 		},
- 		{
- 			.i2s_ctrl_reg = ASYS_I2SIN3_CON,
--			.i2s_pwn_shift = 2,
- 			.i2s_asrc_fs_shift = 10,
- 			.i2s_asrc_fs_mask = 0x1f,
- 
-@@ -1434,14 +1416,12 @@ static const struct mt2701_i2s_data mt27
- 	{
- 		{
- 			.i2s_ctrl_reg = ASYS_I2SO4_CON,
--			.i2s_pwn_shift = 9,
- 			.i2s_asrc_fs_shift = 15,
- 			.i2s_asrc_fs_mask = 0x1f,
- 
- 		},
- 		{
- 			.i2s_ctrl_reg = ASYS_I2SIN4_CON,
--			.i2s_pwn_shift = 3,
- 			.i2s_asrc_fs_shift = 15,
- 			.i2s_asrc_fs_mask = 0x1f,
- 
-@@ -1483,8 +1463,7 @@ static int mt2701_afe_runtime_suspend(st
- {
- 	struct mtk_base_afe *afe = dev_get_drvdata(dev);
- 
--	mt2701_afe_disable_clock(afe);
--	return 0;
-+	return mt2701_afe_disable_clock(afe);
- }
- 
- static int mt2701_afe_runtime_resume(struct device *dev)

target/linux/mediatek/patches-4.14/0182-ASoC-mediatek-cleanup-audio-driver-for-MT2701.patch

@@ -1,428 +0,0 @@
-From 4087c924ec899881951b2170a7bb8888747ec532 Mon Sep 17 00:00:00 2001
-From: Ryder Lee <[email protected]>
-Date: Tue, 2 Jan 2018 19:47:20 +0800
-Subject: [PATCH 182/224] ASoC: mediatek: cleanup audio driver for MT2701
-
-Cleanup unused code such as 'i2s_num' guard, headers, indentation
-and some defines.
-
-Signed-off-by: Ryder Lee <[email protected]>
-Signed-off-by: Mark Brown <[email protected]>
----
- sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 14 +---
- sound/soc/mediatek/mt2701/mt2701-afe-common.h     | 20 +----
- sound/soc/mediatek/mt2701/mt2701-afe-pcm.c        | 94 ++++-------------------
- sound/soc/mediatek/mt2701/mt2701-reg.h            | 41 +---------
- 4 files changed, 24 insertions(+), 145 deletions(-)
-
---- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
-@@ -14,10 +14,6 @@
-  * GNU General Public License for more details.
-  */
- 
--#include <sound/soc.h>
--#include <linux/regmap.h>
--#include <linux/pm_runtime.h>
--
- #include "mt2701-afe-common.h"
- #include "mt2701-afe-clock-ctrl.h"
- 
-@@ -223,8 +219,8 @@ int mt2701_afe_enable_clock(struct mtk_b
- 	}
- 
- 	regmap_update_bits(afe->regmap, ASYS_TOP_CON,
--			   AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
--			   AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
-+			   ASYS_TOP_CON_ASYS_TIMING_ON,
-+			   ASYS_TOP_CON_ASYS_TIMING_ON);
- 	regmap_update_bits(afe->regmap, AFE_DAC_CON0,
- 			   AFE_DAC_CON0_AFE_ON,
- 			   AFE_DAC_CON0_AFE_ON);
-@@ -239,7 +235,7 @@ int mt2701_afe_enable_clock(struct mtk_b
- int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
- {
- 	regmap_update_bits(afe->regmap, ASYS_TOP_CON,
--			   AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
-+			   ASYS_TOP_CON_ASYS_TIMING_ON, 0);
- 	regmap_update_bits(afe->regmap, AFE_DAC_CON0,
- 			   AFE_DAC_CON0_AFE_ON, 0);
- 
-@@ -272,7 +268,3 @@ void mt2701_mclk_configuration(struct mt
- 	if (ret)
- 		dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
- }
--
--MODULE_DESCRIPTION("MT2701 afe clock control");
--MODULE_AUTHOR("Garlic Tseng <[email protected]>");
--MODULE_LICENSE("GPL v2");
---- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
-@@ -16,6 +16,7 @@
- 
- #ifndef _MT_2701_AFE_COMMON_H_
- #define _MT_2701_AFE_COMMON_H_
-+
- #include <sound/soc.h>
- #include <linux/clk.h>
- #include <linux/regmap.h>
-@@ -25,16 +26,7 @@
- #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1)
- #define MT2701_PLL_DOMAIN_0_RATE	98304000
- #define MT2701_PLL_DOMAIN_1_RATE	90316800
--#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2)
--#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2)
--
--enum {
--	MT2701_I2S_1,
--	MT2701_I2S_2,
--	MT2701_I2S_3,
--	MT2701_I2S_4,
--	MT2701_I2S_NUM,
--};
-+#define MT2701_I2S_NUM	4
- 
- enum {
- 	MT2701_MEMIF_DL1,
-@@ -62,8 +54,7 @@ enum {
- };
- 
- enum {
--	MT2701_IRQ_ASYS_START,
--	MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START,
-+	MT2701_IRQ_ASYS_IRQ1,
- 	MT2701_IRQ_ASYS_IRQ2,
- 	MT2701_IRQ_ASYS_IRQ3,
- 	MT2701_IRQ_ASYS_END,
-@@ -100,9 +91,6 @@ static const unsigned int mt2701_afe_bac
- 	AFE_MEMIF_PBUF_SIZE,
- };
- 
--struct snd_pcm_substream;
--struct mtk_base_irq_data;
--
- struct mt2701_i2s_data {
- 	int i2s_ctrl_reg;
- 	int i2s_asrc_fs_shift;
-@@ -120,7 +108,7 @@ struct mt2701_i2s_path {
- 	int mclk_rate;
- 	int on[I2S_DIR_NUM];
- 	int occupied[I2S_DIR_NUM];
--	const struct mt2701_i2s_data *i2s_data[2];
-+	const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM];
- 	struct clk *hop_ck[I2S_DIR_NUM];
- 	struct clk *sel_ck;
- 	struct clk *div_ck;
---- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
-@@ -20,16 +20,12 @@
- #include <linux/of.h>
- #include <linux/of_address.h>
- #include <linux/pm_runtime.h>
--#include <sound/soc.h>
- 
- #include "mt2701-afe-common.h"
--
- #include "mt2701-afe-clock-ctrl.h"
- #include "../common/mtk-afe-platform-driver.h"
- #include "../common/mtk-afe-fe-dai.h"
- 
--#define AFE_IRQ_STATUS_BITS	0xff
--
- static const struct snd_pcm_hardware mt2701_afe_hardware = {
- 	.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
- 		| SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
-@@ -107,21 +103,16 @@ static int mt2701_afe_i2s_startup(struct
- 
- static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
- 					struct snd_soc_dai *dai,
-+					int i2s_num,
- 					int dir_invert)
- {
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
- 	struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
--	int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
--	struct mt2701_i2s_path *i2s_path;
-+	struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
- 	const struct mt2701_i2s_data *i2s_data;
- 	int stream_dir = substream->stream;
- 
--	if (i2s_num < 0)
--		return i2s_num;
--
--	i2s_path = &afe_priv->i2s_path[i2s_num];
--
- 	if (dir_invert)	{
- 		if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
- 			stream_dir = SNDRV_PCM_STREAM_CAPTURE;
-@@ -167,11 +158,11 @@ static void mt2701_afe_i2s_shutdown(stru
- 	else
- 		goto I2S_UNSTART;
- 
--	mt2701_afe_i2s_path_shutdown(substream, dai, 0);
-+	mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 0);
- 
- 	/* need to disable i2s-out path when disable i2s-in */
- 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
--		mt2701_afe_i2s_path_shutdown(substream, dai, 1);
-+		mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 1);
- 
- I2S_UNSTART:
- 	/* disable mclk */
-@@ -180,24 +171,19 @@ I2S_UNSTART:
- 
- static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
- 					  struct snd_soc_dai *dai,
-+					  int i2s_num,
- 					  int dir_invert)
- {
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
- 	struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
--	int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
--	struct mt2701_i2s_path *i2s_path;
-+	struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
- 	const struct mt2701_i2s_data *i2s_data;
- 	struct snd_pcm_runtime * const runtime = substream->runtime;
- 	int reg, fs, w_len = 1; /* now we support bck 64bits only */
- 	int stream_dir = substream->stream;
- 	unsigned int mask = 0, val = 0;
- 
--	if (i2s_num < 0)
--		return i2s_num;
--
--	i2s_path = &afe_priv->i2s_path[i2s_num];
--
- 	if (dir_invert) {
- 		if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
- 			stream_dir = SNDRV_PCM_STREAM_CAPTURE;
-@@ -288,13 +274,13 @@ static int mt2701_afe_i2s_prepare(struct
- 	mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate);
- 
- 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
--		mt2701_i2s_path_prepare_enable(substream, dai, 0);
-+		mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
- 	} else {
- 		/* need to enable i2s-out path when enable i2s-in */
- 		/* prepare for another direction "out" */
--		mt2701_i2s_path_prepare_enable(substream, dai, 1);
-+		mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 1);
- 		/* prepare for "in" */
--		mt2701_i2s_path_prepare_enable(substream, dai, 0);
-+		mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
- 	}
- 
- 	return 0;
-@@ -562,7 +548,6 @@ static const struct snd_soc_dai_ops mt27
- 	.hw_free	= mtk_afe_fe_hw_free,
- 	.prepare	= mtk_afe_fe_prepare,
- 	.trigger	= mtk_afe_fe_trigger,
--
- };
- 
- static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
-@@ -903,31 +888,6 @@ static const struct snd_kcontrol_new mt2
- 				    PWR2_TOP_CON, 19, 1, 0),
- };
- 
--static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc0[] = {
--	SOC_DAPM_SINGLE_AUTODISABLE("Asrc0 out Switch", AUDIO_TOP_CON4, 14, 1,
--				    1),
--};
--
--static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc1[] = {
--	SOC_DAPM_SINGLE_AUTODISABLE("Asrc1 out Switch", AUDIO_TOP_CON4, 15, 1,
--				    1),
--};
--
--static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc2[] = {
--	SOC_DAPM_SINGLE_AUTODISABLE("Asrc2 out Switch", PWR2_TOP_CON, 6, 1,
--				    1),
--};
--
--static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc3[] = {
--	SOC_DAPM_SINGLE_AUTODISABLE("Asrc3 out Switch", PWR2_TOP_CON, 7, 1,
--				    1),
--};
--
--static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc4[] = {
--	SOC_DAPM_SINGLE_AUTODISABLE("Asrc4 out Switch", PWR2_TOP_CON, 8, 1,
--				    1),
--};
--
- static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
- 	/* inter-connections */
- 	SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
-@@ -987,19 +947,6 @@ static const struct snd_soc_dapm_widget
- 	SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
- 			   mt2701_afe_multi_ch_out_i2s3,
- 			   ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
--
--	SND_SOC_DAPM_MIXER("ASRC_O0", SND_SOC_NOPM, 0, 0,
--			   mt2701_afe_multi_ch_out_asrc0,
--			   ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc0)),
--	SND_SOC_DAPM_MIXER("ASRC_O1", SND_SOC_NOPM, 0, 0,
--			   mt2701_afe_multi_ch_out_asrc1,
--			   ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc1)),
--	SND_SOC_DAPM_MIXER("ASRC_O2", SND_SOC_NOPM, 0, 0,
--			   mt2701_afe_multi_ch_out_asrc2,
--			   ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc2)),
--	SND_SOC_DAPM_MIXER("ASRC_O3", SND_SOC_NOPM, 0, 0,
--			   mt2701_afe_multi_ch_out_asrc3,
--			   ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc3)),
- };
- 
- static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
-@@ -1009,7 +956,6 @@ static const struct snd_soc_dapm_route m
- 
- 	{"I2S0 Playback", NULL, "O15"},
- 	{"I2S0 Playback", NULL, "O16"},
--
- 	{"I2S1 Playback", NULL, "O17"},
- 	{"I2S1 Playback", NULL, "O18"},
- 	{"I2S2 Playback", NULL, "O19"},
-@@ -1026,7 +972,6 @@ static const struct snd_soc_dapm_route m
- 
- 	{"I00", NULL, "I2S0 Capture"},
- 	{"I01", NULL, "I2S0 Capture"},
--
- 	{"I02", NULL, "I2S1 Capture"},
- 	{"I03", NULL, "I2S1 Capture"},
- 	/* I02,03 link to UL2, also need to open I2S0 */
-@@ -1034,15 +979,10 @@ static const struct snd_soc_dapm_route m
- 
- 	{"I26", NULL, "BT Capture"},
- 
--	{"ASRC_O0", "Asrc0 out Switch", "DLM"},
--	{"ASRC_O1", "Asrc1 out Switch", "DLM"},
--	{"ASRC_O2", "Asrc2 out Switch", "DLM"},
--	{"ASRC_O3", "Asrc3 out Switch", "DLM"},
--
--	{"I12I13", "Multich I2S0 Out Switch", "ASRC_O0"},
--	{"I14I15", "Multich I2S1 Out Switch", "ASRC_O1"},
--	{"I16I17", "Multich I2S2 Out Switch", "ASRC_O2"},
--	{"I18I19", "Multich I2S3 Out Switch", "ASRC_O3"},
-+	{"I12I13", "Multich I2S0 Out Switch", "DLM"},
-+	{"I14I15", "Multich I2S1 Out Switch", "DLM"},
-+	{"I16I17", "Multich I2S2 Out Switch", "DLM"},
-+	{"I18I19", "Multich I2S3 Out Switch", "DLM"},
- 
- 	{ "I12", NULL, "I12I13" },
- 	{ "I13", NULL, "I12I13" },
-@@ -1067,7 +1007,6 @@ static const struct snd_soc_dapm_route m
- 	{ "O21", "I18 Switch", "I18" },
- 	{ "O22", "I19 Switch", "I19" },
- 	{ "O31", "I35 Switch", "I35" },
--
- };
- 
- static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
-@@ -1484,12 +1423,13 @@ static int mt2701_afe_pcm_dev_probe(stru
- 	afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
- 	if (!afe)
- 		return -ENOMEM;
-+
- 	afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
- 					  GFP_KERNEL);
- 	if (!afe->platform_priv)
- 		return -ENOMEM;
--	afe_priv = afe->platform_priv;
- 
-+	afe_priv = afe->platform_priv;
- 	afe->dev = &pdev->dev;
- 	dev = afe->dev;
- 
-@@ -1524,7 +1464,6 @@ static int mt2701_afe_pcm_dev_probe(stru
- 	afe->memif_size = MT2701_MEMIF_NUM;
- 	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
- 				  GFP_KERNEL);
--
- 	if (!afe->memif)
- 		return -ENOMEM;
- 
-@@ -1537,7 +1476,6 @@ static int mt2701_afe_pcm_dev_probe(stru
- 	afe->irqs_size = MT2701_IRQ_ASYS_END;
- 	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
- 				 GFP_KERNEL);
--
- 	if (!afe->irqs)
- 		return -ENOMEM;
- 
-@@ -1555,7 +1493,6 @@ static int mt2701_afe_pcm_dev_probe(stru
- 	afe->mtk_afe_hardware = &mt2701_afe_hardware;
- 	afe->memif_fs = mt2701_memif_fs;
- 	afe->irq_fs = mt2701_irq_fs;
--
- 	afe->reg_back_up_list = mt2701_afe_backup_list;
- 	afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
- 	afe->runtime_resume = mt2701_afe_runtime_resume;
-@@ -1646,4 +1583,3 @@ module_platform_driver(mt2701_afe_pcm_dr
- MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
- MODULE_AUTHOR("Garlic Tseng <[email protected]>");
- MODULE_LICENSE("GPL v2");
--
---- a/sound/soc/mediatek/mt2701/mt2701-reg.h
-+++ b/sound/soc/mediatek/mt2701/mt2701-reg.h
-@@ -17,17 +17,6 @@
- #ifndef _MT2701_REG_H_
- #define _MT2701_REG_H_
- 
--#include <linux/delay.h>
--#include <linux/module.h>
--#include <linux/of.h>
--#include <linux/of_address.h>
--#include <linux/pm_runtime.h>
--#include <sound/soc.h>
--#include "mt2701-afe-common.h"
--
--/*****************************************************************************
-- *                  R E G I S T E R       D E F I N I T I O N
-- *****************************************************************************/
- #define AUDIO_TOP_CON0 0x0000
- #define AUDIO_TOP_CON4 0x0010
- #define AUDIO_TOP_CON5 0x0014
-@@ -109,18 +98,6 @@
- #define AFE_DAI_BASE 0x1370
- #define AFE_DAI_CUR 0x137c
- 
--/* AUDIO_TOP_CON0 (0x0000) */
--#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON	(0x3 << 0)
--#define AUDIO_TOP_CON0_PDN_AFE		(0x1 << 2)
--#define AUDIO_TOP_CON0_PDN_APLL_CK	(0x1 << 23)
--
--/* AUDIO_TOP_CON4 (0x0010) */
--#define AUDIO_TOP_CON4_I2SO1_PWN	(0x1 << 6)
--#define AUDIO_TOP_CON4_PDN_A1SYS	(0x1 << 21)
--#define AUDIO_TOP_CON4_PDN_A2SYS	(0x1 << 22)
--#define AUDIO_TOP_CON4_PDN_AFE_CONN	(0x1 << 23)
--#define AUDIO_TOP_CON4_PDN_MRGIF	(0x1 << 25)
--
- /* AFE_DAIBT_CON0 (0x001c) */
- #define AFE_DAIBT_CON0_DAIBT_EN		(0x1 << 0)
- #define AFE_DAIBT_CON0_BT_FUNC_EN	(0x1 << 1)
-@@ -137,22 +114,8 @@
- #define AFE_MRGIF_CON_I2S_MODE_MASK	(0xf << 20)
- #define AFE_MRGIF_CON_I2S_MODE_32K	(0x4 << 20)
- 
--/* ASYS_I2SO1_CON (0x061c) */
--#define ASYS_I2SO1_CON_FS		(0x1f << 8)
--#define ASYS_I2SO1_CON_FS_SET(x)	((x) << 8)
--#define ASYS_I2SO1_CON_MULTI_CH		(0x1 << 16)
--#define ASYS_I2SO1_CON_SIDEGEN		(0x1 << 30)
--#define ASYS_I2SO1_CON_I2S_EN		(0x1 << 0)
--/* 0:EIAJ 1:I2S */
--#define ASYS_I2SO1_CON_I2S_MODE		(0x1 << 3)
--#define ASYS_I2SO1_CON_WIDE_MODE	(0x1 << 1)
--#define ASYS_I2SO1_CON_WIDE_MODE_SET(x)	((x) << 1)
--
--/* PWR2_TOP_CON (0x0634) */
--#define PWR2_TOP_CON_INIT_VAL		(0xffe1ffff)
--
--/* ASYS_IRQ_CLR (0x07c0) */
--#define ASYS_IRQ_CLR_ALL		(0xffffffff)
-+/* ASYS_TOP_CON (0x0600) */
-+#define ASYS_TOP_CON_ASYS_TIMING_ON		(0x3 << 0)
- 
- /* PWR2_ASM_CON1 (0x1070) */
- #define PWR2_ASM_CON1_INIT_VAL		(0x492492)

target/linux/mediatek/patches-4.14/0183-ASoC-mediatek-update-clock-related-properties-of-MT2.patch

@@ -1,258 +0,0 @@
-From d5b391bb7208c8a7b6b874c1357d3cd110537167 Mon Sep 17 00:00:00 2001
-From: Ryder Lee <[email protected]>
-Date: Tue, 2 Jan 2018 19:47:21 +0800
-Subject: [PATCH 183/224] ASoC: mediatek: update clock related properties of
- MT2701 AFE
-
-Add 'assigned-clocks*' properties which are used to initialize default
-domain sources of audio system. we could configure different sets of
-input clocks through DTS now. Hence driver no longer cares about that.
-
-Also we change some 'clock-names' to make them more generic so that
-other chips can reuse gracefully.
-
-Signed-off-by: Ryder Lee <[email protected]>
-Signed-off-by: Mark Brown <[email protected]>
----
- .../devicetree/bindings/sound/mt2701-afe-pcm.txt   | 207 +++++++++------------
- 1 file changed, 91 insertions(+), 116 deletions(-)
-
---- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
-+++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
-@@ -6,51 +6,44 @@ Required properties:
- - interrupts: should contain AFE and ASYS interrupts
- - interrupt-names: should be "afe" and "asys"
- - power-domains: should define the power domain
-+- clocks: Must contain an entry for each entry in clock-names
-+  See ../clocks/clock-bindings.txt for details
- - clock-names: should have these clock names:
--		"infra_sys_audio_clk",
- 		"top_audio_mux1_sel",
- 		"top_audio_mux2_sel",
--		"top_audio_mux1_div",
--		"top_audio_mux2_div",
--		"top_audio_48k_timing",
--		"top_audio_44k_timing",
--		"top_audpll_mux_sel",
--		"top_apll_sel",
--		"top_aud1_pll_98M",
--		"top_aud2_pll_90M",
--		"top_hadds2_pll_98M",
--		"top_hadds2_pll_294M",
--		"top_audpll",
--		"top_audpll_d4",
--		"top_audpll_d8",
--		"top_audpll_d16",
--		"top_audpll_d24",
--		"top_audintbus_sel",
--		"clk_26m",
--		"top_syspll1_d4",
--		"top_aud_k1_src_sel",
--		"top_aud_k2_src_sel",
--		"top_aud_k3_src_sel",
--		"top_aud_k4_src_sel",
--		"top_aud_k5_src_sel",
--		"top_aud_k6_src_sel",
--		"top_aud_k1_src_div",
--		"top_aud_k2_src_div",
--		"top_aud_k3_src_div",
--		"top_aud_k4_src_div",
--		"top_aud_k5_src_div",
--		"top_aud_k6_src_div",
--		"top_aud_i2s1_mclk",
--		"top_aud_i2s2_mclk",
--		"top_aud_i2s3_mclk",
--		"top_aud_i2s4_mclk",
--		"top_aud_i2s5_mclk",
--		"top_aud_i2s6_mclk",
--		"top_asm_m_sel",
--		"top_asm_h_sel",
--		"top_univpll2_d4",
--		"top_univpll2_d2",
--		"top_syspll_d5";
-+		"i2s0_src_sel",
-+		"i2s1_src_sel",
-+		"i2s2_src_sel",
-+		"i2s3_src_sel",
-+		"i2s0_src_div",
-+		"i2s1_src_div",
-+		"i2s2_src_div",
-+		"i2s3_src_div",
-+		"i2s0_mclk_en",
-+		"i2s1_mclk_en",
-+		"i2s2_mclk_en",
-+		"i2s3_mclk_en",
-+		"i2so0_hop_ck",
-+		"i2so1_hop_ck",
-+		"i2so2_hop_ck",
-+		"i2so3_hop_ck",
-+		"i2si0_hop_ck",
-+		"i2si1_hop_ck",
-+		"i2si2_hop_ck",
-+		"i2si3_hop_ck",
-+		"asrc0_out_ck",
-+		"asrc1_out_ck",
-+		"asrc2_out_ck",
-+		"asrc3_out_ck",
-+		"audio_afe_pd",
-+		"audio_afe_conn_pd",
-+		"audio_a1sys_pd",
-+		"audio_a2sys_pd",
-+		"audio_mrgif_pd";
-+- assigned-clocks: list of input clocks and dividers for the audio system.
-+		   See ../clocks/clock-bindings.txt for details.
-+- assigned-clocks-parents: parent of input clocks of assigned clocks.
-+- assigned-clock-rates: list of clock frequencies of assigned clocks.
- 
- Example:
- 
-@@ -62,93 +55,75 @@ Example:
- 			     <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
- 		interrupt-names	= "afe", "asys";
- 		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
--		clocks = <&infracfg CLK_INFRA_AUDIO>,
--			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
-+		clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
- 			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
--			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
--			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
--			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
--			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
--			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
--			 <&topckgen CLK_TOP_APLL_SEL>,
--			 <&topckgen CLK_TOP_AUD1PLL_98M>,
--			 <&topckgen CLK_TOP_AUD2PLL_90M>,
--			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
--			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
--			 <&topckgen CLK_TOP_AUDPLL>,
--			 <&topckgen CLK_TOP_AUDPLL_D4>,
--			 <&topckgen CLK_TOP_AUDPLL_D8>,
--			 <&topckgen CLK_TOP_AUDPLL_D16>,
--			 <&topckgen CLK_TOP_AUDPLL_D24>,
--			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
--			 <&clk26m>,
--			 <&topckgen CLK_TOP_SYSPLL1_D4>,
- 			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
- 			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
- 			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
- 			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
--			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
--			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
- 			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
- 			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
- 			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
- 			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
--			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
--			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
- 			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
- 			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
- 			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
- 			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
--			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
--			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
--			 <&topckgen CLK_TOP_ASM_M_SEL>,
--			 <&topckgen CLK_TOP_ASM_H_SEL>,
--			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
--			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
--			 <&topckgen CLK_TOP_SYSPLL_D5>;
-+			 <&audiosys CLK_AUD_I2SO1>,
-+			 <&audiosys CLK_AUD_I2SO2>,
-+			 <&audiosys CLK_AUD_I2SO3>,
-+			 <&audiosys CLK_AUD_I2SO4>,
-+			 <&audiosys CLK_AUD_I2SIN1>,
-+			 <&audiosys CLK_AUD_I2SIN2>,
-+			 <&audiosys CLK_AUD_I2SIN3>,
-+			 <&audiosys CLK_AUD_I2SIN4>,
-+			 <&audiosys CLK_AUD_ASRCO1>,
-+			 <&audiosys CLK_AUD_ASRCO2>,
-+			 <&audiosys CLK_AUD_ASRCO3>,
-+			 <&audiosys CLK_AUD_ASRCO4>,
-+			 <&audiosys CLK_AUD_AFE>,
-+			 <&audiosys CLK_AUD_AFE_CONN>,
-+			 <&audiosys CLK_AUD_A1SYS>,
-+			 <&audiosys CLK_AUD_A2SYS>,
-+			 <&audiosys CLK_AUD_AFE_MRGIF>;
- 
--		clock-names = "infra_sys_audio_clk",
--			      "top_audio_mux1_sel",
-+		clock-names = "top_audio_mux1_sel",
- 			      "top_audio_mux2_sel",
--			      "top_audio_mux1_div",
--			      "top_audio_mux2_div",
--			      "top_audio_48k_timing",
--			      "top_audio_44k_timing",
--			      "top_audpll_mux_sel",
--			      "top_apll_sel",
--			      "top_aud1_pll_98M",
--			      "top_aud2_pll_90M",
--			      "top_hadds2_pll_98M",
--			      "top_hadds2_pll_294M",
--			      "top_audpll",
--			      "top_audpll_d4",
--			      "top_audpll_d8",
--			      "top_audpll_d16",
--			      "top_audpll_d24",
--			      "top_audintbus_sel",
--			      "clk_26m",
--			      "top_syspll1_d4",
--			      "top_aud_k1_src_sel",
--			      "top_aud_k2_src_sel",
--			      "top_aud_k3_src_sel",
--			      "top_aud_k4_src_sel",
--			      "top_aud_k5_src_sel",
--			      "top_aud_k6_src_sel",
--			      "top_aud_k1_src_div",
--			      "top_aud_k2_src_div",
--			      "top_aud_k3_src_div",
--			      "top_aud_k4_src_div",
--			      "top_aud_k5_src_div",
--			      "top_aud_k6_src_div",
--			      "top_aud_i2s1_mclk",
--			      "top_aud_i2s2_mclk",
--			      "top_aud_i2s3_mclk",
--			      "top_aud_i2s4_mclk",
--			      "top_aud_i2s5_mclk",
--			      "top_aud_i2s6_mclk",
--			      "top_asm_m_sel",
--			      "top_asm_h_sel",
--			      "top_univpll2_d4",
--			      "top_univpll2_d2",
--			      "top_syspll_d5";
-+			      "i2s0_src_sel",
-+			      "i2s1_src_sel",
-+			      "i2s2_src_sel",
-+			      "i2s3_src_sel",
-+			      "i2s0_src_div",
-+			      "i2s1_src_div",
-+			      "i2s2_src_div",
-+			      "i2s3_src_div",
-+			      "i2s0_mclk_en",
-+			      "i2s1_mclk_en",
-+			      "i2s2_mclk_en",
-+			      "i2s3_mclk_en",
-+			      "i2so0_hop_ck",
-+			      "i2so1_hop_ck",
-+			      "i2so2_hop_ck",
-+			      "i2so3_hop_ck",
-+			      "i2si0_hop_ck",
-+			      "i2si1_hop_ck",
-+			      "i2si2_hop_ck",
-+			      "i2si3_hop_ck",
-+			      "asrc0_out_ck",
-+			      "asrc1_out_ck",
-+			      "asrc2_out_ck",
-+			      "asrc3_out_ck",
-+			      "audio_afe_pd",
-+			      "audio_afe_conn_pd",
-+			      "audio_a1sys_pd",
-+			      "audio_a2sys_pd",
-+			      "audio_mrgif_pd";
-+
-+		assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
-+				  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
-+				  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
-+				  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
-+		assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
-+					 <&topckgen CLK_TOP_AUD2PLL_90M>;
-+		assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
- 	};

target/linux/mediatek/patches-4.14/0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch

@@ -1,93 +0,0 @@
-From e0e3768b73daae674c69db1f71718894274b7bfc Mon Sep 17 00:00:00 2001
-From: Ryder Lee <[email protected]>
-Date: Thu, 4 Jan 2018 15:44:07 +0800
-Subject: [PATCH 184/224] ASoC: mediatek: add some core clocks for MT2701 AFE
-
-Add three core clocks for MT2701 AFE.
-
-Signed-off-by: Ryder Lee <[email protected]>
-Signed-off-by: Mark Brown <[email protected]>
----
- sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 30 ++++++++++++++++++++++-
- sound/soc/mediatek/mt2701/mt2701-afe-common.h     |  3 +++
- 2 files changed, 32 insertions(+), 1 deletion(-)
-
---- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
-@@ -18,8 +18,11 @@
- #include "mt2701-afe-clock-ctrl.h"
- 
- static const char *const base_clks[] = {
-+	[MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
- 	[MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
- 	[MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
-+	[MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
-+	[MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
- 	[MT2701_AUDSYS_AFE] = "audio_afe_pd",
- 	[MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
- 	[MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
-@@ -169,10 +172,26 @@ static int mt2701_afe_enable_audsys(stru
- 	struct mt2701_afe_private *afe_priv = afe->platform_priv;
- 	int ret;
- 
--	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
-+	/* Enable infra clock gate */
-+	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
- 	if (ret)
- 		return ret;
- 
-+	/* Enable top a1sys clock gate */
-+	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
-+	if (ret)
-+		goto err_a1sys;
-+
-+	/* Enable top a2sys clock gate */
-+	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
-+	if (ret)
-+		goto err_a2sys;
-+
-+	/* Internal clock gates */
-+	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
-+	if (ret)
-+		goto err_afe;
-+
- 	ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
- 	if (ret)
- 		goto err_audio_a1sys;
-@@ -193,6 +212,12 @@ err_audio_a2sys:
- 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
- err_audio_a1sys:
- 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
-+err_afe:
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
-+err_a2sys:
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
-+err_a1sys:
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
- 
- 	return ret;
- }
-@@ -205,6 +230,9 @@ static void mt2701_afe_disable_audsys(st
- 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
- 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
- 	clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
-+	clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
- }
- 
- int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
---- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
-@@ -61,8 +61,11 @@ enum {
- };
- 
- enum audio_base_clock {
-+	MT2701_INFRA_SYS_AUDIO,
- 	MT2701_TOP_AUD_MCLK_SRC0,
- 	MT2701_TOP_AUD_MCLK_SRC1,
-+	MT2701_TOP_AUD_A1SYS,
-+	MT2701_TOP_AUD_A2SYS,
- 	MT2701_AUDSYS_AFE,
- 	MT2701_AUDSYS_AFE_CONN,
- 	MT2701_AUDSYS_A1SYS,

target/linux/mediatek/patches-4.14/0185-ASoC-mediatek-modify-MT2701-AFE-driver-to-adapt-mfd-.patch

@@ -1,128 +0,0 @@
-From 310ca2954c7cce10d716001ff869bc255494e3df Mon Sep 17 00:00:00 2001
-From: Ryder Lee <[email protected]>
-Date: Thu, 4 Jan 2018 15:44:08 +0800
-Subject: [PATCH 185/224] ASoC: mediatek: modify MT2701 AFE driver to adapt mfd
- device
-
-As the new MFD parent is in place, modify MT2701 AFE driver to adapt it.
-
-Signed-off-by: Ryder Lee <[email protected]>
-Signed-off-by: Mark Brown <[email protected]>
----
- sound/soc/mediatek/mt2701/mt2701-afe-pcm.c | 45 +++++++++++++-----------------
- sound/soc/mediatek/mt2701/mt2701-reg.h     |  1 -
- 2 files changed, 20 insertions(+), 26 deletions(-)
-
---- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
-+++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
-@@ -17,6 +17,7 @@
- 
- #include <linux/delay.h>
- #include <linux/module.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
- #include <linux/pm_runtime.h>
-@@ -1368,14 +1369,6 @@ static const struct mt2701_i2s_data mt27
- 	},
- };
- 
--static const struct regmap_config mt2701_afe_regmap_config = {
--	.reg_bits = 32,
--	.reg_stride = 4,
--	.val_bits = 32,
--	.max_register = AFE_END_ADDR,
--	.cache_type = REGCACHE_NONE,
--};
--
- static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
- {
- 	int id;
-@@ -1414,9 +1407,9 @@ static int mt2701_afe_runtime_resume(str
- 
- static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
- {
-+	struct snd_soc_component *component;
- 	struct mtk_base_afe *afe;
- 	struct mt2701_afe_private *afe_priv;
--	struct resource *res;
- 	struct device *dev;
- 	int i, irq_id, ret;
- 
-@@ -1446,17 +1439,11 @@ static int mt2701_afe_pcm_dev_probe(stru
- 		return ret;
- 	}
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--
--	afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
--
--	if (IS_ERR(afe->base_addr))
--		return PTR_ERR(afe->base_addr);
--
--	afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
--		&mt2701_afe_regmap_config);
--	if (IS_ERR(afe->regmap))
--		return PTR_ERR(afe->regmap);
-+	afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
-+	if (!afe->regmap) {
-+		dev_err(dev, "could not get regmap from parent\n");
-+		return -ENODEV;
-+	}
- 
- 	mutex_init(&afe->irq_alloc_lock);
- 
-@@ -1490,6 +1477,12 @@ static int mt2701_afe_pcm_dev_probe(stru
- 			= &mt2701_i2s_data[i][I2S_IN];
- 	}
- 
-+	component = kzalloc(sizeof(*component), GFP_KERNEL);
-+	if (!component)
-+		return -ENOMEM;
-+
-+	component->regmap = afe->regmap;
-+
- 	afe->mtk_afe_hardware = &mt2701_afe_hardware;
- 	afe->memif_fs = mt2701_memif_fs;
- 	afe->irq_fs = mt2701_irq_fs;
-@@ -1502,7 +1495,7 @@ static int mt2701_afe_pcm_dev_probe(stru
- 	ret = mt2701_init_clock(afe);
- 	if (ret) {
- 		dev_err(dev, "init clock error\n");
--		return ret;
-+		goto err_init_clock;
- 	}
- 
- 	platform_set_drvdata(pdev, afe);
-@@ -1521,10 +1514,10 @@ static int mt2701_afe_pcm_dev_probe(stru
- 		goto err_platform;
- 	}
- 
--	ret = snd_soc_register_component(&pdev->dev,
--					 &mt2701_afe_pcm_dai_component,
--					 mt2701_afe_pcm_dais,
--					 ARRAY_SIZE(mt2701_afe_pcm_dais));
-+	ret = snd_soc_add_component(dev, component,
-+				    &mt2701_afe_pcm_dai_component,
-+				    mt2701_afe_pcm_dais,
-+				    ARRAY_SIZE(mt2701_afe_pcm_dais));
- 	if (ret) {
- 		dev_warn(dev, "err_dai_component\n");
- 		goto err_dai_component;
-@@ -1538,6 +1531,8 @@ err_platform:
- 	pm_runtime_put_sync(dev);
- err_pm_disable:
- 	pm_runtime_disable(dev);
-+err_init_clock:
-+	kfree(component);
- 
- 	return ret;
- }
---- a/sound/soc/mediatek/mt2701/mt2701-reg.h
-+++ b/sound/soc/mediatek/mt2701/mt2701-reg.h
-@@ -145,5 +145,4 @@
- #define ASYS_I2S_CON_WIDE_MODE_SET(x)	((x) << 1)
- #define ASYS_I2S_IN_PHASE_FIX		(0x1 << 31)
- 
--#define AFE_END_ADDR 0x15e0
- #endif