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@@ -22,15 +22,16 @@
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- rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
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- rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
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- rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
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- rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
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- rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
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- rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
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+-
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+- rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
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+- rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
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+- rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ /* Default: XO=20MHz , SDM mode */
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+ /* Default: XO=20MHz , SDM mode */
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+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
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+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
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+ rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
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+ rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
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+ rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
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+ rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
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-
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-- rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
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-- rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
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-- rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
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++
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+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
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+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
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+ rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
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+ rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
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+ rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
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+ rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
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@@ -216,6 +217,10 @@
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- rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
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- rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
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- rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
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- rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
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- rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
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- rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
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+-
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+- rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
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+- rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
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+- rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
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+ rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
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+ if (rt2800_clk_is_20mhz(rt2x00dev))
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+ if (rt2800_clk_is_20mhz(rt2x00dev))
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@@ -239,10 +244,7 @@
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+ rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
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+ rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
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+ rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
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+ rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
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+ }
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+ }
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-
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-- rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
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-- rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
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-- rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
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++
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
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+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
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+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
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+ rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
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+ rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
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@@ -286,6 +288,33 @@
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
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+-
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
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+-
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
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+-
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+- /* Initialize RF channel register for DRQFN */
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
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+- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
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@@ -318,16 +347,7 @@
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
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+ }
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+ }
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-
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
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++
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
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+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
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+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
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+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
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@@ -339,13 +359,7 @@
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
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-
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
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++
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
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@@ -353,16 +367,7 @@
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
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+ }
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+ }
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-
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-- /* Initialize RF channel register for DRQFN */
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
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-- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
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++
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+ if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
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+ if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
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+ rt2800_hw_get_chipver(rt2x00dev) == 1) {
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+ rt2800_hw_get_chipver(rt2x00dev) == 1) {
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+ /* Initialize RF channel register for DRQFN */
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+ /* Initialize RF channel register for DRQFN */
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