uboot-mediatek: replace patches with updated versions

Weijie Gao has submitted an updated version of the patchset adding
support for MT7986 and MT7981 to U-Boot. Use that v2 patchset.

Changes of v2:
- Add cpu driver for print_cpuinfo()
- Fix NULL pointer dereference in mtk_image
  (was already fixed in OpenWrt)
- Fix coding style
- Minor changes

https://patchwork.ozlabs.org/project/uboot/list/?series=316148

Signed-off-by: Daniel Golle <[email protected]>

package/boot/uboot-mediatek/patches/002-0000-serial-Replace-CONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch

@@ -0,0 +1,494 @@
+From b62450cf229c50ad2ce819dd02a09726909cc89a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
+Date: Fri, 27 May 2022 22:15:24 +0200
+Subject: [PATCH] serial: Replace CONFIG_DEBUG_UART_BASE by
+ CONFIG_VAL(DEBUG_UART_BASE)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+CONFIG_VAL(DEBUG_UART_BASE) expands to CONFIG_DEBUG_UART_BASE or
+CONFIG_SPL_DEBUG_UART_BASE or CONFIG_TPL_DEBUG_UART_BASE and allows boards
+to set different values for SPL, TPL and U-Boot Proper.
+
+For ns16550 driver this support is there since commit d293759d55cc
+("serial: ns16550: Add support for SPL_DEBUG_UART_BASE").
+
+Signed-off-by: Pali Rohár <[email protected]>
+---
+ arch/arm/mach-uniphier/debug-uart/debug-uart.c | 4 ++--
+ arch/x86/cpu/apollolake/cpu_common.c           | 2 +-
+ board/eets/pdu001/board.c                      | 2 +-
+ drivers/serial/altera_jtag_uart.c              | 2 +-
+ drivers/serial/altera_uart.c                   | 4 ++--
+ drivers/serial/atmel_usart.c                   | 4 ++--
+ drivers/serial/serial_ar933x.c                 | 4 ++--
+ drivers/serial/serial_arc.c                    | 4 ++--
+ drivers/serial/serial_bcm6345.c                | 4 ++--
+ drivers/serial/serial_linflexuart.c            | 4 ++--
+ drivers/serial/serial_meson.c                  | 2 +-
+ drivers/serial/serial_msm_geni.c               | 6 +++---
+ drivers/serial/serial_mt7620.c                 | 4 ++--
+ drivers/serial/serial_mtk.c                    | 4 ++--
+ drivers/serial/serial_mvebu_a3700.c            | 4 ++--
+ drivers/serial/serial_mxc.c                    | 4 ++--
+ drivers/serial/serial_omap.c                   | 4 ++--
+ drivers/serial/serial_pic32.c                  | 4 ++--
+ drivers/serial/serial_pl01x.c                  | 4 ++--
+ drivers/serial/serial_s5p.c                    | 4 ++--
+ drivers/serial/serial_sifive.c                 | 4 ++--
+ drivers/serial/serial_stm32.c                  | 4 ++--
+ drivers/serial/serial_xuartlite.c              | 4 ++--
+ drivers/serial/serial_zynq.c                   | 4 ++--
+ 24 files changed, 45 insertions(+), 45 deletions(-)
+
+--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c
++++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
+@@ -18,7 +18,7 @@
+ 
+ static void _debug_uart_putc(int c)
+ {
+-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
++	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
+ 		;
+@@ -57,7 +57,7 @@ void sg_set_iectrl(unsigned int pin)
+ void _debug_uart_init(void)
+ {
+ #ifdef CONFIG_SPL_BUILD
+-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
++	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	unsigned int divisor;
+ 
+ 	switch (uniphier_get_soc_id()) {
+--- a/arch/x86/cpu/apollolake/cpu_common.c
++++ b/arch/x86/cpu/apollolake/cpu_common.c
+@@ -72,7 +72,7 @@ static void pch_uart_init(void)
+ 	}
+ 
+ #ifdef CONFIG_DEBUG_UART
+-	apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
++	apl_uart_init(PCH_DEV_UART, CONFIG_VAL(DEBUG_UART_BASE));
+ #endif
+ }
+ 
+--- a/board/eets/pdu001/board.c
++++ b/board/eets/pdu001/board.c
+@@ -273,7 +273,7 @@ void board_debug_uart_init(void)
+ 	setup_early_clocks();
+ 
+ 	/* done by pin controller driver if not debugging */
+-	enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
++	enable_uart_pin_mux(CONFIG_VAL(DEBUG_UART_BASE));
+ }
+ #endif
+ 
+--- a/drivers/serial/altera_jtag_uart.c
++++ b/drivers/serial/altera_jtag_uart.c
+@@ -134,7 +134,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct altera_jtaguart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
++	struct altera_jtaguart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (1) {
+ 		u32 st = readl(&regs->control);
+--- a/drivers/serial/altera_uart.c
++++ b/drivers/serial/altera_uart.c
+@@ -123,7 +123,7 @@ U_BOOT_DRIVER(altera_uart) = {
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
++	struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	u32 div;
+ 
+ 	div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1;
+@@ -132,7 +132,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
++	struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (1) {
+ 		u32 st = readl(&regs->status);
+--- a/drivers/serial/atmel_usart.c
++++ b/drivers/serial/atmel_usart.c
+@@ -319,14 +319,14 @@ U_BOOT_DRIVER(serial_atmel) = {
+ #ifdef CONFIG_DEBUG_UART_ATMEL
+ static inline void _debug_uart_init(void)
+ {
+-	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
++	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	_atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+ }
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
++	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
+ 		;
+--- a/drivers/serial/serial_ar933x.c
++++ b/drivers/serial/serial_ar933x.c
+@@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_ar933x) = {
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
++	void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	u32 val, scale, step;
+ 
+ 	/*
+@@ -227,7 +227,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int c)
+ {
+-	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
++	void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	u32 data;
+ 
+ 	do {
+--- a/drivers/serial/serial_arc.c
++++ b/drivers/serial/serial_arc.c
+@@ -137,7 +137,7 @@ U_BOOT_DRIVER(serial_arc) = {
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
++	struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	int arc_console_baud = CONFIG_DEBUG_UART_CLOCK / (CONFIG_BAUDRATE * 4) - 1;
+ 
+ 	writeb(arc_console_baud & 0xff, &regs->baudl);
+@@ -146,7 +146,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int c)
+ {
+-	struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
++	struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (!(readb(&regs->status) & UART_TXEMPTY))
+ 		;
+--- a/drivers/serial/serial_bcm6345.c
++++ b/drivers/serial/serial_bcm6345.c
+@@ -269,7 +269,7 @@ U_BOOT_DRIVER(bcm6345_serial) = {
+ #ifdef CONFIG_DEBUG_UART_BCM6345
+ static inline void _debug_uart_init(void)
+ {
+-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
++	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+ }
+@@ -285,7 +285,7 @@ static inline void wait_xfered(void __io
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
++	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	wait_xfered(base);
+ 	writel(ch, base + UART_FIFO_REG);
+--- a/drivers/serial/serial_linflexuart.c
++++ b/drivers/serial/serial_linflexuart.c
+@@ -201,14 +201,14 @@ U_BOOT_DRIVER(serial_linflex) = {
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
++	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	linflex_serial_init_internal(base);
+ }
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
++	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	/* XXX: Is this OK? Should this use the non-DM version? */
+ 	_linflex_serial_putc(base, ch);
+--- a/drivers/serial/serial_meson.c
++++ b/drivers/serial/serial_meson.c
+@@ -182,7 +182,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE;
++	struct meson_uart *regs = (struct meson_uart *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (readl(&regs->status) & AML_UART_TX_FULL)
+ 		;
+--- a/drivers/serial/serial_msm_geni.c
++++ b/drivers/serial/serial_msm_geni.c
+@@ -569,7 +569,7 @@ U_BOOT_DRIVER(serial_msm_geni) = {
+ #ifdef CONFIG_DEBUG_UART_MSM_GENI
+ 
+ static struct msm_serial_data init_serial_data = {
+-	.base = CONFIG_DEBUG_UART_BASE
++	.base = CONFIG_VAL(DEBUG_UART_BASE)
+ };
+ 
+ /* Serial dumb device, to reuse driver code */
+@@ -587,7 +587,7 @@ static struct udevice init_dev = {
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	phys_addr_t base = CONFIG_DEBUG_UART_BASE;
++	phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	geni_serial_init(&init_dev);
+ 	geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);
+@@ -596,7 +596,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	phys_addr_t base = CONFIG_DEBUG_UART_BASE;
++	phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG);
+ 	qcom_geni_serial_setup_tx(base, 1);
+--- a/drivers/serial/serial_mt7620.c
++++ b/drivers/serial/serial_mt7620.c
+@@ -220,7 +220,7 @@ static inline void _debug_uart_init(void
+ {
+ 	struct mt7620_serial_plat plat;
+ 
+-	plat.regs = (void *)CONFIG_DEBUG_UART_BASE;
++	plat.regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	plat.clock = CONFIG_DEBUG_UART_CLOCK;
+ 
+ 	writel(0, &plat.regs->ier);
+@@ -233,7 +233,7 @@ static inline void _debug_uart_init(void
+ static inline void _debug_uart_putc(int ch)
+ {
+ 	struct mt7620_serial_regs __iomem *regs =
+-		(void *)CONFIG_DEBUG_UART_BASE;
++		(void *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (!(readl(&regs->lsr) & UART_LSR_THRE))
+ 		;
+--- a/drivers/serial/serial_mtk.c
++++ b/drivers/serial/serial_mtk.c
+@@ -426,7 +426,7 @@ static inline void _debug_uart_init(void
+ {
+ 	struct mtk_serial_priv priv;
+ 
+-	priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
++	priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
+ 	priv.clock = CONFIG_DEBUG_UART_CLOCK;
+ 
+ 	writel(0, &priv.regs->ier);
+@@ -439,7 +439,7 @@ static inline void _debug_uart_init(void
+ static inline void _debug_uart_putc(int ch)
+ {
+ 	struct mtk_serial_regs __iomem *regs =
+-		(void *) CONFIG_DEBUG_UART_BASE;
++		(void *) CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (!(readl(&regs->lsr) & UART_LSR_THRE))
+ 		;
+--- a/drivers/serial/serial_mvebu_a3700.c
++++ b/drivers/serial/serial_mvebu_a3700.c
+@@ -321,7 +321,7 @@ U_BOOT_DRIVER(serial_mvebu) = {
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
++	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	u32 parent_rate, divider;
+ 
+ 	/* reset FIFOs */
+@@ -349,7 +349,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
++	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
+ 		;
+--- a/drivers/serial/serial_mxc.c
++++ b/drivers/serial/serial_mxc.c
+@@ -372,7 +372,7 @@ U_BOOT_DRIVER(serial_mxc) = {
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
++	struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	_mxc_serial_init(base, false);
+ 	_mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
+@@ -381,7 +381,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
++	struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (!(readl(&base->ts) & UTS_TXEMPTY))
+ 		WATCHDOG_RESET();
+--- a/drivers/serial/serial_omap.c
++++ b/drivers/serial/serial_omap.c
+@@ -66,7 +66,7 @@ static inline int serial_in_shift(void *
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
++	struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	int baud_divisor;
+ 
+ 	baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
+@@ -85,7 +85,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
++	struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
+ 		;
+--- a/drivers/serial/serial_pic32.c
++++ b/drivers/serial/serial_pic32.c
+@@ -187,14 +187,14 @@ U_BOOT_DRIVER(pic32_serial) = {
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
++	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+ }
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR);
++	writel(ch, CONFIG_VAL(DEBUG_UART_BASE) + U_TXR);
+ }
+ 
+ DEBUG_UART_FUNCS
+--- a/drivers/serial/serial_pl01x.c
++++ b/drivers/serial/serial_pl01x.c
+@@ -403,7 +403,7 @@ U_BOOT_DRIVER(serial_pl01x) = {
+ static void _debug_uart_init(void)
+ {
+ #ifndef CONFIG_DEBUG_UART_SKIP_INIT
+-	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
++	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	enum pl01x_type type;
+ 
+ 	if (IS_ENABLED(CONFIG_DEBUG_UART_PL011))
+@@ -419,7 +419,7 @@ static void _debug_uart_init(void)
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
++	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (pl01x_putc(regs, ch) == -EAGAIN)
+ 		;
+--- a/drivers/serial/serial_s5p.c
++++ b/drivers/serial/serial_s5p.c
+@@ -276,7 +276,7 @@ static inline void _debug_uart_init(void
+ 	if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT))
+ 		return;
+ 
+-	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
++	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	s5p_serial_init(uart);
+ #if CONFIG_IS_ENABLED(ARCH_APPLE)
+@@ -288,7 +288,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
++	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ #if CONFIG_IS_ENABLED(ARCH_APPLE)
+ 	while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL);
+--- a/drivers/serial/serial_sifive.c
++++ b/drivers/serial/serial_sifive.c
+@@ -212,7 +212,7 @@ U_BOOT_DRIVER(serial_sifive) = {
+ static inline void _debug_uart_init(void)
+ {
+ 	struct uart_sifive *regs =
+-			(struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
++			(struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	_sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
+ 			      CONFIG_BAUDRATE);
+@@ -222,7 +222,7 @@ static inline void _debug_uart_init(void
+ static inline void _debug_uart_putc(int ch)
+ {
+ 	struct uart_sifive *regs =
+-			(struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
++			(struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (_sifive_serial_putc(regs, ch) == -EAGAIN)
+ 		WATCHDOG_RESET();
+--- a/drivers/serial/serial_stm32.c
++++ b/drivers/serial/serial_stm32.c
+@@ -270,7 +270,7 @@ static inline struct stm32_uart_info *_d
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
++	fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
+ 	struct stm32_uart_info *uart_info = _debug_uart_info();
+ 
+ 	_stm32_serial_init(base, uart_info);
+@@ -281,7 +281,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int c)
+ {
+-	fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
++	fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
+ 	struct stm32_uart_info *uart_info = _debug_uart_info();
+ 
+ 	while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
+--- a/drivers/serial/serial_xuartlite.c
++++ b/drivers/serial/serial_xuartlite.c
+@@ -143,7 +143,7 @@ U_BOOT_DRIVER(serial_uartlite) = {
+ 
+ static inline void _debug_uart_init(void)
+ {
+-	struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
++	struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE);
+ 	int ret;
+ 
+ 	uart_out32(&regs->control, 0);
+@@ -159,7 +159,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
++	struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
+ 		;
+--- a/drivers/serial/serial_zynq.c
++++ b/drivers/serial/serial_zynq.c
+@@ -295,7 +295,7 @@ U_BOOT_DRIVER(serial_zynq) = {
+ #ifdef CONFIG_DEBUG_UART_ZYNQ
+ static inline void _debug_uart_init(void)
+ {
+-	struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
++	struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	_uart_zynq_serial_init(regs);
+ 	_uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
+@@ -304,7 +304,7 @@ static inline void _debug_uart_init(void
+ 
+ static inline void _debug_uart_putc(int ch)
+ {
+-	struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
++	struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
+ 
+ 	while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
+ 		WATCHDOG_RESET();

package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch

@@ -1,7 +1,7 @@
-From a299de45833df13d4ec28092201ea5fec0ba24fe Mon Sep 17 00:00:00 2001
+From 13d81db4723241e33316d7d134e4d279116e3158 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 15:17:58 +0800
-Subject: [PATCH 01/31] arm: mediatek: add support for MediaTek MT7986 SoC
+Date: Wed, 31 Aug 2022 19:00:17 +0800
+Subject: [PATCH 01/32] arm: mediatek: add support for MediaTek MT7986 SoC
 
 This patch adds basic support for MediaTek MT7986 SoC.
 This include the file that will initialize the SoC after boot and its
@@ -10,11 +10,11 @@ device tree.
 Signed-off-by: Weijie Gao <[email protected]>
 ---
  arch/arm/dts/mt7986-u-boot.dtsi               |  33 ++
- arch/arm/dts/mt7986.dtsi                      | 341 ++++++++++++++++++
- arch/arm/mach-mediatek/Kconfig                |  11 +
+ arch/arm/dts/mt7986.dtsi                      | 346 ++++++++++++++++++
+ arch/arm/mach-mediatek/Kconfig                |  12 +
  arch/arm/mach-mediatek/Makefile               |   1 +
  arch/arm/mach-mediatek/mt7986/Makefile        |   4 +
- arch/arm/mach-mediatek/mt7986/init.c          |  51 +++
+ arch/arm/mach-mediatek/mt7986/init.c          |  45 +++
  arch/arm/mach-mediatek/mt7986/lowlevel_init.S |  32 ++
  7 files changed, 473 insertions(+)
  create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi
@@ -61,7 +61,7 @@ Signed-off-by: Weijie Gao <[email protected]>
 +};
 --- /dev/null
 +++ b/arch/arm/dts/mt7986.dtsi
-@@ -0,0 +1,341 @@
+@@ -0,0 +1,346 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2022 MediaTek Inc.
@@ -118,6 +118,11 @@ Signed-off-by: Weijie Gao <[email protected]>
 +		u-boot,dm-pre-reloc;
 +	};
 +
++	hwver: hwver {
++		compatible = "mediatek,hwver";
++		reg = <0x8000000 0x1000>;
++	};
++
 +	timer {
 +		compatible = "arm,armv8-timer";
 +		interrupt-parent = <&gic>;
@@ -405,13 +410,14 @@ Signed-off-by: Weijie Gao <[email protected]>
 +};
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
-@@ -40,6 +40,14 @@ config TARGET_MT7629
+@@ -40,6 +40,15 @@ config TARGET_MT7629
  	  including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
  	  switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
  
 +config TARGET_MT7986
 +	bool "MediaTek MT7986 SoC"
 +	select ARM64
++	select CPU
 +	help
 +	  The MediaTek MT7986 is a ARM64-based SoC with a quad-core Cortex-A53.
 +	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
@@ -420,7 +426,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  config TARGET_MT8183
  	bool "MediaTek MT8183 SoC"
  	select ARM64
-@@ -84,6 +92,7 @@ config SYS_BOARD
+@@ -84,6 +93,7 @@ config SYS_BOARD
  	default "mt7622" if TARGET_MT7622
  	default "mt7623" if TARGET_MT7623
  	default "mt7629" if TARGET_MT7629
@@ -428,7 +434,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  	default "mt8183" if TARGET_MT8183
  	default "mt8512" if TARGET_MT8512
  	default "mt8516" if TARGET_MT8516
-@@ -99,6 +108,7 @@ config SYS_CONFIG_NAME
+@@ -99,6 +109,7 @@ config SYS_CONFIG_NAME
  	default "mt7622" if TARGET_MT7622
  	default "mt7623" if TARGET_MT7623
  	default "mt7629" if TARGET_MT7629
@@ -436,7 +442,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  	default "mt8183" if TARGET_MT8183
  	default "mt8512" if TARGET_MT8512
  	default "mt8516" if TARGET_MT8516
-@@ -113,6 +123,7 @@ config MTK_BROM_HEADER_INFO
+@@ -113,6 +124,7 @@ config MTK_BROM_HEADER_INFO
  	string
  	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
  	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
@@ -463,7 +469,7 @@ Signed-off-by: Weijie Gao <[email protected]>
 +obj-y += lowlevel_init.o
 --- /dev/null
 +++ b/arch/arm/mach-mediatek/mt7986/init.c
-@@ -0,0 +1,51 @@
+@@ -0,0 +1,45 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (C) 2022 MediaTek Inc.
@@ -477,12 +483,6 @@ Signed-off-by: Weijie Gao <[email protected]>
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
-+int print_cpuinfo(void)
-+{
-+	printf("CPU:   MediaTek MT7986\n");
-+	return 0;
-+}
-+
 +int dram_init(void)
 +{
 +	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);

package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch

@@ -1,7 +1,7 @@
-From 38faebb811868f9e6734dea7894d0fa5a61f3a22 Mon Sep 17 00:00:00 2001
+From 5512a2e8257b0a733cf90ec247f34094ff31f750 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 15:58:11 +0800
-Subject: [PATCH 02/31] arm: mediatek: add support for MediaTek MT7981 SoC
+Date: Wed, 31 Aug 2022 19:00:20 +0800
+Subject: [PATCH 02/32] arm: mediatek: add support for MediaTek MT7981 SoC
 
 This patch adds basic support for MediaTek MT7981 SoC.
 This include the file that will initialize the SoC after boot and its
@@ -9,11 +9,11 @@ device tree.
 
 Signed-off-by: Weijie Gao <[email protected]>
 ---
- arch/arm/dts/mt7981.dtsi                      | 288 ++++++++++++++++++
- arch/arm/mach-mediatek/Kconfig                |  12 +-
+ arch/arm/dts/mt7981.dtsi                      | 293 ++++++++++++++++++
+ arch/arm/mach-mediatek/Kconfig                |  13 +-
  arch/arm/mach-mediatek/Makefile               |   1 +
  arch/arm/mach-mediatek/mt7981/Makefile        |   4 +
- arch/arm/mach-mediatek/mt7981/init.c          |  51 ++++
+ arch/arm/mach-mediatek/mt7981/init.c          |  45 +++
  arch/arm/mach-mediatek/mt7981/lowlevel_init.S |  32 ++
  6 files changed, 387 insertions(+), 1 deletion(-)
  create mode 100644 arch/arm/dts/mt7981.dtsi
@@ -23,7 +23,7 @@ Signed-off-by: Weijie Gao <[email protected]>
 
 --- /dev/null
 +++ b/arch/arm/dts/mt7981.dtsi
-@@ -0,0 +1,288 @@
+@@ -0,0 +1,293 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (c) 2022 MediaTek Inc.
@@ -63,6 +63,11 @@ Signed-off-by: Weijie Gao <[email protected]>
 +		u-boot,dm-pre-reloc;
 +	};
 +
++	hwver: hwver {
++		compatible = "mediatek,hwver";
++		reg = <0x8000000 0x1000>;
++	};
++
 +	timer {
 +		compatible = "arm,armv8-timer";
 +		interrupt-parent = <&gic>;
@@ -314,13 +319,14 @@ Signed-off-by: Weijie Gao <[email protected]>
 +};
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
-@@ -40,6 +40,14 @@ config TARGET_MT7629
+@@ -40,6 +40,15 @@ config TARGET_MT7629
  	  including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
  	  switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
  
 +config TARGET_MT7981
 +	bool "MediaTek MT7981 SoC"
 +	select ARM64
++	select CPU
 +	help
 +	  The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53.
 +	  including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C,
@@ -329,7 +335,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  config TARGET_MT7986
  	bool "MediaTek MT7986 SoC"
  	select ARM64
-@@ -92,6 +100,7 @@ config SYS_BOARD
+@@ -93,6 +102,7 @@ config SYS_BOARD
  	default "mt7622" if TARGET_MT7622
  	default "mt7623" if TARGET_MT7623
  	default "mt7629" if TARGET_MT7629
@@ -337,7 +343,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  	default "mt7986" if TARGET_MT7986
  	default "mt8183" if TARGET_MT8183
  	default "mt8512" if TARGET_MT8512
-@@ -108,6 +117,7 @@ config SYS_CONFIG_NAME
+@@ -109,6 +119,7 @@ config SYS_CONFIG_NAME
  	default "mt7622" if TARGET_MT7622
  	default "mt7623" if TARGET_MT7623
  	default "mt7629" if TARGET_MT7629
@@ -345,7 +351,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  	default "mt7986" if TARGET_MT7986
  	default "mt8183" if TARGET_MT8183
  	default "mt8512" if TARGET_MT8512
-@@ -123,7 +133,7 @@ config MTK_BROM_HEADER_INFO
+@@ -124,7 +135,7 @@ config MTK_BROM_HEADER_INFO
  	string
  	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
  	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
@@ -373,7 +379,7 @@ Signed-off-by: Weijie Gao <[email protected]>
 +obj-y += lowlevel_init.o
 --- /dev/null
 +++ b/arch/arm/mach-mediatek/mt7981/init.c
-@@ -0,0 +1,51 @@
+@@ -0,0 +1,45 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Copyright (C) 2022 MediaTek Inc.
@@ -387,12 +393,6 @@ Signed-off-by: Weijie Gao <[email protected]>
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
-+int print_cpuinfo(void)
-+{
-+	printf("CPU:   MediaTek MT7981\n");
-+	return 0;
-+}
-+
 +int dram_init(void)
 +{
 +	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);

package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch

@@ -1,7 +1,7 @@
-From ab3f81920b4e47bd2894388540363700d5b1e59c Mon Sep 17 00:00:00 2001
+From bad27c737d27f8afc4d597b6de1bdbc26a152ad9 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 15:26:31 +0800
-Subject: [PATCH 03/31] board: mediatek: add MT7986 reference boards
+Date: Wed, 31 Aug 2022 19:00:22 +0800
+Subject: [PATCH 03/32] board: mediatek: add MT7986 reference boards
 
 Add general board files based on MT7986 SoCs.
 

package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch

@@ -1,7 +1,7 @@
-From 89a31bfa05c384a2b4e56ddb9814633325b7feab Mon Sep 17 00:00:00 2001
+From 37bcf4d1acb5f7ce93fa0bd59dc313a79004ae34 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 16:02:37 +0800
-Subject: [PATCH 04/31] board: mediatek: add MT7981 reference boards
+Date: Wed, 31 Aug 2022 19:00:25 +0800
+Subject: [PATCH 04/32] board: mediatek: add MT7981 reference boards
 
 This patch adds general board files based on MT7981 SoCs.
 

package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch

@@ -1,7 +1,7 @@
-From 3831266fedf14ef415791a93dd03a9e637eb8b5e Mon Sep 17 00:00:00 2001
+From 9a10182f21cc4007f46284d5c64c49dc892336be Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Tue, 26 Jul 2022 09:24:13 +0800
-Subject: [PATCH 05/31] mmc: mediatek: add support for MediaTek MT7891/MT7986
+Date: Wed, 31 Aug 2022 19:04:12 +0800
+Subject: [PATCH 05/32] mmc: mediatek: add support for MediaTek MT7891/MT7986
  SoCs
 
 Add eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs

package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch

@@ -1,7 +1,7 @@
-From 5c5af768c4cceaa9d7497c3e5bfbc9d1ea8b279c Mon Sep 17 00:00:00 2001
+From ba6af13fd58c0ec418720d959152e0db47e91b02 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Tue, 26 Jul 2022 10:44:57 +0800
-Subject: [PATCH 06/31] net: mediatek: use a struct to cover variations of all
+Date: Wed, 31 Aug 2022 19:04:19 +0800
+Subject: [PATCH 06/32] net: mediatek: use a struct to cover variations of all
  SoCs
 
 Using a single soc id to control different initialization and TX/RX flow

package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch

@@ -1,7 +1,7 @@
-From b978c067075fddbac341bf551ebef29e78767b75 Mon Sep 17 00:00:00 2001
+From 5f6f3600a334398e27802de33a6a8726aacbe88c Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 09:32:29 +0800
-Subject: [PATCH 07/31] net: mediatek: stop using bitfileds for DMA descriptors
+Date: Wed, 31 Aug 2022 19:04:23 +0800
+Subject: [PATCH 07/32] net: mediatek: stop using bitfileds for DMA descriptors
 
 This patch is a preparation for adding a new version of PDMA of which the
 DMA descriptor fields has changed. Using bitfields will result in a complex

package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch

@@ -1,7 +1,7 @@
-From 2f53795aac940d960bc5f3b08a730c4d480fc5f6 Mon Sep 17 00:00:00 2001
+From 72241607b955639a51b79297776991de7dd59915 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 09:56:30 +0800
-Subject: [PATCH 08/31] net: mediatek: add support for PDMA v2
+Date: Wed, 31 Aug 2022 19:04:27 +0800
+Subject: [PATCH 08/32] net: mediatek: add support for PDMA v2
 
 This patch adds support for PDMA v2 hardware. The PDMA v2 has extended the
 DMA descriptor to 8-words, and some of its fields have changed comparing

package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch

@@ -1,7 +1,7 @@
-From 5e06e9a78bbc81f64fdb4c8502a8e7175d8b6216 Mon Sep 17 00:00:00 2001
+From 4bbe44513bf9dc7041b2ce4aac6e841a0e10d2e6 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 10:03:17 +0800
-Subject: [PATCH 09/31] net: mediatek: add support for MediaTek MT7981/MT7986
+Date: Wed, 31 Aug 2022 19:04:29 +0800
+Subject: [PATCH 09/32] net: mediatek: add support for MediaTek MT7981/MT7986
 
 This patch adds support for MediaTek MT7981 and MT7986. Both chips uses
 PDMA v2.

package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch

@@ -1,7 +1,7 @@
-From 55ed87efb110d13fce6d1a7ee6cb04fac1a2c08a Mon Sep 17 00:00:00 2001
+From d19ad7515a7ef4ee58b5c6606ee9f74c94f28932 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 10:28:05 +0800
-Subject: [PATCH 10/31] serial: mtk: add support for using dynamic baud clock
+Date: Wed, 31 Aug 2022 19:04:32 +0800
+Subject: [PATCH 10/32] serial: mtk: add support for using dynamic baud clock
  souce
 
 The baud clock on some platform may change due to assigned-clock-parent
@@ -187,7 +187,7 @@ Signed-off-by: Weijie Gao <[email protected]>
 @@ -427,13 +441,13 @@ static inline void _debug_uart_init(void
  	struct mtk_serial_priv priv;
  
- 	priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
+ 	priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
 -	priv.clock = CONFIG_DEBUG_UART_CLOCK;
 +	priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
  

package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch

@@ -1,7 +1,7 @@
-From 893368e64049fd770e55fffcc8758d2619dc337d Mon Sep 17 00:00:00 2001
+From 79786aa175010dde78f95970939e8efadd7a3295 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Mon, 25 Jul 2022 16:33:13 +0800
-Subject: [PATCH 11/31] arm: dts: mt7622: force high-speed mode for uart
+Date: Wed, 31 Aug 2022 19:04:34 +0800
+Subject: [PATCH 11/32] arm: dts: mt7622: force high-speed mode for uart
 
 The input clock for uart is too slow (25MHz) which introduces frequent data
 error on both receiving and transmitting even if the baudrate is 115200.

package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch

@@ -1,7 +1,7 @@
-From 63acbf4ffe328809ca479e5c7d344882810d412c Mon Sep 17 00:00:00 2001
+From d7dae84aad997f4f9b5d039f7ab180bd1f54fa37 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 11:00:15 +0800
-Subject: [PATCH 12/31] pwm: mtk: add support for MediaTek MT7986 SoC
+Date: Wed, 31 Aug 2022 19:04:35 +0800
+Subject: [PATCH 12/32] pwm: mtk: add support for MediaTek MT7986 SoC
 
 This patch adds PWM support for MediaTek MT7986 SoC.
 

package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch

@@ -1,7 +1,7 @@
-From 4569ef02981f20b236a8cdc3a57b4d27fbdbc22e Mon Sep 17 00:00:00 2001
+From 230003c14f7beedf4042bf2258b04e2cd5aac270 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 11:01:34 +0800
-Subject: [PATCH 13/31] pwm: mtk: add support for MediaTek MT7981 SoC
+Date: Wed, 31 Aug 2022 19:04:38 +0800
+Subject: [PATCH 13/32] pwm: mtk: add support for MediaTek MT7981 SoC
 
 This patch adds PWM support for MediaTek MT7981 SoC.
 MT7981 uses a different register offset so we have to add a version field

package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch

@@ -1,7 +1,7 @@
-From 7860bc58c43dfa939d2664be518c28aea591aeef Mon Sep 17 00:00:00 2001
+From a77b8f6d9aa90f80090e505d823a6dcf6b877136 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 11:38:33 +0800
-Subject: [PATCH 14/31] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs
+Date: Wed, 31 Aug 2022 19:04:40 +0800
+Subject: [PATCH 14/32] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs
 
 This patch add general-purpose timer support for MediaTek MT7981/MT7986.
 These two SoCs uses a newer version of timer with its register definition

package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch

@@ -1,7 +1,7 @@
-From ec7e5d3e4d6e9239f3d7ac861f07ca4a52bec9fa Mon Sep 17 00:00:00 2001
+From 18f761770d7aa53abf187fa64bbd92f0682d154c Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 11:47:50 +0800
-Subject: [PATCH 15/31] watchdog: mediatek: add support for MediaTek MT7986 SoC
+Date: Wed, 31 Aug 2022 19:04:42 +0800
+Subject: [PATCH 15/32] watchdog: mediatek: add support for MediaTek MT7986 SoC
 
 Add watchdog support for MediaTek MT7986 SoC
 

package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch

@@ -1,7 +1,7 @@
-From f85493e3c2d1e4fd411061540b4f4943c09114df Mon Sep 17 00:00:00 2001
+From e6b225ff8990635dc2d6d8dbd72e78dec1f36c62 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 16:58:38 +0800
-Subject: [PATCH 16/31] spi: add support for MediaTek spi-mem controller
+Date: Wed, 31 Aug 2022 19:04:45 +0800
+Subject: [PATCH 16/32] spi: add support for MediaTek spi-mem controller
 
 This patch adds support for spi-mem controller found on newer MediaTek SoCs
 This controller supports Single/Dual/Quad SPI mode.

package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch

@@ -1,7 +1,7 @@
-From de6f2293ab087f405dbcf7b8df45d1f9b03fc091 Mon Sep 17 00:00:00 2001
+From 987dc8d079cd399e753e10fce12d526b42f90ed0 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 27 Jul 2022 17:16:38 +0800
-Subject: [PATCH 17/31] i2c: add support for MediaTek I2C interface
+Date: Wed, 31 Aug 2022 19:04:47 +0800
+Subject: [PATCH 17/32] i2c: add support for MediaTek I2C interface
 
 This patch adds support for MediaTek I2C interface
 

package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch

@@ -1,7 +1,7 @@
-From 9ae337317d5634569bda83dfc5e0658fce34b1e2 Mon Sep 17 00:00:00 2001
+From ceb4b900586299b12e2c8edffecef1d09b57eb30 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Mon, 25 Jul 2022 16:30:30 +0800
-Subject: [PATCH 18/31] arm: dts: mt7622: add i2c support
+Date: Wed, 31 Aug 2022 19:04:49 +0800
+Subject: [PATCH 18/32] arm: dts: mt7622: add i2c support
 
 Add both hardware and software i2c support for mt7622.
 

package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch

@@ -1,7 +1,7 @@
-From 920ba7b9ba1787fd03dad7a5bdc894073936c197 Mon Sep 17 00:00:00 2001
+From e1c55c0ad21daafcb3551b4f5286c1e11c51acc3 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Thu, 28 Jul 2022 09:37:26 +0800
-Subject: [PATCH 19/31] dt-bindings: pinctrl: mediatek: add a header for common
+Date: Wed, 31 Aug 2022 19:04:51 +0800
+Subject: [PATCH 19/32] dt-bindings: pinctrl: mediatek: add a header for common
  pinconf parameters
 
 This patch adds a pinctrl header for common pinconf parameters such as

package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch

@@ -1,7 +1,7 @@
-From 49e7b1e01cf80437c7e22f8b6579d4a81e7f8a3a Mon Sep 17 00:00:00 2001
+From 95df7f4bfacf810be4f94112ab2a4215f6de288d Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Thu, 28 Jul 2022 09:57:58 +0800
-Subject: [PATCH 20/31] pinctrl: mediatek: add pinctrl driver for MT7981 SoC
+Date: Wed, 31 Aug 2022 19:04:55 +0800
+Subject: [PATCH 20/32] pinctrl: mediatek: add pinctrl driver for MT7981 SoC
 
 This patch adds pinctrl and gpio support for MT7981 SoC
 

package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch

@@ -1,7 +1,7 @@
-From a018800db986d63cf95b0779ebb33b5e246072a7 Mon Sep 17 00:00:00 2001
+From 201880cacf1498dd4c6749780163157148d0445d Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Thu, 28 Jul 2022 10:01:00 +0800
-Subject: [PATCH 21/31] pinctrl: mediatek: add pinctrl driver for MT7986 SoC
+Date: Wed, 31 Aug 2022 19:04:57 +0800
+Subject: [PATCH 21/32] pinctrl: mediatek: add pinctrl driver for MT7986 SoC
 
 This patch adds pinctrl and gpio support for MT7986 SoC
 

package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch

@@ -1,7 +1,7 @@
-From 7f6c8bdfe020c45c398c01b417460e3319476606 Mon Sep 17 00:00:00 2001
+From 907d65c5020fefc9944ec57a9e0bd66dc648823e Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 10:43:39 +0800
-Subject: [PATCH 22/31] clk: mediatek: add CLK_BYPASS_XTAL flag to allow
+Date: Wed, 31 Aug 2022 19:04:59 +0800
+Subject: [PATCH 22/32] clk: mediatek: add CLK_BYPASS_XTAL flag to allow
  bypassing searching clock parent of xtal clock
 
 The mtk clock framework in u-boot uses array index for searching clock
@@ -22,26 +22,20 @@ with ID=0 to call mtk_topckgen_get_mux_rate.
 Reviewed-by: Simon Glass <[email protected]>
 Signed-off-by: Weijie Gao <[email protected]>
 ---
- drivers/clk/mediatek/clk-mtk.c | 5 ++++-
+ drivers/clk/mediatek/clk-mtk.c | 4 +++-
  drivers/clk/mediatek/clk-mtk.h | 6 ++++++
- 2 files changed, 10 insertions(+), 1 deletion(-)
+ 2 files changed, 9 insertions(+), 1 deletion(-)
 
 --- a/drivers/clk/mediatek/clk-mtk.c
 +++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -314,12 +314,15 @@ static ulong mtk_topckgen_get_mux_rate(s
- 	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
- 	const struct mtk_composite *mux = &priv->tree->muxes[off];
- 	u32 index;
-+	u32 flag = 0;
- 
- 	index = readl(priv->base + mux->mux_reg);
+@@ -319,7 +319,9 @@ static ulong mtk_topckgen_get_mux_rate(s
  	index &= mux->mux_mask << mux->mux_shift;
  	index = index >> mux->mux_shift;
  
 -	if (mux->parent[index])
-+	if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
-+		flag = 1;
-+	if (mux->parent[index] > 0 || flag == 1)
++	if (mux->parent[index] > 0 ||
++	    (mux->parent[index] == CLK_XTAL &&
++	     priv->tree->flags & CLK_BYPASS_XTAL))
  		return mtk_clk_find_parent_rate(clk, mux->parent[index],
  						NULL);
  

package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch

@@ -1,7 +1,7 @@
-From cd4d6be5ed0488de2e0df9c388d89ad93d781caa Mon Sep 17 00:00:00 2001
+From 50859bea6a3334834b8250e7e5406507f0d0918a Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 10:57:05 +0800
-Subject: [PATCH 23/31] clk: mediatek: add support to configure clock driver
+Date: Wed, 31 Aug 2022 19:05:06 +0800
+Subject: [PATCH 23/32] clk: mediatek: add support to configure clock driver
  parent
 
 This patch adds support for a clock node to configure its parent clock
@@ -50,14 +50,14 @@ Signed-off-by: Weijie Gao <[email protected]>
  		break;
  	case CLK_PARENT_TOPCKGEN:
  		rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
-@@ -322,9 +316,18 @@ static ulong mtk_topckgen_get_mux_rate(s
+@@ -321,9 +315,18 @@ static ulong mtk_topckgen_get_mux_rate(s
  
- 	if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
- 		flag = 1;
--	if (mux->parent[index] > 0 || flag == 1)
+ 	if (mux->parent[index] > 0 ||
+ 	    (mux->parent[index] == CLK_XTAL &&
+-	     priv->tree->flags & CLK_BYPASS_XTAL))
 -		return mtk_clk_find_parent_rate(clk, mux->parent[index],
 -						NULL);
-+	if (mux->parent[index] > 0 || flag == 1) {
++	     priv->tree->flags & CLK_BYPASS_XTAL)) {
 +		switch (mux->flags & CLK_PARENT_MASK) {
 +		case CLK_PARENT_APMIXED:
 +			return mtk_clk_find_parent_rate(clk, mux->parent[index],
@@ -72,7 +72,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  
  	return priv->tree->xtal_rate;
  }
-@@ -343,7 +346,7 @@ static ulong mtk_topckgen_get_rate(struc
+@@ -342,7 +345,7 @@ static ulong mtk_topckgen_get_rate(struc
  						 priv->tree->muxes_offs);
  }
  
@@ -81,7 +81,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  {
  	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  	const struct mtk_composite *mux;
-@@ -376,7 +379,7 @@ static int mtk_topckgen_enable(struct cl
+@@ -375,7 +378,7 @@ static int mtk_topckgen_enable(struct cl
  	return 0;
  }
  
@@ -90,7 +90,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  {
  	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  	const struct mtk_composite *mux;
-@@ -402,7 +405,7 @@ static int mtk_topckgen_disable(struct c
+@@ -401,7 +404,7 @@ static int mtk_topckgen_disable(struct c
  	return 0;
  }
  
@@ -99,7 +99,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  {
  	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  
-@@ -474,19 +477,7 @@ static ulong mtk_clk_gate_get_rate(struc
+@@ -473,19 +476,7 @@ static ulong mtk_clk_gate_get_rate(struc
  	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
  	const struct mtk_gate *gate = &priv->gates[clk->id];
  
@@ -120,7 +120,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  }
  
  const struct clk_ops mtk_clk_apmixedsys_ops = {
-@@ -497,10 +488,10 @@ const struct clk_ops mtk_clk_apmixedsys_
+@@ -496,10 +487,10 @@ const struct clk_ops mtk_clk_apmixedsys_
  };
  
  const struct clk_ops mtk_clk_topckgen_ops = {
@@ -134,7 +134,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  };
  
  const struct clk_ops mtk_clk_gate_ops = {
-@@ -513,11 +504,22 @@ int mtk_common_clk_init(struct udevice *
+@@ -512,11 +503,22 @@ int mtk_common_clk_init(struct udevice *
  			const struct mtk_clk_tree *tree)
  {
  	struct mtk_clk_priv *priv = dev_get_priv(dev);
@@ -157,7 +157,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  	priv->tree = tree;
  
  	return 0;
-@@ -528,11 +530,22 @@ int mtk_common_clk_gate_init(struct udev
+@@ -527,11 +529,22 @@ int mtk_common_clk_gate_init(struct udev
  			     const struct mtk_gate *gates)
  {
  	struct mtk_cg_priv *priv = dev_get_priv(dev);

package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch

@@ -1,16 +1,16 @@
-From e9c0c2ebd346aa578007c2aa88fc0974af6afb40 Mon Sep 17 00:00:00 2001
+From c53d249df9a75f77f5d0abb986a8913bc13070d0 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 11:14:33 +0800
-Subject: [PATCH 24/31] clk: mediatek: add infrasys clock mux support
+Date: Wed, 31 Aug 2022 19:05:09 +0800
+Subject: [PATCH 24/32] clk: mediatek: add infrasys clock mux support
 
 This patch adds infrasys clock mux support for mediatek clock drivers.
 
 Reviewed-by: Simon Glass <[email protected]>
 Signed-off-by: Weijie Gao <[email protected]>
 ---
- drivers/clk/mediatek/clk-mtk.c | 72 ++++++++++++++++++++++++++++++++++
+ drivers/clk/mediatek/clk-mtk.c | 71 ++++++++++++++++++++++++++++++++++
  drivers/clk/mediatek/clk-mtk.h |  4 +-
- 2 files changed, 75 insertions(+), 1 deletion(-)
+ 2 files changed, 74 insertions(+), 1 deletion(-)
 
 --- a/drivers/clk/mediatek/clk-mtk.c
 +++ b/drivers/clk/mediatek/clk-mtk.c
@@ -39,7 +39,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
  {
  	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
-@@ -332,6 +350,34 @@ static ulong mtk_topckgen_get_mux_rate(s
+@@ -331,6 +349,33 @@ static ulong mtk_topckgen_get_mux_rate(s
  	return priv->tree->xtal_rate;
  }
  
@@ -48,15 +48,14 @@ Signed-off-by: Weijie Gao <[email protected]>
 +	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 +	const struct mtk_composite *mux = &priv->tree->muxes[off];
 +	u32 index;
-+	u32 flag;
 +
 +	index = readl(priv->base + mux->mux_reg);
 +	index &= mux->mux_mask << mux->mux_shift;
 +	index = index >> mux->mux_shift;
 +
-+	if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
-+		flag = 1;
-+	if (mux->parent[index] > 0 || flag == 1) {
++	if (mux->parent[index] > 0 ||
++	    (mux->parent[index] == CLK_XTAL &&
++	     priv->tree->flags & CLK_BYPASS_XTAL)) {
 +		switch (mux->flags & CLK_PARENT_MASK) {
 +		case CLK_PARENT_TOPCKGEN:
 +			return mtk_clk_find_parent_rate(clk, mux->parent[index],
@@ -74,7 +73,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  static ulong mtk_topckgen_get_rate(struct clk *clk)
  {
  	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
-@@ -346,6 +392,25 @@ static ulong mtk_topckgen_get_rate(struc
+@@ -345,6 +390,25 @@ static ulong mtk_topckgen_get_rate(struc
  						 priv->tree->muxes_offs);
  }
  
@@ -100,7 +99,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  static int mtk_clk_mux_enable(struct clk *clk)
  {
  	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
-@@ -494,6 +559,13 @@ const struct clk_ops mtk_clk_topckgen_op
+@@ -493,6 +557,13 @@ const struct clk_ops mtk_clk_topckgen_op
  	.set_parent = mtk_common_clk_set_parent,
  };
  

package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch

@@ -1,10 +1,10 @@
-From cf70b726c9844bb5d1ba4bc3c202c5ab3ba4d421 Mon Sep 17 00:00:00 2001
+From 0a2cd71e3b16eaa8797b5eec78356970186e552e Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 11:15:35 +0800
-Subject: [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver
+Date: Wed, 31 Aug 2022 19:05:11 +0800
+Subject: [PATCH 25/32] clk: mediatek: add CLK_XTAL support for clock driver
 
-This add CLK_XTAL macro and flag to mediatek clock driver common part,
-to make thi SoC that has clock directlly connect to XTAL working.
+This adds the CLK_XTAL macro/flag to allow modeling clocks which are
+directly connected to the xtal clock.
 
 Signed-off-by: Weijie Gao <[email protected]>
 ---

package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch

@@ -1,11 +1,12 @@
-From ba4acf55044a8a11fc7e11a558a8a93e3c126391 Mon Sep 17 00:00:00 2001
+From 54b66dd24310dba4798caa6e4c02b8571f522602 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 11:21:59 +0800
-Subject: [PATCH 26/31] clk: mediatek: add clock driver support for MediaTek
+Date: Wed, 31 Aug 2022 19:05:13 +0800
+Subject: [PATCH 26/32] clk: mediatek: add clock driver support for MediaTek
  MT7986 SoC
 
 This patch adds clock driver support for MediaTek MT7986 SoC
 
+Reviewed-by: Sean Anderson <[email protected]>
 Reviewed-by: Simon Glass <[email protected]>
 Signed-off-by: Weijie Gao <[email protected]>
 ---

package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch

@@ -1,11 +1,12 @@
-From 79bca945dbfafcd08d71437b11e8ee57d64b4305 Mon Sep 17 00:00:00 2001
+From d525836896235c4678f6144cc4608d5b15e02660 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Fri, 29 Jul 2022 11:22:51 +0800
-Subject: [PATCH 27/31] clk: mediatek: add clock driver support for MediaTek
+Date: Wed, 31 Aug 2022 19:05:16 +0800
+Subject: [PATCH 27/32] clk: mediatek: add clock driver support for MediaTek
  MT7981 SoC
 
 This patch adds clock driver support for MediaTek MT7981 SoC
 
+Reviewed-by: Sean Anderson <[email protected]>
 Reviewed-by: Simon Glass <[email protected]>
 Signed-off-by: Weijie Gao <[email protected]>
 ---

package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch

@@ -0,0 +1,133 @@
+From e3c707d23a3a5bc1ba9b8c03731a32c3714ae56a Mon Sep 17 00:00:00 2001
+From: Weijie Gao <[email protected]>
+Date: Wed, 31 Aug 2022 19:05:20 +0800
+Subject: [PATCH 28/32] cpu: add basic cpu driver for MediaTek ARM chips
+
+Add basic CPU driver used to retrieve CPU model information.
+
+Signed-off-by: Weijie Gao <[email protected]>
+---
+ drivers/cpu/Makefile  |   1 +
+ drivers/cpu/mtk_cpu.c | 106 ++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 107 insertions(+)
+ create mode 100644 drivers/cpu/mtk_cpu.c
+
+--- a/drivers/cpu/Makefile
++++ b/drivers/cpu/Makefile
+@@ -9,6 +9,7 @@ obj-$(CONFIG_CPU) += cpu-uclass.o
+ obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
+ obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
+ obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
++obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
+ obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
+ obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
+ obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
+--- /dev/null
++++ b/drivers/cpu/mtk_cpu.c
+@@ -0,0 +1,106 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
++ *
++ * Author: Weijie Gao <[email protected]>
++ */
++
++#include <linux/types.h>
++#include <cpu.h>
++#include <dm.h>
++#include <fdt_support.h>
++#include <mapmem.h>
++#include <asm/global_data.h>
++#include <linux/io.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++struct mtk_cpu_plat {
++	void __iomem *hwver_base;
++};
++
++static int mtk_cpu_get_desc(const struct udevice *dev, char *buf, int size)
++{
++	struct mtk_cpu_plat *plat = dev_get_plat(dev);
++
++	snprintf(buf, size, "MediaTek MT%04X", readl(plat->hwver_base));
++
++	return 0;
++}
++
++static int mtk_cpu_get_count(const struct udevice *dev)
++{
++	return 1;
++}
++
++static int mtk_cpu_get_vendor(const struct udevice *dev, char *buf, int size)
++{
++	snprintf(buf, size, "MediaTek");
++
++	return 0;
++}
++
++static int mtk_cpu_probe(struct udevice *dev)
++{
++	struct mtk_cpu_plat *plat = dev_get_plat(dev);
++	const void *fdt = gd->fdt_blob, *reg;
++	int offset, parent, len, na, ns;
++	u64 addr;
++
++	if (!fdt)
++		return -ENODEV;
++
++	offset = fdt_path_offset(fdt, "/hwver");
++	if (offset < 0)
++		return -ENODEV;
++
++	parent = fdt_parent_offset(fdt, offset);
++	if (parent < 0)
++		return -ENODEV;
++
++	na = fdt_address_cells(fdt, parent);
++	if (na < 1)
++		return -ENODEV;
++
++	ns = fdt_size_cells(gd->fdt_blob, parent);
++	if (ns < 0)
++		return -ENODEV;
++
++	reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
++	if (!reg)
++		return -ENODEV;
++
++	if (ns)
++		addr = fdt_translate_address(fdt, offset, reg);
++	else
++		addr = fdt_read_number(reg, na);
++
++	plat->hwver_base = map_sysmem(addr, 0);
++	if (!plat->hwver_base)
++		return -EINVAL;
++
++	return 0;
++}
++
++static const struct cpu_ops mtk_cpu_ops = {
++	.get_desc	= mtk_cpu_get_desc,
++	.get_count	= mtk_cpu_get_count,
++	.get_vendor	= mtk_cpu_get_vendor,
++};
++
++static const struct udevice_id mtk_cpu_ids[] = {
++	{ .compatible = "arm,cortex-a7" },
++	{ .compatible = "arm,cortex-a53" },
++	{ .compatible = "arm,cortex-a73" },
++	{ /* sentinel */ }
++};
++
++U_BOOT_DRIVER(cpu_mtk) = {
++	.name		= "mtk-cpu",
++	.id		= UCLASS_CPU,
++	.of_match	= mtk_cpu_ids,
++	.ops		= &mtk_cpu_ops,
++	.probe		= mtk_cpu_probe,
++	.plat_auto	= sizeof(struct mtk_cpu_plat),
++	.flags		= DM_FLAG_PRE_RELOC,
++};

package/boot/uboot-mediatek/patches/002-0028-tools-mtk_image-split-gfh-header-verification-into-a.patch → package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch

@@ -1,7 +1,7 @@
-From b6bb61fd3818f4a3025fedbe4d15dbeeaef6ee82 Mon Sep 17 00:00:00 2001
+From 1c9174cbf57ddc75bb5a25b2563333d974fd1a55 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Tue, 2 Aug 2022 17:21:34 +0800
-Subject: [PATCH 28/31] tools: mtk_image: split gfh header verification into a
+Date: Wed, 31 Aug 2022 19:05:22 +0800
+Subject: [PATCH 29/32] tools: mtk_image: split gfh header verification into a
  new function
 
 The verification code of gfh header for NAND and non-NAND are identical.

package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-the-code-of-generating-NAND-he.patch → package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch

@@ -1,7 +1,7 @@
-From 20ebf03eab571b25e9f62b2764ab84932111dcd6 Mon Sep 17 00:00:00 2001
+From 8867a5e66369d4a7da667e0f505597e1ac91209e Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Tue, 2 Aug 2022 17:23:57 +0800
-Subject: [PATCH 29/31] tools: mtk_image: split the code of generating NAND
+Date: Wed, 31 Aug 2022 19:05:24 +0800
+Subject: [PATCH 30/32] tools: mtk_image: split the code of generating NAND
  header into a new file
 
 The predefined NAND headers take too much spaces in the mtk_image.c.

package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-add-support-for-nand-headers-used-by.patch → package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch

@@ -1,7 +1,7 @@
-From fbf296f9ed5daab70020686e9ba072efe663bbab Mon Sep 17 00:00:00 2001
+From d459092aca25e081401606e18b7097f33b575188 Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Wed, 3 Aug 2022 11:14:36 +0800
-Subject: [PATCH 30/31] tools: mtk_image: add support for nand headers used by
+Date: Wed, 31 Aug 2022 19:05:26 +0800
+Subject: [PATCH 31/32] tools: mtk_image: add support for nand headers used by
  newer chips
 
 This patch adds more nand headers in two new types:

package/boot/uboot-mediatek/patches/002-0031-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch → package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch

@@ -1,7 +1,7 @@
-From ca90c165157c19af9bf46a69dcf719b8aab636b1 Mon Sep 17 00:00:00 2001
+From 180f8ce7cac9277406ee702ea9390a6f78981bda Mon Sep 17 00:00:00 2001
 From: Weijie Gao <[email protected]>
-Date: Thu, 4 Aug 2022 09:50:40 +0800
-Subject: [PATCH 31/31] MAINTAINERS: update maintainer for MediaTek ARM
+Date: Wed, 31 Aug 2022 19:05:28 +0800
+Subject: [PATCH 32/32] MAINTAINERS: update maintainer for MediaTek ARM
  platform
 
 Add new files for MediaTek ARM platform
@@ -9,15 +9,16 @@ Add new files for MediaTek ARM platform
 Reviewed-by: Simon Glass <[email protected]>
 Signed-off-by: Weijie Gao <[email protected]>
 ---
- MAINTAINERS | 5 +++++
- 1 file changed, 5 insertions(+)
+ MAINTAINERS | 6 ++++++
+ 1 file changed, 6 insertions(+)
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -340,20 +340,25 @@ F:	doc/device-tree-bindings/phy/phy-mtk-
+@@ -340,20 +340,26 @@ F:	doc/device-tree-bindings/phy/phy-mtk-
  F:	doc/device-tree-bindings/usb/mediatek,*
  F:	doc/README.mediatek
  F:	drivers/clk/mediatek/
++F:	drivers/cpu/mtk_cpu.c
 +F:	drivers/i2c/mtk_i2c.c
  F:	drivers/mmc/mtk-sd.c
  F:	drivers/phy/phy-mtk-*

package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch

@@ -89,7 +89,7 @@ Signed-off-by: Weijie Gao <[email protected]>
  		reg = <0x11014000 0x1000>;
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
-@@ -131,9 +131,11 @@ config SYS_CONFIG_NAME
+@@ -133,9 +133,11 @@ config SYS_CONFIG_NAME
  
  config MTK_BROM_HEADER_INFO
  	string

package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch

@@ -40,7 +40,7 @@
  }
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
-@@ -138,4 +138,8 @@ config MTK_BROM_HEADER_INFO
+@@ -140,4 +140,8 @@ config MTK_BROM_HEADER_INFO
  
  source "board/mediatek/mt7629/Kconfig"
  

package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch

@@ -51,6 +51,7 @@
 +CONFIG_CMD_BUTTON=y
 +CONFIG_CMD_CACHE=y
 +CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
 +CONFIG_CMD_DHCP=y
 +CONFIG_CMD_DM=y
 +CONFIG_CMD_DNS=y
@@ -246,6 +247,7 @@
 +CONFIG_CMD_BUTTON=y
 +CONFIG_CMD_CACHE=y
 +CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
 +CONFIG_CMD_DHCP=y
 +CONFIG_CMD_DM=y
 +CONFIG_CMD_DNS=y
@@ -442,6 +444,7 @@
 +CONFIG_CMD_BUTTON=y
 +CONFIG_CMD_CACHE=y
 +CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
 +CONFIG_CMD_DHCP=y
 +CONFIG_CMD_DM=y
 +CONFIG_CMD_DNS=y
@@ -637,6 +640,7 @@
 +CONFIG_CMD_BUTTON=y
 +CONFIG_CMD_CACHE=y
 +CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
 +CONFIG_CMD_DHCP=y
 +CONFIG_CMD_DM=y
 +CONFIG_CMD_DNS=y