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@@ -0,0 +1,541 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Copyright (c) 2021, Flole <[email protected]>
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+ * Copyright (c) 2023, Andrew Smith <[email protected]>
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+ */
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+
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+/dts-v1/;
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+
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+#include "ipq8074.dtsi"
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+#include "ipq8074-ess.dtsi"
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+#include "ipq8074-hk-cpu.dtsi"
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/leds/common.h>
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+
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+/ {
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+ aliases {
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+ serial0 = &blsp1_uart5;
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+ led-boot = &led_front_blue;
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+ led-failsafe = &led_front_red;
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+ led-running = &led_front_green;
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+ led-upgrade = &led_front_white;
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+ label-mac-device = &dp2;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ bootargs-append = " ubi.mtd=rootfs root=/dev/ubiblock0_0";
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+ };
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+
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+ keys {
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+ compatible = "gpio-keys";
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+
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+ reset {
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+ label = "reset";
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+ gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_RESTART>;
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+ };
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+
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+ wps {
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+ label = "wps";
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+ gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_WPS_BUTTON>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ led_front_blue: front-blue {
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+ function = LED_FUNCTION_STATUS;
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+ gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
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+ color = <LED_COLOR_ID_BLUE>;
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+ };
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+
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+ led_front_green: front-green {
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+ function = LED_FUNCTION_STATUS;
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+ gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
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+ color = <LED_COLOR_ID_GREEN>;
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+ };
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+
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+ led_front_red: front-red {
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+ function = LED_FUNCTION_STATUS;
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+ gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
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+ color = <LED_COLOR_ID_RED>;
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+ };
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+
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+ led_front_white: front-white {
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+ function = LED_FUNCTION_STATUS;
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+ gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
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+ color = <LED_COLOR_ID_WHITE>;
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+ };
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+
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+ led_power_green: power-green {
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+ function = LED_FUNCTION_POWER;
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+ gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
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+ color = <LED_COLOR_ID_GREEN>;
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+ default-state = "on";
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+ };
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+
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+ led_power_red: power-red {
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+ function = LED_FUNCTION_POWER;
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+ gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
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+ color = <LED_COLOR_ID_RED>;
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+ panic-indicator;
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+ };
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+ };
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+};
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+
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+&tlmm {
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+ mdio_pins: mdio-pins {
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+ mdc {
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+ pins = "gpio68";
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+ function = "mdc";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+
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+ mdio {
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+ pins = "gpio69";
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+ function = "mdio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+ };
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+
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+ leds_pins: leds_pinmux {
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+ led_power_green {
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+ pins = "gpio21";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+
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+ led_power_red {
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+ pins = "gpio22";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+
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+ led_white {
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+ pins = "gpio26";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+
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+ led_green {
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+ pins = "gpio29";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+
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+ led_red {
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+ pins = "gpio31";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+
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+ led_blue {
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+ pins = "gpio33";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+ };
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+};
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+
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+&blsp1_uart5 {
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+ status = "okay";
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+};
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+
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+&blsp1_i2c2 {
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+ pinctrl-0 = <&i2c_0_pins>;
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+ pinctrl-names = "default";
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+
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+ status = "okay";
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+
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+ tlc59208f@27 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "ti,tlc59108";
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+ reg = <0x27>;
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+
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+ led@0 {
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+ label = "rgb:led0";
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+ reg = <0>;
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+ linux,default-trigger = "default-off";
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+ };
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+
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+ led@1 {
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+ label = "rgb:led1";
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+ reg = <1>;
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+ linux,default-trigger = "default-off";
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+ };
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+
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+ led@2 {
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+ label = "rgb:led2";
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+ reg = <2>;
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+ linux,default-trigger = "default-off";
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+ };
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+
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+ led@3 {
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+ label = "rgb:led3";
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+ reg = <3>;
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+ linux,default-trigger = "default-off";
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+ };
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+ };
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+};
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+
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+&prng {
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+ status = "okay";
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+};
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+
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+&cryptobam {
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+ status = "okay";
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+};
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+
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+&crypto {
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+ status = "okay";
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+};
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+
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+&qpic_bam {
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+ status = "okay";
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+};
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+
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+&qpic_nand {
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+ status = "okay";
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+
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+ /*
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+ * Bootloader will find the NAND DT node by the compatible and
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+ * then "fixup" it by adding the partitions from the SMEM table
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+ * using the legacy bindings thus making it impossible for us
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+ * to change the partition table or utilize NVMEM for calibration.
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+ * So add a dummy partitions node that bootloader will populate
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+ * and set it as disabled so the kernel ignores it instead of
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+ * printing warnings due to the broken way bootloader adds the
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+ * partitions.
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+ */
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+ partitions {
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+ status = "disabled";
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+ };
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+
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+ nand@0 {
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+ reg = <0>;
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ nand-bus-width = <8>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "0:sbl1";
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+ reg = <0x00 0x100000>;
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+ read-only;
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+ };
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+
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+ partition@100000 {
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+ label = "0:mibib";
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+ reg = <0x100000 0x100000>;
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+ read-only;
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+ };
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+
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+ partition@200000 {
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+ label = "0:bootconfig";
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+ reg = <0x200000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@280000 {
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+ label = "0:bootconfig_1";
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+ reg = <0x280000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@300000 {
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+ label = "0:qsee";
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+ reg = <0x300000 0x300000>;
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+ read-only;
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+ };
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+
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+ partition@600000 {
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+ label = "0:qsee_1";
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+ reg = <0x600000 0x300000>;
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+ read-only;
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+ };
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+
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+ partition@900000 {
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+ label = "0:devcfg";
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+ reg = <0x900000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@980000 {
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+ label = "0:devcfg_1";
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+ reg = <0x980000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@a00000 {
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+ label = "0:apdp";
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+ reg = <0xa00000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@a80000 {
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+ label = "0:apdp_1";
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+ reg = <0xa80000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@b00000 {
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+ label = "0:rpm";
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+ reg = <0xb00000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@b80000 {
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+ label = "0:rpm_1";
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+ reg = <0xb80000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@c00000 {
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+ label = "0:cdt";
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+ reg = <0xc00000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@c80000 {
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+ label = "0:cdt_1";
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+ reg = <0xc80000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@d00000 {
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+ label = "0:appsblenv";
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+ reg = <0xd00000 0x80000>;
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+ };
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+
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+ partition@d80000 {
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+ label = "0:appsbl";
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+ reg = <0xd80000 0x100000>;
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+ read-only;
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+ };
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+
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+ partition@e80000 {
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+ label = "0:appsbl_1";
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+ reg = <0xe80000 0x100000>;
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+ read-only;
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+ };
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+
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+ partition@f80000 {
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+ label = "0:art";
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+ reg = <0xf80000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@1000000 {
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+ label = "0:art.bak";
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+ reg = <0x1000000 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@1080000 {
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+ label = "config";
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+ reg = <0x1080000 0x100000>;
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+ };
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+
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+ partition@1180000 {
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+ label = "boarddata1";
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+ reg = <0x1180000 0x100000>;
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+
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+ nvmem-layout {
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+ compatible = "fixed-layout";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ macaddr_boarddata1_0: macaddr@0 {
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+ reg = <0x0 0x6>;
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+ };
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+
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+ macaddr_boarddata1_6: macaddr@6 {
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+ reg = <0x6 0x6>;
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+ };
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+ };
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+ };
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+
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+ partition@1280000 {
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+ label = "boarddata2";
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+ reg = <0x1280000 0x100000>;
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+ };
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+
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+ partition@1380000 {
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+ label = "pot";
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+ reg = <0x1380000 0x100000>;
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+ read-only;
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+ };
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+
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+ partition@1480000 {
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+ label = "dnidata";
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+ reg = <0x1480000 0x500000>;
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+ read-only;
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+ };
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+
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+ partition@1980000 {
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+ label = "kernel";
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+ reg = <0x1980000 0x620000>;
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+ };
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+
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+ partition@1fa0000 {
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+ label = "rootfs";
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+ reg = <0x1fa0000 0x66e0000>;
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+ };
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+
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+ partition@8680000 {
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+ label = "kernel2";
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+ reg = <0x8680000 0x620000>;
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+ read-only;
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+ };
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+
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+ partition@8ca0000 {
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+ label = "rootfs2";
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+ reg = <0x8ca0000 0x66e0000>;
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+ read-only;
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+ };
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+ };
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+ };
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+};
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+
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+&mdio {
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+ status = "okay";
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+
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+ pinctrl-0 = <&mdio_pins>;
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+ pinctrl-names = "default";
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+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
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+
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+ ethernet-phy-package@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ compatible = "qcom,qca8075-package";
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+
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+ qca8075_1: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+
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+ qca8075_2: ethernet-phy@2 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <2>;
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+ };
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+
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+ qca8075_3: ethernet-phy@3 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <3>;
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+ };
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+
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+ qca8075_4: ethernet-phy@4 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <4>;
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+ };
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+ };
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+
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+ qca8081_28: ethernet-phy@28 {
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+ compatible = "ethernet-phy-id004d.d101";
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+ reg = <28>;
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+ reset-deassert-us = <10000>;
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+ reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
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+ };
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+};
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+
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+&switch {
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+ status = "okay";
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+
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+ switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT5)>; /* lan port bitmap */
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+ switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
|
|
|
+ switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
|
|
|
+ switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
|
|
|
+
|
|
|
+ qcom,port_phyinfo {
|
|
|
+ port@2 {
|
|
|
+ port_id = <2>;
|
|
|
+ phy_address = <1>;
|
|
|
+ };
|
|
|
+ port@3 {
|
|
|
+ port_id = <3>;
|
|
|
+ phy_address = <2>;
|
|
|
+ };
|
|
|
+ port@4 {
|
|
|
+ port_id = <4>;
|
|
|
+ phy_address = <3>;
|
|
|
+ };
|
|
|
+ port@5 {
|
|
|
+ port_id = <5>;
|
|
|
+ phy_address = <4>;
|
|
|
+ };
|
|
|
+ port@6 {
|
|
|
+ port_id = <6>;
|
|
|
+ phy_address = <28>;
|
|
|
+ port_mac_sel = "QGMAC_PORT";
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&edma {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&dp2 {
|
|
|
+ status = "okay";
|
|
|
+ phy-handle = <&qca8075_1>;
|
|
|
+ label = "lan2";
|
|
|
+ nvmem-cells = <&macaddr_boarddata1_0>;
|
|
|
+ nvmem-cell-names = "mac-address";
|
|
|
+};
|
|
|
+
|
|
|
+&dp3 {
|
|
|
+ status = "okay";
|
|
|
+ phy-handle = <&qca8075_2>;
|
|
|
+ label = "lan3";
|
|
|
+ nvmem-cells = <&macaddr_boarddata1_0>;
|
|
|
+ nvmem-cell-names = "mac-address";
|
|
|
+};
|
|
|
+
|
|
|
+&dp4 {
|
|
|
+ status = "okay";
|
|
|
+ phy-handle = <&qca8075_3>;
|
|
|
+ label = "lan4";
|
|
|
+ nvmem-cells = <&macaddr_boarddata1_0>;
|
|
|
+ nvmem-cell-names = "mac-address";
|
|
|
+};
|
|
|
+
|
|
|
+&dp5 {
|
|
|
+ status = "okay";
|
|
|
+ phy-handle = <&qca8075_4>;
|
|
|
+ label = "lan5";
|
|
|
+ nvmem-cells = <&macaddr_boarddata1_0>;
|
|
|
+ nvmem-cell-names = "mac-address";
|
|
|
+};
|
|
|
+
|
|
|
+&dp6 {
|
|
|
+ status = "okay";
|
|
|
+ phy-handle = <&qca8081_28>;
|
|
|
+ label = "wan";
|
|
|
+ nvmem-cells = <&macaddr_boarddata1_6>;
|
|
|
+ nvmem-cell-names = "mac-address";
|
|
|
+};
|
|
|
+
|
|
|
+&wifi {
|
|
|
+ status = "okay";
|
|
|
+
|
|
|
+ qcom,ath11k-calibration-variant = "Netgear-SXK80";
|
|
|
+};
|