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@@ -10,8 +10,6 @@
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#include <linux/phylink.h>
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#include <linux/regmap.h>
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-#include <asm/mach-rtl838x/mach-rtl83xx.h>
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-
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#define RTPCS_PORT_CNT 57
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#define RTPCS_SPEED_10 0
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@@ -54,6 +52,9 @@
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#define RTPCS_93XX_MAC_LINK_SPD_BITS 4
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+#define RTL93XX_MODEL_NAME_INFO (0x0004)
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+#define RTL93XX_CHIP_INFO (0x0008)
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+
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/* Registers of the internal SerDes of the 9310 */
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#define RTL931X_SERDES_MODE_CTRL (0x13cc)
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#define RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR (0x13F4)
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@@ -177,23 +178,29 @@ static struct rtpcs_link *rtpcs_phylink_pcs_to_link(struct phylink_pcs *pcs)
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/* RTL931X */
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-static void rtpcs_931x_sds_reset(u32 sds)
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+static void rtpcs_931x_sds_reset(struct rtpcs_ctrl *ctrl, u32 sds)
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{
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u32 o, v, o_mode;
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int shift = ((sds & 0x3) << 3);
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/* TODO: We need to lock this! */
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- o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
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+ regmap_read(ctrl->map, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR, &o);
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v = o | BIT(sds);
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- sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
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+ regmap_write(ctrl->map, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR, v);
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- o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
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+ regmap_read(ctrl->map, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2), &o_mode);
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v = BIT(7) | 0x1F;
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- sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
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- sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
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+ regmap_write_bits(ctrl->map, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2),
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+ 0xff << shift, v << shift);
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+ regmap_write(ctrl->map, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2), o_mode);
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+
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+ regmap_write(ctrl->map, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR, o);
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+}
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- sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
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+static void rtpcs_931x_sds_disable(struct rtpcs_ctrl *ctrl, u32 sds)
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+{
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+ regmap_write(ctrl->map, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4, 0x9f);
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}
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static void rtpcs_931x_sds_symerr_clear(struct rtpcs_ctrl *ctrl, u32 sds,
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@@ -244,8 +251,7 @@ static void rtpcs_931x_sds_fiber_mode_set(struct rtpcs_ctrl *ctrl, u32 sds,
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/* clear symbol error count before changing mode */
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rtpcs_931x_sds_symerr_clear(ctrl, sds, mode);
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- val = 0x9F;
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- sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
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+ rtpcs_931x_sds_disable(ctrl, sds);
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switch (mode) {
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case PHY_INTERFACE_MODE_SGMII:
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@@ -411,16 +417,8 @@ static void rtpcs_931x_sds_rx_reset(struct rtpcs_ctrl *ctrl, u32 sds)
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mdelay(50);
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}
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-__attribute__((unused))
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-static void rtpcs_931x_sds_disable(u32 sds)
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-{
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- u32 v = 0x1f;
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-
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- v |= BIT(7);
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- sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
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-}
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-
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-static void rtpcs_931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
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+static void rtpcs_931x_sds_mii_mode_set(struct rtpcs_ctrl *ctrl, u32 sds,
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+ phy_interface_t mode)
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{
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u32 val;
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@@ -444,7 +442,7 @@ static void rtpcs_931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
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val |= (1 << 7);
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- sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
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+ regmap_write(ctrl->map, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2), val);
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}
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static int rtpcs_931x_sds_cmu_band_set(struct rtpcs_ctrl *ctrl, int sds,
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@@ -467,7 +465,7 @@ static int rtpcs_931x_sds_cmu_band_set(struct rtpcs_ctrl *ctrl, int sds,
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rtpcs_sds_write_bits(ctrl, sds, page, 0x7, 4, 0, band);
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- rtpcs_931x_sds_reset(sds);
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+ rtpcs_931x_sds_reset(ctrl, sds);
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return 0;
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}
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@@ -573,7 +571,7 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
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pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x100, 0xe));
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pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x200, 0xe));
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- model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
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+ regmap_read(ctrl->map, RTL93XX_MODEL_NAME_INFO, &model_info);
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if ((model_info >> 4) & 0x1) {
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pr_info("detected chiptype 1\n");
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chiptype = 1;
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@@ -584,10 +582,10 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
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pr_info("%s: 2.5gbit %08X", __func__,
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rtpcs_sds_read(ctrl, sds, 0x101, 0x14));
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- pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
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- ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
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+ regmap_read(ctrl->map, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR, &ori);
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+ pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, ori);
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val = ori | (1 << sds);
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- sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
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+ regmap_write(ctrl->map, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR, val);
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/* this was in rtl931x_phylink_mac_config in dsa/rtl83xx/dsa.c before */
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band = rtpcs_931x_sds_cmu_band_get(ctrl, sds, mode);
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@@ -708,8 +706,8 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
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rtpcs_sds_write(ctrl, sds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
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else {
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val = 0xa0000;
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- sw_w32(val, RTL93XX_CHIP_INFO);
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- val = sw_r32(RTL93XX_CHIP_INFO);
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+ regmap_write(ctrl->map, RTL93XX_CHIP_INFO, val);
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+ regmap_read(ctrl->map, RTL93XX_CHIP_INFO, &val);
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if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
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{
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rtpcs_sds_write(ctrl, sds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
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@@ -717,20 +715,21 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
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rtpcs_sds_write(ctrl, sds, 0x2E, 0x1, board_sds_tx[sds - 2]);
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}
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val = 0;
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- sw_w32(val, RTL93XX_CHIP_INFO);
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+ regmap_write(ctrl->map, RTL93XX_CHIP_INFO, val);
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}
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}
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val = ori & ~BIT(sds);
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- sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
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- pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
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+ regmap_write(ctrl->map, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR, val);
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+ regmap_read(ctrl->map, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR, &val);
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+ pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, val);
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if (mode == PHY_INTERFACE_MODE_XGMII ||
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mode == PHY_INTERFACE_MODE_QSGMII ||
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mode == PHY_INTERFACE_MODE_SGMII ||
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mode == PHY_INTERFACE_MODE_USXGMII) {
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if (mode == PHY_INTERFACE_MODE_XGMII)
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- rtpcs_931x_sds_mii_mode_set(sds, mode);
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+ rtpcs_931x_sds_mii_mode_set(ctrl, sds, mode);
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else
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rtpcs_931x_sds_fiber_mode_set(ctrl, sds, mode);
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}
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