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@@ -0,0 +1,116 @@
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+From: Lorenzo Bianconi <[email protected]>
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+Date: Tue, 12 Aug 2025 06:57:23 +0200
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+Subject: [PATCH] net: mediatek: wed: Introduce MT7992 WED support to MT7988
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+ SoC
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+
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+Introduce the second WDMA RX ring in WED driver for MT7988 SoC since the
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+Mediatek MT7992 WiFi chipset supports two separated WDMA rings.
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+Add missing MT7988 configurations to properly support WED for MT7992 in
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+MT76 driver.
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+
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+Co-developed-by: Rex Lu <[email protected]>
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+Signed-off-by: Rex Lu <[email protected]>
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+Signed-off-by: Lorenzo Bianconi <[email protected]>
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+Link: https://patch.msgid.link/[email protected]
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+Signed-off-by: Jakub Kicinski <[email protected]>
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+---
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+
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+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
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++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
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+@@ -59,7 +59,9 @@ struct mtk_wed_flow_block_priv {
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+ static const struct mtk_wed_soc_data mt7622_data = {
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+ .regmap = {
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+ .tx_bm_tkid = 0x088,
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+- .wpdma_rx_ring0 = 0x770,
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++ .wpdma_rx_ring = {
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++ 0x770,
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++ },
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+ .reset_idx_tx_mask = GENMASK(3, 0),
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+ .reset_idx_rx_mask = GENMASK(17, 16),
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+ },
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+@@ -70,7 +72,9 @@ static const struct mtk_wed_soc_data mt7
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+ static const struct mtk_wed_soc_data mt7986_data = {
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+ .regmap = {
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+ .tx_bm_tkid = 0x0c8,
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+- .wpdma_rx_ring0 = 0x770,
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++ .wpdma_rx_ring = {
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++ 0x770,
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++ },
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+ .reset_idx_tx_mask = GENMASK(1, 0),
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+ .reset_idx_rx_mask = GENMASK(7, 6),
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+ },
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+@@ -81,7 +85,10 @@ static const struct mtk_wed_soc_data mt7
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+ static const struct mtk_wed_soc_data mt7988_data = {
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+ .regmap = {
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+ .tx_bm_tkid = 0x0c8,
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+- .wpdma_rx_ring0 = 0x7d0,
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++ .wpdma_rx_ring = {
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++ 0x7d0,
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++ 0x7d8,
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++ },
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+ .reset_idx_tx_mask = GENMASK(1, 0),
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+ .reset_idx_rx_mask = GENMASK(7, 6),
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+ },
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+@@ -621,8 +628,8 @@ mtk_wed_amsdu_init(struct mtk_wed_device
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+ return ret;
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+ }
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+
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+- /* eagle E1 PCIE1 tx ring 22 flow control issue */
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+- if (dev->wlan.id == 0x7991)
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++ /* Kite and Eagle E1 PCIE1 tx ring 22 flow control issue */
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++ if (dev->wlan.id == 0x7991 || dev->wlan.id == 0x7992)
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+ wed_clr(dev, MTK_WED_AMSDU_FIFO, MTK_WED_AMSDU_IS_PRIOR0_RING);
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+
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+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
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+@@ -1239,7 +1246,11 @@ mtk_wed_set_wpdma(struct mtk_wed_device
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+ return;
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+
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+ wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
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+- wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
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++ wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring[0],
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++ dev->wlan.wpdma_rx[0]);
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++ if (mtk_wed_is_v3_or_greater(dev->hw))
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++ wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring[1],
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++ dev->wlan.wpdma_rx[1]);
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+
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+ if (!dev->wlan.hw_rro)
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+ return;
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+@@ -2335,6 +2346,16 @@ mtk_wed_start(struct mtk_wed_device *dev
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+ if (!dev->rx_wdma[i].desc)
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+ mtk_wed_wdma_rx_ring_setup(dev, i, 16, false);
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+
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++ if (dev->wlan.hw_rro) {
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++ for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++) {
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++ u32 addr = MTK_WED_RRO_MSDU_PG_CTRL0(i) +
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++ MTK_WED_RING_OFS_COUNT;
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++
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++ if (!wed_r32(dev, addr))
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++ wed_w32(dev, addr, 1);
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++ }
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++ }
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++
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+ mtk_wed_hw_init(dev);
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+ mtk_wed_configure_irq(dev, irq_mask);
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+
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+--- a/drivers/net/ethernet/mediatek/mtk_wed.h
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++++ b/drivers/net/ethernet/mediatek/mtk_wed.h
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+@@ -17,7 +17,7 @@ struct mtk_wed_wo;
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+ struct mtk_wed_soc_data {
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+ struct {
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+ u32 tx_bm_tkid;
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+- u32 wpdma_rx_ring0;
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++ u32 wpdma_rx_ring[MTK_WED_RX_QUEUES];
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+ u32 reset_idx_tx_mask;
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+ u32 reset_idx_rx_mask;
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+ } regmap;
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+--- a/include/linux/soc/mediatek/mtk_wed.h
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++++ b/include/linux/soc/mediatek/mtk_wed.h
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+@@ -147,7 +147,7 @@ struct mtk_wed_device {
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+ u32 wpdma_tx;
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+ u32 wpdma_txfree;
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+ u32 wpdma_rx_glo;
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+- u32 wpdma_rx;
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++ u32 wpdma_rx[MTK_WED_RX_QUEUES];
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+ u32 wpdma_rx_rro[MTK_WED_RX_QUEUES];
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+ u32 wpdma_rx_pg;
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+
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Felix Fietkau