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+From 352c071bc18855238565cc6417a4c15a4e24bad8 Mon Sep 17 00:00:00 2001
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+From: Mikhail Kshevetskiy <[email protected]>
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+Date: Wed, 9 Jul 2025 12:28:09 +0300
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+Subject: [PATCH 3/5] drivers/net/airoha_eth: fix stalling in package
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+ receiving
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+
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+ARCH_DMA_MINALIGN is 64 for ARMv7a/ARMv8a architectures, but RX/TX
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+descriptors are 32 bytes long. So they may not be aligned on an
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+ARCH_DMA_MINALIGN boundary. In case of RX path, this may cause the
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+following problem
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+
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+1) Assume that a packet has arrived and the EVEN rx descriptor has been
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+ updated with the incoming data. The driver will invalidate and check
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+ the corresponding rx descriptor.
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+
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+2) Now suppose the next descriptor (ODD) has not yet completed.
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+
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+ Please note that all even descriptors starts on 64-byte boundary,
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+ and the odd ones are NOT aligned on 64-byte boundary.
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+
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+ Inspecting even descriptor, we will read the entire CPU cache line
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+ (64 bytes). So we read and sore in CPU cache also the next (odd)
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+ descriptor.
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+
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+3) Now suppose the next packet (for the odd rx descriptor) arrived
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+ while the first packet was being processed. So we have new data
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+ in memory but old data in cache.
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+
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+4) After packet processing (in arht_eth_free_pkt() function) we will
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+ cleanup the descriptor and put it back to rx queue.
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+
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+ This will call flush_dcache_range() function for the even descriptor,
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+ so the odd one will be flushed as well (it is in the same cache line).
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+ So the old data will be written to the next rx descriptor.
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+
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+5) We get a freeze. The next descriptor is empty (so the driver is
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+ waiting for packets), but the hardware will continue to receive
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+ packets on other available descriptors. This will continue until
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+ the last available rx descriptor is full. Then the hardware will
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+ also freeze.
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+
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+The problem will be solved if:
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+ * do nothing in even descriptor case,
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+ * return 2 descriptor to the queue (current and previous) in the odd
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+ descriptor case.
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+
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+If the current descriptor is even nothing will be done, so no issue
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+will arrise.
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+
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+If the current descriptor is odd, then the previous descriptor is on
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+the same cache line. Both (current and previous) descriptors are not
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+currently in use, so issue will not arrise as well.
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+
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+WARNING: The following restrictions on PKTBUFSRX must be held:
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+ * PKTBUFSRX is even,
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+ * PKTBUFSRX >= 4. Observations shows that PKTBUFSRX must be at least 8.
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+
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+The bug appears on 32-bit airoha platform, but should be present on
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+64-bit as well.
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+
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+The code was tested both on 32-bit and 64-bit airoha boards.
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+
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+Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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+---
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+ drivers/net/airoha_eth.c | 33 ++++++++++++++++++++++++++-------
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+ 1 file changed, 26 insertions(+), 7 deletions(-)
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+
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+diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
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+index aae6922f3c7..44d4773bc5d 100644
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+--- a/drivers/net/airoha_eth.c
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++++ b/drivers/net/airoha_eth.c
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+@@ -435,13 +435,14 @@ static int airoha_fe_init(struct airoha_eth *eth)
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+ return 0;
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+ }
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+
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+-static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index,
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+- uchar *rx_packet)
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++static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index)
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+ {
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+ struct airoha_qdma_desc *desc;
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++ uchar *rx_packet;
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+ u32 val;
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+
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+ desc = &q->desc[index];
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++ rx_packet = net_rx_packets[index];
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+ index = (index + 1) % q->ndesc;
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+
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+ dma_map_single(rx_packet, PKTSIZE_ALIGN, DMA_TO_DEVICE);
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+@@ -463,7 +464,7 @@ static void airoha_qdma_init_rx_desc(struct airoha_queue *q)
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+ int i;
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+
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+ for (i = 0; i < q->ndesc; i++)
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+- airoha_qdma_reset_rx_desc(q, i, net_rx_packets[i]);
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++ airoha_qdma_reset_rx_desc(q, i);
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+ }
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+
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+ static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
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+@@ -1003,12 +1004,30 @@ static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
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+ qid = 0;
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+ q = &qdma->q_rx[qid];
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+
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+- dma_map_single(packet, length, DMA_TO_DEVICE);
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++ /*
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++ * Due to cpu cache issue the airoha_qdma_reset_rx_desc() function
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++ * will always touch 2 descriptors placed on the same cacheline:
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++ * - if current descriptor is even, then current and next
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++ * descriptors will be touched
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++ * - if current descriptor is odd, then current and previous
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++ * descriptors will be touched
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++ *
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++ * Thus, to prevent possible destroying of rx queue, we should:
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++ * - do nothing in the even descriptor case,
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++ * - utilize 2 descriptors (current and previous one) in the
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++ * odd descriptor case.
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++ *
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++ * WARNING: Observations shows that PKTBUFSRX must be even and
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++ * larger than 7 for reliable driver operations.
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++ */
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++ if (q->head & 0x01) {
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++ airoha_qdma_reset_rx_desc(q, q->head - 1);
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++ airoha_qdma_reset_rx_desc(q, q->head);
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+
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+- airoha_qdma_reset_rx_desc(q, q->head, packet);
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++ airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK,
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++ FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head));
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++ }
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+
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+- airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK,
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+- FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head));
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+ q->head = (q->head + 1) % q->ndesc;
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+
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+ return 0;
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+--
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+2.51.0
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+
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Mikhail Kshevetskiy