oxnas: backport another fix for irqchip

Sungbo Eo <[email protected]> submitted another patch fixing an error
on reboot:
  irqchip/versatile-fpga: Apply clear-mask earlier

Signed-off-by: Daniel Golle <[email protected]>

target/linux/oxnas/patches-5.4/002-irqchip-versatile-fpga-Apply-clear-mask-earlier.patch

@@ -0,0 +1,58 @@
+From patchwork Sat Mar 21 13:38:42 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Sungbo Eo <[email protected]>
+X-Patchwork-Id: 11451163
+From: Sungbo Eo <[email protected]>
+To: [email protected], Linus Walleij <[email protected]>,
+ Thomas Gleixner <[email protected]>, Jason Cooper <[email protected]>,
+ Marc Zyngier <[email protected]>, [email protected],
+ [email protected]
+Subject: [PATCH] irqchip/versatile-fpga: Apply clear-mask earlier
+Date: Sat, 21 Mar 2020 22:38:42 +0900
+Message-Id: <[email protected]>
+MIME-Version: 1.0
+Sender: "linux-arm-kernel" <[email protected]>
+
+Clear its own IRQs before the parent IRQ get enabled, so that the
+remaining IRQs do not accidentally interrupt the parent IRQ controller.
+
+This patch also fixes a reboot bug on OX820 SoC, where the remaining
+rps-timer IRQ raises a GIC interrupt that is left pending. After that,
+the rps-timer IRQ is cleared during driver initialization, and there's
+no IRQ left in rps-irq when local_irq_enable() is called, which evokes
+an error message "unexpected IRQ trap".
+
+Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded interrupts from DT")
+Signed-off-by: Sungbo Eo <[email protected]>
+Cc: Neil Armstrong <[email protected]>
+Cc: Daniel Golle <[email protected]>
+---
+ drivers/irqchip/irq-versatile-fpga.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c
+index 70e2cfff8175..f1386733d3bc 100644
+--- a/drivers/irqchip/irq-versatile-fpga.c
++++ b/drivers/irqchip/irq-versatile-fpga.c
+@@ -212,6 +212,9 @@ int __init fpga_irq_of_init(struct device_node *node,
+ 	if (of_property_read_u32(node, "valid-mask", &valid_mask))
+ 		valid_mask = 0;
+ 
++	writel(clear_mask, base + IRQ_ENABLE_CLEAR);
++	writel(clear_mask, base + FIQ_ENABLE_CLEAR);
++
+ 	/* Some chips are cascaded from a parent IRQ */
+ 	parent_irq = irq_of_parse_and_map(node, 0);
+ 	if (!parent_irq) {
+@@ -221,9 +224,6 @@ int __init fpga_irq_of_init(struct device_node *node,
+ 
+ 	fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
+ 
+-	writel(clear_mask, base + IRQ_ENABLE_CLEAR);
+-	writel(clear_mask, base + FIQ_ENABLE_CLEAR);
+-
+ 	/*
+ 	 * On Versatile AB/PB, some secondary interrupts have a direct
+ 	 * pass-thru to the primary controller for IRQs 20 and 22-31 which need