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@@ -1,51 +0,0 @@
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-From 33573ea6842198cfdb5b3fdd320db9e2045855e9 Mon Sep 17 00:00:00 2001
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-From: Valentin Caron <[email protected]>
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-Date: Wed, 11 Dec 2024 11:20:04 +0100
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-Subject: [PATCH] fix(stm32mp1-fdts): re-enable RTC clock
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-
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-On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
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-yet. Re-enable it temporary to get LSE as clock source of RTC.
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-
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-Signed-off-by: Valentin Caron <[email protected]>
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-Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7
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----
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- fdts/stm32mp157c-ed1.dts | 2 ++
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- fdts/stm32mp15xx-dkx.dtsi | 2 ++
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- 2 files changed, 4 insertions(+)
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-
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---- a/fdts/stm32mp157c-ed1.dts
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-+++ b/fdts/stm32mp157c-ed1.dts
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-@@ -194,6 +194,7 @@
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- CLK_MPU_PLL1P
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- CLK_AXI_PLL2P
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- CLK_MCU_PLL3P
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-+ CLK_RTC_LSE
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- CLK_MCO1_DISABLED
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- CLK_MCO2_DISABLED
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- CLK_CKPER_HSE
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-@@ -242,6 +243,7 @@
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- DIV(DIV_APB3, 1)
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- DIV(DIV_APB4, 1)
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- DIV(DIV_APB5, 2)
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-+ DIV(DIV_RTC, 23)
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- DIV(DIV_MCO1, 0)
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- DIV(DIV_MCO2, 0)
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- >;
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---- a/fdts/stm32mp15xx-dkx.dtsi
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-+++ b/fdts/stm32mp15xx-dkx.dtsi
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-@@ -198,6 +198,7 @@
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- CLK_MPU_PLL1P
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- CLK_AXI_PLL2P
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- CLK_MCU_PLL3P
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-+ CLK_RTC_LSE
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- CLK_MCO1_DISABLED
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- CLK_MCO2_DISABLED
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- CLK_CKPER_HSE
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-@@ -246,6 +247,7 @@
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- DIV(DIV_APB3, 1)
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- DIV(DIV_APB4, 1)
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- DIV(DIV_APB5, 2)
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-+ DIV(DIV_RTC, 23)
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- DIV(DIV_MCO1, 0)
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- DIV(DIV_MCO2, 0)
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- >;
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