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@@ -0,0 +1,106 @@
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+From 526c8ee04bdbd4d8d19a583b1f3b06700229a815 Mon Sep 17 00:00:00 2001
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+From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <[email protected]>
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+Date: Wed, 4 Oct 2023 11:19:04 +0200
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+Subject: [PATCH 2/2] net: dsa: qca8k: fix potential MDIO bus conflict when
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+ accessing internal PHYs via management frames
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+MIME-Version: 1.0
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+Content-Type: text/plain; charset=UTF-8
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+Content-Transfer-Encoding: 8bit
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+
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+Besides the QCA8337 switch the Turris 1.x device has on it's MDIO bus
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+also Micron ethernet PHY (dedicated to the WAN port).
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+
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+We've been experiencing a strange behavior of the WAN ethernet
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+interface, wherein the WAN PHY started timing out the MDIO accesses, for
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+example when the interface was brought down and then back up.
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+
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+Bisecting led to commit 2cd548566384 ("net: dsa: qca8k: add support for
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+phy read/write with mgmt Ethernet"), which added support to access the
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+QCA8337 switch's internal PHYs via management ethernet frames.
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+
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+Connecting the MDIO bus pins onto an oscilloscope, I was able to see
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+that the MDIO bus was active whenever a request to read/write an
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+internal PHY register was done via an management ethernet frame.
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+
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+My theory is that when the switch core always communicates with the
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+internal PHYs via the MDIO bus, even when externally we request the
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+access via ethernet. This MDIO bus is the same one via which the switch
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+and internal PHYs are accessible to the board, and the board may have
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+other devices connected on this bus. An ASCII illustration may give more
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+insight:
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+
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+ +---------+
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+ +----| |
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+ | | WAN PHY |
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+ | +--| |
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+ | | +---------+
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+ | |
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+ | | +----------------------------------+
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+ | | | QCA8337 |
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+MDC | | | +-------+ |
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+------o-+--|--------o------------o--| | |
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+MDIO | | | | | PHY 1 |-|--to RJ45
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+--------o--|---o----+---------o--+--| | |
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+ | | | | | +-------+ |
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+ | +-------------+ | o--| | |
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+ | | MDIO MDC | | | | PHY 2 |-|--to RJ45
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+eth1 | | | o--+--| | |
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+-----------|-|port0 | | | +-------+ |
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+ | | | | o--| | |
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+ | | switch core | | | | PHY 3 |-|--to RJ45
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+ | +-------------+ o--+--| | |
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+ | | | +-------+ |
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+ | | o--| ... | |
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+ +----------------------------------+
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+
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+When we send a request to read an internal PHY register via an ethernet
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+management frame via eth1, the switch core receives the ethernet frame
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+on port 0 and then communicates with the internal PHY via MDIO. At this
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+time, other potential devices, such as the WAN PHY on Turris 1.x, cannot
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+use the MDIO bus, since it may cause a bus conflict.
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+
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+Fix this issue by locking the MDIO bus even when we are accessing the
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+PHY registers via ethernet management frames.
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+
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+Fixes: 2cd548566384 ("net: dsa: qca8k: add support for phy read/write with mgmt Ethernet")
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+Signed-off-by: Marek Behún <[email protected]>
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+Reviewed-by: Christian Marangi <[email protected]>
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+Signed-off-by: David S. Miller <[email protected]>
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+---
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+ drivers/net/dsa/qca/qca8k-8xxx.c | 11 +++++++++++
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+ 1 file changed, 11 insertions(+)
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+
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+--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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++++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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+@@ -665,6 +665,15 @@ qca8k_phy_eth_command(struct qca8k_priv
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+ goto err_read_skb;
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+ }
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+
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++ /* It seems that accessing the switch's internal PHYs via management
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++ * packets still uses the MDIO bus within the switch internally, and
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++ * these accesses can conflict with external MDIO accesses to other
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++ * devices on the MDIO bus.
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++ * We therefore need to lock the MDIO bus onto which the switch is
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++ * connected.
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++ */
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++ mutex_lock(&priv->bus->mdio_lock);
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++
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+ /* Actually start the request:
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+ * 1. Send mdio master packet
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+ * 2. Busy Wait for mdio master command
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+@@ -677,6 +686,7 @@ qca8k_phy_eth_command(struct qca8k_priv
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+ mgmt_master = priv->mgmt_master;
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+ if (!mgmt_master) {
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+ mutex_unlock(&mgmt_eth_data->mutex);
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++ mutex_unlock(&priv->bus->mdio_lock);
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+ ret = -EINVAL;
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+ goto err_mgmt_master;
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+ }
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+@@ -764,6 +774,7 @@ exit:
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+ QCA8K_ETHERNET_TIMEOUT);
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+
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+ mutex_unlock(&mgmt_eth_data->mutex);
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++ mutex_unlock(&priv->bus->mdio_lock);
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+
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+ return ret;
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+
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Christian Marangi