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+From 0bc16c6a8744a1c0293a31253020205b312895d3 Mon Sep 17 00:00:00 2001
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+From: Tianling Shen <[email protected]>
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+Date: Sat, 23 Dec 2023 12:00:07 +0800
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+Subject: [PATCH] board: rockchip: Add support for FriendlyARM NanoPi R2C Plus
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+
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+The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
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+eMMC flash (8G) included.
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+
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+The device tree is taken from the kernel v6.5.
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+
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+Signed-off-by: Tianling Shen <[email protected]>
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+Reviewed-by: Kever Yang <[email protected]>
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+---
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+ arch/arm/dts/Makefile | 1 +
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+ .../dts/rk3328-nanopi-r2c-plus-u-boot.dtsi | 9 ++
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+ arch/arm/dts/rk3328-nanopi-r2c-plus.dts | 33 +++++
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+ board/rockchip/evb_rk3328/MAINTAINERS | 6 +
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+ configs/nanopi-r2c-plus-rk3328_defconfig | 114 ++++++++++++++++++
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+ 5 files changed, 163 insertions(+)
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+ create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
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+ create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus.dts
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+ create mode 100644 configs/nanopi-r2c-plus-rk3328_defconfig
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+
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+--- a/arch/arm/dts/Makefile
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++++ b/arch/arm/dts/Makefile
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+@@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
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+ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
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+ rk3328-evb.dtb \
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+ rk3328-nanopi-r2c.dtb \
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++ rk3328-nanopi-r2c-plus.dtb \
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+ rk3328-nanopi-r2s.dtb \
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+ rk3328-orangepi-r1-plus.dtb \
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+ rk3328-orangepi-r1-plus-lts.dtb \
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+--- /dev/null
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++++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
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+@@ -0,0 +1,9 @@
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++// SPDX-License-Identifier: GPL-2.0-or-later
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++
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++#include "rk3328-nanopi-r2c-u-boot.dtsi"
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++
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++/ {
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++ chosen {
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++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
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++ };
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++};
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+--- /dev/null
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++++ b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts
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+@@ -0,0 +1,33 @@
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++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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++/*
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++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
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++ * (http://www.friendlyarm.com)
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++ *
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++ * Copyright (c) 2023 Tianling Shen <[email protected]>
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++ */
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++
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++/dts-v1/;
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++#include "rk3328-nanopi-r2c.dts"
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++
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++/ {
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++ model = "FriendlyElec NanoPi R2C Plus";
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++ compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
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++
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++ aliases {
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++ mmc1 = &emmc;
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++ };
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++};
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++
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++&emmc {
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++ bus-width = <8>;
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++ cap-mmc-highspeed;
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++ max-frequency = <150000000>;
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++ mmc-ddr-1_8v;
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++ mmc-hs200-1_8v;
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++ non-removable;
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++ pinctrl-names = "default";
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++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
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++ vmmc-supply = <&vcc_io_33>;
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++ vqmmc-supply = <&vcc18_emmc>;
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++ status = "okay";
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++};
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+--- a/board/rockchip/evb_rk3328/MAINTAINERS
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++++ b/board/rockchip/evb_rk3328/MAINTAINERS
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+@@ -11,6 +11,12 @@ S: Maintained
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+ F: configs/nanopi-r2c-rk3328_defconfig
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+ F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
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+
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++NANOPI-R2C-PLUS-RK3328
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++M: Tianling Shen <[email protected]>
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++S: Maintained
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++F: configs/nanopi-r2c-plus-rk3328_defconfig
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++F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
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++
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+ NANOPI-R2S-RK3328
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+ M: David Bauer <[email protected]>
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+ S: Maintained
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+--- /dev/null
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++++ b/configs/nanopi-r2c-plus-rk3328_defconfig
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+@@ -0,0 +1,114 @@
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++CONFIG_ARM=y
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++CONFIG_SKIP_LOWLEVEL_INIT=y
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++CONFIG_COUNTER_FREQUENCY=24000000
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++CONFIG_ARCH_ROCKCHIP=y
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++CONFIG_TEXT_BASE=0x00200000
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++CONFIG_SPL_GPIO=y
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++CONFIG_NR_DRAM_BANKS=1
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++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
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++CONFIG_SF_DEFAULT_SPEED=20000000
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++CONFIG_ENV_OFFSET=0x3F8000
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++CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus"
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++CONFIG_DM_RESET=y
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++CONFIG_ROCKCHIP_RK3328=y
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++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
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++CONFIG_TPL_LIBCOMMON_SUPPORT=y
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++CONFIG_TPL_LIBGENERIC_SUPPORT=y
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++CONFIG_SPL_DRIVERS_MISC=y
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++CONFIG_SPL_STACK_R_ADDR=0x600000
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++CONFIG_SPL_STACK=0x400000
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++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
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++CONFIG_DEBUG_UART_BASE=0xFF130000
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++CONFIG_DEBUG_UART_CLOCK=24000000
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++CONFIG_SYS_LOAD_ADDR=0x800800
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++CONFIG_DEBUG_UART=y
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++# CONFIG_ANDROID_BOOT_IMAGE is not set
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++CONFIG_FIT=y
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++CONFIG_FIT_VERBOSE=y
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++CONFIG_SPL_LOAD_FIT=y
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++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
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++# CONFIG_DISPLAY_CPUINFO is not set
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++CONFIG_DISPLAY_BOARDINFO_LATE=y
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++CONFIG_MISC_INIT_R=y
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++CONFIG_SPL_MAX_SIZE=0x40000
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++CONFIG_SPL_PAD_TO=0x7f8000
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++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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++CONFIG_SPL_BSS_START_ADDR=0x2000000
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++CONFIG_SPL_BSS_MAX_SIZE=0x2000
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++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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++CONFIG_SPL_STACK_R=y
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++CONFIG_SPL_I2C=y
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++CONFIG_SPL_POWER=y
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++CONFIG_SPL_ATF=y
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++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
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++CONFIG_CMD_BOOTZ=y
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++CONFIG_CMD_GPT=y
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++CONFIG_CMD_MMC=y
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++CONFIG_CMD_USB=y
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++# CONFIG_CMD_SETEXPR is not set
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++CONFIG_CMD_TIME=y
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++CONFIG_SPL_OF_CONTROL=y
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++CONFIG_TPL_OF_CONTROL=y
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++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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++CONFIG_TPL_OF_PLATDATA=y
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++CONFIG_ENV_IS_IN_MMC=y
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++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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++CONFIG_SYS_MMC_ENV_DEV=1
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++CONFIG_NET_RANDOM_ETHADDR=y
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++CONFIG_TPL_DM=y
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++CONFIG_REGMAP=y
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++CONFIG_SPL_REGMAP=y
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++CONFIG_TPL_REGMAP=y
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++CONFIG_SYSCON=y
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++CONFIG_SPL_SYSCON=y
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++CONFIG_TPL_SYSCON=y
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++CONFIG_CLK=y
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++CONFIG_SPL_CLK=y
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++CONFIG_FASTBOOT_BUF_ADDR=0x800800
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++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
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++CONFIG_ROCKCHIP_GPIO=y
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++CONFIG_SYS_I2C_ROCKCHIP=y
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++CONFIG_MISC=y
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++CONFIG_MMC_DW=y
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++CONFIG_MMC_DW_ROCKCHIP=y
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++CONFIG_ETH_DESIGNWARE=y
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++CONFIG_GMAC_ROCKCHIP=y
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++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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++CONFIG_PINCTRL=y
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++CONFIG_SPL_PINCTRL=y
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++CONFIG_DM_PMIC=y
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++CONFIG_PMIC_RK8XX=y
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++CONFIG_SPL_PMIC_RK8XX=y
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++CONFIG_SPL_DM_REGULATOR=y
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++CONFIG_REGULATOR_PWM=y
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++CONFIG_DM_REGULATOR_FIXED=y
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++CONFIG_SPL_DM_REGULATOR_FIXED=y
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++CONFIG_REGULATOR_RK8XX=y
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++CONFIG_PWM_ROCKCHIP=y
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++CONFIG_RAM=y
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++CONFIG_SPL_RAM=y
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++CONFIG_TPL_RAM=y
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++CONFIG_BAUDRATE=1500000
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++CONFIG_DEBUG_UART_SHIFT=2
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++CONFIG_SYS_NS16550_MEM32=y
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++CONFIG_SYSINFO=y
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++CONFIG_SYSRESET=y
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++# CONFIG_TPL_SYSRESET is not set
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++CONFIG_USB=y
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++CONFIG_USB_XHCI_HCD=y
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++CONFIG_USB_EHCI_HCD=y
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++CONFIG_USB_EHCI_GENERIC=y
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++CONFIG_USB_OHCI_HCD=y
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++CONFIG_USB_OHCI_GENERIC=y
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++CONFIG_USB_DWC2=y
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++CONFIG_USB_DWC3=y
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++# CONFIG_USB_DWC3_GADGET is not set
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++CONFIG_USB_DWC3_GENERIC=y
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++CONFIG_USB_GADGET=y
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++CONFIG_USB_GADGET_DWC2_OTG=y
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++CONFIG_SPL_TINY_MEMSET=y
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++CONFIG_TPL_TINY_MEMSET=y
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++CONFIG_ERRNO_STR=y
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Tianling Shen