arm-trusted-firmware-mediatek: import patchset for Fidelix flash on SNFI

Import pending patches to set pinconf settings for SPI-NAND pins on
MT7622 identical to what the old proprietary preloader did.

Should further increase the reliability of some SNFI-attached SPI-NAND
flash chips.

Link: https://github.com/mtk-openwrt/arm-trusted-firmware/pull/7
Signed-off-by: Daniel Golle <[email protected]>

package/boot/arm-trusted-firmware-mediatek/Makefile

@@ -9,7 +9,7 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=arm-trusted-firmware-mediatek
-PKG_RELEASE:=1
+PKG_RELEASE:=2
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git

package/boot/arm-trusted-firmware-mediatek/patches/0001-mediatek-snfi-FM35Q1GA-is-x4-only.patch

@@ -0,0 +1,23 @@
+From fb2a2b669ec9bbf5c448d4b56499bc83de075c93 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Thu, 29 Feb 2024 18:01:08 +0000
+Subject: [PATCH 1/3] mediatek: snfi: FM35Q1GA is x4-only
+
+Dont allow x2 read and cache read operations on FM35Q1GA.
+
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
++++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
+@@ -423,7 +423,7 @@ static const struct snand_flash_info sna
+ 
+ 	SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
+ 		   SNAND_MEMORG_1G_2K_64,
+-		   &snand_cap_read_from_cache_x4,
++		   &snand_cap_read_from_cache_x4_only,
+ 		   &snand_cap_program_load_x4),
+ 
+ 	SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),

package/boot/arm-trusted-firmware-mediatek/patches/0002-mediatek-snfi-adjust-pin-drive-strength-for-Fidelix-.patch

@@ -0,0 +1,99 @@
+From 6470986f037880ce76960c369d6e5a5270e7ce32 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Sun, 10 Mar 2024 15:39:07 +0000
+Subject: [PATCH 2/3] mediatek: snfi: adjust pin drive strength for Fidelix
+ SPI-NAND
+
+It seems like we might need to adjust the pin driver strength to 12mA
+for Fidelix SPI-NAND chip on MT7622 to avoid SPI data corruption on
+some devices.
+
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ .../apsoc_common/drivers/snfi/mtk-snand-def.h |  7 +++++
+ .../apsoc_common/drivers/snfi/mtk-snand-ids.c |  4 ++-
+ .../apsoc_common/drivers/snfi/mtk-snand.c     | 30 +++++++++++++++++++
+ 3 files changed, 40 insertions(+), 1 deletion(-)
+
+--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
++++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
+@@ -86,6 +86,12 @@ struct snand_mem_org {
+ 
+ typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx);
+ 
++enum snand_drv {
++	SNAND_DRV_NO_CHANGE = 0,
++	SNAND_DRV_8mA = 8,
++	SNAND_DRV_12mA = 12,
++};
++
+ struct snand_flash_info {
+ 	const char *model;
+ 	struct snand_id id;
+@@ -93,6 +99,7 @@ struct snand_flash_info {
+ 	const struct snand_io_cap *cap_rd;
+ 	const struct snand_io_cap *cap_pl;
+ 	snand_select_die_t select_die;
++	enum snand_drv drv;
+ };
+ 
+ #define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \
+--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
++++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
+@@ -424,7 +424,9 @@ static const struct snand_flash_info sna
+ 	SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
+ 		   SNAND_MEMORG_1G_2K_64,
+ 		   &snand_cap_read_from_cache_x4_only,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 
+ 	SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
+ 		   SNAND_MEMORG_1G_2K_128,
+--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
++++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
+@@ -1845,6 +1845,33 @@ static int mtk_snand_id_probe(struct mtk
+ 	return -EINVAL;
+ }
+ 
++#define MT7622_GPIO_BASE    (void *)0x10211000
++#define MT7622_GPIO_DRIV(x) (MT7622_GPIO_BASE + 0x900 + 0x10 * x)
++
++void mtk_mt7622_snand_adjust_drive(void *dev, enum snand_drv drv)
++{
++	uint32_t e4, e8;
++
++	e4 = readl(MT7622_GPIO_DRIV(6)) & ~(0x3f00);
++	e8 = readl(MT7622_GPIO_DRIV(7)) & ~(0x3f00);
++
++	switch (drv) {
++	case SNAND_DRV_8mA:
++		e4 |= 0x3f00;
++		break;
++	case SNAND_DRV_12mA:
++		e8 |= 0x3f00;
++		break;
++	default:
++		return;
++	}
++
++	snand_log_chip(dev, "adjusting SPI-NAND pin drive strength to %umA\n", drv);
++
++	writel(e4, MT7622_GPIO_DRIV(6));
++	writel(e8, MT7622_GPIO_DRIV(7));
++}
++
+ int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
+ 		   struct mtk_snand **psnf)
+ {
+@@ -1888,6 +1915,9 @@ int mtk_snand_init(void *dev, const stru
+ 	if (ret)
+ 		return ret;
+ 
++	if (pdata->soc == SNAND_SOC_MT7622 && snand_info->drv)
++		mtk_mt7622_snand_adjust_drive(dev, snand_info->drv);
++
+ 	rawpage_size = snand_info->memorg.pagesize +
+ 		       snand_info->memorg.sparesize;
+ 

package/boot/arm-trusted-firmware-mediatek/patches/0003-mediatek-snfi-adjust-drive-strength-to-12mA-like-old.patch

@@ -0,0 +1,135 @@
+From 40a3661bebb3d738ab95b7de66e9d8382d5b9ab1 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Sun, 10 Mar 2024 17:48:09 +0000
+Subject: [PATCH 3/3] mediatek: snfi: adjust drive strength to 12mA like old
+ loader does
+
+In addition to FM35X1GA, also change the driver strength to 12mA for
+all chips where this is done by the old/legacy U-Boot:
+ * Winbond 512Mb
+ * Winbond 1Gb
+ * Winbond 2Gb
+ * GD5F4GQ4UBYIG
+ * GD5F4GQ4UAYIG
+ * GD5F1GQ4UX
+ * GD5F1GQ4UE
+ * GD5F2GQ4UX
+ * GD5F2GQ4UE
+
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ .../apsoc_common/drivers/snfi/mtk-snand-ids.c | 59 ++++++++++++++-----
+ 1 file changed, 44 insertions(+), 15 deletions(-)
+
+--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
++++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
+@@ -80,65 +80,94 @@ static const struct snand_flash_info sna
+ 	SNAND_INFO("W25N512GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x20),
+ 		   SNAND_MEMORG_512M_2K_64,
+ 		   &snand_cap_read_from_cache_quad,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("W25N01GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x21),
+ 		   SNAND_MEMORG_1G_2K_64,
+ 		   &snand_cap_read_from_cache_quad,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("W25M02GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xab, 0x21),
+ 		   SNAND_MEMORG_2G_2K_64_2D,
+ 		   &snand_cap_read_from_cache_quad,
+ 		   &snand_cap_program_load_x4,
+-		   mtk_snand_winbond_select_die),
++		   mtk_snand_winbond_select_die,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("W25N02KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22),
+ 		   SNAND_MEMORG_2G_2K_128,
+ 		   &snand_cap_read_from_cache_quad,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 
+ 	SNAND_INFO("GD5F1GQ4UAWxx", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x10),
+ 		   SNAND_MEMORG_1G_2K_64,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F1GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd1),
+ 		   SNAND_MEMORG_1G_2K_128,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F1GQ4UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd9),
+ 		   SNAND_MEMORG_1G_2K_64,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F1GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf1),
+ 		   SNAND_MEMORG_1G_2K_64,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),
+ 		   SNAND_MEMORG_2G_2K_128,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F2GQ5UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x32),
+ 		   SNAND_MEMORG_2G_2K_64,
+ 		   &snand_cap_read_from_cache_quad_a8d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F2GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf2),
+ 		   SNAND_MEMORG_2G_2K_64,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F4GQ4UBxIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd4),
+ 		   SNAND_MEMORG_4G_4K_256,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F4GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf4),
+ 		   SNAND_MEMORG_4G_2K_64,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F2GQ5UExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52),
+ 		   SNAND_MEMORG_2G_2K_128,
+ 		   &snand_cap_read_from_cache_quad_a8d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 	SNAND_INFO("GD5F4GQ4UCxIG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4),
+ 		   SNAND_MEMORG_4G_4K_256,
+ 		   &snand_cap_read_from_cache_quad_q2d,
+-		   &snand_cap_program_load_x4),
++		   &snand_cap_program_load_x4,
++		   NULL,
++		   SNAND_DRV_12mA),
+ 
+ 	SNAND_INFO("MX35LF1GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x12),
+ 		   SNAND_MEMORG_1G_2K_64,