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@@ -30,29 +30,6 @@ Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-co
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config LASAT
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bool "LASAT Networks platforms"
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select CEVT_R4K
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-@@ -677,6 +680,7 @@ source "arch/mips/alchemy/Kconfig"
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- source "arch/mips/basler/excite/Kconfig"
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- source "arch/mips/bcm63xx/Kconfig"
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- source "arch/mips/jazz/Kconfig"
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-+source "arch/mips/jz4740/Kconfig"
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- source "arch/mips/lasat/Kconfig"
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- source "arch/mips/pmc-sierra/Kconfig"
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- source "arch/mips/sgi-ip27/Kconfig"
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-@@ -1913,6 +1917,14 @@ config NR_CPUS
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-
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- source "kernel/time/Kconfig"
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-
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-+# the value of (max order + 1)
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-+config FORCE_MAX_ZONEORDER
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-+ prompt "MAX_ZONEORDER"
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-+ int
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-+ default "12"
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-+ help
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-+ The max memory that can be allocated = 4KB * 2^(CONFIG_FORCE_MAX_ZONEORDER - 1)
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-+
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- #
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- # Timer Interrupt Frequency Configuration
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- #
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -184,6 +184,14 @@ cflags-$(CONFIG_AR7) += -I$(srctree)/ar
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@@ -157,7 +134,7 @@ Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-co
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+/*
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+ * Valid machtype for group INGENIC
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+ */
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-+#define MACH_INGENIC_JZ4720 0 /* JZ4730 SOC */
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++#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */
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+#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
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+
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#define CL_SIZE COMMAND_LINE_SIZE
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@@ -199,17 +176,6 @@ Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-co
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CPU_LAST
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};
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---- a/arch/mips/include/asm/mach-generic/irq.h
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-+++ b/arch/mips/include/asm/mach-generic/irq.h
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-@@ -9,7 +9,7 @@
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- #define __ASM_MACH_GENERIC_IRQ_H
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-
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- #ifndef NR_IRQS
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--#define NR_IRQS 128
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-+#define NR_IRQS 256
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- #endif
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-
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- #ifdef CONFIG_I8259
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--- a/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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@@ -17,6 +17,58 @@
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@@ -535,18 +501,6 @@ Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-co
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+#endif /* CONFIG_JZRISC */
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+
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#endif /* _ASM_R4KCACHE_H */
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---- a/arch/mips/include/asm/suspend.h
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-+++ b/arch/mips/include/asm/suspend.h
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-@@ -2,6 +2,9 @@
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- #define __ASM_SUSPEND_H
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-
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- static inline int arch_prepare_suspend(void) { return 0; }
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-+#if defined(CONFIG_PM) && defined(CONFIG_JZSOC)
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-+extern int jz_pm_init(void);
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-+#endif
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-
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- /* References to section boundaries */
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- extern const void __nosave_begin, __nosave_end;
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--- a/arch/mips/kernel/cpu-probe.c
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+++ b/arch/mips/kernel/cpu-probe.c
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@@ -160,6 +160,7 @@ void __init check_wait(void)
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@@ -557,7 +511,7 @@ Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-co
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cpu_wait = r4k_wait;
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break;
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-@@ -902,6 +903,23 @@ static inline void cpu_probe_cavium(stru
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+@@ -902,6 +903,21 @@ static inline void cpu_probe_cavium(stru
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}
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}
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@@ -568,8 +522,6 @@ Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-co
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+ switch (c->processor_id & 0xff00) {
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+ case PRID_IMP_JZRISC:
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+ c->cputype = CPU_JZRISC;
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-+ c->isa_level = MIPS_CPU_ISA_M32R1;
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-+ c->tlbsize = 32;
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+ __cpu_name[cpu] = "Ingenic JZRISC";
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+ break;
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+ default:
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@@ -591,56 +543,6 @@ Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-co
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}
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BUG_ON(!__cpu_name[cpu]);
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---- a/arch/mips/mm/c-r4k.c
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-+++ b/arch/mips/mm/c-r4k.c
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-@@ -928,6 +928,36 @@ static void __cpuinit probe_pcache(void)
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- c->dcache.waybit = 0;
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- break;
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-
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-+ case CPU_JZRISC:
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-+ config1 = read_c0_config1();
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-+ config1 = (config1 >> 22) & 0x07;
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-+ if (config1 == 0x07)
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-+ config1 = 10;
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-+ else
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-+ config1 = config1 + 11;
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-+ config1 += 2;
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-+ icache_size = (1 << config1);
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-+ c->icache.linesz = 32;
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-+ c->icache.ways = 4;
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-+ c->icache.waybit = __ffs(icache_size / c->icache.ways);
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-+
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-+ config1 = read_c0_config1();
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-+ config1 = (config1 >> 13) & 0x07;
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-+ if (config1 == 0x07)
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-+ config1 = 10;
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-+ else
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-+ config1 = config1 + 11;
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-+ config1 += 2;
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-+ dcache_size = (1 << config1);
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-+ c->dcache.linesz = 32;
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-+ c->dcache.ways = 4;
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-+ c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
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-+
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-+ c->dcache.flags = 0;
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-+ c->options |= MIPS_CPU_PREFETCH;
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-+
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-+ break;
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-+
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- default:
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- if (!(config & MIPS_CONF_M))
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- panic("Don't know how to probe P-caches on this cpu.");
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---- a/arch/mips/mm/cache.c
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-+++ b/arch/mips/mm/cache.c
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-@@ -52,6 +52,8 @@ void (*_dma_cache_wback)(unsigned long s
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- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
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-
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- EXPORT_SYMBOL(_dma_cache_wback_inv);
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-+EXPORT_SYMBOL(_dma_cache_wback);
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-+EXPORT_SYMBOL(_dma_cache_inv);
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-
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- #endif /* CONFIG_DMA_NONCOHERENT */
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-
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -389,6 +389,11 @@ static void __cpuinit build_tlb_write_en
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Lars-Peter Clausen