imx6: kernel: update 3.14 pcie patches

Remove old irq map patch and replace it with the propper upstream patches
allowing IMX6 PCIe devices behind PCIe switches to work properly.

Signed-off-by: Tim Harvey <[email protected]>

SVN-Revision: 41004

target/linux/imx6/patches-3.14/0055-ARM_dts_imx_fix-invallid-#address-cells-value.patch

@@ -0,0 +1,55 @@
+commit d644122d8420c425fdf5c74e50d440d5f146bc0c
+Author: Tim Harvey <[email protected]>
+Date:   Thu Mar 13 09:37:51 2014 -0700
+
+    ARM: dts: imx: fix invalid #address-cells value
+    
+    The invalid value of #address-cells in the imx6 pcie host controller node
+    causes of_irq_parse_raw() to incorrectly advance through an interrupt-map
+    table of more than one interrupt. We also take the opportunity to drop the
+    unused #size-cells here.
+    
+    This patch resolves this issue and allows proper interrupt mapping for an
+    imx6 pcie host connected to a P2P bridge when using legacy interrupts.
+    
+    Signed-off-by: Tim Harvey <[email protected]>
+    Cc: Jason Gunthorpe <[email protected]>
+    Cc: Jingoo Han <[email protected]>
+    Cc: Lucas Stach <[email protected]>
+    Cc: Mark Rutland <[email protected]>
+    Cc: linux-samsung-soc <[email protected]>
+    Cc: Richard Zhu <[email protected]>
+    Cc: Sascha Hauer <[email protected]>
+    Cc: Arnd Bergmann <[email protected]>
+    Cc: Stephen Warren <[email protected]>
+    Cc: Bjorn Helgaas <[email protected]>
+    Cc: Simon Horman <[email protected]>
+    Cc: Thierry Reding <[email protected]>
+    Cc: Ben Dooks <[email protected]>
+    Cc: linux-tegra <[email protected]>
+    Cc: Kukjin Kim <[email protected]>
+    Cc: Shawn Guo <[email protected]>
+    Cc: Grant Likely <[email protected]>
+
+--- a/arch/arm/boot/dts/imx6qdl.dtsi
++++ b/arch/arm/boot/dts/imx6qdl.dtsi
+@@ -38,8 +38,6 @@
+ 	intc: interrupt-controller@00a01000 {
+ 		compatible = "arm,cortex-a9-gic";
+ 		#interrupt-cells = <3>;
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+ 		interrupt-controller;
+ 		reg = <0x00a01000 0x1000>,
+ 		      <0x00a00100 0x100>;
+--- a/arch/arm/boot/dts/imx6sl.dtsi
++++ b/arch/arm/boot/dts/imx6sl.dtsi
+@@ -44,8 +44,6 @@
+ 	intc: interrupt-controller@00a01000 {
+ 		compatible = "arm,cortex-a9-gic";
+ 		#interrupt-cells = <3>;
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+ 		interrupt-controller;
+ 		reg = <0x00a01000 0x1000>,
+ 		      <0x00a00100 0x100>;

target/linux/imx6/patches-3.14/0060-pci_designware_use-new-OF-interrupt-mapping-when-possible.patch

@@ -0,0 +1,58 @@
+commit 62fe03d1dd629a98c6da86cabb2a98b85e89d516
+Author: Lucas Stach <[email protected]>
+Date:   Wed Mar 5 14:25:51 2014 +0100
+
+    PCI: designware: use new OF interrupt mapping when possible
+    
+    This is the recommended method of doing the IRQ
+    mapping. For old devicetrees we fall back to the
+    previous practice.
+    
+    Signed-off-by: Lucas Stach <[email protected]>
+    Acked-by: Arnd Bergmann <[email protected]>
+    Acked-by: Jingoo Han <[email protected]>
+    Reviewed-by: Marek Vasut <[email protected]>
+
+--- a/drivers/pci/host/pcie-designware.c
++++ b/drivers/pci/host/pcie-designware.c
+@@ -17,6 +17,7 @@
+ #include <linux/module.h>
+ #include <linux/msi.h>
+ #include <linux/of_address.h>
++#include <linux/of_pci.h>
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
+ #include <linux/types.h>
+@@ -492,7 +493,7 @@ int __init dw_pcie_host_init(struct pcie
+ 	dw_pci.nr_controllers = 1;
+ 	dw_pci.private_data = (void **)&pp;
+ 
+-	pci_common_init(&dw_pci);
++	pci_common_init_dev(pp->dev, &dw_pci);
+ 	pci_assign_unassigned_resources();
+ #ifdef CONFIG_PCI_DOMAINS
+ 	dw_pci.domain++;
+@@ -725,7 +726,7 @@ static struct pci_bus *dw_pcie_scan_bus(
+ 
+ 	if (pp) {
+ 		pp->root_bus_nr = sys->busnr;
+-		bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
++		bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
+ 					sys, &sys->resources);
+ 	} else {
+ 		bus = NULL;
+@@ -738,8 +739,13 @@ static struct pci_bus *dw_pcie_scan_bus(
+ static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
+ 	struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
++	int irq;
+ 
+-	return pp->irq;
++	irq = of_irq_parse_and_map_pci(dev, slot, pin);
++	if (!irq)
++		irq = pp->irq;
++
++	return irq;
+ }
+ 
+ static void dw_pcie_add_bus(struct pci_bus *bus)

target/linux/imx6/patches-3.14/0065-ARM-dts-imx6-add-PCIe-interrupt-mapping-properties.patch

@@ -0,0 +1,38 @@
+From 07134a365f1c4be6e840a00ae452d1593f15c5fc Mon Sep 17 00:00:00 2001
+From: Lucas Stach <[email protected]>
+Date: Wed, 5 Mar 2014 14:25:50 +0100
+Subject: [PATCH] ARM: dts: imx6: add PCIe interrupt mapping properties
+
+As defined by the common PCI bindings.
+
+Signed-off-by: Lucas Stach <[email protected]>
+Acked-by: Arnd Bergmann <[email protected]>
+Signed-off-by: Shawn Guo <[email protected]>
+---
+ arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl.dtsi
++++ b/arch/arm/boot/dts/imx6qdl.dtsi
+@@ -10,6 +10,8 @@
+  * http://www.gnu.org/copyleft/gpl.html
+  */
+ 
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
+ #include "skeleton.dtsi"
+ 
+ / {
+@@ -125,6 +127,12 @@
+ 				  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
+ 			num-lanes = <1>;
+ 			interrupts = <0 123 0x04>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0x7>;
++			interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++			                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++			                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++			                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
+ 			clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
+ 			status = "disabled";

target/linux/imx6/patches-3.14/200-PCI-imx6-add-support-for-legacy-irqs.patch

@@ -1,43 +0,0 @@
-From: Tim Harvey <[email protected]>
-Subject: [PATCH] PCI: imx6: add support for legacy irqs
-
-The i.MX6 supports legacy IRQ's via 155,154,153,152.  When devices
-are behind a PCIe-to-PCIe switch (at least for the TI XIO2001) the 
-mapping is reversed from when they are behind a PCIe switch.
-
-This patch still needs some review and clarification before going
-upstream.
----
- drivers/pci/host/pcie-designware.c | 21 ++++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
---- a/drivers/pci/host/pcie-designware.c
-+++ b/drivers/pci/host/pcie-designware.c
-@@ -739,7 +739,26 @@ static int dw_pcie_map_irq(const struct
- {
- 	struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
- 
--	return pp->irq;
-+	/* TI XIO2001 PCIe-to-PCI bridge IRQs are flipped it seems */
-+	if ( dev->bus && dev->bus->self
-+	 && (dev->bus->self->vendor == 0x104c)
-+	 && (dev->bus->self->device == 0x8240)) {
-+		switch (pin) {
-+		case 1: return pp->irq - 3;
-+		case 2: return pp->irq - 2;
-+		case 3: return pp->irq - 1;
-+		case 4: return pp->irq;
-+		default: return -1;
-+		}
-+	} else {
-+		switch (pin) {
-+		case 1: return pp->irq;
-+		case 2: return pp->irq - 1;
-+		case 3: return pp->irq - 2;
-+		case 4: return pp->irq - 3;
-+		default: return -1;
-+		}
-+	}
- }
- 
- static void dw_pcie_add_bus(struct pci_bus *bus)