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@@ -0,0 +1,124 @@
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+From d34db686a3d74bd564bfce2ada15011c556269fc Mon Sep 17 00:00:00 2001
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+From: Sergio Paracuellos <[email protected]>
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+Date: Tue, 10 Sep 2024 06:40:23 +0200
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+Subject: [PATCH 2/3] clk: ralink: mtmips: fix clocks probe order in oldest
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+ ralink SoCs
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+
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+Base clocks are the first in being probed and are real dependencies of the
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+rest of fixed, factor and peripheral clocks. For old ralink SoCs RT2880,
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+RT305x and RT3883 'xtal' must be defined first since in any other case,
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+when fixed clocks are probed they are delayed until 'xtal' is probed so the
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+following warning appears:
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+
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+ WARNING: CPU: 0 PID: 0 at drivers/clk/ralink/clk-mtmips.c:499 rt3883_bus_recalc_rate+0x98/0x138
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+ Modules linked in:
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+ CPU: 0 PID: 0 Comm: swapper Not tainted 6.6.43 #0
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+ Stack : 805e58d0 00000000 00000004 8004f950 00000000 00000004 00000000 00000000
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+ 80669c54 80830000 80700000 805ae570 80670068 00000001 80669bf8 00000000
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+ 00000000 00000000 805ae570 80669b38 00000020 804db7dc 00000000 00000000
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+ 203a6d6d 80669b78 80669e48 70617773 00000000 805ae570 00000000 00000009
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+ 00000000 00000001 00000004 00000001 00000000 00000000 83fe43b0 00000000
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+ ...
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+ Call Trace:
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+ [<800065d0>] show_stack+0x64/0xf4
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+ [<804bca14>] dump_stack_lvl+0x38/0x60
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+ [<800218ac>] __warn+0x94/0xe4
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+ [<8002195c>] warn_slowpath_fmt+0x60/0x94
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+ [<80259ff8>] rt3883_bus_recalc_rate+0x98/0x138
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+ [<80254530>] __clk_register+0x568/0x688
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+ [<80254838>] of_clk_hw_register+0x18/0x2c
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+ [<8070b910>] rt2880_clk_of_clk_init_driver+0x18c/0x594
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+ [<8070b628>] of_clk_init+0x1c0/0x23c
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+ [<806fc448>] plat_time_init+0x58/0x18c
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+ [<806fdaf0>] time_init+0x10/0x6c
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+ [<806f9bc4>] start_kernel+0x458/0x67c
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+
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+ ---[ end trace 0000000000000000 ]---
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+
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+When this driver was mainlined we could not find any active users of old
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+ralink SoCs so we cannot perform any real tests for them. Now, one user
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+of a Belkin f9k1109 version 1 device which uses RT3883 SoC appeared and
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+reported some issues in openWRT:
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+- https://github.com/openwrt/openwrt/issues/16054
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+
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+Thus, define a 'rt2880_xtal_recalc_rate()' just returning the expected
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+frequency 40Mhz and use it along the old ralink SoCs to have a correct
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+boot trace with no warnings and a working clock plan from the beggining.
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+
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+Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
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+Signed-off-by: Sergio Paracuellos <[email protected]>
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+Link: https://lore.kernel.org/r/[email protected]
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+Signed-off-by: Stephen Boyd <[email protected]>
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+---
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+ drivers/clk/ralink/clk-mtmips.c | 21 +++++++++++++--------
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+ 1 file changed, 13 insertions(+), 8 deletions(-)
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+
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+--- a/drivers/clk/ralink/clk-mtmips.c
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++++ b/drivers/clk/ralink/clk-mtmips.c
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+@@ -263,10 +263,6 @@ err_clk_unreg:
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+ .rate = _rate \
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+ }
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+
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+-static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
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+- CLK_FIXED("xtal", NULL, 40000000)
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+-};
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+-
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+ static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
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+ CLK_FIXED("xtal", NULL, 40000000),
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+ CLK_FIXED("periph", "xtal", 40000000)
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+@@ -371,6 +367,12 @@ static inline struct mtmips_clk *to_mtmi
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+ return container_of(hw, struct mtmips_clk, hw);
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+ }
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+
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++static unsigned long rt2880_xtal_recalc_rate(struct clk_hw *hw,
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++ unsigned long parent_rate)
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++{
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++ return 40000000;
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++}
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++
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+ static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+ {
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+@@ -682,10 +684,12 @@ static unsigned long mt76x8_cpu_recalc_r
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+ }
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+
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+ static struct mtmips_clk rt2880_clks_base[] = {
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++ { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
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+ { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
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+ };
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+
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+ static struct mtmips_clk rt305x_clks_base[] = {
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++ { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
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+ { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
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+ };
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+
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+@@ -695,6 +699,7 @@ static struct mtmips_clk rt3352_clks_bas
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+ };
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+
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+ static struct mtmips_clk rt3883_clks_base[] = {
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++ { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
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+ { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
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+ { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
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+ };
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+@@ -751,8 +756,8 @@ err_clk_unreg:
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+ static const struct mtmips_clk_data rt2880_clk_data = {
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+ .clk_base = rt2880_clks_base,
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+ .num_clk_base = ARRAY_SIZE(rt2880_clks_base),
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+- .clk_fixed = rt305x_fixed_clocks,
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+- .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
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++ .clk_fixed = NULL,
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++ .num_clk_fixed = 0,
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+ .clk_factor = rt2880_factor_clocks,
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+ .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
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+ .clk_periph = rt2880_pherip_clks,
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+@@ -762,8 +767,8 @@ static const struct mtmips_clk_data rt28
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+ static const struct mtmips_clk_data rt305x_clk_data = {
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+ .clk_base = rt305x_clks_base,
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+ .num_clk_base = ARRAY_SIZE(rt305x_clks_base),
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+- .clk_fixed = rt305x_fixed_clocks,
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+- .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
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++ .clk_fixed = NULL,
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++ .num_clk_fixed = 0,
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+ .clk_factor = rt305x_factor_clocks,
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+ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
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+ .clk_periph = rt305x_pherip_clks,
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Shiji Yang