|
@@ -41,7 +41,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
};
|
|
};
|
|
|
|
|
|
|
|
cpus {
|
|
cpus {
|
|
|
-@@ -132,6 +134,12 @@
|
|
|
|
|
|
|
+@@ -136,6 +138,12 @@
|
|
|
};
|
|
};
|
|
|
};
|
|
};
|
|
|
|
|
|
|
@@ -54,7 +54,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
timer {
|
|
timer {
|
|
|
compatible = "arm,armv7-timer";
|
|
compatible = "arm,armv7-timer";
|
|
|
interrupts = <1 2 0xf08>,
|
|
interrupts = <1 2 0xf08>,
|
|
|
-@@ -177,13 +185,13 @@
|
|
|
|
|
|
|
+@@ -181,13 +189,13 @@
|
|
|
#gpio-cells = <2>;
|
|
#gpio-cells = <2>;
|
|
|
interrupt-controller;
|
|
interrupt-controller;
|
|
|
#interrupt-cells = <2>;
|
|
#interrupt-cells = <2>;
|
|
@@ -70,7 +70,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
|
|
|
clock-names = "bam_clk";
|
|
clock-names = "bam_clk";
|
|
|
#dma-cells = <1>;
|
|
#dma-cells = <1>;
|
|
|
-@@ -191,7 +199,7 @@
|
|
|
|
|
|
|
+@@ -195,7 +203,7 @@
|
|
|
status = "disabled";
|
|
status = "disabled";
|
|
|
};
|
|
};
|
|
|
|
|
|
|
@@ -79,7 +79,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
|
reg = <0x78b5000 0x600>;
|
|
reg = <0x78b5000 0x600>;
|
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
-@@ -200,10 +208,26 @@
|
|
|
|
|
|
|
+@@ -204,10 +212,26 @@
|
|
|
clock-names = "core", "iface";
|
|
clock-names = "core", "iface";
|
|
|
#address-cells = <1>;
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
#size-cells = <0>;
|
|
@@ -107,7 +107,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
|
reg = <0x78b7000 0x600>;
|
|
reg = <0x78b7000 0x600>;
|
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
-@@ -212,14 +236,29 @@
|
|
|
|
|
|
|
+@@ -216,14 +240,29 @@
|
|
|
clock-names = "iface", "core";
|
|
clock-names = "iface", "core";
|
|
|
#address-cells = <1>;
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
#size-cells = <0>;
|
|
@@ -138,7 +138,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
|
|
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
|
|
|
clock-names = "bam_clk";
|
|
clock-names = "bam_clk";
|
|
|
#dma-cells = <1>;
|
|
#dma-cells = <1>;
|
|
|
-@@ -293,7 +332,7 @@
|
|
|
|
|
|
|
+@@ -297,7 +336,7 @@
|
|
|
serial@78af000 {
|
|
serial@78af000 {
|
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
|
reg = <0x78af000 0x200>;
|
|
reg = <0x78af000 0x200>;
|
|
@@ -147,7 +147,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
status = "disabled";
|
|
status = "disabled";
|
|
|
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
|
|
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
|
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
|
-@@ -305,7 +344,7 @@
|
|
|
|
|
|
|
+@@ -309,7 +348,7 @@
|
|
|
serial@78b0000 {
|
|
serial@78b0000 {
|
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
|
reg = <0x78b0000 0x200>;
|
|
reg = <0x78b0000 0x200>;
|
|
@@ -156,7 +156,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
status = "disabled";
|
|
status = "disabled";
|
|
|
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
|
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
|
-@@ -327,6 +366,101 @@
|
|
|
|
|
|
|
+@@ -331,6 +370,101 @@
|
|
|
reg = <0x4ab000 0x4>;
|
|
reg = <0x4ab000 0x4>;
|
|
|
};
|
|
};
|
|
|
|
|
|
|
@@ -258,7 +258,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
wifi0: wifi@a000000 {
|
|
wifi0: wifi@a000000 {
|
|
|
compatible = "qcom,ipq4019-wifi";
|
|
compatible = "qcom,ipq4019-wifi";
|
|
|
reg = <0xa000000 0x200000>;
|
|
reg = <0xa000000 0x200000>;
|
|
|
-@@ -360,7 +494,7 @@
|
|
|
|
|
|
|
+@@ -364,7 +498,7 @@
|
|
|
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
|
|
|
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
|
|
|
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
|
|
@@ -267,7 +267,7 @@ Signed-off-by: Andy Gross <[email protected]>
|
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
|
"msi4", "msi5", "msi6", "msi7",
|
|
"msi4", "msi5", "msi6", "msi7",
|
|
|
"msi8", "msi9", "msi10", "msi11",
|
|
"msi8", "msi9", "msi10", "msi11",
|
|
|
-@@ -402,7 +536,7 @@
|
|
|
|
|
|
|
+@@ -406,7 +540,7 @@
|
|
|
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
|
|
|
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
|
|
|
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
|