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@@ -0,0 +1,58 @@
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+--- a/arch/mips/ralink/mt7621.c
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++++ b/arch/mips/ralink/mt7621.c
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+@@ -56,7 +56,9 @@
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+ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18
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+ #define MT7621_GPIO_MODE_SDHCI_GPIO 1
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+
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+-static void *detect_magic __initdata = detect_memory_region;
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++#define MT7621_MEM_TEST_PATTERN 0xaa5555aa
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++
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++static u32 detect_magic __initdata;
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+
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+ static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
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+ static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
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+@@ -142,24 +144,32 @@ static struct clk *__init mt7621_add_sys
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+ return clk;
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+ }
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+
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++static bool __init mt7621_addr_wraparound_test(phys_addr_t size)
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++{
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++ void *dm = (void *)KSEG1ADDR(&detect_magic);
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++ if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)
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++ return true;
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++ __raw_writel(MT7621_MEM_TEST_PATTERN, dm);
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++ if (__raw_readl(dm) != __raw_readl(dm + size))
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++ return false;
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++ __raw_writel(!MT7621_MEM_TEST_PATTERN, dm);
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++ return __raw_readl(dm) == __raw_readl(dm + size);
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++}
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++
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+ void __init mt7621_memory_detect(void)
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+ {
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+- void *dm = &detect_magic;
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+ phys_addr_t size;
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+
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+- for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {
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+- if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))
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+- break;
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++ for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {
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++ if (mt7621_addr_wraparound_test(size)) {
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++ memblock_add(MT7621_LOWMEM_BASE, size);
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++ return;
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++ }
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+ }
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+
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+- if ((size == 256 * SZ_1M) &&
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+- (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&
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+- __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {
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+- memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
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+- memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
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+- } else {
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+- memblock_add(MT7621_LOWMEM_BASE, size);
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+- }
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++ /* addr doesn't wrap around at dm + 256M, assume 512M memory. */
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++ memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
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++ memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
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+ }
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+
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+ void __init ralink_clk_init(void)
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