mediatek: update patches

Signed-off-by: John Crispin <[email protected]>

SVN-Revision: 49243

target/linux/mediatek/base-files/lib/preinit/01_affinity

@@ -0,0 +1,4 @@
+#!/bin/sh
+
+echo 4 > /proc/irq/32/smp_affinity
+echo 8 > /proc/irq/33/smp_affinity

target/linux/mediatek/patches-4.4/0001-NET-multi-phy-support.patch

@@ -1,7 +1,7 @@
 From c30a296646a42302065ba452abe95b0b4b550883 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Sun, 27 Jul 2014 09:38:50 +0100
-Subject: [PATCH 01/81] NET: multi phy support
+Subject: [PATCH 01/91] NET: multi phy support
 
 Signed-off-by: John Crispin <[email protected]>
 ---
@@ -9,9 +9,11 @@ Signed-off-by: John Crispin <[email protected]>
  include/linux/phy.h   |    1 +
  2 files changed, 7 insertions(+), 3 deletions(-)
 
+diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
+index 47cd306..f69d12f 100644
 --- a/drivers/net/phy/phy.c
 +++ b/drivers/net/phy/phy.c
-@@ -888,7 +888,8 @@ void phy_state_machine(struct work_struc
+@@ -844,7 +844,8 @@ void phy_state_machine(struct work_struct *work)
  		/* If the link is down, give up on negotiation for now */
  		if (!phydev->link) {
  			phydev->state = PHY_NOLINK;
@@ -21,7 +23,7 @@ Signed-off-by: John Crispin <[email protected]>
  			phydev->adjust_link(phydev->attached_dev);
  			break;
  		}
-@@ -971,7 +972,8 @@ void phy_state_machine(struct work_struc
+@@ -927,7 +928,8 @@ void phy_state_machine(struct work_struct *work)
  			netif_carrier_on(phydev->attached_dev);
  		} else {
  			phydev->state = PHY_NOLINK;
@@ -31,7 +33,7 @@ Signed-off-by: John Crispin <[email protected]>
  		}
  
  		phydev->adjust_link(phydev->attached_dev);
-@@ -983,7 +985,8 @@ void phy_state_machine(struct work_struc
+@@ -939,7 +941,8 @@ void phy_state_machine(struct work_struct *work)
  	case PHY_HALTED:
  		if (phydev->link) {
  			phydev->link = 0;
@@ -41,6 +43,8 @@ Signed-off-by: John Crispin <[email protected]>
  			phydev->adjust_link(phydev->attached_dev);
  			do_suspend = true;
  		}
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index 05fde31..276ab8a 100644
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
 @@ -377,6 +377,7 @@ struct phy_device {
@@ -51,3 +55,6 @@ Signed-off-by: John Crispin <[email protected]>
  
  	enum phy_state state;
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0002-soc-mediatek-Separate-scpsys-driver-common-code.patch

@@ -1,7 +1,7 @@
 From 2c93328ed05061a50e3bd4111379dbcf6946d3ac Mon Sep 17 00:00:00 2001
 From: James Liao <[email protected]>
 Date: Wed, 30 Dec 2015 14:41:43 +0800
-Subject: [PATCH 02/81] soc: mediatek: Separate scpsys driver common code
+Subject: [PATCH 02/91] soc: mediatek: Separate scpsys driver common code
 
 Separate scpsys driver common code to mtk-scpsys.c, and move MT8173
 platform code to mtk-scpsys-mt8173.c.
@@ -17,6 +17,8 @@ Signed-off-by: James Liao <[email protected]>
  create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt8173.c
  create mode 100644 drivers/soc/mediatek/mtk-scpsys.h
 
+diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
+index 0a4ea80..eca6fb7 100644
 --- a/drivers/soc/mediatek/Kconfig
 +++ b/drivers/soc/mediatek/Kconfig
 @@ -22,11 +22,20 @@ config MTK_PMIC_WRAP
@@ -42,6 +44,8 @@ Signed-off-by: James Liao <[email protected]>
 +	  driver.
 +	  The System Control Processor System (SCPSYS) has several power
 +	  management related tasks in the system.
+diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
+index 12998b0..3b22baa 100644
 --- a/drivers/soc/mediatek/Makefile
 +++ b/drivers/soc/mediatek/Makefile
 @@ -1,3 +1,4 @@
@@ -49,6 +53,9 @@ Signed-off-by: James Liao <[email protected]>
  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
 +obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt8173.c b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
+new file mode 100644
+index 0000000..3c7b569
 --- /dev/null
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
 @@ -0,0 +1,179 @@
@@ -231,6 +238,8 @@ Signed-off-by: James Liao <[email protected]>
 +};
 +
 +module_platform_driver_probe(scpsys_drv, scpsys_probe);
+diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
+index 4d4203c..a0943c5 100644
 --- a/drivers/soc/mediatek/mtk-scpsys.c
 +++ b/drivers/soc/mediatek/mtk-scpsys.c
 @@ -11,28 +11,14 @@
@@ -248,7 +257,7 @@ Signed-off-by: James Liao <[email protected]>
 -#include <linux/regmap.h>
  #include <linux/soc/mediatek/infracfg.h>
 -#include <dt-bindings/power/mt8173-power.h>
- 
+-
 -#define SPM_VDE_PWR_CON			0x0210
 -#define SPM_MFG_PWR_CON			0x0214
 -#define SPM_VEN_PWR_CON			0x0230
@@ -259,6 +268,7 @@ Signed-off-by: James Liao <[email protected]>
 -#define SPM_MFG_2D_PWR_CON		0x02c0
 -#define SPM_MFG_ASYNC_PWR_CON		0x02c4
 -#define SPM_USB_PWR_CON			0x02cc
++
 +#include "mtk-scpsys.h"
 +
  #define SPM_PWR_STATUS			0x060c
@@ -418,7 +428,7 @@ Signed-off-by: James Liao <[email protected]>
  static int scpsys_domain_is_on(struct scp_domain *scpd)
  {
  	struct scp *scp = scpd->scp;
-@@ -398,63 +237,89 @@ static bool scpsys_active_wakeup(struct
+@@ -398,63 +237,89 @@ static bool scpsys_active_wakeup(struct device *dev)
  	return scpd->active_wakeup;
  }
  
@@ -508,13 +518,13 @@ Signed-off-by: James Liao <[email protected]>
 +		return ERR_PTR(-ENOMEM);
 +
 +	pd_data = &scp->pd_data;
- 
--	for (i = 0; i < NUM_DOMAINS; i++) {
++
 +	pd_data->domains = devm_kzalloc(&pdev->dev,
 +			sizeof(*pd_data->domains) * num, GFP_KERNEL);
 +	if (!pd_data->domains)
 +		return ERR_PTR(-ENOMEM);
-+
+ 
+-	for (i = 0; i < NUM_DOMAINS; i++) {
 +	pd_data->num_domains = num;
 +
 +	init_clks(pdev, clk);
@@ -539,7 +549,7 @@ Signed-off-by: James Liao <[email protected]>
  		pd_data->domains[i] = genpd;
  		scpd->scp = scp;
  
-@@ -464,13 +329,25 @@ static int __init scpsys_probe(struct pl
+@@ -464,13 +329,25 @@ static int __init scpsys_probe(struct platform_device *pdev)
  		scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
  		scpd->bus_prot_mask = data->bus_prot_mask;
  		scpd->active_wakeup = data->active_wakeup;
@@ -567,7 +577,7 @@ Signed-off-by: James Liao <[email protected]>
  
  		/*
  		 * Initially turn on all domains to make the domains usable
-@@ -489,37 +366,9 @@ static int __init scpsys_probe(struct pl
+@@ -489,37 +366,9 @@ static int __init scpsys_probe(struct platform_device *pdev)
  	 * valid.
  	 */
  
@@ -606,6 +616,9 @@ Signed-off-by: James Liao <[email protected]>
 -};
 -
 -module_platform_driver_probe(scpsys_drv, scpsys_probe);
+diff --git a/drivers/soc/mediatek/mtk-scpsys.h b/drivers/soc/mediatek/mtk-scpsys.h
+new file mode 100644
+index 0000000..466728d
 --- /dev/null
 +++ b/drivers/soc/mediatek/mtk-scpsys.h
 @@ -0,0 +1,54 @@
@@ -663,3 +676,6 @@ Signed-off-by: James Liao <[email protected]>
 +				struct scp *scp, int num);
 +
 +#endif /* __DRV_SOC_MTK_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0003-soc-mediatek-Init-MT8173-scpsys-driver-earlier.patch

@@ -1,7 +1,7 @@
 From c359272f86805259c5801385d60fdeea9d629cf9 Mon Sep 17 00:00:00 2001
 From: James Liao <[email protected]>
 Date: Wed, 30 Dec 2015 14:41:44 +0800
-Subject: [PATCH 03/81] soc: mediatek: Init MT8173 scpsys driver earlier
+Subject: [PATCH 03/91] soc: mediatek: Init MT8173 scpsys driver earlier
 
 Some power domain comsumers may init before module_init.
 So the power domain provider (scpsys) need to be initialized
@@ -12,9 +12,11 @@ Signed-off-by: James Liao <[email protected]>
  drivers/soc/mediatek/mtk-scpsys-mt8173.c |   13 ++++++++++++-
  1 file changed, 12 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt8173.c b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
+index 3c7b569..827e696 100644
 --- a/drivers/soc/mediatek/mtk-scpsys-mt8173.c
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
-@@ -176,4 +176,15 @@ static struct platform_driver scpsys_drv
+@@ -176,4 +176,15 @@ static struct platform_driver scpsys_drv = {
  	},
  };
  
@@ -31,3 +33,6 @@ Signed-off-by: James Liao <[email protected]>
 +
 +subsys_initcall(scpsys_drv_init);
 +module_exit(scpsys_drv_exit);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0004-soc-mediatek-Add-MT2701-power-dt-bindings.patch

@@ -1,7 +1,7 @@
 From f371844374fff273f817d6c43f679606417af59e Mon Sep 17 00:00:00 2001
 From: Shunli Wang <[email protected]>
 Date: Wed, 30 Dec 2015 14:41:45 +0800
-Subject: [PATCH 04/81] soc: mediatek: Add MT2701 power dt-bindings
+Subject: [PATCH 04/91] soc: mediatek: Add MT2701 power dt-bindings
 
 Add power dt-bindings for MT2701.
 
@@ -12,6 +12,9 @@ Signed-off-by: James Liao <[email protected]>
  1 file changed, 27 insertions(+)
  create mode 100644 include/dt-bindings/power/mt2701-power.h
 
+diff --git a/include/dt-bindings/power/mt2701-power.h b/include/dt-bindings/power/mt2701-power.h
+new file mode 100644
+index 0000000..64cc826
 --- /dev/null
 +++ b/include/dt-bindings/power/mt2701-power.h
 @@ -0,0 +1,27 @@
@@ -42,3 +45,6 @@ Signed-off-by: James Liao <[email protected]>
 +#define MT2701_POWER_DOMAIN_IFR_MSC	8
 +
 +#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0005-soc-mediatek-Add-MT2701-MT7623-scpsys-driver.patch

@@ -1,7 +1,7 @@
 From c6711565985f359d7d3c05f01f081e4c216902de Mon Sep 17 00:00:00 2001
 From: Shunli Wang <[email protected]>
 Date: Wed, 30 Dec 2015 14:41:46 +0800
-Subject: [PATCH 05/81] soc: mediatek: Add MT2701/MT7623 scpsys driver
+Subject: [PATCH 05/91] soc: mediatek: Add MT2701/MT7623 scpsys driver
 
 Add scpsys driver for MT2701 and MT7623.
 
@@ -14,6 +14,8 @@ Signed-off-by: James Liao <[email protected]>
  3 files changed, 173 insertions(+)
  create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt2701.c
 
+diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
+index eca6fb7..92cf838 100644
 --- a/drivers/soc/mediatek/Kconfig
 +++ b/drivers/soc/mediatek/Kconfig
 @@ -39,3 +39,14 @@ config MTK_SCPSYS_MT8173
@@ -31,13 +33,18 @@ Signed-off-by: James Liao <[email protected]>
 +	  domain driver.
 +	  The System Control Processor System (SCPSYS) has several power
 +	  management related tasks in the system.
+diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
+index 3b22baa..822986d 100644
 --- a/drivers/soc/mediatek/Makefile
 +++ b/drivers/soc/mediatek/Makefile
-@@ -2,3 +2,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infrac
+@@ -2,3 +2,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
  obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
 +obj-$(CONFIG_MTK_SCPSYS_MT2701) += mtk-scpsys-mt2701.o
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
+new file mode 100644
+index 0000000..339d5b8
 --- /dev/null
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
 @@ -0,0 +1,161 @@
@@ -202,3 +209,6 @@ Signed-off-by: James Liao <[email protected]>
 +
 +MODULE_DESCRIPTION("MediaTek MT2701 scpsys driver");
 +MODULE_LICENSE("GPL v2");
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0006-clk-mediatek-Refine-the-makefile-to-support-multiple.patch

@@ -1,7 +1,7 @@
 From 0c39bcd17fa6ce723f56ad3756b4bb36c4690342 Mon Sep 17 00:00:00 2001
 From: James Liao <[email protected]>
 Date: Tue, 5 Jan 2016 14:30:17 +0800
-Subject: [PATCH 06/81] clk: mediatek: Refine the makefile to support multiple
+Subject: [PATCH 06/91] clk: mediatek: Refine the makefile to support multiple
  clock drivers
 
 Add a Kconfig to define clock configuration for each SoC, and
@@ -16,6 +16,8 @@ Signed-off-by: James Liao <[email protected]>
  3 files changed, 27 insertions(+), 3 deletions(-)
  create mode 100644 drivers/clk/mediatek/Kconfig
 
+diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
+index c3e3a02..b7a37dc 100644
 --- a/drivers/clk/Kconfig
 +++ b/drivers/clk/Kconfig
 @@ -198,3 +198,4 @@ source "drivers/clk/mvebu/Kconfig"
@@ -23,6 +25,9 @@ Signed-off-by: James Liao <[email protected]>
  source "drivers/clk/samsung/Kconfig"
  source "drivers/clk/tegra/Kconfig"
 +source "drivers/clk/mediatek/Kconfig"
+diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
+new file mode 100644
+index 0000000..dc224e6
 --- /dev/null
 +++ b/drivers/clk/mediatek/Kconfig
 @@ -0,0 +1,23 @@
@@ -49,6 +54,8 @@ Signed-off-by: James Liao <[email protected]>
 +	default ARCH_MEDIATEK
 +	---help---
 +	  This driver supports Mediatek MT8173 clocks.
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 95fdfac..32e7222 100644
 --- a/drivers/clk/mediatek/Makefile
 +++ b/drivers/clk/mediatek/Makefile
 @@ -1,4 +1,4 @@
@@ -59,3 +66,6 @@ Signed-off-by: James Liao <[email protected]>
 -obj-y += clk-mt8173.o
 +obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 +obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0007-dt-bindings-ARM-Mediatek-Document-bindings-for-MT270.patch

@@ -1,7 +1,7 @@
 From d7e96f87f66c571e9f4171ecd89c656fbd2de89b Mon Sep 17 00:00:00 2001
 From: James Liao <[email protected]>
 Date: Tue, 5 Jan 2016 14:30:18 +0800
-Subject: [PATCH 07/81] dt-bindings: ARM: Mediatek: Document bindings for
+Subject: [PATCH 07/91] dt-bindings: ARM: Mediatek: Document bindings for
  MT2701
 
 This patch adds the binding documentation for apmixedsys, bdpsys,
@@ -25,9 +25,11 @@ Signed-off-by: James Liao <[email protected]>
  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
 
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+index 936166f..a701e19 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
-@@ -6,6 +6,7 @@ The Mediatek apmixedsys controller provi
+@@ -6,6 +6,7 @@ The Mediatek apmixedsys controller provides the PLLs to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -35,6 +37,9 @@ Signed-off-by: James Liao <[email protected]>
  	- "mediatek,mt8135-apmixedsys"
  	- "mediatek,mt8173-apmixedsys"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
+new file mode 100644
+index 0000000..4137196
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
 @@ -0,0 +1,22 @@
@@ -60,6 +65,9 @@ Signed-off-by: James Liao <[email protected]>
 +	reg = <0 0x1c000000 0 0x1000>;
 +	#clock-cells = <1>;
 +};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+new file mode 100644
+index 0000000..768f3a5
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
 @@ -0,0 +1,22 @@
@@ -85,6 +93,9 @@ Signed-off-by: James Liao <[email protected]>
 +	reg = <0 0x1b000000 0 0x1000>;
 +	#clock-cells = <1>;
 +};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
+new file mode 100644
+index 0000000..b7a39b6
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
 @@ -0,0 +1,22 @@
@@ -110,9 +121,11 @@ Signed-off-by: James Liao <[email protected]>
 +	reg = <0 0x1a000000 0 0x1000>;
 +	#clock-cells = <1>;
 +};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+index b1f2ce1..9bda7f7 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
-@@ -6,6 +6,7 @@ The Mediatek imgsys controller provides
+@@ -6,6 +6,7 @@ The Mediatek imgsys controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -120,6 +133,8 @@ Signed-off-by: James Liao <[email protected]>
  	- "mediatek,mt8173-imgsys", "syscon"
  - #clock-cells: Must be 1
  
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+index f6cd3e4..2f11a69 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
 @@ -7,6 +7,7 @@ outputs to the system.
@@ -130,9 +145,11 @@ Signed-off-by: James Liao <[email protected]>
  	- "mediatek,mt8135-infracfg", "syscon"
  	- "mediatek,mt8173-infracfg", "syscon"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+index 4385946..c9d9d43 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
-@@ -6,6 +6,7 @@ The Mediatek mmsys controller provides v
+@@ -6,6 +6,7 @@ The Mediatek mmsys controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -140,6 +157,8 @@ Signed-off-by: James Liao <[email protected]>
  	- "mediatek,mt8173-mmsys", "syscon"
  - #clock-cells: Must be 1
  
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+index f25b854..d3454cd 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 @@ -7,6 +7,7 @@ outputs to the system.
@@ -150,9 +169,11 @@ Signed-off-by: James Liao <[email protected]>
  	- "mediatek,mt8135-pericfg", "syscon"
  	- "mediatek,mt8173-pericfg", "syscon"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+index f9e9179..602e5bc 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
-@@ -6,6 +6,7 @@ The Mediatek topckgen controller provide
+@@ -6,6 +6,7 @@ The Mediatek topckgen controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -160,9 +181,11 @@ Signed-off-by: James Liao <[email protected]>
  	- "mediatek,mt8135-topckgen"
  	- "mediatek,mt8173-topckgen"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+index 1faacf1..f5b1e7d 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
-@@ -6,6 +6,7 @@ The Mediatek vdecsys controller provides
+@@ -6,6 +6,7 @@ The Mediatek vdecsys controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -170,3 +193,6 @@ Signed-off-by: James Liao <[email protected]>
  	- "mediatek,mt8173-vdecsys", "syscon"
  - #clock-cells: Must be 1
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0008-clk-mediatek-Add-dt-bindings-for-MT2701-clocks.patch

@@ -1,7 +1,7 @@
 From 2fcbc15da2f13164e0851b9c7fae290249f0b44d Mon Sep 17 00:00:00 2001
 From: Shunli Wang <[email protected]>
 Date: Tue, 5 Jan 2016 14:30:19 +0800
-Subject: [PATCH 08/81] clk: mediatek: Add dt-bindings for MT2701 clocks
+Subject: [PATCH 08/91] clk: mediatek: Add dt-bindings for MT2701 clocks
 
 Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
 infracfg, pericfg and subsystem clocks.
@@ -13,6 +13,9 @@ Signed-off-by: James Liao <[email protected]>
  1 file changed, 481 insertions(+)
  create mode 100644 include/dt-bindings/clock/mt2701-clk.h
 
+diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
+new file mode 100644
+index 0000000..50972d1
 --- /dev/null
 +++ b/include/dt-bindings/clock/mt2701-clk.h
 @@ -0,0 +1,481 @@
@@ -497,3 +500,6 @@ Signed-off-by: James Liao <[email protected]>
 +#define CLK_BDP_NR				50
 +
 +#endif /* _DT_BINDINGS_CLK_MT2701_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0009-clk-mediatek-Add-MT2701-clock-support.patch

@@ -1,7 +1,7 @@
 From f2c07eaa2df52f9acac9ffc3457d3d81079dd723 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <[email protected]>
 Date: Tue, 5 Jan 2016 14:30:20 +0800
-Subject: [PATCH 09/81] clk: mediatek: Add MT2701 clock support
+Subject: [PATCH 09/91] clk: mediatek: Add MT2701 clock support
 
 Add MT2701 clock support, include topckgen, apmixedsys,
 infracfg, pericfg and subsystem clocks.
@@ -19,6 +19,8 @@ Signed-off-by: James Liao <[email protected]>
  7 files changed, 1334 insertions(+), 3 deletions(-)
  create mode 100644 drivers/clk/mediatek/clk-mt2701.c
 
+diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
+index dc224e6..6c7cdc0 100644
 --- a/drivers/clk/mediatek/Kconfig
 +++ b/drivers/clk/mediatek/Kconfig
 @@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
@@ -36,6 +38,8 @@ Signed-off-by: James Liao <[email protected]>
  config COMMON_CLK_MT8135
  	bool "Clock driver for Mediatek MT8135"
  	depends on COMMON_CLK
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 32e7222..5b2b91b 100644
 --- a/drivers/clk/mediatek/Makefile
 +++ b/drivers/clk/mediatek/Makefile
 @@ -1,4 +1,5 @@
@@ -44,9 +48,11 @@ Signed-off-by: James Liao <[email protected]>
 +obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
  obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
  obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
+index 576bdb7..38badb4 100644
 --- a/drivers/clk/mediatek/clk-gate.c
 +++ b/drivers/clk/mediatek/clk-gate.c
-@@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw
+@@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
  	regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
  }
  
@@ -73,7 +79,7 @@ Signed-off-by: James Liao <[email protected]>
  static int mtk_cg_enable(struct clk_hw *hw)
  {
  	mtk_cg_clr_bit(hw);
-@@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct cl
+@@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct clk_hw *hw)
  	mtk_cg_clr_bit(hw);
  }
  
@@ -104,7 +110,7 @@ Signed-off-by: James Liao <[email protected]>
  const struct clk_ops mtk_clk_gate_ops_setclr = {
  	.is_enabled	= mtk_cg_bit_is_cleared,
  	.enable		= mtk_cg_enable,
-@@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_se
+@@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
  	.disable	= mtk_cg_disable_inv,
  };
  
@@ -123,9 +129,11 @@ Signed-off-by: James Liao <[email protected]>
  struct clk * __init mtk_clk_register_gate(
  		const char *name,
  		const char *parent_name,
+diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
+index 11e25c9..7f7ef34 100644
 --- a/drivers/clk/mediatek/clk-gate.h
 +++ b/drivers/clk/mediatek/clk-gate.h
-@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_cl
+@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
  
  extern const struct clk_ops mtk_clk_gate_ops_setclr;
  extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
@@ -134,6 +142,9 @@ Signed-off-by: James Liao <[email protected]>
  
  struct clk *mtk_clk_register_gate(
  		const char *name,
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+new file mode 100644
+index 0000000..2f521f4
 --- /dev/null
 +++ b/drivers/clk/mediatek/clk-mt2701.c
 @@ -0,0 +1,1210 @@
@@ -1347,9 +1358,11 @@ Signed-off-by: James Liao <[email protected]>
 +}
 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
 +							mtk_apmixedsys_init);
+diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
+index cf08db6..be19a41 100644
 --- a/drivers/clk/mediatek/clk-mtk.c
 +++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -242,3 +242,28 @@ void __init mtk_clk_register_composites(
+@@ -242,3 +242,28 @@ void __init mtk_clk_register_composites(const struct mtk_composite *mcs,
  			clk_data->clks[mc->id] = clk;
  	}
  }
@@ -1378,6 +1391,8 @@ Signed-off-by: James Liao <[email protected]>
 +			clk_data->clks[mcd->id] = clk;
 +	}
 +}
+diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
+index 32d2e45..60701e8 100644
 --- a/drivers/clk/mediatek/clk-mtk.h
 +++ b/drivers/clk/mediatek/clk-mtk.h
 @@ -110,7 +110,8 @@ struct mtk_composite {
@@ -1429,3 +1444,6 @@ Signed-off-by: James Liao <[email protected]>
  
  struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch

@@ -1,7 +1,7 @@
 From 8d134cbe750b59d15c591622d81e2e9daa09f0c4 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <[email protected]>
 Date: Tue, 5 Jan 2016 14:30:21 +0800
-Subject: [PATCH 10/81] reset: mediatek: mt2701 reset controller dt-binding
+Subject: [PATCH 10/91] reset: mediatek: mt2701 reset controller dt-binding
  file
 
 Dt-binding file about reset controller is used to provide
@@ -14,6 +14,9 @@ Signed-off-by: Shunli Wang <[email protected]>
  1 file changed, 74 insertions(+)
  create mode 100644 include/dt-bindings/reset-controller/mt2701-resets.h
 
+diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h b/include/dt-bindings/reset-controller/mt2701-resets.h
+new file mode 100644
+index 0000000..00efeb0
 --- /dev/null
 +++ b/include/dt-bindings/reset-controller/mt2701-resets.h
 @@ -0,0 +1,74 @@
@@ -91,3 +94,6 @@ Signed-off-by: Shunli Wang <[email protected]>
 +#define MT2701_TOPRGU_BDP_DISP_RST		13
 +
 +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0011-reset-mediatek-mt2701-reset-driver.patch

@@ -1,7 +1,7 @@
 From b86d3303db25a8296e4c3de46ee1470f60f71b0c Mon Sep 17 00:00:00 2001
 From: Shunli Wang <[email protected]>
 Date: Tue, 5 Jan 2016 14:30:22 +0800
-Subject: [PATCH 11/81] reset: mediatek: mt2701 reset driver
+Subject: [PATCH 11/91] reset: mediatek: mt2701 reset driver
 
 In infrasys and perifsys, there are many reset
 control bits for kinds of modules. These bits are
@@ -14,9 +14,11 @@ Acked-by: Philipp Zabel <[email protected]>
  drivers/clk/mediatek/clk-mt2701.c |    4 ++++
  1 file changed, 4 insertions(+)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 2f521f4..39472e4 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -665,6 +665,8 @@ static void __init mtk_infrasys_init(str
+@@ -665,6 +665,8 @@ static void __init mtk_infrasys_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -25,7 +27,7 @@ Acked-by: Philipp Zabel <[email protected]>
  }
  CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg", mtk_infrasys_init);
  
-@@ -782,6 +784,8 @@ static void __init mtk_pericfg_init(stru
+@@ -782,6 +784,8 @@ static void __init mtk_pericfg_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -34,3 +36,6 @@ Acked-by: Philipp Zabel <[email protected]>
  }
  CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt2701-pericfg", mtk_pericfg_init);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0012-ARM-mediatek-Add-MT2701-config-options-for-mediatek-.patch

@@ -1,7 +1,7 @@
 From 3b5df542d52b13a1b20d25311fa4c4029a3b83af Mon Sep 17 00:00:00 2001
 From: Erin Lo <[email protected]>
 Date: Mon, 28 Dec 2015 15:09:02 +0800
-Subject: [PATCH 12/81] ARM: mediatek: Add MT2701 config options for mediatek
+Subject: [PATCH 12/91] ARM: mediatek: Add MT2701 config options for mediatek
  SoCs.
 
 The upcoming MTK pinctrl driver have a big pin table for each SoC
@@ -14,6 +14,8 @@ Acked-by: Linus Walleij <[email protected]>
  arch/arm/mach-mediatek/Kconfig |    4 ++++
  1 file changed, 4 insertions(+)
 
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index aeece17..37dd438 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -9,6 +9,10 @@ menuconfig ARCH_MEDIATEK
@@ -27,3 +29,6 @@ Acked-by: Linus Walleij <[email protected]>
  config MACH_MT6589
  	bool "MediaTek MT6589 SoCs support"
  	default ARCH_MEDIATEK
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0013-dt-bindings-mediatek-Modify-pinctrl-bindings-for-mt2.patch

@@ -1,7 +1,7 @@
 From 1a254735cad9db5c8605c972b0f16b3929dc0d6e Mon Sep 17 00:00:00 2001
 From: Biao Huang <[email protected]>
 Date: Mon, 28 Dec 2015 15:09:03 +0800
-Subject: [PATCH 13/81] dt-bindings: mediatek: Modify pinctrl bindings for
+Subject: [PATCH 13/91] dt-bindings: mediatek: Modify pinctrl bindings for
  mt2701
 
 Signed-off-by: Biao Huang <[email protected]>
@@ -11,9 +11,11 @@ Reviewed-by: Mathias Brugger <[email protected]>
  Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt |    9 +++++----
  1 file changed, 5 insertions(+), 4 deletions(-)
 
+diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+index 0480bc3..9ffb0b2 100644
 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
-@@ -4,10 +4,11 @@ The Mediatek's Pin controller is used to
+@@ -4,10 +4,11 @@ The Mediatek's Pin controller is used to control SoC pins.
  
  Required properties:
  - compatible: value should be one of the following.
@@ -29,3 +31,6 @@ Reviewed-by: Mathias Brugger <[email protected]>
  - pins-are-numbered: Specify the subnodes are using numbered pinmux to
    specify pins.
  - gpio-controller : Marks the device node as a gpio controller.
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0014-pinctrl-dt-bindings-Add-pinfunc-header-file-for-mt27.patch

@@ -1,7 +1,7 @@
 From 416720ba33d4fd7d3166c17be7c13651cc08d408 Mon Sep 17 00:00:00 2001
 From: Biao Huang <[email protected]>
 Date: Mon, 28 Dec 2015 15:09:04 +0800
-Subject: [PATCH 14/81] pinctrl: dt bindings: Add pinfunc header file for
+Subject: [PATCH 14/91] pinctrl: dt bindings: Add pinfunc header file for
  mt2701
 
 Add pinfunc header file, mt2701 related dts will include it
@@ -21,6 +21,9 @@ Acked-by: Linus Walleij <[email protected]>
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2701.c
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
 
+diff --git a/arch/arm/boot/dts/mt2701-pinfunc.h b/arch/arm/boot/dts/mt2701-pinfunc.h
+new file mode 100644
+index 0000000..e24ebc8
 --- /dev/null
 +++ b/arch/arm/boot/dts/mt2701-pinfunc.h
 @@ -0,0 +1,735 @@
@@ -759,6 +762,8 @@ Acked-by: Linus Walleij <[email protected]>
 +#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
 +
 +#endif /* __DTS_MT2701_PINFUNC_H */
+diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
+index 02f6f92..13e9939 100644
 --- a/drivers/pinctrl/mediatek/Kconfig
 +++ b/drivers/pinctrl/mediatek/Kconfig
 @@ -9,6 +9,12 @@ config PINCTRL_MTK_COMMON
@@ -774,6 +779,8 @@ Acked-by: Linus Walleij <[email protected]>
  config PINCTRL_MT8135
  	bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
  	depends on OF
+diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
+index eb923d6..da30314 100644
 --- a/drivers/pinctrl/mediatek/Makefile
 +++ b/drivers/pinctrl/mediatek/Makefile
 @@ -2,6 +2,7 @@
@@ -784,6 +791,9 @@ Acked-by: Linus Walleij <[email protected]>
  obj-$(CONFIG_PINCTRL_MT8135)		+= pinctrl-mt8135.o
  obj-$(CONFIG_PINCTRL_MT8127)		+= pinctrl-mt8127.o
  obj-$(CONFIG_PINCTRL_MT8173)		+= pinctrl-mt8173.o
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
+new file mode 100644
+index 0000000..4861b5d
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
 @@ -0,0 +1,586 @@
@@ -1373,6 +1383,8 @@ Acked-by: Linus Walleij <[email protected]>
 +}
 +
 +arch_initcall(mtk_pinctrl_init);
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+index 5c71727..05ba7a8 100644
 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
 @@ -47,6 +47,8 @@
@@ -1384,7 +1396,7 @@ Acked-by: Linus Walleij <[email protected]>
  };
  
  /*
-@@ -81,6 +83,9 @@ static int mtk_pmx_gpio_set_direction(st
+@@ -81,6 +83,9 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  	reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
  	bit = BIT(offset & 0xf);
  
@@ -1394,7 +1406,7 @@ Acked-by: Linus Walleij <[email protected]>
  	if (input)
  		/* Different SoC has different alignment offset. */
  		reg_addr = CLR_ADDR(reg_addr, pctl);
-@@ -347,6 +352,7 @@ static int mtk_pconf_parse_conf(struct p
+@@ -347,6 +352,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
  		ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
  		break;
  	case PIN_CONFIG_INPUT_ENABLE:
@@ -1402,7 +1414,7 @@ Acked-by: Linus Walleij <[email protected]>
  		ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
  		break;
  	case PIN_CONFIG_OUTPUT:
-@@ -354,6 +360,7 @@ static int mtk_pconf_parse_conf(struct p
+@@ -354,6 +360,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
  		ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
  		break;
  	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
@@ -1410,7 +1422,7 @@ Acked-by: Linus Walleij <[email protected]>
  		ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
  		break;
  	case PIN_CONFIG_DRIVE_STRENGTH:
-@@ -667,9 +674,14 @@ static int mtk_pmx_set_mode(struct pinct
+@@ -667,9 +674,14 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
  	unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
  	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  
@@ -1425,7 +1437,7 @@ Acked-by: Linus Walleij <[email protected]>
  	bit = pin % MAX_GPIO_MODE_PER_REG;
  	mask <<= (GPIO_MODE_BITS * bit);
  	val = (mode << (GPIO_MODE_BITS * bit));
-@@ -746,6 +758,10 @@ static int mtk_gpio_get_direction(struct
+@@ -746,6 +758,10 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  
  	reg_addr =  mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
  	bit = BIT(offset & 0xf);
@@ -1436,6 +1448,8 @@ Acked-by: Linus Walleij <[email protected]>
  	regmap_read(pctl->regmap1, reg_addr, &read_val);
  	return !(read_val & bit);
  }
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+index 55a5343..8543bc4 100644
 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
 @@ -209,7 +209,14 @@ struct mtk_eint_offsets {
@@ -1464,6 +1478,9 @@ Acked-by: Linus Walleij <[email protected]>
  	unsigned int dir_offset;
  	unsigned int ies_offset;
  	unsigned int smt_offset;
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
+new file mode 100644
+index 0000000..f906420
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
 @@ -0,0 +1,2323 @@
@@ -3790,3 +3807,6 @@ Acked-by: Linus Walleij <[email protected]>
 +};
 +
 +#endif /* __PINCTRL_MTK_MT2701_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0015-dt-bindings-mediatek-Modify-pinctrl-bindings-for-mt7.patch

@@ -1,7 +1,7 @@
 From ddc72b659b3642d0496dee4e1ee39416ca008053 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Thu, 7 Jan 2016 23:42:06 +0100
-Subject: [PATCH 15/81] dt-bindings: mediatek: Modify pinctrl bindings for
+Subject: [PATCH 15/91] dt-bindings: mediatek: Modify pinctrl bindings for
  mt7623
 
 Signed-off-by: John Crispin <[email protected]>
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <[email protected]>
  2 files changed, 522 insertions(+)
  create mode 100644 include/dt-bindings/pinctrl/mt7623-pinfunc.h
 
+diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+index 9ffb0b2..17631d0 100644
 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 @@ -6,6 +6,7 @@ Required properties:
@@ -21,6 +23,9 @@ Signed-off-by: John Crispin <[email protected]>
  	"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
  	"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
  	"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
+diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+new file mode 100644
+index 0000000..891b173
 --- /dev/null
 +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 @@ -0,0 +1,521 @@
@@ -545,3 +550,6 @@ Signed-off-by: John Crispin <[email protected]>
 +
 +#endif /* __DTS_MT7623_PINFUNC_H */
 +
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0016-pinctrl-dt-bindings-Add-pinctrl-file-for-mt7623.patch

@@ -1,7 +1,7 @@
 From 1255eaacd6cc9d1fa6bb33185380efed22008baf Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Sat, 27 Jun 2015 13:13:05 +0200
-Subject: [PATCH 16/81] pinctrl: dt bindings: Add pinctrl file for mt7623
+Subject: [PATCH 16/91] pinctrl: dt bindings: Add pinctrl file for mt7623
 
 Add the driver and header files required to make pinctrl work on MediaTek
 MT7623.
@@ -17,6 +17,8 @@ Signed-off-by: John Crispin <[email protected]>
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
 
+diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
+index 13e9939..78654a8 100644
 --- a/drivers/pinctrl/mediatek/Kconfig
 +++ b/drivers/pinctrl/mediatek/Kconfig
 @@ -15,6 +15,12 @@ config PINCTRL_MT2701
@@ -32,9 +34,11 @@ Signed-off-by: John Crispin <[email protected]>
  config PINCTRL_MT8135
  	bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
  	depends on OF
+diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
+index da30314..1be2f3f 100644
 --- a/drivers/pinctrl/mediatek/Makefile
 +++ b/drivers/pinctrl/mediatek/Makefile
-@@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON)	+= pinc
+@@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON)	+= pinctrl-mtk-common.o
  
  # SoC Drivers
  obj-$(CONFIG_PINCTRL_MT2701)		+= pinctrl-mt2701.o
@@ -42,6 +46,9 @@ Signed-off-by: John Crispin <[email protected]>
  obj-$(CONFIG_PINCTRL_MT8135)		+= pinctrl-mt8135.o
  obj-$(CONFIG_PINCTRL_MT8127)		+= pinctrl-mt8127.o
  obj-$(CONFIG_PINCTRL_MT8173)		+= pinctrl-mt8173.o
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+new file mode 100644
+index 0000000..bf0d05b
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
 @@ -0,0 +1,380 @@
@@ -425,6 +432,9 @@ Signed-off-by: John Crispin <[email protected]>
 +}
 +
 +arch_initcall(mtk_pinctrl_init);
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
+new file mode 100644
+index 0000000..fb63c01
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
 @@ -0,0 +1,1937 @@
@@ -2365,6 +2375,8 @@ Signed-off-by: John Crispin <[email protected]>
 +};
 +
 +#endif /* __PINCTRL_MTK_MT7623_H */
+diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+index 891b173..eeb2380 100644
 --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 @@ -505,6 +505,9 @@
@@ -2377,3 +2389,6 @@ Signed-off-by: John Crispin <[email protected]>
  #define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
  #define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0017-clk-add-hifsys-reset.patch

@@ -1,7 +1,7 @@
 From 294cf90337d70ad74edf147180bbeef837298bd0 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 6 Jan 2016 20:06:49 +0100
-Subject: [PATCH 17/81] clk: add hifsys reset
+Subject: [PATCH 17/91] clk: add hifsys reset
 
 Hi,
 
@@ -18,9 +18,11 @@ Signed-off-by: John Crispin <[email protected]>
  include/dt-bindings/reset-controller/mt2701-resets.h |    9 +++++++++
  2 files changed, 11 insertions(+)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 39472e4..0e40bb8 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struc
+@@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -29,6 +31,8 @@ Signed-off-by: John Crispin <[email protected]>
  }
  CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt2701-hifsys", mtk_hifsys_init);
  
+diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h b/include/dt-bindings/reset-controller/mt2701-resets.h
+index 00efeb0..aaf0305 100644
 --- a/include/dt-bindings/reset-controller/mt2701-resets.h
 +++ b/include/dt-bindings/reset-controller/mt2701-resets.h
 @@ -71,4 +71,13 @@
@@ -45,3 +49,6 @@ Signed-off-by: John Crispin <[email protected]>
 +#define MT2701_HIFSYS_PCIE2_RST			26
 +
  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0018-dt-bindings-Add-a-binding-for-Mediatek-xHCI-host-con.patch

@@ -1,7 +1,7 @@
 From 84d37aeef94deae3ce87e677f6016a5d980429e8 Mon Sep 17 00:00:00 2001
 From: "[email protected]" <[email protected]>
 Date: Tue, 17 Nov 2015 17:18:39 +0800
-Subject: [PATCH 18/81] dt-bindings: Add a binding for Mediatek xHCI host
+Subject: [PATCH 18/91] dt-bindings: Add a binding for Mediatek xHCI host
  controller
 
 add a DT binding documentation of xHCI host controller for the
@@ -13,6 +13,9 @@ Signed-off-by: Chunfeng Yun <[email protected]>
  1 file changed, 51 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
 
+diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
+new file mode 100644
+index 0000000..a78f20b
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
 @@ -0,0 +1,51 @@
@@ -67,3 +70,6 @@ Signed-off-by: Chunfeng Yun <[email protected]>
 +	mediatek,syscon-wakeup = <&pericfg>;
 +	mediatek,wakeup-src = <1>;
 +};
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0019-xhci-mediatek-support-MTK-xHCI-host-controller.patch

@@ -1,7 +1,7 @@
 From 651d8fff94718c7e48b8a40d7774878eb8ed62ee Mon Sep 17 00:00:00 2001
 From: "[email protected]" <[email protected]>
 Date: Tue, 17 Nov 2015 17:18:40 +0800
-Subject: [PATCH 19/81] xhci: mediatek: support MTK xHCI host controller
+Subject: [PATCH 19/91] xhci: mediatek: support MTK xHCI host controller
 
 There some vendor quirks for MTK xhci host controller:
 1. It defines some extra SW scheduling parameters for HW
@@ -31,6 +31,8 @@ Reviewed-by: Daniel Thompson <[email protected]>
  create mode 100644 drivers/usb/host/xhci-mtk.c
  create mode 100644 drivers/usb/host/xhci-mtk.h
 
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index 3bb0887..daa563f 100644
 --- a/drivers/usb/host/Kconfig
 +++ b/drivers/usb/host/Kconfig
 @@ -41,6 +41,15 @@ config USB_XHCI_PLATFORM
@@ -49,6 +51,8 @@ Reviewed-by: Daniel Thompson <[email protected]>
  config USB_XHCI_MVEBU
  	tristate "xHCI support for Marvell Armada 375/38x"
  	select USB_XHCI_PLATFORM
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index e7558ab..65a06b4 100644
 --- a/drivers/usb/host/Makefile
 +++ b/drivers/usb/host/Makefile
 @@ -13,6 +13,9 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
@@ -69,6 +73,9 @@ Reviewed-by: Daniel Thompson <[email protected]>
  obj-$(CONFIG_USB_SL811_HCD)	+= sl811-hcd.o
  obj-$(CONFIG_USB_SL811_CS)	+= sl811_cs.o
  obj-$(CONFIG_USB_U132_HCD)	+= u132-hcd.o
+diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c
+new file mode 100644
+index 0000000..c30de7c
 --- /dev/null
 +++ b/drivers/usb/host/xhci-mtk-sch.c
 @@ -0,0 +1,415 @@
@@ -487,6 +494,9 @@ Reviewed-by: Daniel Thompson <[email protected]>
 +	}
 +}
 +EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+new file mode 100644
+index 0000000..c9ab6a4
 --- /dev/null
 +++ b/drivers/usb/host/xhci-mtk.c
 @@ -0,0 +1,763 @@
@@ -1253,6 +1263,9 @@ Reviewed-by: Daniel Thompson <[email protected]>
 +MODULE_AUTHOR("Chunfeng Yun <[email protected]>");
 +MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
 +MODULE_LICENSE("GPL v2");
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+new file mode 100644
+index 0000000..7da677c
 --- /dev/null
 +++ b/drivers/usb/host/xhci-mtk.h
 @@ -0,0 +1,162 @@
@@ -1418,6 +1431,8 @@ Reviewed-by: Daniel Thompson <[email protected]>
 +#endif
 +
 +#endif		/* _XHCI_MTK_H_ */
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index eeaa6c6..f1c21c4 100644
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
 @@ -68,6 +68,7 @@
@@ -1428,7 +1443,7 @@ Reviewed-by: Daniel Thompson <[email protected]>
  
  /*
   * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
-@@ -3065,17 +3066,22 @@ static u32 xhci_td_remainder(struct xhci
+@@ -3075,17 +3076,22 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
  {
  	u32 maxp, total_packet_count;
  
@@ -1455,7 +1470,7 @@ Reviewed-by: Daniel Thompson <[email protected]>
  	/* Queueing functions don't count the current TRB into transferred */
  	return (total_packet_count - ((transferred + trb_buff_len) / maxp));
  }
-@@ -3463,7 +3469,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+@@ -3473,7 +3479,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
  		field |= 0x1;
  
  	/* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
@@ -1464,6 +1479,8 @@ Reviewed-by: Daniel Thompson <[email protected]>
  		if (urb->transfer_buffer_length > 0) {
  			if (setup->bRequestType & USB_DIR_IN)
  				field |= TRB_TX_TYPE(TRB_DATA_IN);
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 3f91270..15fedb2 100644
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
 @@ -31,6 +31,7 @@
@@ -1487,7 +1504,7 @@ Reviewed-by: Daniel Thompson <[email protected]>
  	writel(temp, &xhci->ir_set->irq_control);
  
  	/* Set the HCD state before we enable the irqs */
-@@ -1700,6 +1705,9 @@ int xhci_drop_endpoint(struct usb_hcd *h
+@@ -1698,6 +1703,9 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  
  	xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
  
@@ -1497,7 +1514,7 @@ Reviewed-by: Daniel Thompson <[email protected]>
  	xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
  			(unsigned int) ep->desc.bEndpointAddress,
  			udev->slot_id,
-@@ -1795,6 +1803,15 @@ int xhci_add_endpoint(struct usb_hcd *hc
+@@ -1793,6 +1801,15 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  		return -ENOMEM;
  	}
  
@@ -1513,6 +1530,8 @@ Reviewed-by: Daniel Thompson <[email protected]>
  	ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
  	new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
  
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 0b94512..40cf36e 100644
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
 @@ -1630,6 +1630,7 @@ struct xhci_hcd {
@@ -1523,3 +1542,6 @@ Reviewed-by: Daniel Thompson <[email protected]>
  	unsigned int		num_active_eps;
  	unsigned int		limit_active_eps;
  	/* There are two roothubs to keep track of bus suspend info for */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0020-arm64-dts-mediatek-add-xHCI-usb-phy-for-mt8173.patch

@@ -1,7 +1,7 @@
 From 31a22fbd0d3b187be61c4c5d22b19c95abb327c3 Mon Sep 17 00:00:00 2001
 From: "[email protected]" <[email protected]>
 Date: Tue, 17 Nov 2015 17:18:41 +0800
-Subject: [PATCH 20/81] arm64: dts: mediatek: add xHCI & usb phy for mt8173
+Subject: [PATCH 20/91] arm64: dts: mediatek: add xHCI & usb phy for mt8173
 
 add xHCI and phy drivers for MT8173-EVB
 
@@ -11,6 +11,8 @@ Signed-off-by: Chunfeng Yun <[email protected]>
  arch/arm64/boot/dts/mediatek/mt8173.dtsi    |   42 +++++++++++++++++++++++++++
  2 files changed, 58 insertions(+)
 
+diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+index 811cb76..9b1482a 100644
 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
 @@ -13,6 +13,7 @@
@@ -47,6 +49,8 @@ Signed-off-by: Chunfeng Yun <[email protected]>
 +	vbus-supply = <&usb_p1_vbus>;
 +	mediatek,wakeup-src = <1>;
 +};
+diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+index 4dd5f93..c1fd275 100644
 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
 @@ -14,6 +14,7 @@
@@ -105,3 +109,6 @@ Signed-off-by: Chunfeng Yun <[email protected]>
  		mmsys: clock-controller@14000000 {
  			compatible = "mediatek,mt8173-mmsys", "syscon";
  			reg = <0 0x14000000 0 0x1000>;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0021-Document-DT-Add-bindings-for-mediatek-MT7623-SoC-Pla.patch

@@ -1,7 +1,7 @@
 From 162deec293400cb132161606629654acaec7cb4b Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 5 Jan 2016 12:13:54 +0100
-Subject: [PATCH 21/81] Document: DT: Add bindings for mediatek MT7623 SoC
+Subject: [PATCH 21/91] Document: DT: Add bindings for mediatek MT7623 SoC
  Platform
 
 This adds a DT binding documentation for the MT7623 SoC from Mediatek.
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <[email protected]>
  Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt |    1 +
  3 files changed, 6 insertions(+)
 
+diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
+index 618a9199..40e9d32 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek.txt
 @@ -10,6 +10,7 @@ compatible: Must contain one of
@@ -33,6 +35,8 @@ Signed-off-by: John Crispin <[email protected]>
  - MTK mt8127 tablet moose EVB:
      Required root node properties:
        - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
+diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
+index 2d47add..474f0cf 100644
 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
 +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
 @@ -2,6 +2,7 @@
@@ -43,6 +47,8 @@ Signed-off-by: John Crispin <[email protected]>
    * "mediatek,mt8135-uart" for MT8135 compatible UARTS
    * "mediatek,mt8127-uart" for MT8127 compatible UARTS
    * "mediatek,mt8173-uart" for MT8173 compatible UARTS
+diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+index 64083bc..6bacda1b3 100644
 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
 +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
 @@ -5,6 +5,7 @@ Required properties:
@@ -53,3 +59,6 @@ Signed-off-by: John Crispin <[email protected]>
  	* "mediatek,mt8127-timer" for MT8127 compatible timers
  	* "mediatek,mt8135-timer" for MT8135 compatible timers
  	* "mediatek,mt8173-timer" for MT8173 compatible timers
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0022-soc-mediatek-add-compat-string-for-mt7623-to-scpsys.patch

@@ -1,16 +1,18 @@
 From fa5d94d6b4b314f751b1c32bb5a87a80b866d05e Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 5 Jan 2016 16:52:31 +0100
-Subject: [PATCH 22/81] soc: mediatek: add compat string for mt7623 to scpsys
+Subject: [PATCH 22/91] soc: mediatek: add compat string for mt7623 to scpsys
 
 Signed-off-by: John Crispin <[email protected]>
 ---
  drivers/soc/mediatek/mtk-scpsys-mt2701.c |    2 ++
  1 file changed, 2 insertions(+)
 
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
+index 339d5b8..3a31946 100644
 --- a/drivers/soc/mediatek/mtk-scpsys-mt2701.c
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
-@@ -136,6 +136,8 @@ static const struct of_device_id of_scps
+@@ -136,6 +136,8 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
  	{
  		.compatible = "mediatek,mt2701-scpsys",
  	}, {
@@ -19,3 +21,6 @@ Signed-off-by: John Crispin <[email protected]>
  		/* sentinel */
  	}
  };
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch

@@ -1,21 +1,23 @@
-From a4df3e7e4e906a4e9dac1f8c43f6192f22ef6242 Mon Sep 17 00:00:00 2001
+From 5536a546755527a862cb2494814c5244d3d8e30a Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 5 Jan 2016 12:16:17 +0100
-Subject: [PATCH 23/81] ARM: dts: mediatek: add MT7623 basic support
+Subject: [PATCH 23/91] ARM: dts: mediatek: add MT7623 basic support
 
 This adds basic chip support for Mediatek MT7623.
 
 Signed-off-by: John Crispin <[email protected]>
 ---
  arch/arm/boot/dts/Makefile        |    1 +
- arch/arm/boot/dts/mt7623-evb.dts  |  459 +++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7623.dtsi     |  510 +++++++++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7623-evb.dts  |  474 ++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7623.dtsi     |  583 +++++++++++++++++++++++++++++++++++++
  arch/arm/mach-mediatek/Kconfig    |    4 +
  arch/arm/mach-mediatek/mediatek.c |    1 +
- 5 files changed, 975 insertions(+)
+ 5 files changed, 1063 insertions(+)
  create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
  create mode 100644 arch/arm/boot/dts/mt7623.dtsi
 
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 30bbc37..2bce370 100644
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -26,9 +28,12 @@ Signed-off-by: John Crispin <[email protected]>
  	mt8127-moose.dtb \
  	mt8135-evbp1.dtb
  dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
+diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
+new file mode 100644
+index 0000000..70b92a4
 --- /dev/null
 +++ b/arch/arm/boot/dts/mt7623-evb.dts
-@@ -0,0 +1,459 @@
+@@ -0,0 +1,474 @@
 +/*
 + * Copyright (c) 2016 MediaTek Inc.
 + * Author: John Crispin <[email protected]>
@@ -70,6 +75,22 @@ Signed-off-by: John Crispin <[email protected]>
 +	};
 +};
 +
++&cpu0 {
++	proc-supply = <&mt6323_vproc_reg>;
++};
++
++&cpu1 {
++	proc-supply = <&mt6323_vproc_reg>;
++};
++
++&cpu2 {
++	proc-supply = <&mt6323_vproc_reg>;
++};
++
++&cpu3 {
++	proc-supply = <&mt6323_vproc_reg>;
++};
++
 +&pwrap {
 +	pmic: mt6323 {
 +		compatible = "mediatek,mt6323";
@@ -456,7 +477,6 @@ Signed-off-by: John Crispin <[email protected]>
 +&usb1 {
 +	vusb33-supply = <&mt6323_vusb_reg>;
 +	vbus-supply = <&usb_p1_vbus>;
-+//	mediatek,wakeup-src = <1>;
 +	status = "okay";
 +};
 +
@@ -488,9 +508,12 @@ Signed-off-by: John Crispin <[email protected]>
 +	mediatek,reset-pin = <&pio 15 0>;
 +	status = "okay";
 +};
+diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
+new file mode 100644
+index 0000000..0536b2c
 --- /dev/null
 +++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -0,0 +1,510 @@
+@@ -0,0 +1,583 @@
 +/*
 + * Copyright (c) 2016 MediaTek Inc.
 + * Author: John Crispin <[email protected]>
@@ -524,25 +547,65 @@ Signed-off-by: John Crispin <[email protected]>
 +		#size-cells = <0>;
 +		enable-method = "mediatek,mt6589-smp";
 +
-+		cpu@0 {
++		cpu0: cpu@0 {
 +			device_type = "cpu";
 +			compatible = "arm,cortex-a7";
 +			reg = <0x0>;
++			clocks = <&infracfg CLK_INFRA_CPUSEL>,
++				 <&apmixedsys CLK_APMIXED_MAINPLL>;
++			clock-names = "cpu", "intermediate";
++			operating-points = <
++				598000 1150000
++				747500 1150000
++				1040000 1150000
++				1196000 1200000
++				1300000 1300000
++			>;
 +		};
-+		cpu@1 {
++		cpu1: cpu@1 {
 +			device_type = "cpu";
 +			compatible = "arm,cortex-a7";
 +			reg = <0x1>;
++			clocks = <&infracfg CLK_INFRA_CPUSEL>,
++				 <&apmixedsys CLK_APMIXED_MAINPLL>;
++			clock-names = "cpu", "intermediate";
++			operating-points = <
++				598000 1150000
++				747500 1150000
++				1040000 1150000
++				1196000 1200000
++				1300000 1300000
++			>;
 +		};
-+		cpu@2 {
++		cpu2: cpu@2 {
 +			device_type = "cpu";
 +			compatible = "arm,cortex-a7";
 +			reg = <0x2>;
++			clocks = <&infracfg CLK_INFRA_CPUSEL>,
++				 <&apmixedsys CLK_APMIXED_MAINPLL>;
++			clock-names = "cpu", "intermediate";
++			operating-points = <
++				598000 1150000
++				747500 1150000
++				1040000 1150000
++				1196000 1200000
++				1300000 1300000
++			>;
 +		};
-+		cpu@3 {
++		cpu3: cpu@3 {
 +			device_type = "cpu";
 +			compatible = "arm,cortex-a7";
 +			reg = <0x3>;
++			clocks = <&infracfg CLK_INFRA_CPUSEL>,
++				 <&apmixedsys CLK_APMIXED_MAINPLL>;
++			clock-names = "cpu", "intermediate";
++			operating-points = <
++				598000 1150000
++				747500 1150000
++				1040000 1150000
++				1196000 1200000
++				1300000 1300000
++			>;
 +		};
 +	};
 +
@@ -573,6 +636,8 @@ Signed-off-by: John Crispin <[email protected]>
 +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++		clock-frequency = <13000000>;
++		arm,cpu-registers-not-fw-configured;
 +	};
 +
 +	topckgen: power-controller@10000000 {
@@ -785,6 +850,18 @@ Signed-off-by: John Crispin <[email protected]>
 +		status = "disabled";
 +	};
 +
++	nand: nfi@1100d000 {
++		compatible = "mediatek,mt2701-nfc";
++		reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
++		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
++			     <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
++			 <&pericfg CLK_PERI_NFI_PAD>;
++		clock-names = "nfi_clk", "nfiecc_clk", "pad_clk";
++	//	nand-on-flash-bbt;
++		status = "disabled";
++	};
++
 +	mmc0: mmc@11230000 {
 +		compatible = "mediatek,mt7623-mmc",
 +			     "mediatek,mt8135-mmc";
@@ -934,25 +1011,32 @@ Signed-off-by: John Crispin <[email protected]>
 +	};
 +
 +	ethsys: syscon@1b000000 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
 +		compatible = "mediatek,mt2701-ethsys", "syscon";
 +		reg = <0 0x1b000000 0 0x1000>;
++		#reset-cells = <1>;
 +		#clock-cells = <1>;
 +	};
 +
 +	eth: ethernet@1b100000 {
 +		compatible = "mediatek,mt7623-eth";
-+		reg = <0 0x1b100000 0 0x10000>;
++		reg = <0 0x1b100000 0 0x20000>;
 +	
-+		clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
-+		clock-names = "ethif";
++		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
++			 <&ethsys CLK_ETHSYS_ESW>,
++			 <&ethsys CLK_ETHSYS_GP2>,
++			 <&ethsys CLK_ETHSYS_GP1>;
++		clock-names = "ethif", "esw", "gp2", "gp1";
 +		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
 +			      GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
 +			      GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 +
++		resets = <&ethsys 6>;
++		reset-names = "eth";
++
 +		mediatek,ethsys = <&ethsys>;
++		mediatek,pctl = <&syscfg_pctl_a>;
++
 +		mediatek,switch = <&gsw>;
 +
 +		#address-cells = <1>;
@@ -965,12 +1049,21 @@ Signed-off-by: John Crispin <[email protected]>
 +			reg = <0>;
 +
 +			status = "disabled";
++			
++			phy-mode = "rgmii";
++			
++			fixed-link {
++				speed = <1000>;
++				full-duplex;
++				pause;
++			};
 +		};
 +
 +		gmac2: mac@1 {
 +			compatible = "mediatek,eth-mac";
 +			reg = <1>;
 +
++			phy-handle = <&phy5>;
 +			status = "disabled";
 +		};
 +	
@@ -978,6 +1071,11 @@ Signed-off-by: John Crispin <[email protected]>
 +			#address-cells = <1>;
 +			#size-cells = <0>;
 +
++			phy5: ethernet-phy@5 {
++				reg = <5>;
++				phy-mode = "rgmii-rxid";
++			};
++
 +			phy1f: ethernet-phy@1f {
 +				reg = <0x1f>;
 +				phy-mode = "rgmii";
@@ -987,20 +1085,20 @@ Signed-off-by: John Crispin <[email protected]>
 +
 +	gsw: switch@1b100000 {
 +		compatible = "mediatek,mt7623-gsw";
-+		reg = <0 0x1b110000 0 0x300000>;
 +		interrupt-parent = <&pio>;
 +		interrupts = <168 IRQ_TYPE_EDGE_RISING>;
-+		clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
-+			 <&ethsys CLK_ETHSYS_ESW>,
-+			 <&ethsys CLK_ETHSYS_GP2>,
-+			 <&ethsys CLK_ETHSYS_GP1>;
-+		clock-names = "trgpll", "esw", "gp2", "gp1";
++		resets = <&ethsys 2>;
++		reset-names = "eth";
++		clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
++		clock-names = "trgpll";
 +		mt7530-supply = <&mt6323_vpa_reg>;
 +		mediatek,pctl-regmap = <&syscfg_pctl_a>;
 +		mediatek,ethsys = <&ethsys>;
 +		status = "disabled";
 +	};
 +};
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index 37dd438..7fb605e 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -21,6 +21,10 @@ config MACH_MT6592
@@ -1014,9 +1112,11 @@ Signed-off-by: John Crispin <[email protected]>
  config MACH_MT8127
  	bool "MediaTek MT8127 SoCs support"
  	default ARCH_MEDIATEK
+diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
+index d019a08..bcfca37 100644
 --- a/arch/arm/mach-mediatek/mediatek.c
 +++ b/arch/arm/mach-mediatek/mediatek.c
-@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(v
+@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(void)
  static const char * const mediatek_board_dt_compat[] = {
  	"mediatek,mt6589",
  	"mediatek,mt6592",
@@ -1024,3 +1124,6 @@ Signed-off-by: John Crispin <[email protected]>
  	"mediatek,mt8127",
  	"mediatek,mt8135",
  	NULL,
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0024-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch

@@ -1,15 +1,17 @@
-From 97478bae3a11b5e87d61b88267e915f7c5ddf4e9 Mon Sep 17 00:00:00 2001
+From 0afae16fffe2cf547fad21279c120bedf19e9b8e Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 6 Jan 2016 21:55:10 +0100
-Subject: [PATCH 24/81] dt-bindings: add MediaTek PCIe binding documentation
+Subject: [PATCH 24/91] dt-bindings: add MediaTek PCIe binding documentation
 
 Signed-off-by: John Crispin <[email protected]>
 ---
  .../devicetree/bindings/pci/mediatek-pcie.txt      |  140 ++++++++++++++++++++
- arch/arm/boot/dts/mt7623.dtsi                      |   12 ++
- 2 files changed, 152 insertions(+)
+ 1 file changed, 140 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 
+diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+new file mode 100644
+index 0000000..8fea3ed
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 @@ -0,0 +1,140 @@
@@ -153,24 +155,6 @@ Signed-off-by: John Crispin <[email protected]>
 +			status = "okay";
 +		};
 +	};
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -292,6 +292,18 @@
- 		status = "disabled";
- 	};
- 
-+	nand: nfi@1100d000 {
-+		compatible = "mediatek,mt2701-nfc";
-+		reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
-+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
-+		clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
-+			 <&pericfg CLK_PERI_NFI_PAD>;
-+		clock-names = "nfi_clk", "nfiecc_clk", "pad_clk";
-+		nand-on-flash-bbt;
-+		status = "disabled";
-+	};
-+
- 	mmc0: mmc@11230000 {
- 		compatible = "mediatek,mt7623-mmc",
- 			     "mediatek,mt8135-mmc";
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0025-PCI-mediatek-add-support-for-PCIe-found-on-MT7623-MT.patch

@@ -1,7 +1,7 @@
-From b44b44cfdcb9b2d7ba513d24df1b16b8c57cce59 Mon Sep 17 00:00:00 2001
+From 4e9a4574e833ee42d646de2dc3b0cb912360e6c5 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 5 Jan 2016 20:20:04 +0100
-Subject: [PATCH 25/81] PCI: mediatek: add support for PCIe found on
+Subject: [PATCH 25/91] PCI: mediatek: add support for PCIe found on
  MT7623/MT2701
 
 Add PCIe controller support on MediaTek MT2701/MT7623. The driver supports
@@ -17,6 +17,8 @@ Signed-off-by: John Crispin <[email protected]>
  4 files changed, 654 insertions(+)
  create mode 100644 drivers/pci/host/pcie-mediatek.c
 
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index 7fb605e..a7fef77 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -24,6 +24,7 @@ config MACH_MT6592
@@ -27,9 +29,11 @@ Signed-off-by: John Crispin <[email protected]>
  
  config MACH_MT8127
  	bool "MediaTek MT8127 SoCs support"
+diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
+index f131ba9..912f0e1 100644
 --- a/drivers/pci/host/Kconfig
 +++ b/drivers/pci/host/Kconfig
-@@ -173,4 +173,15 @@ config PCI_HISI
+@@ -172,4 +172,15 @@ config PCI_HISI
  	help
  	  Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
  
@@ -45,13 +49,18 @@ Signed-off-by: John Crispin <[email protected]>
 +	  PCIe include one Host/PCI bridge and 3 PCIe MAC.
 +
  endmenu
+diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
+index 9d4d3c6..3b53374 100644
 --- a/drivers/pci/host/Makefile
 +++ b/drivers/pci/host/Makefile
-@@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-ip
+@@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
  obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
  obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
  obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
 +obj-$(CONFIG_PCIE_MTK) += pcie-mediatek.o
+diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
+new file mode 100644
+index 0000000..ef03952
 --- /dev/null
 +++ b/drivers/pci/host/pcie-mediatek.c
 @@ -0,0 +1,641 @@
@@ -696,3 +705,6 @@ Signed-off-by: John Crispin <[email protected]>
 +}
 +
 +module_init(mtk_pcie_init);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0026-scpsys-various-fixes.patch

@@ -1,7 +1,7 @@
-From fe8fd85507870bf3aa5ff257944f15b50888d17c Mon Sep 17 00:00:00 2001
+From e56caadcf189eafcd2c7a9e22f22c0b67e89df75 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Sun, 21 Feb 2016 13:52:12 +0100
-Subject: [PATCH 26/81] scpsys: various fixes
+Subject: [PATCH 26/91] scpsys: various fixes
 
 ---
  drivers/clk/mediatek/clk-mt2701.c        |    2 ++
@@ -9,9 +9,11 @@ Subject: [PATCH 26/81] scpsys: various fixes
  include/dt-bindings/power/mt2701-power.h |    4 ++--
  3 files changed, 4 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 0e40bb8..812b347 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -1043,6 +1043,8 @@ static void __init mtk_ethsys_init(struc
+@@ -1043,6 +1043,8 @@ static void __init mtk_ethsys_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -20,9 +22,11 @@ Subject: [PATCH 26/81] scpsys: various fixes
  }
  CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt2701-ethsys", mtk_ethsys_init);
  
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
+index 3a31946..19489bc 100644
 --- a/drivers/soc/mediatek/mtk-scpsys-mt2701.c
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
-@@ -61,14 +61,6 @@ static const struct scp_domain_data scp_
+@@ -61,14 +61,6 @@ static const struct scp_domain_data scp_domain_data[] = {
  		.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_DISP,
  		.active_wakeup = true,
  	},
@@ -37,6 +41,8 @@ Subject: [PATCH 26/81] scpsys: various fixes
  	[MT2701_POWER_DOMAIN_VDEC] = {
  		.name = "vdec",
  		.sta_mask = VDE_PWR_STA_MASK,
+diff --git a/include/dt-bindings/power/mt2701-power.h b/include/dt-bindings/power/mt2701-power.h
+index 64cc826..c168597 100644
 --- a/include/dt-bindings/power/mt2701-power.h
 +++ b/include/dt-bindings/power/mt2701-power.h
 @@ -16,12 +16,12 @@
@@ -54,3 +60,6 @@ Subject: [PATCH 26/81] scpsys: various fixes
 +#define MT2701_POWER_DOMAIN_IFR_MSC	2
  
  #endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0027-soc-mediatek-PMIC-wrap-Clear-the-vldclr-if-state-mac.patch

@@ -1,7 +1,7 @@
-From 2fc7dd0f48d9c2096d76562a1960b78b064701f7 Mon Sep 17 00:00:00 2001
+From 036862011a5d13e8c54d9d0f9fe838fea986df89 Mon Sep 17 00:00:00 2001
 From: Henry Chen <[email protected]>
 Date: Mon, 4 Jan 2016 20:02:52 +0800
-Subject: [PATCH 27/81] soc: mediatek: PMIC wrap: Clear the vldclr if state
+Subject: [PATCH 27/91] soc: mediatek: PMIC wrap: Clear the vldclr if state
  machine stay on FSM_VLDCLR state.
 
 Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout,
@@ -20,9 +20,11 @@ Signed-off-by: Matthias Brugger <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   22 ++++++++++++++++++++--
  1 file changed, 20 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 105597a..696071b 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -412,6 +412,20 @@ static bool pwrap_is_fsm_vldclr(struct p
+@@ -412,6 +412,20 @@ static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
  	return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
  }
  
@@ -43,7 +45,7 @@ Signed-off-by: Matthias Brugger <[email protected]>
  static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
  {
  	return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
-@@ -445,8 +459,10 @@ static int pwrap_write(struct pmic_wrapp
+@@ -445,8 +459,10 @@ static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
  	int ret;
  
  	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
@@ -55,7 +57,7 @@ Signed-off-by: Matthias Brugger <[email protected]>
  
  	pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
  			PWRAP_WACS2_CMD);
-@@ -459,8 +475,10 @@ static int pwrap_read(struct pmic_wrappe
+@@ -459,8 +475,10 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
  	int ret;
  
  	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
@@ -67,3 +69,6 @@ Signed-off-by: Matthias Brugger <[email protected]>
  
  	pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0028-ARM-mediatek-add-MT7623-smp-bringup-code.patch

@@ -1,7 +1,7 @@
-From b7d11ec865f99085a907f1a082f70404734e954c Mon Sep 17 00:00:00 2001
+From a7b6aff661303f2c67e3f8d03b152fd6a0a19ac2 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 5 Jan 2016 17:24:28 +0100
-Subject: [PATCH 28/81] ARM: mediatek: add MT7623 smp bringup code
+Subject: [PATCH 28/91] ARM: mediatek: add MT7623 smp bringup code
 
 Add support for booting secondary CPUs on MT7623.
 
@@ -11,9 +11,11 @@ Signed-off-by: Matthias Brugger <[email protected]>
  arch/arm/mach-mediatek/platsmp.c |    7 +++++++
  1 file changed, 7 insertions(+)
 
+diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
+index 8141f3f..8151400 100644
 --- a/arch/arm/mach-mediatek/platsmp.c
 +++ b/arch/arm/mach-mediatek/platsmp.c
-@@ -44,6 +44,12 @@ static const struct mtk_smp_boot_info mt
+@@ -44,6 +44,12 @@ static const struct mtk_smp_boot_info mtk_mt6589_boot = {
  	{ 0x38, 0x3c, 0x40 },
  };
  
@@ -26,7 +28,7 @@ Signed-off-by: Matthias Brugger <[email protected]>
  static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
  	{ .compatible   = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
  	{ .compatible   = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
-@@ -51,6 +57,7 @@ static const struct of_device_id mtk_tz_
+@@ -51,6 +57,7 @@ static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
  
  static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
  	{ .compatible   = "mediatek,mt6589", .data = &mtk_mt6589_boot },
@@ -34,3 +36,6 @@ Signed-off-by: Matthias Brugger <[email protected]>
  };
  
  static void __iomem *mtk_smp_base;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0029-soc-mediatek-PMIC-wrap-clear-the-STAUPD_TRIG-bit-of-.patch

@@ -1,7 +1,7 @@
-From 7e0c3f4f4c7a55eda670c97b1b3b793ceecc1655 Mon Sep 17 00:00:00 2001
+From 4fbf092b199a344abe60528732c712ec3b22aa67 Mon Sep 17 00:00:00 2001
 From: Henry Chen <[email protected]>
 Date: Thu, 21 Jan 2016 19:04:00 +0800
-Subject: [PATCH 29/81] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of
+Subject: [PATCH 29/91] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of
  WDT_SRC_EN
 
 Since STAUPD interrupts aren't handled on mt8173, disable watchdog timeout
@@ -14,6 +14,8 @@ Signed-off-by: Matthias Brugger <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   19 +++++++++++++++++--
  1 file changed, 17 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 696071b..0d9b19a 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -60,6 +60,15 @@
@@ -32,7 +34,7 @@ Signed-off-by: Matthias Brugger <[email protected]>
  /* macro for slave device wrapper registers */
  #define PWRAP_DEW_BASE			0xbc00
  #define PWRAP_DEW_EVENT_OUT_EN		(PWRAP_DEW_BASE + 0x0)
-@@ -822,7 +831,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_t
+@@ -822,7 +831,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
  
  static int pwrap_probe(struct platform_device *pdev)
  {
@@ -41,7 +43,7 @@ Signed-off-by: Matthias Brugger <[email protected]>
  	struct pmic_wrapper *wrp;
  	struct device_node *np = pdev->dev.of_node;
  	const struct of_device_id *of_id =
-@@ -912,7 +921,13 @@ static int pwrap_probe(struct platform_d
+@@ -912,7 +921,13 @@ static int pwrap_probe(struct platform_device *pdev)
  
  	/* Initialize watchdog, may not be done by the bootloader */
  	pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
@@ -56,3 +58,6 @@ Signed-off-by: Matthias Brugger <[email protected]>
  	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
  	pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0030-ARM-mediatek-add-mt2701-smp-bringup-code.patch

@@ -1,7 +1,7 @@
-From 672ed0995e4ebf3f14bb58d08d6ba4c78337b90b Mon Sep 17 00:00:00 2001
+From 4203a164bbf1785b649bc8d7a94ede53a33ad92a Mon Sep 17 00:00:00 2001
 From: Louis Yu <[email protected]>
 Date: Thu, 7 Jan 2016 20:09:43 +0800
-Subject: [PATCH 30/81] ARM: mediatek: add mt2701 smp bringup code
+Subject: [PATCH 30/91] ARM: mediatek: add mt2701 smp bringup code
 
 Add support for booting secondary CPUs on mt2701.
 
@@ -11,9 +11,11 @@ Signed-off-by: Matthias Brugger <[email protected]>
  arch/arm/mach-mediatek/platsmp.c |    1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
+index 8151400..2078f92d5 100644
 --- a/arch/arm/mach-mediatek/platsmp.c
 +++ b/arch/arm/mach-mediatek/platsmp.c
-@@ -53,6 +53,7 @@ static const struct mtk_smp_boot_info mt
+@@ -53,6 +53,7 @@ static const struct mtk_smp_boot_info mtk_mt7623_boot = {
  static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
  	{ .compatible   = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
  	{ .compatible   = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
@@ -21,3 +23,6 @@ Signed-off-by: Matthias Brugger <[email protected]>
  };
  
  static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0031-dt-bindings-ARM-Mediatek-add-MT2701-7623-string-to-t.patch

@@ -1,7 +1,7 @@
-From 1474be4d7f9559804671ab01911232368496a1de Mon Sep 17 00:00:00 2001
+From 55308931b04c0353fd1f3367fb018af5bb643a9a Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 13:12:19 +0100
-Subject: [PATCH 31/81] dt-bindings: ARM: Mediatek: add MT2701/7623 string to
+Subject: [PATCH 31/91] dt-bindings: ARM: Mediatek: add MT2701/7623 string to
  the PMIC wrapper doc
 
 Signed-off-by: John Crispin <[email protected]>
@@ -11,6 +11,8 @@ Cc: [email protected]
  Documentation/devicetree/bindings/soc/mediatek/pwrap.txt |    1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+index ddeb5b6..107700d 100644
 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
 +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
 @@ -18,6 +18,7 @@ IP Pairing
@@ -21,3 +23,6 @@ Cc: [email protected]
  	"mediatek,mt8135-pwrap" for MT8135 SoCs
  	"mediatek,mt8173-pwrap" for MT8173 SoCs
  - interrupts: IRQ for pwrap in SOC
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0032-soc-mediatek-PMIC-wrap-don-t-duplicate-the-wrapper-d.patch

@@ -1,7 +1,7 @@
-From 542f2cd3287fb955efcc5ceca14b690ba19f8c57 Mon Sep 17 00:00:00 2001
+From e2b8f38b1a794b7a0912d0bbaa1454055b5cbac2 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 06:42:01 +0100
-Subject: [PATCH 32/81] soc: mediatek: PMIC wrap: don't duplicate the wrapper
+Subject: [PATCH 32/91] soc: mediatek: PMIC wrap: don't duplicate the wrapper
  data
 
 As we add support for more devices struct pmic_wrapper_type will grow and
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   22 ++++++++--------------
  1 file changed, 8 insertions(+), 14 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 0d9b19a..340c4b5 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -376,9 +376,7 @@ struct pmic_wrapper {
@@ -53,7 +55,7 @@ Signed-off-by: John Crispin <[email protected]>
  }
  
  static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
-@@ -697,7 +695,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -697,7 +695,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  
  	pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
  
@@ -62,7 +64,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
  
-@@ -742,7 +740,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -742,7 +740,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
  	pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
  	pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
@@ -71,7 +73,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	if (pwrap_is_mt8135(wrp))
  		pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
-@@ -836,7 +834,6 @@ static int pwrap_probe(struct platform_d
+@@ -836,7 +834,6 @@ static int pwrap_probe(struct platform_device *pdev)
  	struct device_node *np = pdev->dev.of_node;
  	const struct of_device_id *of_id =
  		of_match_device(of_pwrap_match_tbl, &pdev->dev);
@@ -79,7 +81,7 @@ Signed-off-by: John Crispin <[email protected]>
  	struct resource *res;
  
  	wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
-@@ -845,10 +842,7 @@ static int pwrap_probe(struct platform_d
+@@ -845,10 +842,7 @@ static int pwrap_probe(struct platform_device *pdev)
  
  	platform_set_drvdata(pdev, wrp);
  
@@ -91,3 +93,6 @@ Signed-off-by: John Crispin <[email protected]>
  	wrp->dev = &pdev->dev;
  
  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0033-soc-mediatek-PMIC-wrap-add-wrapper-callbacks-for-ini.patch

@@ -1,7 +1,7 @@
-From 915340f70c0594d1f0717fee3eb678fa71206509 Mon Sep 17 00:00:00 2001
+From 4265837216132e2b1c04b23e77281c1a4feb6ca8 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 05:27:17 +0100
-Subject: [PATCH 33/81] soc: mediatek: PMIC wrap: add wrapper callbacks for
+Subject: [PATCH 33/91] soc: mediatek: PMIC wrap: add wrapper callbacks for
  init_reg_clock
 
 Split init_reg_clock up into SoC specific callbacks. The patch also
@@ -12,6 +12,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   70 ++++++++++++++++++----------------
  1 file changed, 38 insertions(+), 32 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 340c4b5..b22b664 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -354,24 +354,6 @@ enum pwrap_type {
@@ -53,7 +55,7 @@ Signed-off-by: John Crispin <[email protected]>
  static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
  {
  	return wrp->master->type == PWRAP_MT8135;
-@@ -578,20 +567,23 @@ static int pwrap_init_sidly(struct pmic_
+@@ -578,20 +567,23 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
  	return 0;
  }
  
@@ -90,7 +92,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	return 0;
  }
-@@ -699,7 +691,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -699,7 +691,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  
  	pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
  
@@ -99,7 +101,7 @@ Signed-off-by: John Crispin <[email protected]>
  	if (ret)
  		return ret;
  
-@@ -814,6 +806,20 @@ static const struct regmap_config pwrap_
+@@ -814,6 +806,20 @@ static const struct regmap_config pwrap_regmap_config = {
  	.max_register = 0xffff,
  };
  
@@ -120,3 +122,6 @@ Signed-off-by: John Crispin <[email protected]>
  static struct of_device_id of_pwrap_match_tbl[] = {
  	{
  		.compatible = "mediatek,mt8135-pwrap",
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0034-soc-mediatek-PMIC-wrap-split-SoC-specific-init-into-.patch

@@ -1,7 +1,7 @@
-From b2287b0afb757870ce0f4324bb4bc597d3f90a2a Mon Sep 17 00:00:00 2001
+From b164dff8be266b531574e89a27eb3ce9e0b4e40a Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 10:12:00 +0100
-Subject: [PATCH 34/81] soc: mediatek: PMIC wrap: split SoC specific init into
+Subject: [PATCH 34/91] soc: mediatek: PMIC wrap: split SoC specific init into
  callback
 
 This patch moves the SoC specific wrapper init code into separate callback
@@ -16,6 +16,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   67 +++++++++++++++++++++-------------
  1 file changed, 42 insertions(+), 25 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index b22b664..22c89e9 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -372,6 +372,7 @@ struct pmic_wrapper_type {
@@ -26,7 +28,7 @@ Signed-off-by: John Crispin <[email protected]>
  };
  
  static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
-@@ -665,6 +666,41 @@ static int pwrap_init_cipher(struct pmic
+@@ -665,6 +666,41 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	return 0;
  }
  
@@ -68,7 +70,7 @@ Signed-off-by: John Crispin <[email protected]>
  static int pwrap_init(struct pmic_wrapper *wrp)
  {
  	int ret;
-@@ -743,31 +779,10 @@ static int pwrap_init(struct pmic_wrappe
+@@ -743,31 +779,10 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
  	pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
  
@@ -104,7 +106,7 @@ Signed-off-by: John Crispin <[email protected]>
  	}
  
  	/* Setup the init done registers */
-@@ -811,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -811,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.type = PWRAP_MT8135,
  	.arb_en_all = 0x1ff,
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
@@ -112,7 +114,7 @@ Signed-off-by: John Crispin <[email protected]>
  };
  
  static struct pmic_wrapper_type pwrap_mt8173 = {
-@@ -818,6 +834,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -818,6 +834,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.type = PWRAP_MT8173,
  	.arb_en_all = 0x3f,
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
@@ -120,3 +122,6 @@ Signed-off-by: John Crispin <[email protected]>
  };
  
  static struct of_device_id of_pwrap_match_tbl[] = {
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0035-soc-mediatek-PMIC-wrap-WRAP_INT_EN-needs-a-different.patch

@@ -1,7 +1,7 @@
-From 76f0c7770046ed436be085af1257e0ab06fdd41f Mon Sep 17 00:00:00 2001
+From 7046dc2a485b2b2ec993d7c933820c8ae2b45718 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 10:14:39 +0100
-Subject: [PATCH 35/81] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
+Subject: [PATCH 35/91] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
  different bitmask for MT2701/7623
 
 MT2701 and MT7623 use a different bitmask for PWRAP_INT_EN.
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |    5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 22c89e9..9df1135 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -371,6 +371,7 @@ struct pmic_wrapper_type {
@@ -21,7 +23,7 @@ Signed-off-by: John Crispin <[email protected]>
  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
  };
-@@ -825,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -825,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.regs = mt8135_regs,
  	.type = PWRAP_MT8135,
  	.arb_en_all = 0x1ff,
@@ -29,7 +31,7 @@ Signed-off-by: John Crispin <[email protected]>
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -833,6 +835,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -833,6 +835,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.regs = mt8173_regs,
  	.type = PWRAP_MT8173,
  	.arb_en_all = 0x3f,
@@ -37,7 +39,7 @@ Signed-off-by: John Crispin <[email protected]>
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
  	.init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
-@@ -946,7 +949,7 @@ static int pwrap_probe(struct platform_d
+@@ -946,7 +949,7 @@ static int pwrap_probe(struct platform_device *pdev)
  			PWRAP_WDT_SRC_MASK_NO_STAUPD : PWRAP_WDT_SRC_MASK_ALL;
  	pwrap_writel(wrp, wdt_src, PWRAP_WDT_SRC_EN);
  	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
@@ -46,3 +48,6 @@ Signed-off-by: John Crispin <[email protected]>
  
  	irq = platform_get_irq(pdev, 0);
  	ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0036-soc-mediatek-PMIC-wrap-SPI_WRITE-needs-a-different-b.patch

@@ -1,7 +1,7 @@
-From fca1819591e7824d474c900a3524c0c1fee6a300 Mon Sep 17 00:00:00 2001
+From 506b811d75ec94b10eda673f8677ef507f870077 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 10:21:42 +0100
-Subject: [PATCH 36/81] soc: mediatek: PMIC wrap: SPI_WRITE needs a different
+Subject: [PATCH 36/91] soc: mediatek: PMIC wrap: SPI_WRITE needs a different
  bitmask for MT2701/7623
 
 Different SoCs will use different bitmask for the SPI_WRITE command. This
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   11 +++++++----
  1 file changed, 7 insertions(+), 4 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 9df1135..8ce1bad 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -372,6 +372,7 @@ struct pmic_wrapper_type {
@@ -23,7 +25,7 @@ Signed-off-by: John Crispin <[email protected]>
  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
  };
-@@ -511,15 +512,15 @@ static int pwrap_reset_spislave(struct p
+@@ -511,15 +512,15 @@ static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 1, PWRAP_MAN_EN);
  	pwrap_writel(wrp, 0, PWRAP_DIO_EN);
  
@@ -43,7 +45,7 @@ Signed-off-by: John Crispin <[email protected]>
  				PWRAP_MAN_CMD);
  
  	ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
-@@ -827,6 +828,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -827,6 +828,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.type = PWRAP_MT8135,
  	.arb_en_all = 0x1ff,
  	.int_en_all = ~(BIT(31) | BIT(1)),
@@ -51,7 +53,7 @@ Signed-off-by: John Crispin <[email protected]>
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -836,6 +838,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -836,6 +838,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.type = PWRAP_MT8173,
  	.arb_en_all = 0x3f,
  	.int_en_all = ~(BIT(31) | BIT(1)),
@@ -59,3 +61,6 @@ Signed-off-by: John Crispin <[email protected]>
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
  	.init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0037-soc-mediatek-PMIC-wrap-move-wdt_src-into-the-pmic_wr.patch

@@ -1,7 +1,7 @@
-From dfdef729324d87d40468f76f0f2767a09c9b0ab0 Mon Sep 17 00:00:00 2001
+From df7e52743b8159b2cc58fce14841135de84ec81a Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 10:48:35 +0100
-Subject: [PATCH 37/81] soc: mediatek: PMIC wrap: move wdt_src into the
+Subject: [PATCH 37/91] soc: mediatek: PMIC wrap: move wdt_src into the
  pmic_wrapper_type struct
 
 Different SoCs will use different bitmask for the wdt_src. This patch
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |    9 +++++----
  1 file changed, 5 insertions(+), 4 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 8ce1bad..aa54df3 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -373,6 +373,7 @@ struct pmic_wrapper_type {
@@ -23,7 +25,7 @@ Signed-off-by: John Crispin <[email protected]>
  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
  };
-@@ -829,6 +830,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -829,6 +830,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.arb_en_all = 0x1ff,
  	.int_en_all = ~(BIT(31) | BIT(1)),
  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
@@ -31,7 +33,7 @@ Signed-off-by: John Crispin <[email protected]>
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -839,6 +841,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -839,6 +841,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.arb_en_all = 0x3f,
  	.int_en_all = ~(BIT(31) | BIT(1)),
  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
@@ -39,7 +41,7 @@ Signed-off-by: John Crispin <[email protected]>
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
  	.init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
-@@ -858,7 +861,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_t
+@@ -858,7 +861,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
  
  static int pwrap_probe(struct platform_device *pdev)
  {
@@ -48,7 +50,7 @@ Signed-off-by: John Crispin <[email protected]>
  	struct pmic_wrapper *wrp;
  	struct device_node *np = pdev->dev.of_node;
  	const struct of_device_id *of_id =
-@@ -948,9 +951,7 @@ static int pwrap_probe(struct platform_d
+@@ -948,9 +951,7 @@ static int pwrap_probe(struct platform_device *pdev)
  	 * Since STAUPD was not used on mt8173 platform,
  	 * so STAUPD of WDT_SRC which should be turned off
  	 */
@@ -59,3 +61,6 @@ Signed-off-by: John Crispin <[email protected]>
  	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
  	pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0038-soc-mediatek-PMIC-wrap-remove-pwrap_is_mt8135-and-pw.patch

@@ -1,7 +1,7 @@
-From 34d49f015488dcb3de31060846414bd4254e752a Mon Sep 17 00:00:00 2001
+From e16393b2c78cc95ec124a46e8da8cfb2af333f00 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 10:54:18 +0100
-Subject: [PATCH 38/81] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and
+Subject: [PATCH 38/91] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and
  pwrap_is_mt8173()
 
 With more SoCs being added the list of helper functions like these would
@@ -18,6 +18,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   28 ++++++++++++----------------
  1 file changed, 12 insertions(+), 16 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index aa54df3..a2bacda 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -374,20 +374,11 @@ struct pmic_wrapper_type {
@@ -42,7 +44,7 @@ Signed-off-by: John Crispin <[email protected]>
  static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
  {
  	return readl(wrp->base + wrp->master->regs[reg]);
-@@ -619,11 +610,14 @@ static int pwrap_init_cipher(struct pmic
+@@ -619,11 +610,14 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
  	pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
  
@@ -59,7 +61,7 @@ Signed-off-by: John Crispin <[email protected]>
  	}
  
  	/* Config cipher mode @PMIC */
-@@ -713,7 +707,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -713,7 +707,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	if (wrp->rstc_bridge)
  		reset_control_reset(wrp->rstc_bridge);
  
@@ -68,7 +70,7 @@ Signed-off-by: John Crispin <[email protected]>
  		/* Enable DCM */
  		pwrap_writel(wrp, 3, PWRAP_DCM_EN);
  		pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
-@@ -773,7 +767,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -773,7 +767,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
  	pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
  
@@ -77,7 +79,7 @@ Signed-off-by: John Crispin <[email protected]>
  		pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
  
  	pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
-@@ -793,7 +787,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -793,7 +787,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
  	pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
  
@@ -86,7 +88,7 @@ Signed-off-by: John Crispin <[email protected]>
  		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
  		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
  	}
-@@ -831,6 +825,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -831,6 +825,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.int_en_all = ~(BIT(31) | BIT(1)),
  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
  	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
@@ -94,7 +96,7 @@ Signed-off-by: John Crispin <[email protected]>
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -842,6 +837,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -842,6 +837,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.int_en_all = ~(BIT(31) | BIT(1)),
  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
  	.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
@@ -102,7 +104,7 @@ Signed-off-by: John Crispin <[email protected]>
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
  	.init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
-@@ -889,7 +885,7 @@ static int pwrap_probe(struct platform_d
+@@ -889,7 +885,7 @@ static int pwrap_probe(struct platform_device *pdev)
  		return ret;
  	}
  
@@ -111,3 +113,6 @@ Signed-off-by: John Crispin <[email protected]>
  		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  				"pwrap-bridge");
  		wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0039-soc-mediatek-PMIC-wrap-add-a-slave-specific-struct.patch

@@ -1,7 +1,7 @@
-From ae593b270b87f9ed6c35dec3ac69dd6bda43c0a0 Mon Sep 17 00:00:00 2001
+From 6dc9d9e08025ebc758981ea0396a41f95f669715 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 09:55:08 +0100
-Subject: [PATCH 39/81] soc: mediatek: PMIC wrap: add a slave specific struct
+Subject: [PATCH 39/91] soc: mediatek: PMIC wrap: add a slave specific struct
 
 This patch adds a new struct pwrap_slv_type that we use to store the slave
 specific data. The patch adds 2 new helper functions to access the dew
@@ -12,6 +12,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |  159 ++++++++++++++++++++++++----------
  1 file changed, 112 insertions(+), 47 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index a2bacda..bcc841e 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -69,33 +69,54 @@
@@ -123,7 +125,7 @@ Signed-off-by: John Crispin <[email protected]>
  	struct clk *clk_spi;
  	struct clk *clk_wrap;
  	struct reset_control *rstc;
-@@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_
+@@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
  
  	for (i = 0; i < 4; i++) {
  		pwrap_writel(wrp, i, PWRAP_SIDLY);
@@ -133,7 +135,7 @@ Signed-off-by: John Crispin <[email protected]>
  		if (rdata == PWRAP_DEW_READ_TEST_VAL) {
  			dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
  			pass |= 1 << i;
-@@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(s
+@@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
  	u32 rdata;
  	int ret;
  
@@ -143,7 +145,7 @@ Signed-off-by: John Crispin <[email protected]>
  	if (ret)
  		return 0;
  
-@@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic
+@@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	}
  
  	/* Config cipher mode @PMIC */
@@ -162,7 +164,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	/* wait for cipher data ready@AP */
  	ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
-@@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic
+@@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	}
  
  	/* wait for cipher mode idle */
@@ -171,7 +173,7 @@ Signed-off-by: John Crispin <[email protected]>
  	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
  	if (ret) {
  		dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
-@@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic
+@@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
  
  	/* Write Test */
@@ -186,7 +188,7 @@ Signed-off-by: John Crispin <[email protected]>
  		dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
  		return -EFAULT;
  	}
-@@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specifi
+@@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
  	writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
  
  	/* enable PMIC event out and sources */
@@ -199,7 +201,7 @@ Signed-off-by: John Crispin <[email protected]>
  		dev_err(wrp->dev, "enable dewrap fail\n");
  		return -EFAULT;
  	}
-@@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specifi
+@@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
  static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
  {
  	/* PMIC_DEWRAP enables */
@@ -212,7 +214,7 @@ Signed-off-by: John Crispin <[email protected]>
  		dev_err(wrp->dev, "enable dewrap fail\n");
  		return -EFAULT;
  	}
-@@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  		return ret;
  
  	/* Enable dual IO mode */
@@ -221,7 +223,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	/* Check IDLE & INIT_DONE in advance */
  	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
-@@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 1, PWRAP_DIO_EN);
  
  	/* Read Test */
@@ -230,7 +232,7 @@ Signed-off-by: John Crispin <[email protected]>
  	if (rdata != PWRAP_DEW_READ_TEST_VAL) {
  		dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
  				PWRAP_DEW_READ_TEST_VAL, rdata);
-@@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrappe
+@@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  		return ret;
  
  	/* Signature checking - using CRC */
@@ -246,7 +248,7 @@ Signed-off-by: John Crispin <[email protected]>
  	pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
  
  	if (wrp->master->type == PWRAP_MT8135)
-@@ -818,6 +858,21 @@ static const struct regmap_config pwrap_
+@@ -818,6 +858,21 @@ static const struct regmap_config pwrap_regmap_config = {
  	.max_register = 0xffff,
  };
  
@@ -268,7 +270,7 @@ Signed-off-by: John Crispin <[email protected]>
  static struct pmic_wrapper_type pwrap_mt8135 = {
  	.regs = mt8135_regs,
  	.type = PWRAP_MT8135,
-@@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_d
+@@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_device *pdev)
  	struct device_node *np = pdev->dev.of_node;
  	const struct of_device_id *of_id =
  		of_match_device(of_pwrap_match_tbl, &pdev->dev);
@@ -286,7 +288,7 @@ Signed-off-by: John Crispin <[email protected]>
  	wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
  	if (!wrp)
  		return -ENOMEM;
-@@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_d
+@@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_device *pdev)
  	platform_set_drvdata(pdev, wrp);
  
  	wrp->master = of_id->data;
@@ -294,3 +296,6 @@ Signed-off-by: John Crispin <[email protected]>
  	wrp->dev = &pdev->dev;
  
  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0040-soc-mediatek-PMIC-wrap-add-mt6323-slave-support.patch

@@ -1,7 +1,7 @@
-From 8f3597ca8c8a28d2501d03643569f0cea920c24d Mon Sep 17 00:00:00 2001
+From 2ff8338c16c86856fc6e3f636cf0df9a2562bc95 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 11:40:43 +0100
-Subject: [PATCH 40/81] soc: mediatek: PMIC wrap: add mt6323 slave support
+Subject: [PATCH 40/91] soc: mediatek: PMIC wrap: add mt6323 slave support
 
 Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623
 EVB. The only function that we need to touch is pwrap_init_cipher().
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   43 ++++++++++++++++++++++++++++++++++
  1 file changed, 43 insertions(+)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index bcc841e..0e4ebb8 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -93,6 +93,27 @@ enum dew_regs {
@@ -49,7 +51,7 @@ Signed-off-by: John Crispin <[email protected]>
  	PMIC_MT6397,
  };
  
-@@ -661,6 +683,19 @@ static int pwrap_init_cipher(struct pmic
+@@ -661,6 +683,19 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
  	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
  
@@ -69,7 +71,7 @@ Signed-off-by: John Crispin <[email protected]>
  	/* wait for cipher data ready@AP */
  	ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
  	if (ret) {
-@@ -858,6 +893,11 @@ static const struct regmap_config pwrap_
+@@ -858,6 +893,11 @@ static const struct regmap_config pwrap_regmap_config = {
  	.max_register = 0xffff,
  };
  
@@ -81,7 +83,7 @@ Signed-off-by: John Crispin <[email protected]>
  static const struct pwrap_slv_type pmic_mt6397 = {
  	.dew_regs = mt6397_regs,
  	.type = PMIC_MT6397,
-@@ -865,6 +905,9 @@ static const struct pwrap_slv_type pmic_
+@@ -865,6 +905,9 @@ static const struct pwrap_slv_type pmic_mt6397 = {
  
  static const struct of_device_id of_slave_match_tbl[] = {
  	{
@@ -91,3 +93,6 @@ Signed-off-by: John Crispin <[email protected]>
  		.compatible = "mediatek,mt6397",
  		.data = &pmic_mt6397,
  	}, {
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0041-soc-mediatek-PMIC-wrap-add-MT2701-7623-support.patch

@@ -1,7 +1,7 @@
-From 09351f7c59e08d9c259546e03af3af05c10d644c Mon Sep 17 00:00:00 2001
+From ec6ad56b62c6cd769b5a35e7009518d99bbbb7b6 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 20 Jan 2016 12:09:14 +0100
-Subject: [PATCH 41/81] soc: mediatek: PMIC wrap: add MT2701/7623 support
+Subject: [PATCH 41/91] soc: mediatek: PMIC wrap: add MT2701/7623 support
 
 Add the registers, callbacks and data structures required to make the
 wrapper work on MT2701 and MT7623.
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/soc/mediatek/mtk-pmic-wrap.c |  154 ++++++++++++++++++++++++++++++++++
  1 file changed, 154 insertions(+)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 0e4ebb8..3c3e56d 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -52,6 +52,7 @@
@@ -136,7 +138,7 @@ Signed-off-by: John Crispin <[email protected]>
  	PWRAP_MT8135,
  	PWRAP_MT8173,
  };
-@@ -637,6 +732,31 @@ static int pwrap_mt8173_init_reg_clock(s
+@@ -637,6 +732,31 @@ static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
  	return 0;
  }
  
@@ -168,7 +170,7 @@ Signed-off-by: John Crispin <[email protected]>
  static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
  {
  	return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
-@@ -670,6 +790,7 @@ static int pwrap_init_cipher(struct pmic
+@@ -670,6 +790,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  		pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
  		pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
  		break;
@@ -176,7 +178,7 @@ Signed-off-by: John Crispin <[email protected]>
  	case PWRAP_MT8173:
  		pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
  		break;
-@@ -772,6 +893,24 @@ static int pwrap_mt8173_init_soc_specifi
+@@ -772,6 +893,24 @@ static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
  	return 0;
  }
  
@@ -201,7 +203,7 @@ Signed-off-by: John Crispin <[email protected]>
  static int pwrap_init(struct pmic_wrapper *wrp)
  {
  	int ret;
-@@ -916,6 +1055,18 @@ static const struct of_device_id of_slav
+@@ -916,6 +1055,18 @@ static const struct of_device_id of_slave_match_tbl[] = {
  };
  MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
  
@@ -220,7 +222,7 @@ Signed-off-by: John Crispin <[email protected]>
  static struct pmic_wrapper_type pwrap_mt8135 = {
  	.regs = mt8135_regs,
  	.type = PWRAP_MT8135,
-@@ -942,6 +1093,9 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -942,6 +1093,9 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  
  static struct of_device_id of_pwrap_match_tbl[] = {
  	{
@@ -230,3 +232,6 @@ Signed-off-by: John Crispin <[email protected]>
  		.compatible = "mediatek,mt8135-pwrap",
  		.data = &pwrap_mt8135,
  	}, {
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0042-dt-bindings-mfd-Add-bindings-for-the-MediaTek-MT6323.patch

@@ -1,7 +1,7 @@
-From 94f7b9dabcd073bf629268514f87e5dbd2cafd13 Mon Sep 17 00:00:00 2001
+From 51deb5b355f0a26cc5f2a5e4a83e904f5c4c34df Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Sun, 10 Jan 2016 17:12:37 +0100
-Subject: [PATCH 42/81] dt-bindings: mfd: Add bindings for the MediaTek MT6323
+Subject: [PATCH 42/91] dt-bindings: mfd: Add bindings for the MediaTek MT6323
  PMIC
 
 Signed-off-by: John Crispin <[email protected]>
@@ -11,6 +11,8 @@ Cc: [email protected]
  Documentation/devicetree/bindings/mfd/mt6397.txt |   10 ++++++----
  1 file changed, 6 insertions(+), 4 deletions(-)
 
+diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
+index 15043e6..949c85f 100644
 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt
 +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
 @@ -1,6 +1,6 @@
@@ -22,7 +24,7 @@ Cc: [email protected]
  - Regulator
  - RTC
  - Audio codec
-@@ -8,14 +8,14 @@ MT6397 is a multifunction device with th
+@@ -8,14 +8,14 @@ MT6397 is a multifunction device with the following sub modules:
  - Clock
  
  It is interfaced to host controller using SPI interface by a proprietary hardware
@@ -48,3 +50,6 @@ Cc: [email protected]
  - codec
  	Required properties:
  		- compatible: "mediatek,mt6397-codec"
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0043-mfd-mt6397-int_con-and-int_status-may-vary-in-locati.patch

@@ -1,7 +1,7 @@
-From aa90d988b627b41c774891fd72560699f30faefa Mon Sep 17 00:00:00 2001
+From 3989b27c0a7cc16d29de14e1cb509b8ee82f7449 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Fri, 8 Jan 2016 08:33:17 +0100
-Subject: [PATCH 43/81] mfd: mt6397: int_con and int_status may vary in
+Subject: [PATCH 43/91] mfd: mt6397: int_con and int_status may vary in
  location
 
 MT6323 has the INT_CON and INT_STATUS located at a different position.
@@ -13,9 +13,11 @@ Signed-off-by: John Crispin <[email protected]>
  include/linux/mfd/mt6397/core.h |    2 ++
  2 files changed, 19 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
+index 1749c1c..75ad0fe 100644
 --- a/drivers/mfd/mt6397-core.c
 +++ b/drivers/mfd/mt6397-core.c
-@@ -69,8 +69,10 @@ static void mt6397_irq_sync_unlock(struc
+@@ -69,8 +69,10 @@ static void mt6397_irq_sync_unlock(struct irq_data *data)
  {
  	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
  
@@ -28,7 +30,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	mutex_unlock(&mt6397->irqlock);
  }
-@@ -147,8 +149,8 @@ static irqreturn_t mt6397_irq_thread(int
+@@ -147,8 +149,8 @@ static irqreturn_t mt6397_irq_thread(int irq, void *data)
  {
  	struct mt6397_chip *mt6397 = data;
  
@@ -39,7 +41,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	return IRQ_HANDLED;
  }
-@@ -177,8 +179,8 @@ static int mt6397_irq_init(struct mt6397
+@@ -177,8 +179,8 @@ static int mt6397_irq_init(struct mt6397_chip *mt6397)
  	mutex_init(&mt6397->irqlock);
  
  	/* Mask all interrupt sources */
@@ -50,7 +52,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
  		MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
-@@ -203,8 +205,8 @@ static int mt6397_irq_suspend(struct dev
+@@ -203,8 +205,8 @@ static int mt6397_irq_suspend(struct device *dev)
  {
  	struct mt6397_chip *chip = dev_get_drvdata(dev);
  
@@ -61,7 +63,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	enable_irq_wake(chip->irq);
  
-@@ -215,8 +217,8 @@ static int mt6397_irq_resume(struct devi
+@@ -215,8 +217,8 @@ static int mt6397_irq_resume(struct device *dev)
  {
  	struct mt6397_chip *chip = dev_get_drvdata(dev);
  
@@ -72,7 +74,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	disable_irq_wake(chip->irq);
  
-@@ -237,6 +239,11 @@ static int mt6397_probe(struct platform_
+@@ -237,6 +239,11 @@ static int mt6397_probe(struct platform_device *pdev)
  		return -ENOMEM;
  
  	mt6397->dev = &pdev->dev;
@@ -84,6 +86,8 @@ Signed-off-by: John Crispin <[email protected]>
  	/*
  	 * mt6397 MFD is child device of soc pmic wrapper.
  	 * Regmap is set from its parent.
+diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
+index 45b8e8a..d678f52 100644
 --- a/include/linux/mfd/mt6397/core.h
 +++ b/include/linux/mfd/mt6397/core.h
 @@ -60,6 +60,8 @@ struct mt6397_chip {
@@ -95,3 +99,6 @@ Signed-off-by: John Crispin <[email protected]>
  };
  
  #endif /* __MFD_MT6397_CORE_H__ */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0044-mfd-mt6397-add-support-for-different-Slave-types.patch

@@ -1,13 +1,15 @@
-From 1ef53a11f0c282008aa572eb7c97fa1e79621ea3 Mon Sep 17 00:00:00 2001
+From bd51286bc2a310bc1ba2297e97e862bbdb102183 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Fri, 8 Jan 2016 08:41:52 +0100
-Subject: [PATCH 44/81] mfd: mt6397: add support for different Slave types
+Subject: [PATCH 44/91] mfd: mt6397: add support for different Slave types
 
 Signed-off-by: John Crispin <[email protected]>
 ---
  drivers/mfd/mt6397-core.c |   58 ++++++++++++++++++++++++++++++++-------------
  1 file changed, 41 insertions(+), 17 deletions(-)
 
+diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
+index 75ad0fe..aa91606 100644
 --- a/drivers/mfd/mt6397-core.c
 +++ b/drivers/mfd/mt6397-core.c
 @@ -24,6 +24,9 @@
@@ -20,7 +22,7 @@ Signed-off-by: John Crispin <[email protected]>
  static const struct resource mt6397_rtc_resources[] = {
  	{
  		.start = MT6397_RTC_BASE,
-@@ -232,39 +235,60 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops,
+@@ -232,39 +235,60 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
  static int mt6397_probe(struct platform_device *pdev)
  {
  	int ret;
@@ -98,3 +100,6 @@ Signed-off-by: John Crispin <[email protected]>
  
  	return ret;
  }
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0045-mfd-mt6397-add-MT6323-support-to-MT6397-driver.patch

@@ -1,7 +1,7 @@
-From 49d9c28b1252c7920840662425aa7e4705cfbccf Mon Sep 17 00:00:00 2001
+From 52dde352cc7a558eab85458c3f7ab90dc652f761 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Fri, 8 Jan 2016 04:09:43 +0100
-Subject: [PATCH 45/81] mfd: mt6397: add MT6323 support to MT6397 driver
+Subject: [PATCH 45/91] mfd: mt6397: add MT6323 support to MT6397 driver
 
 Signed-off-by: John Crispin <[email protected]>
 ---
@@ -12,6 +12,8 @@ Signed-off-by: John Crispin <[email protected]>
  create mode 100644 include/linux/mfd/mt6323/core.h
  create mode 100644 include/linux/mfd/mt6323/registers.h
 
+diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
+index aa91606..8234cd3 100644
 --- a/drivers/mfd/mt6397-core.c
 +++ b/drivers/mfd/mt6397-core.c
 @@ -19,11 +19,14 @@
@@ -29,7 +31,7 @@ Signed-off-by: John Crispin <[email protected]>
  #define MT6391_CID_CODE		0x91
  #define MT6397_CID_CODE		0x97
  
-@@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_
+@@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_resources[] = {
  	},
  };
  
@@ -43,7 +45,7 @@ Signed-off-by: John Crispin <[email protected]>
  static const struct mfd_cell mt6397_devs[] = {
  	{
  		.name = "mt6397-rtc",
-@@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_
+@@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_device *pdev)
  	}
  
  	switch (id & 0xff) {
@@ -59,7 +61,7 @@ Signed-off-by: John Crispin <[email protected]>
  	case MT6397_CID_CODE:
  	case MT6391_CID_CODE:
  		pmic->int_con[0] = MT6397_INT_CON0;
-@@ -302,6 +321,7 @@ static int mt6397_remove(struct platform
+@@ -302,6 +321,7 @@ static int mt6397_remove(struct platform_device *pdev)
  
  static const struct of_device_id mt6397_of_match[] = {
  	{ .compatible = "mediatek,mt6397" },
@@ -67,6 +69,9 @@ Signed-off-by: John Crispin <[email protected]>
  	{ }
  };
  MODULE_DEVICE_TABLE(of, mt6397_of_match);
+diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h
+new file mode 100644
+index 0000000..06d0ec3
 --- /dev/null
 +++ b/include/linux/mfd/mt6323/core.h
 @@ -0,0 +1,36 @@
@@ -106,6 +111,9 @@ Signed-off-by: John Crispin <[email protected]>
 +};
 +
 +#endif /* __MFD_MT6323_CORE_H__ */
+diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h
+new file mode 100644
+index 0000000..160f3c0
 --- /dev/null
 +++ b/include/linux/mfd/mt6323/registers.h
 @@ -0,0 +1,408 @@
@@ -517,3 +525,6 @@ Signed-off-by: John Crispin <[email protected]>
 +#define MT6323_ACCDET_CON16       0x079A
 +
 +#endif /* __MFD_MT6323_REGISTERS_H__ */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0046-regulator-Add-document-for-MT6323-regulator.patch

@@ -1,7 +1,7 @@
-From f5b5c70021187c0ef70edf83865b62fec473e8fb Mon Sep 17 00:00:00 2001
+From 8113b9e7b599162ae4abf6bc940210ce2f826099 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Sun, 10 Jan 2016 17:31:46 +0100
-Subject: [PATCH 46/81] regulator: Add document for MT6323 regulator
+Subject: [PATCH 46/91] regulator: Add document for MT6323 regulator
 
 Signed-off-by: John Crispin <[email protected]>
 Cc: [email protected]
@@ -10,6 +10,9 @@ Cc: [email protected]
  1 file changed, 239 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
 
+diff --git a/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
+new file mode 100644
+index 0000000..9fd95e7
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
 @@ -0,0 +1,239 @@
@@ -252,3 +255,6 @@ Cc: [email protected]
 +			};
 +		};
 +	};
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0047-regulator-mt6323-Add-support-for-MT6323-regulator.patch

@@ -1,7 +1,7 @@
-From 031a2ff537366855e88bc95e5d42ea522b6c5ad8 Mon Sep 17 00:00:00 2001
+From 257b7279661d1d6fca41e053bcfb4368b238f049 Mon Sep 17 00:00:00 2001
 From: Chen Zhong <[email protected]>
 Date: Fri, 8 Jan 2016 04:17:37 +0100
-Subject: [PATCH 47/81] regulator: mt6323: Add support for MT6323 regulator
+Subject: [PATCH 47/91] regulator: mt6323: Add support for MT6323 regulator
 
 The MT6323 is a regulator found on boards based on MediaTek MT7623 and
 probably other SoCs. It is a so called pmic and connects as a slave to
@@ -18,9 +18,11 @@ Signed-off-by: John Crispin <[email protected]>
  create mode 100644 drivers/regulator/mt6323-regulator.c
  create mode 100644 include/linux/regulator/mt6323-regulator.h
 
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+index 8df0b0e..4aec931 100644
 --- a/drivers/regulator/Kconfig
 +++ b/drivers/regulator/Kconfig
-@@ -453,6 +453,15 @@ config REGULATOR_MT6311
+@@ -452,6 +452,15 @@ config REGULATOR_MT6311
  	  This driver supports the control of different power rails of device
  	  through regulator interface.
  
@@ -36,9 +38,11 @@ Signed-off-by: John Crispin <[email protected]>
  config REGULATOR_MT6397
  	tristate "MediaTek MT6397 PMIC"
  	depends on MFD_MT6397
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+index 0f81749..b42a84e 100644
 --- a/drivers/regulator/Makefile
 +++ b/drivers/regulator/Makefile
-@@ -60,6 +60,7 @@ obj-$(CONFIG_REGULATOR_MC13783) += mc137
+@@ -60,6 +60,7 @@ obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
  obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
  obj-$(CONFIG_REGULATOR_MC13XXX_CORE) +=  mc13xxx-regulator-core.o
  obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
@@ -46,6 +50,9 @@ Signed-off-by: John Crispin <[email protected]>
  obj-$(CONFIG_REGULATOR_MT6397)	+= mt6397-regulator.o
  obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
  obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o
+diff --git a/drivers/regulator/mt6323-regulator.c b/drivers/regulator/mt6323-regulator.c
+new file mode 100644
+index 0000000..28ebbda
 --- /dev/null
 +++ b/drivers/regulator/mt6323-regulator.c
 @@ -0,0 +1,432 @@
@@ -481,6 +488,9 @@ Signed-off-by: John Crispin <[email protected]>
 +MODULE_AUTHOR("Chen Zhong <[email protected]>");
 +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC");
 +MODULE_LICENSE("GPL v2");
+diff --git a/include/linux/regulator/mt6323-regulator.h b/include/linux/regulator/mt6323-regulator.h
+new file mode 100644
+index 0000000..67011cd
 --- /dev/null
 +++ b/include/linux/regulator/mt6323-regulator.h
 @@ -0,0 +1,52 @@
@@ -536,3 +546,6 @@ Signed-off-by: John Crispin <[email protected]>
 +#define MT6323_MAX_REGULATOR	MT6323_ID_RG_MAX
 +
 +#endif /* __LINUX_REGULATOR_MT6323_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch

@@ -1,7 +1,7 @@
-From b79b0519fb67c22cbed341c5e9dca5ad0aa4d15c Mon Sep 17 00:00:00 2001
+From 1e759a179923236660f7f2070fd52e9d2cc09b22 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 2 Mar 2016 07:18:52 +0100
-Subject: [PATCH 48/81] net-next: mediatek: document MediaTek SoC ethernet
+Subject: [PATCH 48/91] net-next: mediatek: document MediaTek SoC ethernet
  binding
 
 This adds the binding documentation for the MediaTek Ethernet
@@ -15,6 +15,9 @@ Cc: [email protected]
  1 file changed, 77 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
 
+diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
+new file mode 100644
+index 0000000..5ca7929
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
 @@ -0,0 +1,77 @@
@@ -95,3 +98,6 @@ Cc: [email protected]
 +		};
 +	};
 +};
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0049-net-next-mediatek-add-support-for-MT7623-ethernet.patch

@@ -1,7 +1,7 @@
-From 999621b6bfff903d16691799a23bfccac91c31df Mon Sep 17 00:00:00 2001
+From 15f1cb9603c22910f1cd6a8c63fd279a6d5acfd4 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 2 Mar 2016 04:27:10 +0100
-Subject: [PATCH 49/81] net-next: mediatek: add support for MT7623 ethernet
+Subject: [PATCH 49/91] net-next: mediatek: add support for MT7623 ethernet
 
 Add ethernet support for MediaTek SoCs from the MT7623 family. These have
 dual GMAC. Depending on the exact version, there might be a built-in
@@ -26,6 +26,9 @@ Signed-off-by: John Crispin <[email protected]>
  create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.c
  create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.h
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+new file mode 100644
+index 0000000..ba3afa5
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 @@ -0,0 +1,1807 @@
@@ -1836,6 +1839,9 @@ Signed-off-by: John Crispin <[email protected]>
 +MODULE_LICENSE("GPL");
 +MODULE_AUTHOR("John Crispin <[email protected]>");
 +MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+new file mode 100644
+index 0000000..48a5292
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 @@ -0,0 +1,421 @@
@@ -2260,3 +2266,6 @@ Signed-off-by: John Crispin <[email protected]>
 +u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
 +
 +#endif /* MTK_ETH_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0050-net-next-mediatek-add-Kconfig-and-Makefile.patch

@@ -1,7 +1,7 @@
-From 0189b71d0ce9feef1c3fac7d9c3eb7dae57dabdf Mon Sep 17 00:00:00 2001
+From 80d88cdd398bf0c33ca5e655ded3bb62339b9565 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 2 Mar 2016 04:32:43 +0100
-Subject: [PATCH 50/81] net-next: mediatek: add Kconfig and Makefile
+Subject: [PATCH 50/91] net-next: mediatek: add Kconfig and Makefile
 
 This patch adds the Makefile and Kconfig required to make the driver build.
 
@@ -15,6 +15,8 @@ Signed-off-by: John Crispin <[email protected]>
  create mode 100644 drivers/net/ethernet/mediatek/Kconfig
  create mode 100644 drivers/net/ethernet/mediatek/Makefile
 
+diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
+index 31c5e47..cd28b95 100644
 --- a/drivers/net/ethernet/Kconfig
 +++ b/drivers/net/ethernet/Kconfig
 @@ -106,6 +106,7 @@ config LANTIQ_ETOP
@@ -25,6 +27,8 @@ Signed-off-by: John Crispin <[email protected]>
  source "drivers/net/ethernet/mellanox/Kconfig"
  source "drivers/net/ethernet/micrel/Kconfig"
  source "drivers/net/ethernet/microchip/Kconfig"
+diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
+index 071f84e..c62191f 100644
 --- a/drivers/net/ethernet/Makefile
 +++ b/drivers/net/ethernet/Makefile
 @@ -46,6 +46,7 @@ obj-$(CONFIG_JME) += jme.o
@@ -35,6 +39,9 @@ Signed-off-by: John Crispin <[email protected]>
  obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
  obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
  obj-$(CONFIG_NET_VENDOR_MICROCHIP) += microchip/
+diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig
+new file mode 100644
+index 0000000..b0229f4
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/Kconfig
 @@ -0,0 +1,17 @@
@@ -55,6 +62,9 @@ Signed-off-by: John Crispin <[email protected]>
 +	  MediaTek MT2701/MT7623 chipset family.
 +
 +endif #NET_VENDOR_MEDIATEK
+diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile
+new file mode 100644
+index 0000000..aa3f1c8
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/Makefile
 @@ -0,0 +1,5 @@
@@ -63,3 +73,6 @@ Signed-off-by: John Crispin <[email protected]>
 +#
 +
 +obj-$(CONFIG_NET_MEDIATEK_SOC)			+= mtk_eth_soc.o
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0051-net-next-mediatek-add-an-entry-to-MAINTAINERS.patch

@@ -1,7 +1,7 @@
-From 76ac7ac355452b4a2cf5cf7b1d9ab5b08e349b4b Mon Sep 17 00:00:00 2001
+From 859c0e3dfcc227b6f3fd324ef2ea5fa22cfc7f17 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 2 Mar 2016 04:34:04 +0100
-Subject: [PATCH 51/81] net-next: mediatek: add an entry to MAINTAINERS
+Subject: [PATCH 51/91] net-next: mediatek: add an entry to MAINTAINERS
 
 Add myself and Felix as the Maintainers for the MediaTek ethernet driver.
 
@@ -11,9 +11,11 @@ Signed-off-by: John Crispin <[email protected]>
  MAINTAINERS |    7 +++++++
  1 file changed, 7 insertions(+)
 
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 156e1d3..7737042 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -6907,6 +6907,13 @@ F:	include/uapi/linux/meye.h
+@@ -6908,6 +6908,13 @@ F:	include/uapi/linux/meye.h
  F:	include/uapi/linux/ivtv*
  F:	include/uapi/linux/uvcvideo.h
  
@@ -27,3 +29,6 @@ Signed-off-by: John Crispin <[email protected]>
  MEDIATEK MT7601U WIRELESS LAN DRIVER
  M:	Jakub Kicinski <[email protected]>
  L:	[email protected]
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0052-mtd-nand-add-an-mtd_to_nand-helper.patch

@@ -1,7 +1,7 @@
-From 17b9724cf84aa32f15334c23d5df34ad3cb885f3 Mon Sep 17 00:00:00 2001
+From 3126b17c9123daf9f96f513d53f08c06f4d08a7c Mon Sep 17 00:00:00 2001
 From: Boris BREZILLON <[email protected]>
 Date: Mon, 16 Nov 2015 14:37:35 +0100
-Subject: [PATCH 52/81] mtd: nand: add an mtd_to_nand() helper
+Subject: [PATCH 52/91] mtd: nand: add an mtd_to_nand() helper
 
 Some drivers are retrieving the nand_chip pointer using the container_of
 macro on a struct wrapping both the nand_chip and the mtd_info struct while
@@ -14,6 +14,8 @@ Signed-off-by: Brian Norris <[email protected]>
  include/linux/mtd/nand.h |    5 +++++
  1 file changed, 5 insertions(+)
 
+diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
+index 5a9d1d4..a4839b3 100644
 --- a/include/linux/mtd/nand.h
 +++ b/include/linux/mtd/nand.h
 @@ -719,6 +719,11 @@ struct nand_chip {
@@ -28,3 +30,6 @@ Signed-off-by: Brian Norris <[email protected]>
  /*
   * NAND Flash Manufacturer ID Codes
   */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0053-mtd-nand-add-nand_to_mtd-helper.patch

@@ -1,7 +1,7 @@
-From 86e5fe2edbe2ca4f0d83a26d9b3d02620cd78f37 Mon Sep 17 00:00:00 2001
+From 5175e1d27c52c0958b2d1cb4391a611444aaf432 Mon Sep 17 00:00:00 2001
 From: Boris BREZILLON <[email protected]>
 Date: Tue, 1 Dec 2015 12:03:07 +0100
-Subject: [PATCH 53/81] mtd: nand: add nand_to_mtd() helper
+Subject: [PATCH 53/91] mtd: nand: add nand_to_mtd() helper
 
 Add a new helper to retrieve the MTD device attached to a NAND chip.
 
@@ -11,9 +11,11 @@ Signed-off-by: Brian Norris <[email protected]>
  include/linux/mtd/nand.h |    5 +++++
  1 file changed, 5 insertions(+)
 
+diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
+index a4839b3..c75424f 100644
 --- a/include/linux/mtd/nand.h
 +++ b/include/linux/mtd/nand.h
-@@ -724,6 +724,11 @@ static inline struct nand_chip *mtd_to_n
+@@ -724,6 +724,11 @@ static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
  	return mtd->priv;
  }
  
@@ -25,3 +27,6 @@ Signed-off-by: Brian Norris <[email protected]>
  /*
   * NAND Flash Manufacturer ID Codes
   */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0054-mtd-nand-add-helpers-to-access-priv.patch

@@ -1,7 +1,7 @@
-From ca10b32de369729b8e7947fe1945e8e393d803cd Mon Sep 17 00:00:00 2001
+From ad8a96526816abfa75b19998bbf41857f9bae6cc Mon Sep 17 00:00:00 2001
 From: Boris BREZILLON <[email protected]>
 Date: Thu, 10 Dec 2015 09:00:39 +0100
-Subject: [PATCH 54/81] mtd: nand: add helpers to access ->priv
+Subject: [PATCH 54/91] mtd: nand: add helpers to access ->priv
 
 Add two helpers to access the field reserved for private controller data.
 This makes it clearer what this field is reserved for and ease future
@@ -13,9 +13,11 @@ Signed-off-by: Brian Norris <[email protected]>
  include/linux/mtd/nand.h |   10 ++++++++++
  1 file changed, 10 insertions(+)
 
+diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
+index c75424f..345f864 100644
 --- a/include/linux/mtd/nand.h
 +++ b/include/linux/mtd/nand.h
-@@ -729,6 +729,16 @@ static inline struct mtd_info *nand_to_m
+@@ -729,6 +729,16 @@ static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
  	return &chip->mtd;
  }
  
@@ -32,3 +34,6 @@ Signed-off-by: Brian Norris <[email protected]>
  /*
   * NAND Flash Manufacturer ID Codes
   */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0055-mtd-nand-embed-an-mtd_info-structure-into-nand_chip.patch

@@ -1,7 +1,7 @@
-From b4a93bff70545d73337e2cae7209fd1ae4d9d8e8 Mon Sep 17 00:00:00 2001
+From addd0678f84712ac6f70b8e6cda84e11c5d348f4 Mon Sep 17 00:00:00 2001
 From: Boris BREZILLON <[email protected]>
 Date: Tue, 1 Dec 2015 12:03:06 +0100
-Subject: [PATCH 55/81] mtd: nand: embed an mtd_info structure into nand_chip
+Subject: [PATCH 55/91] mtd: nand: embed an mtd_info structure into nand_chip
 
 Currently all NAND controller drivers are providing both the mtd_info and
 nand_chip struct and then let the NAND subsystem to initialize a few
@@ -17,6 +17,8 @@ Signed-off-by: Brian Norris <[email protected]>
  include/linux/mtd/nand.h |    2 ++
  1 file changed, 2 insertions(+)
 
+diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
+index 345f864..1ded588 100644
 --- a/include/linux/mtd/nand.h
 +++ b/include/linux/mtd/nand.h
 @@ -540,6 +540,7 @@ struct nand_buffers {
@@ -35,3 +37,6 @@ Signed-off-by: Brian Norris <[email protected]>
  	void __iomem *IO_ADDR_R;
  	void __iomem *IO_ADDR_W;
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0056-mtd-add-get-set-of_node-flash_node-helpers.patch

@@ -1,7 +1,7 @@
-From 3ed29e95facfd50427721f8e9093dc36c2304e42 Mon Sep 17 00:00:00 2001
+From 6b4858de63badb90d820a1d343528d8575f3f28c Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 22 Mar 2016 03:52:07 +0100
-Subject: [PATCH 56/81] mtd: add get/set of_node/flash_node helpers
+Subject: [PATCH 56/91] mtd: add get/set of_node/flash_node helpers
 
 We are going to begin using the mtd->dev.of_node field for MTD device
 nodes, so let's add helpers for it. Also, we'll be making some
@@ -16,9 +16,11 @@ Reviewed-by: Boris Brezillon <[email protected]>
  include/linux/mtd/spi-nor.h |   11 +++++++++++
  3 files changed, 33 insertions(+)
 
+diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
+index f17fa75..cc84923 100644
 --- a/include/linux/mtd/mtd.h
 +++ b/include/linux/mtd/mtd.h
-@@ -258,6 +258,17 @@ struct mtd_info {
+@@ -254,6 +254,17 @@ struct mtd_info {
  	int usecount;
  };
  
@@ -36,9 +38,11 @@ Reviewed-by: Boris Brezillon <[email protected]>
  int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
  int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
  	      void **virt, resource_size_t *phys);
+diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
+index 1ded588..3c34ca4 100644
 --- a/include/linux/mtd/nand.h
 +++ b/include/linux/mtd/nand.h
-@@ -741,6 +741,17 @@ static inline void nand_set_controller_d
+@@ -741,6 +741,17 @@ static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
  	chip->priv = priv;
  }
  
@@ -56,9 +60,11 @@ Reviewed-by: Boris Brezillon <[email protected]>
  /*
   * NAND Flash Manufacturer ID Codes
   */
+diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
+index c8723b6..6d991df 100644
 --- a/include/linux/mtd/spi-nor.h
 +++ b/include/linux/mtd/spi-nor.h
-@@ -184,6 +184,17 @@ struct spi_nor {
+@@ -185,6 +185,17 @@ struct spi_nor {
  	void *priv;
  };
  
@@ -76,3 +82,6 @@ Reviewed-by: Boris Brezillon <[email protected]>
  /**
   * spi_nor_scan() - scan the SPI NOR
   * @nor:	the spi_nor structure
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0057-mtd-mediatek-device-tree-docs-for-MTK-Smart-Device-G.patch

@@ -1,7 +1,7 @@
-From 5f0a1fa77e5d53b8dbb751fcfc59c7ef3d78ddf2 Mon Sep 17 00:00:00 2001
+From 47589c3a100ae3dd0081866fd60ef31a67ba7fa9 Mon Sep 17 00:00:00 2001
 From: Jorge Ramirez-Ortiz <[email protected]>
 Date: Wed, 2 Mar 2016 12:00:11 -0500
-Subject: [PATCH 57/81] mtd: mediatek: device tree docs for MTK Smart Device
+Subject: [PATCH 57/91] mtd: mediatek: device tree docs for MTK Smart Device
  Gen1 NAND
 
 This patch adds documentation support for Smart Device Gen1 type of
@@ -15,6 +15,9 @@ Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
  1 file changed, 38 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
 
+diff --git a/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt b/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
+new file mode 100644
+index 0000000..129d17b
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
 @@ -0,0 +1,38 @@
@@ -56,3 +59,6 @@ Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
 +
 +		...
 +	};
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0058-mtd-mediatek-driver-for-MTK-Smart-Device-Gen1-NAND.patch

@@ -1,7 +1,7 @@
-From cc1959d5bc9a709729fcd02d78f4c27394393109 Mon Sep 17 00:00:00 2001
+From a97e38f34b59d18d9ca3626c2611c63cc6c6b48a Mon Sep 17 00:00:00 2001
 From: Jorge Ramirez-Ortiz <[email protected]>
 Date: Wed, 2 Mar 2016 12:00:12 -0500
-Subject: [PATCH 58/81] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
+Subject: [PATCH 58/91] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
 
 This patch adds support for mediatek's SDG1 NFC nand controller
 embedded in SoC 2701.
@@ -20,6 +20,8 @@ Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
  create mode 100644 drivers/mtd/nand/mtksdg1_nand_ecc.h
  create mode 100644 drivers/mtd/nand/mtksdg1_nand_nfi.h
 
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index 2896640..5ec072a 100644
 --- a/drivers/mtd/nand/Kconfig
 +++ b/drivers/mtd/nand/Kconfig
 @@ -546,4 +546,10 @@ config MTD_NAND_HISI504
@@ -33,15 +35,20 @@ Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
 +	Enables support for NAND controller on MTK Smart Device SoCs.
 +
  endif # MTD_NAND
+diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
+index 2c7f014..2a2620c 100644
 --- a/drivers/mtd/nand/Makefile
 +++ b/drivers/mtd/nand/Makefile
-@@ -55,5 +55,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+=
+@@ -55,5 +55,6 @@ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
  obj-$(CONFIG_MTD_NAND_SUNXI)		+= sunxi_nand.o
  obj-$(CONFIG_MTD_NAND_HISI504)	        += hisi504_nand.o
  obj-$(CONFIG_MTD_NAND_BRCMNAND)		+= brcmnand/
 +obj-$(CONFIG_MTD_NAND_MTKSDG1)		+= mtksdg1_nand.o
  
  nand-objs := nand_base.o nand_bbt.o nand_timings.o
+diff --git a/drivers/mtd/nand/mtksdg1_nand.c b/drivers/mtd/nand/mtksdg1_nand.c
+new file mode 100644
+index 0000000..55dd17d
 --- /dev/null
 +++ b/drivers/mtd/nand/mtksdg1_nand.c
 @@ -0,0 +1,1535 @@
@@ -1580,6 +1587,9 @@ Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
 +MODULE_AUTHOR("Xiaolei Li <[email protected]>");
 +MODULE_DESCRIPTION("MTK Nand Flash Controller Driver");
 +
+diff --git a/drivers/mtd/nand/mtksdg1_nand_ecc.h b/drivers/mtd/nand/mtksdg1_nand_ecc.h
+new file mode 100644
+index 0000000..d90b196
 --- /dev/null
 +++ b/drivers/mtd/nand/mtksdg1_nand_ecc.h
 @@ -0,0 +1,75 @@
@@ -1658,6 +1668,9 @@ Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
 +#define		DECFSM_MASK		(0x7f0f0f0f)
 +#define		DECFSM_IDLE		(0x01010101)
 +#endif
+diff --git a/drivers/mtd/nand/mtksdg1_nand_nfi.h b/drivers/mtd/nand/mtksdg1_nand_nfi.h
+new file mode 100644
+index 0000000..a9aa6f6
 --- /dev/null
 +++ b/drivers/mtd/nand/mtksdg1_nand_nfi.h
 @@ -0,0 +1,119 @@
@@ -1780,3 +1793,6 @@ Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
 +
 +#endif
 +
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0059-mtd-nand-backport-fixes.patch

@@ -1,15 +1,17 @@
-From 96ec6b2ee8a19799835209d0a6753519b96277f8 Mon Sep 17 00:00:00 2001
+From bb79410956e03e7c775c38338c5826f8591378a9 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Thu, 31 Mar 2016 02:28:08 +0200
-Subject: [PATCH 59/81] mtd: nand: backport fixes
+Subject: [PATCH 59/91] mtd: nand: backport fixes
 
 ---
  drivers/mtd/nand/mtksdg1_nand.c |    9 ++++++++-
  1 file changed, 8 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/mtd/nand/mtksdg1_nand.c b/drivers/mtd/nand/mtksdg1_nand.c
+index 55dd17d..f92b949 100644
 --- a/drivers/mtd/nand/mtksdg1_nand.c
 +++ b/drivers/mtd/nand/mtksdg1_nand.c
-@@ -107,6 +107,9 @@ static struct nand_ecclayout nand_4k_128
+@@ -107,6 +107,9 @@ static struct nand_ecclayout nand_4k_128 = {
  	.oobfree = { {0, 32} },
  };
  
@@ -19,7 +21,7 @@ Subject: [PATCH 59/81] mtd: nand: backport fixes
  /* NFI register access */
  static inline void mtk_nfi_writel(struct mtk_nfc_host *host, u32 val, u32 reg)
  {
-@@ -1298,6 +1301,7 @@ static int mtk_nfc_probe(struct platform
+@@ -1298,6 +1301,7 @@ static int mtk_nfc_probe(struct platform_device *pdev)
  
  	chip = &host->chip;
  	mtd = nand_to_mtd(chip);
@@ -27,7 +29,7 @@ Subject: [PATCH 59/81] mtd: nand: backport fixes
  	host->dev = dev;
  
  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-@@ -1428,7 +1432,10 @@ static int mtk_nfc_probe(struct platform
+@@ -1428,7 +1432,10 @@ static int mtk_nfc_probe(struct platform_device *pdev)
  	}
  	host->switch_oob = false;
  
@@ -39,3 +41,6 @@ Subject: [PATCH 59/81] mtd: nand: backport fixes
  	if (ret) {
  		dev_err(dev, "mtd parse partition error\n");
  		goto nand_free;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0060-clk-dont-disable-unused-clocks.patch

@@ -0,0 +1,26 @@
+From e31a6402c10f50bf45fd073fbfd622f16bfca031 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Thu, 7 Apr 2016 07:18:35 +0200
+Subject: [PATCH 60/91] clk: dont disable unused clocks
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/clk/clk.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
+index f13c3f4..5e9ddae 100644
+--- a/drivers/clk/clk.c
++++ b/drivers/clk/clk.c
+@@ -233,7 +233,7 @@ unlock_out:
+ 	clk_enable_unlock(flags);
+ }
+ 
+-static bool clk_ignore_unused;
++static bool clk_ignore_unused = true;
+ static int __init clk_ignore_unused_setup(char *__unused)
+ {
+ 	clk_ignore_unused = true;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0061-clk-mediatek-enable-critical-clocks.patch

@@ -0,0 +1,74 @@
+From 8304c8eb6b43d29fd5794bece27faaa7b7a59a2b Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Thu, 31 Mar 2016 06:46:51 +0200
+Subject: [PATCH 61/91] clk: mediatek: enable critical clocks
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt2701.c |   22 ++++++++++++++++++++--
+ 1 file changed, 20 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 812b347..1634288 100644
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -573,6 +573,20 @@ static const struct mtk_gate top_clks[] __initconst = {
+ 	GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
+ };
+ 
++static struct clk_onecell_data *mt7623_top_clk_data __initdata;
++static struct clk_onecell_data *mt7623_pll_clk_data __initdata;
++
++static void __init mtk_clk_enable_critical(void)
++{
++	if (!mt7623_top_clk_data || !mt7623_pll_clk_data)
++		return;
++
++	clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]);
++	clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]);
++	clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
++	clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
++}
++
+ static void __init mtk_topckgen_init(struct device_node *node)
+ {
+ 	struct clk_onecell_data *clk_data;
+@@ -585,7 +599,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
+ 		return;
+ 	}
+ 
+-	clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
++	mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
+ 
+ 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ 								clk_data);
+@@ -606,6 +620,8 @@ static void __init mtk_topckgen_init(struct device_node *node)
+ 	if (r)
+ 		pr_err("%s(): could not register clock provider: %d\n",
+ 			__func__, r);
++
++	mtk_clk_enable_critical();
+ }
+ CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
+ 
+@@ -1202,7 +1218,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
+ 	struct clk_onecell_data *clk_data;
+ 	int r;
+ 
+-	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
++	mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
+ 	if (!clk_data)
+ 		return;
+ 
+@@ -1213,6 +1229,8 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
+ 	if (r)
+ 		pr_err("%s(): could not register clock provider: %d\n",
+ 			__func__, r);
++
++	mtk_clk_enable_critical();
+ }
+ CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
+ 							mtk_apmixedsys_init);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0062-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch

@@ -0,0 +1,306 @@
+From c906caf00335b78ae1275eea4bfceca5273f3154 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Thu, 31 Mar 2016 02:26:37 +0200
+Subject: [PATCH 62/91] clk: mediatek: Export CPU mux clocks for CPU frequency
+ control
+
+This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
+for intermediate clock source switching.
+
+Signed-off-by: Pi-Cheng Chen <[email protected]>
+---
+ drivers/clk/mediatek/Makefile          |    2 +-
+ drivers/clk/mediatek/clk-cpumux.c      |  127 ++++++++++++++++++++++++++++++++
+ drivers/clk/mediatek/clk-cpumux.h      |   22 ++++++
+ drivers/clk/mediatek/clk-mt2701.c      |    8 ++
+ drivers/clk/mediatek/clk-mt8173.c      |   23 ++++++
+ include/dt-bindings/clock/mt2701-clk.h |    3 +-
+ include/dt-bindings/clock/mt8173-clk.h |    4 +-
+ 7 files changed, 186 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/clk/mediatek/clk-cpumux.c
+ create mode 100644 drivers/clk/mediatek/clk-cpumux.h
+
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 5b2b91b..76bfab6 100644
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -1,4 +1,4 @@
+-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
++obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
+ obj-$(CONFIG_RESET_CONTROLLER) += reset.o
+ obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+ obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
+new file mode 100644
+index 0000000..91b5238
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-cpumux.c
+@@ -0,0 +1,127 @@
++/*
++ * Copyright (c) 2015 Linaro Ltd.
++ * Author: Pi-Cheng Chen <[email protected]>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/mfd/syscon.h>
++#include <linux/slab.h>
++
++#include "clk-mtk.h"
++#include "clk-cpumux.h"
++
++struct mtk_clk_cpumux {
++	struct clk_hw	hw;
++	struct regmap	*regmap;
++	u32		reg;
++	u32		mask;
++	u8		shift;
++};
++
++static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
++{
++	return container_of(_hw, struct mtk_clk_cpumux, hw);
++}
++
++static u8 clk_cpumux_get_parent(struct clk_hw *hw)
++{
++	struct mtk_clk_cpumux *mux = to_clk_mux(hw);
++	int num_parents = clk_hw_get_num_parents(hw);
++	unsigned int val;
++
++	regmap_read(mux->regmap, mux->reg, &val);
++
++	val >>= mux->shift;
++	val &= mux->mask;
++
++	if (val >= num_parents)
++		return -EINVAL;
++
++	return val;
++}
++
++static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
++{
++	struct mtk_clk_cpumux *mux = to_clk_mux(hw);
++	u32 mask, val;
++
++	val = index << mux->shift;
++	mask = mux->mask << mux->shift;
++
++	return regmap_update_bits(mux->regmap, mux->reg, mask, val);
++}
++
++static const struct clk_ops clk_cpumux_ops = {
++	.get_parent = clk_cpumux_get_parent,
++	.set_parent = clk_cpumux_set_parent,
++};
++
++static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux,
++					   struct regmap *regmap)
++{
++	struct mtk_clk_cpumux *cpumux;
++	struct clk *clk;
++	struct clk_init_data init;
++
++	cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
++	if (!cpumux)
++		return ERR_PTR(-ENOMEM);
++
++	init.name = mux->name;
++	init.ops = &clk_cpumux_ops;
++	init.parent_names = mux->parent_names;
++	init.num_parents = mux->num_parents;
++	init.flags = mux->flags;
++
++	cpumux->reg = mux->mux_reg;
++	cpumux->shift = mux->mux_shift;
++	cpumux->mask = BIT(mux->mux_width) - 1;
++	cpumux->regmap = regmap;
++	cpumux->hw.init = &init;
++
++	clk = clk_register(NULL, &cpumux->hw);
++	if (IS_ERR(clk))
++		kfree(cpumux);
++
++	return clk;
++}
++
++int __init mtk_clk_register_cpumuxes(struct device_node *node,
++			      const struct mtk_composite *clks, int num,
++			      struct clk_onecell_data *clk_data)
++{
++	int i;
++	struct clk *clk;
++	struct regmap *regmap;
++
++	regmap = syscon_node_to_regmap(node);
++	if (IS_ERR(regmap)) {
++		pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
++		       PTR_ERR(regmap));
++		return PTR_ERR(regmap);
++	}
++
++	for (i = 0; i < num; i++) {
++		const struct mtk_composite *mux = &clks[i];
++
++		clk = mtk_clk_register_cpumux(mux, regmap);
++		if (IS_ERR(clk)) {
++			pr_err("Failed to register clk %s: %ld\n",
++			       mux->name, PTR_ERR(clk));
++			continue;
++		}
++
++		clk_data->clks[mux->id] = clk;
++	}
++
++	return 0;
++}
+diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
+new file mode 100644
+index 0000000..52c769f
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-cpumux.h
+@@ -0,0 +1,22 @@
++/*
++ * Copyright (c) 2015 Linaro Ltd.
++ * Author: Pi-Cheng Chen <[email protected]>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __DRV_CLK_CPUMUX_H
++#define __DRV_CLK_CPUMUX_H
++
++int mtk_clk_register_cpumuxes(struct device_node *node,
++			      const struct mtk_composite *clks, int num,
++			      struct clk_onecell_data *clk_data);
++
++#endif /* __DRV_CLK_CPUMUX_H */
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 1634288..5c37fcb 100644
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -18,6 +18,7 @@
+ 
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
++#include "clk-cpumux.h"
+ 
+ #include <dt-bindings/clock/mt2701-clk.h>
+ 
+@@ -465,6 +466,10 @@ static const char * const cpu_parents[] __initconst = {
+ 	"mmpll"
+ };
+ 
++static const struct mtk_composite cpu_muxes[] __initconst = {
++	MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
++};
++
+ static const struct mtk_composite top_muxes[] __initconst = {
+ 	MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
+ 		0x0040, 0, 3, INVALID_MUX_GATE_BIT),
+@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
+ 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ 						clk_data);
+ 
++	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
++						clk_data);
++
+ 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ 	if (r)
+ 		pr_err("%s(): could not register clock provider: %d\n",
+diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
+index 227e356..b82c0e2 100644
+--- a/drivers/clk/mediatek/clk-mt8173.c
++++ b/drivers/clk/mediatek/clk-mt8173.c
+@@ -18,6 +18,7 @@
+ 
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
++#include "clk-cpumux.h"
+ 
+ #include <dt-bindings/clock/mt8173-clk.h>
+ 
+@@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
+ 	"apll2_div5"
+ };
+ 
++static const char * const ca53_parents[] __initconst = {
++	"clk26m",
++	"armca7pll",
++	"mainpll",
++	"univpll"
++};
++
++static const char * const ca57_parents[] __initconst = {
++	"clk26m",
++	"armca15pll",
++	"mainpll",
++	"univpll"
++};
++
++static const struct mtk_composite cpu_muxes[] __initconst = {
++	MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
++	MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
++};
++
+ static const struct mtk_composite top_muxes[] __initconst = {
+ 	/* CLK_CFG_0 */
+ 	MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
+@@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
+ 						clk_data);
+ 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+ 
++	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
++						clk_data);
++
+ 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ 	if (r)
+ 		pr_err("%s(): could not register clock provider: %d\n",
+diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
+index 50972d1..a6c63b8 100644
+--- a/include/dt-bindings/clock/mt2701-clk.h
++++ b/include/dt-bindings/clock/mt2701-clk.h
+@@ -217,7 +217,8 @@
+ #define CLK_INFRA_PMICWRAP			17
+ #define CLK_INFRA_DDCCI				18
+ #define CLK_INFRA_CLK_13M                       19
+-#define CLK_INFRA_NR				20
++#define CLK_INFRA_CPUSEL			20
++#define CLK_INFRA_NR				21
+ 
+ /* PERICFG */
+ 
+diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
+index 7956ba1..c82ed7c 100644
+--- a/include/dt-bindings/clock/mt8173-clk.h
++++ b/include/dt-bindings/clock/mt8173-clk.h
+@@ -192,7 +192,9 @@
+ #define CLK_INFRA_PMICSPI		10
+ #define CLK_INFRA_PMICWRAP		11
+ #define CLK_INFRA_CLK_13M		12
+-#define CLK_INFRA_NR_CLK		13
++#define CLK_INFRA_CA53SEL		13
++#define CLK_INFRA_CA57SEL		14
++#define CLK_INFRA_NR_CLK		15
+ 
+ /* PERI_SYS */
+ 
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0063-cpufreq-mediatek-add-driver.patch

@@ -0,0 +1,443 @@
+From a430fa942b3ff0e51f472e53110b7f6b16290295 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Wed, 30 Mar 2016 23:48:53 +0200
+Subject: [PATCH 63/91] cpufreq: mediatek: add driver
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/cpufreq/Kconfig.arm      |    9 +
+ drivers/cpufreq/Makefile         |    1 +
+ drivers/cpufreq/mt7623-cpufreq.c |  389 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 399 insertions(+)
+ create mode 100644 drivers/cpufreq/mt7623-cpufreq.c
+
+diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
+index b1f8a73..baf945e 100644
+--- a/drivers/cpufreq/Kconfig.arm
++++ b/drivers/cpufreq/Kconfig.arm
+@@ -81,6 +81,15 @@ config ARM_KIRKWOOD_CPUFREQ
+ 	  This adds the CPUFreq driver for Marvell Kirkwood
+ 	  SoCs.
+ 
++config ARM_MT7623_CPUFREQ
++	bool "Mediatek MT7623 CPUFreq support"
++	depends on ARCH_MEDIATEK && REGULATOR
++	depends on ARM || (ARM_CPU_TOPOLOGY && COMPILE_TEST)
++	depends on !CPU_THERMAL || THERMAL=y
++	select PM_OPP
++	help
++	  This adds the CPUFreq driver support for Mediatek MT7623 SoC.
++
+ config ARM_MT8173_CPUFREQ
+ 	bool "Mediatek MT8173 CPUFreq support"
+ 	depends on ARCH_MEDIATEK && REGULATOR
+diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
+index c0af1a1..e198752 100644
+--- a/drivers/cpufreq/Makefile
++++ b/drivers/cpufreq/Makefile
+@@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ)	+= hisi-acpu-cpufreq.o
+ obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)		+= imx6q-cpufreq.o
+ obj-$(CONFIG_ARM_INTEGRATOR)		+= integrator-cpufreq.o
+ obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ)	+= kirkwood-cpufreq.o
++obj-$(CONFIG_ARM_MT7623_CPUFREQ)	+= mt7623-cpufreq.o
+ obj-$(CONFIG_ARM_MT8173_CPUFREQ)	+= mt8173-cpufreq.o
+ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)	+= omap-cpufreq.o
+ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)	+= pxa2xx-cpufreq.o
+diff --git a/drivers/cpufreq/mt7623-cpufreq.c b/drivers/cpufreq/mt7623-cpufreq.c
+new file mode 100644
+index 0000000..8d154ce
+--- /dev/null
++++ b/drivers/cpufreq/mt7623-cpufreq.c
+@@ -0,0 +1,389 @@
++/*
++ * Copyright (c) 2015 Linaro Ltd.
++ * Author: Pi-Cheng Chen <[email protected]>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/cpu.h>
++#include <linux/cpu_cooling.h>
++#include <linux/cpufreq.h>
++#include <linux/cpumask.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_opp.h>
++#include <linux/regulator/consumer.h>
++#include <linux/slab.h>
++#include <linux/thermal.h>
++
++#define VOLT_TOL		(10000)
++
++/*
++ * When scaling the clock frequency of a CPU clock domain, the clock source
++ * needs to be switched to another stable PLL clock temporarily until
++ * the original PLL becomes stable at target frequency.
++ */
++struct mtk_cpu_dvfs_info {
++	struct device *cpu_dev;
++	struct regulator *proc_reg;
++	struct clk *cpu_clk;
++	struct clk *inter_clk;
++	struct thermal_cooling_device *cdev;
++	int intermediate_voltage;
++};
++
++static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
++{
++	return regulator_set_voltage(info->proc_reg, vproc,
++				     vproc + VOLT_TOL);
++}
++
++static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
++				  unsigned int index)
++{
++	struct cpufreq_frequency_table *freq_table = policy->freq_table;
++	struct clk *cpu_clk = policy->clk;
++	struct clk *armpll = clk_get_parent(cpu_clk);
++	struct mtk_cpu_dvfs_info *info = policy->driver_data;
++	struct device *cpu_dev = info->cpu_dev;
++	struct dev_pm_opp *opp;
++	long freq_hz, old_freq_hz;
++	int vproc, old_vproc, inter_vproc, target_vproc, ret;
++
++	inter_vproc = info->intermediate_voltage;
++
++	old_freq_hz = clk_get_rate(cpu_clk);
++	old_vproc = regulator_get_voltage(info->proc_reg);
++
++	freq_hz = freq_table[index].frequency * 1000;
++
++	rcu_read_lock();
++	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
++	if (IS_ERR(opp)) {
++		rcu_read_unlock();
++		pr_err("cpu%d: failed to find OPP for %ld\n",
++		       policy->cpu, freq_hz);
++		return PTR_ERR(opp);
++	}
++	vproc = dev_pm_opp_get_voltage(opp);
++	rcu_read_unlock();
++
++	/*
++	 * If the new voltage or the intermediate voltage is higher than the
++	 * current voltage, scale up voltage first.
++	 */
++	target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
++	if (old_vproc < target_vproc) {
++		ret = mtk_cpufreq_set_voltage(info, target_vproc);
++		if (ret) {
++			pr_err("cpu%d: failed to scale up voltage!\n",
++			       policy->cpu);
++			mtk_cpufreq_set_voltage(info, old_vproc);
++			return ret;
++		}
++	}
++
++	/* Reparent the CPU clock to intermediate clock. */
++	ret = clk_set_parent(cpu_clk, info->inter_clk);
++	if (ret) {
++		pr_err("cpu%d: failed to re-parent cpu clock!\n",
++		       policy->cpu);
++		mtk_cpufreq_set_voltage(info, old_vproc);
++		WARN_ON(1);
++		return ret;
++	}
++
++	/* Set the original PLL to target rate. */
++	ret = clk_set_rate(armpll, freq_hz);
++	if (ret) {
++		pr_err("cpu%d: failed to scale cpu clock rate!\n",
++		       policy->cpu);
++		clk_set_parent(cpu_clk, armpll);
++		mtk_cpufreq_set_voltage(info, old_vproc);
++		return ret;
++	}
++
++	/* Set parent of CPU clock back to the original PLL. */
++	ret = clk_set_parent(cpu_clk, armpll);
++	if (ret) {
++		pr_err("cpu%d: failed to re-parent cpu clock!\n",
++		       policy->cpu);
++		mtk_cpufreq_set_voltage(info, inter_vproc);
++		WARN_ON(1);
++		return ret;
++	}
++
++	/*
++	 * If the new voltage is lower than the intermediate voltage or the
++	 * original voltage, scale down to the new voltage.
++	 */
++	if (vproc < inter_vproc || vproc < old_vproc) {
++		ret = mtk_cpufreq_set_voltage(info, vproc);
++		if (ret) {
++			pr_err("cpu%d: failed to scale down voltage!\n",
++			       policy->cpu);
++			clk_set_parent(cpu_clk, info->inter_clk);
++			clk_set_rate(armpll, old_freq_hz);
++			clk_set_parent(cpu_clk, armpll);
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static void mtk_cpufreq_ready(struct cpufreq_policy *policy)
++{
++	struct mtk_cpu_dvfs_info *info = policy->driver_data;
++	struct device_node *np = of_node_get(info->cpu_dev->of_node);
++
++	if (WARN_ON(!np))
++		return;
++
++	if (of_find_property(np, "#cooling-cells", NULL)) {
++		info->cdev = of_cpufreq_cooling_register(np,
++							 policy->related_cpus);
++
++		if (IS_ERR(info->cdev)) {
++			dev_err(info->cpu_dev,
++				"running cpufreq without cooling device: %ld\n",
++				PTR_ERR(info->cdev));
++
++			info->cdev = NULL;
++		}
++	}
++
++	of_node_put(np);
++}
++
++static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
++{
++	struct device *cpu_dev;
++	struct regulator *proc_reg = ERR_PTR(-ENODEV);
++	struct clk *cpu_clk = ERR_PTR(-ENODEV);
++	struct clk *inter_clk = ERR_PTR(-ENODEV);
++	struct dev_pm_opp *opp;
++	unsigned long rate;
++	int ret;
++
++	cpu_dev = get_cpu_device(cpu);
++	if (!cpu_dev) {
++		pr_err("failed to get cpu%d device\n", cpu);
++		return -ENODEV;
++	}
++
++	cpu_clk = clk_get(cpu_dev, "cpu");
++	if (IS_ERR(cpu_clk)) {
++		if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
++			pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
++		else
++			pr_err("failed to get cpu clk for cpu%d\n", cpu);
++
++		ret = PTR_ERR(cpu_clk);
++		return ret;
++	}
++
++	inter_clk = clk_get(cpu_dev, "intermediate");
++	if (IS_ERR(inter_clk)) {
++		if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
++			pr_warn("intermediate clk for cpu%d not ready, retry.\n",
++				cpu);
++		else
++			pr_err("failed to get intermediate clk for cpu%d\n",
++			       cpu);
++
++		ret = PTR_ERR(inter_clk);
++		goto out_free_resources;
++	}
++
++	proc_reg = regulator_get_exclusive(cpu_dev, "proc");
++	if (IS_ERR(proc_reg)) {
++		if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
++			pr_warn("proc regulator for cpu%d not ready, retry.\n",
++				cpu);
++		else
++			pr_err("failed to get proc regulator for cpu%d\n",
++			       cpu);
++
++		ret = PTR_ERR(proc_reg);
++		goto out_free_resources;
++	}
++
++	ret = dev_pm_opp_of_add_table(cpu_dev);
++	if (ret) {
++		pr_warn("no OPP table for cpu%d\n", cpu);
++		goto out_free_resources;
++	}
++
++	/* Search a safe voltage for intermediate frequency. */
++	rate = clk_get_rate(inter_clk);
++	rcu_read_lock();
++	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
++	if (IS_ERR(opp)) {
++		rcu_read_unlock();
++		pr_err("failed to get intermediate opp for cpu%d\n", cpu);
++		ret = PTR_ERR(opp);
++		goto out_free_opp_table;
++	}
++	info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
++	rcu_read_unlock();
++
++	info->cpu_dev = cpu_dev;
++	info->proc_reg = proc_reg;
++	info->cpu_clk = cpu_clk;
++	info->inter_clk = inter_clk;
++
++	return 0;
++
++out_free_opp_table:
++	dev_pm_opp_of_remove_table(cpu_dev);
++
++out_free_resources:
++	if (!IS_ERR(proc_reg))
++		regulator_put(proc_reg);
++	if (!IS_ERR(cpu_clk))
++		clk_put(cpu_clk);
++	if (!IS_ERR(inter_clk))
++		clk_put(inter_clk);
++
++	return ret;
++}
++
++static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
++{
++	if (!IS_ERR(info->proc_reg))
++		regulator_put(info->proc_reg);
++	if (!IS_ERR(info->cpu_clk))
++		clk_put(info->cpu_clk);
++	if (!IS_ERR(info->inter_clk))
++		clk_put(info->inter_clk);
++
++	dev_pm_opp_of_remove_table(info->cpu_dev);
++}
++
++static int mtk_cpufreq_init(struct cpufreq_policy *policy)
++{
++	struct mtk_cpu_dvfs_info *info;
++	struct cpufreq_frequency_table *freq_table;
++	int ret;
++
++	info = kzalloc(sizeof(*info), GFP_KERNEL);
++	if (!info)
++		return -ENOMEM;
++
++	ret = mtk_cpu_dvfs_info_init(info, policy->cpu);
++	if (ret) {
++		pr_err("%s failed to initialize dvfs info for cpu%d\n",
++		       __func__, policy->cpu);
++		goto out_free_dvfs_info;
++	}
++
++	ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
++	if (ret) {
++		pr_err("failed to init cpufreq table for cpu%d: %d\n",
++		       policy->cpu, ret);
++		goto out_release_dvfs_info;
++	}
++
++	ret = cpufreq_table_validate_and_show(policy, freq_table);
++	if (ret) {
++		pr_err("%s: invalid frequency table: %d\n", __func__, ret);
++		goto out_free_cpufreq_table;
++	}
++
++	/* CPUs in the same cluster share a clock and power domain. */
++	cpumask_setall(policy->cpus);
++	policy->driver_data = info;
++	policy->clk = info->cpu_clk;
++
++	return 0;
++
++out_free_cpufreq_table:
++	dev_pm_opp_free_cpufreq_table(info->cpu_dev, &freq_table);
++
++out_release_dvfs_info:
++	mtk_cpu_dvfs_info_release(info);
++
++out_free_dvfs_info:
++	kfree(info);
++
++	return ret;
++}
++
++static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
++{
++	struct mtk_cpu_dvfs_info *info = policy->driver_data;
++
++	cpufreq_cooling_unregister(info->cdev);
++	dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
++	mtk_cpu_dvfs_info_release(info);
++	kfree(info);
++
++	return 0;
++}
++
++static struct cpufreq_driver mt7623_cpufreq_driver = {
++	.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
++	.verify = cpufreq_generic_frequency_table_verify,
++	.target_index = mtk_cpufreq_set_target,
++	.get = cpufreq_generic_get,
++	.init = mtk_cpufreq_init,
++	.exit = mtk_cpufreq_exit,
++	.ready = mtk_cpufreq_ready,
++	.name = "mtk-cpufreq",
++	.attr = cpufreq_generic_attr,
++};
++
++static int mt7623_cpufreq_probe(struct platform_device *pdev)
++{
++	int ret;
++
++	ret = cpufreq_register_driver(&mt7623_cpufreq_driver);
++	if (ret)
++		pr_err("failed to register mtk cpufreq driver\n");
++
++	return ret;
++}
++
++static struct platform_driver mt7623_cpufreq_platdrv = {
++	.driver = {
++		.name	= "mt7623-cpufreq",
++	},
++	.probe		= mt7623_cpufreq_probe,
++};
++
++static int mt7623_cpufreq_driver_init(void)
++{
++	struct platform_device *pdev;
++	int err;
++
++	if (!of_machine_is_compatible("mediatek,mt7623"))
++		return -ENODEV;
++
++	err = platform_driver_register(&mt7623_cpufreq_platdrv);
++	if (err)
++		return err;
++
++	/*
++	 * Since there's no place to hold device registration code and no
++	 * device tree based way to match cpufreq driver yet, both the driver
++	 * and the device registration codes are put here to handle defer
++	 * probing.
++	 */
++	pdev = platform_device_register_simple("mt7623-cpufreq", -1, NULL, 0);
++	if (IS_ERR(pdev)) {
++		pr_err("failed to register mtk-cpufreq platform device\n");
++		return PTR_ERR(pdev);
++	}
++
++	return 0;
++}
++device_initcall(mt7623_cpufreq_driver_init);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0064-arm-mediatek-make-a7-timer-work.patch

@@ -0,0 +1,38 @@
+From cf070892e774e76e1bd969020d8e7f31af1d2e3d Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Thu, 31 Mar 2016 06:07:01 +0200
+Subject: [PATCH 64/91] arm: mediatek: make a7 timer work Signed-off-by: John
+ Crispin <[email protected]>
+
+---
+ arch/arm/mach-mediatek/Kconfig    |    1 +
+ arch/arm/mach-mediatek/mediatek.c |    1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index a7fef77..2c05bc31 100644
+--- a/arch/arm/mach-mediatek/Kconfig
++++ b/arch/arm/mach-mediatek/Kconfig
+@@ -24,6 +24,7 @@ config MACH_MT6592
+ config MACH_MT7623
+ 	bool "MediaTek MT7623 SoCs support"
+ 	default ARCH_MEDIATEK
++	select HAVE_ARM_ARCH_TIMER
+ 	select MIGHT_HAVE_PCI
+ 
+ config MACH_MT8127
+diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
+index bcfca37..7553a8c 100644
+--- a/arch/arm/mach-mediatek/mediatek.c
++++ b/arch/arm/mach-mediatek/mediatek.c
+@@ -29,6 +29,7 @@ static void __init mediatek_timer_init(void)
+ 	void __iomem *gpt_base;
+ 
+ 	if (of_machine_is_compatible("mediatek,mt6589") ||
++	    of_machine_is_compatible("mediatek,mt7623") ||
+ 	    of_machine_is_compatible("mediatek,mt8135") ||
+ 	    of_machine_is_compatible("mediatek,mt8127")) {
+ 		/* turn on GPT6 which ungates arch timer clocks */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0060-net-mediatek-checking-for-IS_ERR-instead-of-NULL.patch → target/linux/mediatek/patches-4.4/0065-net-mediatek-checking-for-IS_ERR-instead-of-NULL.patch

@@ -1,7 +1,7 @@
-From c657573d75d71076fef8294f9d4f7f9a0e6f7a9e Mon Sep 17 00:00:00 2001
+From 56b33ebf188a59d8307c3b748eccf8cda1062981 Mon Sep 17 00:00:00 2001
 From: Dan Carpenter <[email protected]>
 Date: Tue, 15 Mar 2016 10:18:49 +0300
-Subject: [PATCH 60/81] net: mediatek: checking for IS_ERR() instead of NULL
+Subject: [PATCH 65/91] net: mediatek: checking for IS_ERR() instead of NULL
 
 of_phy_connect() returns NULL on error, it never returns error pointers.
 
@@ -11,9 +11,11 @@ Signed-off-by: Dan Carpenter <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index ba3afa5..9759fe5 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -186,9 +186,9 @@ static int mtk_phy_connect_node(struct m
+@@ -186,9 +186,9 @@ static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
  
  	phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
  				mtk_phy_link_adjust, 0, phy_mode);
@@ -25,3 +27,6 @@ Signed-off-by: Dan Carpenter <[email protected]>
  	}
  
  	dev_info(eth->dev,
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0061-net-mediatek-unlock-on-error-in-mtk_tx_map.patch → target/linux/mediatek/patches-4.4/0066-net-mediatek-unlock-on-error-in-mtk_tx_map.patch

@@ -1,7 +1,7 @@
-From d8261ad9e408adfa5d1758a0f655c7726f0f831b Mon Sep 17 00:00:00 2001
+From 223a164816ee104df9fbd01c0c52587bd8d7d758 Mon Sep 17 00:00:00 2001
 From: Dan Carpenter <[email protected]>
 Date: Tue, 15 Mar 2016 10:19:04 +0300
-Subject: [PATCH 61/81] net: mediatek: unlock on error in mtk_tx_map()
+Subject: [PATCH 66/91] net: mediatek: unlock on error in mtk_tx_map()
 
 There was a missing unlock on the error path.
 
@@ -11,6 +11,8 @@ Signed-off-by: Dan Carpenter <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    2 ++
  1 file changed, 2 insertions(+)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 9759fe5..c2c2e206 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 @@ -661,6 +661,8 @@ err_dma:
@@ -22,3 +24,6 @@ Signed-off-by: Dan Carpenter <[email protected]>
  	return -ENOMEM;
  }
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0062-net-mediatek-use-dma_addr_t-correctly.patch → target/linux/mediatek/patches-4.4/0067-net-mediatek-use-dma_addr_t-correctly.patch

@@ -1,7 +1,7 @@
-From 26c749e825e87e8be46498be7ac425e83b0f22c6 Mon Sep 17 00:00:00 2001
+From d57c2d08cdceba377a35f69ceb807ae58f4bdbb2 Mon Sep 17 00:00:00 2001
 From: Arnd Bergmann <[email protected]>
 Date: Mon, 14 Mar 2016 15:07:10 +0100
-Subject: [PATCH 62/81] net: mediatek: use dma_addr_t correctly
+Subject: [PATCH 67/91] net: mediatek: use dma_addr_t correctly
 
 dma_alloc_coherent() expects a dma_addr_t pointer as its argument,
 not an 'unsigned int', and gcc correctly warns about broken
@@ -17,9 +17,11 @@ Signed-off-by: Arnd Bergmann <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index c2c2e206..a005bc4 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -453,7 +453,7 @@ static inline void mtk_rx_get_desc(struc
+@@ -453,7 +453,7 @@ static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
  /* the qdma core needs scratch memory to be setup */
  static int mtk_init_fq_dma(struct mtk_eth *eth)
  {
@@ -28,3 +30,6 @@ Signed-off-by: Arnd Bergmann <[email protected]>
  	int cnt = MTK_DMA_SIZE;
  	dma_addr_t dma_addr;
  	int i;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0063-net-mediatek-remove-incorrect-dma_mask-assignment.patch → target/linux/mediatek/patches-4.4/0068-net-mediatek-remove-incorrect-dma_mask-assignment.patch

@@ -1,7 +1,7 @@
-From 21f52c7a0ec569ae9dd72bfc619a7161e40a2e9d Mon Sep 17 00:00:00 2001
+From 6cf7d8453b9ef0a1e51144969141a92dade6b540 Mon Sep 17 00:00:00 2001
 From: Arnd Bergmann <[email protected]>
 Date: Mon, 14 Mar 2016 15:07:11 +0100
-Subject: [PATCH 63/81] net: mediatek: remove incorrect dma_mask assignment
+Subject: [PATCH 68/91] net: mediatek: remove incorrect dma_mask assignment
 
 Device drivers should not mess with the DMA mask directly,
 but instead call dma_set_mask() etc if needed.
@@ -17,9 +17,11 @@ Signed-off-by: Arnd Bergmann <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    3 ---
  1 file changed, 3 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index a005bc4..fcd4ed7 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1678,9 +1678,6 @@ static int mtk_probe(struct platform_dev
+@@ -1678,9 +1678,6 @@ static int mtk_probe(struct platform_device *pdev)
  	struct mtk_eth *eth;
  	int err;
  
@@ -29,3 +31,6 @@ Signed-off-by: Arnd Bergmann <[email protected]>
  	device_reset(&pdev->dev);
  
  	match = of_match_device(of_mtk_match, &pdev->dev);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0064-net-mediatek-check-device_reset-return-code.patch → target/linux/mediatek/patches-4.4/0069-net-mediatek-check-device_reset-return-code.patch

@@ -1,7 +1,7 @@
-From e1e7d841480b3a0febdb999fd1c6c4213ee18ea7 Mon Sep 17 00:00:00 2001
+From 592d94e0e580341fdcce975a97bebb90e71b38fc Mon Sep 17 00:00:00 2001
 From: Arnd Bergmann <[email protected]>
 Date: Mon, 14 Mar 2016 15:07:12 +0100
-Subject: [PATCH 64/81] net: mediatek: check device_reset return code
+Subject: [PATCH 69/91] net: mediatek: check device_reset return code
 
 The device_reset() function may fail, so we have to check
 its return value, e.g. to make deferred probing work correctly.
@@ -18,9 +18,11 @@ Signed-off-by: Arnd Bergmann <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index fcd4ed7..7f2126b 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1678,7 +1678,9 @@ static int mtk_probe(struct platform_dev
+@@ -1678,7 +1678,9 @@ static int mtk_probe(struct platform_device *pdev)
  	struct mtk_eth *eth;
  	int err;
  
@@ -31,3 +33,6 @@ Signed-off-by: Arnd Bergmann <[email protected]>
  
  	match = of_match_device(of_mtk_match, &pdev->dev);
  	soc = (struct mtk_soc_data *)match->data;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0065-net-mediatek-watchdog_timeo-was-not-set.patch → target/linux/mediatek/patches-4.4/0070-net-mediatek-watchdog_timeo-was-not-set.patch

@@ -1,7 +1,7 @@
-From 103d950e6201ab54a8b64402bb0b32a35831b028 Mon Sep 17 00:00:00 2001
+From d59c125296df424b8e7c5c4900e1b8084b6dd3ba Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Wed, 30 Mar 2016 03:18:17 +0200
-Subject: [PATCH 65/81] net: mediatek: watchdog_timeo was not set
+Subject: [PATCH 70/91] net: mediatek: watchdog_timeo was not set
 
 The original commit failed to set watchdog_timeo. This patch sets
 watchdog_timeo to HZ.
@@ -11,9 +11,11 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 7f2126b..7e6d2e2 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1645,6 +1645,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -1645,6 +1645,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
  	mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
  
  	SET_NETDEV_DEV(eth->netdev[id], eth->dev);
@@ -21,3 +23,6 @@ Signed-off-by: John Crispin <[email protected]>
  	eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
  	eth->netdev[id]->base_addr = (unsigned long)eth->base;
  	eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0066-net-mediatek-mtk_cal_txd_req-returns-bad-value.patch → target/linux/mediatek/patches-4.4/0071-net-mediatek-mtk_cal_txd_req-returns-bad-value.patch

@@ -1,7 +1,7 @@
-From 1212704e8270f0e673e10a49960318ade0096cf9 Mon Sep 17 00:00:00 2001
+From b6f1b24448de1d294f9668b14bf02391ff6bef5c Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 22 Mar 2016 04:42:27 +0100
-Subject: [PATCH 66/81] net: mediatek: mtk_cal_txd_req() returns bad value
+Subject: [PATCH 71/91] net: mediatek: mtk_cal_txd_req() returns bad value
 
 The code used to also support the PDMA engine, which had 2 packet pointers
 per descriptor. Because of this we have to divide the result by 2 and round
@@ -12,9 +12,11 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 7e6d2e2..4d8d0a3 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -681,7 +681,7 @@ static inline int mtk_cal_txd_req(struct
+@@ -681,7 +681,7 @@ static inline int mtk_cal_txd_req(struct sk_buff *skb)
  		nfrags += skb_shinfo(skb)->nr_frags;
  	}
  
@@ -23,3 +25,6 @@ Signed-off-by: John Crispin <[email protected]>
  }
  
  static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0068-net-mediatek-remove-superflous-reset-call.patch → target/linux/mediatek/patches-4.4/0072-net-mediatek-remove-superflous-reset-call.patch

@@ -1,7 +1,7 @@
-From 3c8781211140cc23750544a52b7310edb3b57f00 Mon Sep 17 00:00:00 2001
+From dd061dc7eacb22853981978fa94205292444fa49 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Fri, 25 Mar 2016 04:24:27 +0100
-Subject: [PATCH 68/81] net: mediatek: remove superflous reset call
+Subject: [PATCH 72/91] net: mediatek: remove superflous reset call
 
 HW reset is triggered int he mtk_hw_init() function. There is no need to
 reset the core during probe.
@@ -11,9 +11,11 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    4 ----
  1 file changed, 4 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 4d8d0a3..293ea59 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1679,10 +1679,6 @@ static int mtk_probe(struct platform_dev
+@@ -1679,10 +1679,6 @@ static int mtk_probe(struct platform_device *pdev)
  	struct mtk_eth *eth;
  	int err;
  
@@ -24,3 +26,6 @@ Signed-off-by: John Crispin <[email protected]>
  	match = of_match_device(of_mtk_match, &pdev->dev);
  	soc = (struct mtk_soc_data *)match->data;
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0069-net-mediatek-fix-stop-and-wakeup-of-queue.patch → target/linux/mediatek/patches-4.4/0073-net-mediatek-fix-stop-and-wakeup-of-queue.patch

@@ -1,7 +1,7 @@
-From 6f8bfdfe2984467177d2a88982517659ec09ab5d Mon Sep 17 00:00:00 2001
+From 283001c04f395f32e55345632d8129f5395cde33 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 29 Mar 2016 16:41:07 +0200
-Subject: [PATCH 69/81] net: mediatek: fix stop and wakeup of queue
+Subject: [PATCH 73/91] net: mediatek: fix stop and wakeup of queue
 
 The driver supports 2 MACs. Both run on the same DMA ring. If we go
 above/below the TX rings thershold value, we always need to wake/stop
@@ -13,9 +13,11 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |   37 +++++++++++++++++++--------
  1 file changed, 27 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 293ea59..04bdb9d 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -684,6 +684,28 @@ static inline int mtk_cal_txd_req(struct
+@@ -684,6 +684,28 @@ static inline int mtk_cal_txd_req(struct sk_buff *skb)
  	return nfrags;
  }
  
@@ -44,7 +46,7 @@ Signed-off-by: John Crispin <[email protected]>
  static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  {
  	struct mtk_mac *mac = netdev_priv(dev);
-@@ -695,7 +717,7 @@ static int mtk_start_xmit(struct sk_buff
+@@ -695,7 +717,7 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  
  	tx_num = mtk_cal_txd_req(skb);
  	if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
@@ -53,7 +55,7 @@ Signed-off-by: John Crispin <[email protected]>
  		netif_err(eth, tx_queued, dev,
  			  "Tx Ring full when queue awake!\n");
  		return NETDEV_TX_BUSY;
-@@ -720,10 +742,10 @@ static int mtk_start_xmit(struct sk_buff
+@@ -720,10 +742,10 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  		goto drop;
  
  	if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) {
@@ -66,7 +68,7 @@ Signed-off-by: John Crispin <[email protected]>
  	}
  
  	return NETDEV_TX_OK;
-@@ -897,13 +919,8 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -897,13 +919,8 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
  	if (!total)
  		return 0;
  
@@ -82,3 +84,6 @@ Signed-off-by: John Crispin <[email protected]>
  
  	return total;
  }
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0070-net-mediatek-fix-mtk_pending_work.patch → target/linux/mediatek/patches-4.4/0074-net-mediatek-fix-mtk_pending_work.patch

@@ -1,7 +1,7 @@
-From a2dfb33c8a0dc03fe2ec2121490df2b9352febef Mon Sep 17 00:00:00 2001
+From 46e02ea6c0468ce01b6e370a20f01a7f7311af34 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 29 Mar 2016 17:00:47 +0200
-Subject: [PATCH 70/81] net: mediatek: fix mtk_pending_work
+Subject: [PATCH 74/91] net: mediatek: fix mtk_pending_work
 
 The driver supports 2 MACs. Both run on the same DMA ring. If we hit a TX
 timeout we need to stop both netdevs before retarting them again. If we
@@ -13,9 +13,11 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |   30 +++++++++++++++++++--------
  1 file changed, 21 insertions(+), 9 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 04bdb9d..26eeb1a 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1430,19 +1430,31 @@ static int mtk_do_ioctl(struct net_devic
+@@ -1430,19 +1430,31 @@ static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  
  static void mtk_pending_work(struct work_struct *work)
  {
@@ -56,3 +58,6 @@ Signed-off-by: John Crispin <[email protected]>
  	}
  	rtnl_unlock();
  }
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0071-net-mediatek-fix-TX-locking.patch → target/linux/mediatek/patches-4.4/0075-net-mediatek-fix-TX-locking.patch

@@ -1,7 +1,7 @@
-From b9df14f712866925856c0ffb2d899511c21e1b8a Mon Sep 17 00:00:00 2001
+From 25e46afc7324196c89dfb6f83a9c518942e23b33 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 29 Mar 2016 17:20:01 +0200
-Subject: [PATCH 71/81] net: mediatek: fix TX locking
+Subject: [PATCH 75/91] net: mediatek: fix TX locking
 
 Inside the TX path there is a lock inside the tx_map function. This is
 however too late. The patch moves the lock to the start of the xmit
@@ -15,9 +15,11 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |   20 ++++++++++----------
  1 file changed, 10 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 26eeb1a..67b18f9 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -536,7 +536,6 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -536,7 +536,6 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
  	struct mtk_eth *eth = mac->hw;
  	struct mtk_tx_dma *itxd, *txd;
  	struct mtk_tx_buf *tx_buf;
@@ -25,7 +27,7 @@ Signed-off-by: John Crispin <[email protected]>
  	dma_addr_t mapped_addr;
  	unsigned int nr_frags;
  	int i, n_desc = 1;
-@@ -568,11 +567,6 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -568,11 +567,6 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
  	if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
  		return -ENOMEM;
  
@@ -37,7 +39,7 @@ Signed-off-by: John Crispin <[email protected]>
  	WRITE_ONCE(itxd->txd1, mapped_addr);
  	tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
  	dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
-@@ -632,8 +626,6 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -632,8 +626,6 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
  	WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
  				(!nr_frags * TX_DMA_LS0)));
  
@@ -55,7 +57,7 @@ Signed-off-by: John Crispin <[email protected]>
  	return -ENOMEM;
  }
  
-@@ -712,14 +702,22 @@ static int mtk_start_xmit(struct sk_buff
+@@ -712,14 +702,22 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  	struct mtk_eth *eth = mac->hw;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	struct net_device_stats *stats = &dev->stats;
@@ -78,7 +80,7 @@ Signed-off-by: John Crispin <[email protected]>
  		return NETDEV_TX_BUSY;
  	}
  
-@@ -747,10 +745,12 @@ static int mtk_start_xmit(struct sk_buff
+@@ -747,10 +745,12 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  			     ring->thresh))
  			mtk_wake_queue(eth);
  	}
@@ -91,3 +93,6 @@ Signed-off-by: John Crispin <[email protected]>
  	stats->tx_dropped++;
  	dev_kfree_skb(skb);
  	return NETDEV_TX_OK;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0072-net-mediatek-move-the-pending_work-struct-to-the-dev.patch → target/linux/mediatek/patches-4.4/0076-net-mediatek-move-the-pending_work-struct-to-the-dev.patch

@@ -1,7 +1,7 @@
-From 147dab4408adcccf702f8c5143e9c6b91f746790 Mon Sep 17 00:00:00 2001
+From 8830adaea03aafc1e35f739e436dc36af7c54428 Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 29 Mar 2016 17:24:24 +0200
-Subject: [PATCH 72/81] net: mediatek: move the pending_work struct to the
+Subject: [PATCH 76/91] net: mediatek: move the pending_work struct to the
  device generic struct
 
 The worker always touches both netdevs. It is ethernet core and not MAC
@@ -13,9 +13,11 @@ Signed-off-by: John Crispin <[email protected]>
  drivers/net/ethernet/mediatek/mtk_eth_soc.h |    4 ++--
  2 files changed, 6 insertions(+), 8 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 67b18f9..bbcd607 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1193,7 +1193,7 @@ static void mtk_tx_timeout(struct net_de
+@@ -1193,7 +1193,7 @@ static void mtk_tx_timeout(struct net_device *dev)
  	eth->netdev[mac->id]->stats.tx_errors++;
  	netif_err(eth, tx_err, dev,
  		  "transmit timed out\n");
@@ -24,7 +26,7 @@ Signed-off-by: John Crispin <[email protected]>
  }
  
  static irqreturn_t mtk_handle_irq(int irq, void *_eth)
-@@ -1438,7 +1438,7 @@ static void mtk_pending_work(struct work
+@@ -1438,7 +1438,7 @@ static void mtk_pending_work(struct work_struct *work)
  
  	/* stop all devices to make sure that dma is properly shut down */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
@@ -33,7 +35,7 @@ Signed-off-by: John Crispin <[email protected]>
  			continue;
  		mtk_stop(eth->netdev[i]);
  		__set_bit(i, &restart);
-@@ -1464,15 +1464,13 @@ static int mtk_cleanup(struct mtk_eth *e
+@@ -1464,15 +1464,13 @@ static int mtk_cleanup(struct mtk_eth *eth)
  	int i;
  
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
@@ -50,7 +52,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	return 0;
  }
-@@ -1660,7 +1658,6 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -1660,7 +1658,6 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
  	mac->id = id;
  	mac->hw = eth;
  	mac->of_node = np;
@@ -58,7 +60,7 @@ Signed-off-by: John Crispin <[email protected]>
  
  	mac->hw_stats = devm_kzalloc(eth->dev,
  				     sizeof(*mac->hw_stats),
-@@ -1762,6 +1759,7 @@ static int mtk_probe(struct platform_dev
+@@ -1762,6 +1759,7 @@ static int mtk_probe(struct platform_device *pdev)
  
  	eth->dev = &pdev->dev;
  	eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
@@ -66,6 +68,8 @@ Signed-off-by: John Crispin <[email protected]>
  
  	err = mtk_hw_init(eth);
  	if (err)
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+index 48a5292..eed626d 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 @@ -363,6 +363,7 @@ struct mtk_rx_ring {
@@ -100,3 +104,6 @@ Signed-off-by: John Crispin <[email protected]>
  };
  
  /* the struct describing the SoC. these are declared in the soc_xyz.c files */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0077-net-mediatek-do-not-set-the-QID-field-in-the-TX-DMA-.patch

@@ -0,0 +1,37 @@
+From 6a6f264e82649f8d9933271f2e9b08af94daad50 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Thu, 7 Apr 2016 17:36:23 +0200
+Subject: [PATCH 77/91] net: mediatek: do not set the QID field in the TX DMA
+ descriptors
+
+The QID field gets set to the mac id. This made the DMA linked list queue
+the traffic of each MAC on a different internal queue. However during long
+term testing we found that this will cause traffic stalls as the multi
+queue setup requires a more complete initialisation which is not part of
+the upstream driver yet.
+
+This patch removes the code setting the QID field, resulting in all
+traffic ending up in queue 0 which works without any special setup.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index bbcd607..bab5d45 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -603,8 +603,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
+ 			WRITE_ONCE(txd->txd1, mapped_addr);
+ 			WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
+ 					       TX_DMA_PLEN0(frag_map_size) |
+-					       last_frag * TX_DMA_LS0) |
+-					       mac->id);
++					       last_frag * TX_DMA_LS0));
+ 			WRITE_ONCE(txd->txd4, 0);
+ 
+ 			tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0067-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch → target/linux/mediatek/patches-4.4/0078-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch

@@ -1,7 +1,7 @@
-From 429b5becfb1e4aacf392c4b246a17b83faad3072 Mon Sep 17 00:00:00 2001
+From 9dd4e96d415d1e1910ec42058729380cddb22f9d Mon Sep 17 00:00:00 2001
 From: John Crispin <[email protected]>
 Date: Tue, 29 Mar 2016 14:32:07 +0200
-Subject: [PATCH 67/81] net: mediatek: update the IRQ part of the binding
+Subject: [PATCH 78/91] net: mediatek: update the IRQ part of the binding
  document
 
 The current binding document only describes a single interrupt. Update the
@@ -13,21 +13,24 @@ to using IRQ grouping to split TX and RX onto separate GIC irqs.
 Signed-off-by: John Crispin <[email protected]>
  Acked-by: Rob Herring <[email protected]>
 ---
- Documentation/devicetree/bindings/net/mediatek-net.txt |    6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
+ Documentation/devicetree/bindings/net/mediatek-net.txt |    7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
 
+diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
+index 5ca7929..32eaaca 100644
 --- a/Documentation/devicetree/bindings/net/mediatek-net.txt
 +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
-@@ -9,7 +9,7 @@ have dual GMAC each represented by a chi
+@@ -9,7 +9,8 @@ have dual GMAC each represented by a child node..
  Required properties:
  - compatible: Should be "mediatek,mt7623-eth"
  - reg: Address and length of the register set for the device
 -- interrupts: Should contain the frame engines interrupt
-+- interrupts: Should contain the three frame engines interrupts
++- interrupts: Should contain the three frame engines interrupts in numeric
++	order. These are fe_int0, fe_int1 and fe_int2.
  - clocks: the clock used by the core
  - clock-names: the names of the clock listed in the clocks property. These are
  	"ethif", "esw", "gp2", "gp1"
-@@ -42,7 +42,9 @@ eth: ethernet@1b100000 {
+@@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
  		 <&ethsys CLK_ETHSYS_GP2>,
  		 <&ethsys CLK_ETHSYS_GP1>;
  	clock-names = "ethif", "esw", "gp2", "gp1";
@@ -38,3 +41,6 @@ Signed-off-by: John Crispin <[email protected]>
  	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  	resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
  	reset-names = "eth";
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0079-net-next-fix-BQL-support.patch

@@ -0,0 +1,90 @@
+From f84a8ad5cc385fe414758fa4d423e26197a79c28 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Sat, 23 Apr 2016 11:57:21 +0200
+Subject: [PATCH 79/91] net-next: fix BQL support
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |   33 +++++++++++++++------------
+ 1 file changed, 19 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index bab5d45..ded09bc 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -625,7 +625,15 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
+ 	WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
+ 				(!nr_frags * TX_DMA_LS0)));
+ 
+-	netdev_sent_queue(dev, skb->len);
++	/* we have a single DMA ring so BQL needs to be updated for all devices
++	 * sitting on this ring
++	 */
++	for (i = 0; i < MTK_MAC_COUNT; i++) {
++		if (!eth->netdev[i])
++			continue;
++		netdev_sent_queue(dev, skb->len);
++	}
++
+ 	skb_tx_timestamp(skb);
+ 
+ 	ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
+@@ -853,21 +861,18 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
+ 	struct mtk_tx_dma *desc;
+ 	struct sk_buff *skb;
+ 	struct mtk_tx_buf *tx_buf;
+-	int total = 0, done[MTK_MAX_DEVS];
+-	unsigned int bytes[MTK_MAX_DEVS];
++	int total = 0, done = 0;
++	unsigned int bytes = 0;
+ 	u32 cpu, dma;
+ 	static int condition;
+ 	int i;
+ 
+-	memset(done, 0, sizeof(done));
+-	memset(bytes, 0, sizeof(bytes));
+-
+ 	cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
+ 	dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
+ 
+ 	desc = mtk_qdma_phys_to_virt(ring, cpu);
+ 
+-	while ((cpu != dma) && budget) {
++	while ((cpu != dma) && done < budget) {
+ 		u32 next_cpu = desc->txd2;
+ 		int mac;
+ 
+@@ -887,9 +892,8 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
+ 		}
+ 
+ 		if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
+-			bytes[mac] += skb->len;
+-			done[mac]++;
+-			budget--;
++			bytes += skb->len;
++			done++;
+ 		}
+ 		mtk_tx_unmap(eth->dev, tx_buf);
+ 
+@@ -902,13 +906,14 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
+ 
+ 	mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
+ 
++	/* we have a single DMA ring so BQL needs to be updated for all devices
++	 * sitting on this ring
++	 */
+ 	for (i = 0; i < MTK_MAC_COUNT; i++) {
+-		if (!eth->netdev[i] || !done[i])
++		if (!eth->netdev[i])
+ 			continue;
+-		netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
+-		total += done[i];
++		netdev_completed_queue(eth->netdev[i], done, bytes);
+ 	}
+-
+ 	/* read hw index again make sure no new tx packet */
+ 	if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
+ 		*tx_again = true;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0080-net-next-mediatek-fix-gigabit-and-flow-control-adver.patch

@@ -0,0 +1,59 @@
+From 46bfe9068a6e1594affeab30c206d2bd05c1e8f3 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Fri, 22 Apr 2016 11:05:23 +0200
+Subject: [PATCH 80/91] net-next: mediatek: fix gigabit and flow control
+ advertisement
+
+The current code will not setup the PHYs advertisement features correctly.
+Fix this and properly advertise Gigabit features and properly handle
+asymmetric pause frames.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |   16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index ded09bc..959d2cb 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -133,6 +133,8 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
+ static void mtk_phy_link_adjust(struct net_device *dev)
+ {
+ 	struct mtk_mac *mac = netdev_priv(dev);
++	u16 lcl_adv, rmt_adv = 0;
++	u8 flowctrl;
+ 	u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
+ 		  MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
+ 		  MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
+@@ -154,7 +156,16 @@ static void mtk_phy_link_adjust(struct net_device *dev)
+ 		mcr |= MAC_MCR_FORCE_DPX;
+ 
+ 	if (mac->phy_dev->pause)
+-		mcr |= MAC_MCR_FORCE_RX_FC | MAC_MCR_FORCE_TX_FC;
++		rmt_adv = LPA_PAUSE_CAP;
++	if (mac->phy_dev->asym_pause)
++		rmt_adv |= LPA_PAUSE_ASYM;
++
++	lcl_adv = mii_advertise_flowctrl(FLOW_CTRL_RX | FLOW_CTRL_TX);
++	flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
++	if (flowctrl & FLOW_CTRL_TX)
++		mcr |= MAC_MCR_FORCE_TX_FC;
++	if (flowctrl & FLOW_CTRL_RX)
++		mcr |= MAC_MCR_FORCE_RX_FC;
+ 
+ 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
+ 
+@@ -236,7 +247,8 @@ static int mtk_phy_connect(struct mtk_mac *mac)
+ 	mac->phy_dev->autoneg = AUTONEG_ENABLE;
+ 	mac->phy_dev->speed = 0;
+ 	mac->phy_dev->duplex = 0;
+-	mac->phy_dev->supported &= PHY_BASIC_FEATURES;
++	mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
++			           ~SUPPORTED_Asym_Pause;
+ 	mac->phy_dev->advertising = mac->phy_dev->supported |
+ 				    ADVERTISED_Autoneg;
+ 	phy_start_aneg(mac->phy_dev);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0081-net-next-mediatek-add-fixed-phy-support.patch

@@ -0,0 +1,32 @@
+From 3950bdb0a4e6fe45611e75fa4c92f3114e6729fd Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Fri, 22 Apr 2016 11:06:03 +0200
+Subject: [PATCH 81/91] net-next: mediatek: add fixed-phy support
+
+The MT7623 SoC has a builtin gigabit switch. If we want to use it, GMAC1
+needs to be configured using a fixed link speed and flow control settings.
+The easiest way to do this is to used the fixed-phy driver, allowing us to
+reuse the existing mdio polling code to setup the MAC.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 959d2cb..92c7886 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -219,6 +219,9 @@ static int mtk_phy_connect(struct mtk_mac *mac)
+ 	u32 val, ge_mode;
+ 
+ 	np = of_parse_phandle(mac->of_node, "phy-handle", 0);
++	if (!np && of_phy_is_fixed_link(mac->of_node))
++		if (!of_phy_register_fixed_link(mac->of_node))
++			np = of_node_get(mac->of_node);
+ 	if (!np)
+ 		return -ENODEV;
+ 
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0082-net-next-mediatek-add-RX-delay-support.patch

@@ -0,0 +1,29 @@
+From a4271fcf69eae0b10353600f75618ed760fad05b Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Fri, 22 Apr 2016 11:08:43 +0200
+Subject: [PATCH 82/91] net-next: mediatek: add RX delay support
+
+If an external Gigabit PHY is connected to either of the MACs we need to
+tell the to use a RX delay. Not doing so will result in heavy packet loss
+and/or data corruption of RX traffic.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 92c7886..674e8e3 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -226,6 +226,7 @@ static int mtk_phy_connect(struct mtk_mac *mac)
+ 		return -ENODEV;
+ 
+ 	switch (of_get_phy_mode(np)) {
++	case PHY_INTERFACE_MODE_RGMII_RXID:
+ 	case PHY_INTERFACE_MODE_RGMII:
+ 		ge_mode = 0;
+ 		break;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0083-net-next-mediatek-add-missing-return-code-check.patch

@@ -0,0 +1,30 @@
+From 2206de729d8a873898b983f5ff7633a2489aa71c Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Sat, 23 Apr 2016 09:06:05 +0200
+Subject: [PATCH 83/91] net-next: mediatek: add missing return code check
+
+The code fails to check if the scratch memory was properly allocated. Add
+this check and return with an error if the allocation failed.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 674e8e3..37e9260 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -483,6 +483,9 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
+ 
+ 	eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
+ 				    GFP_KERNEL);
++	if (unlikely(!eth->scratch_head))
++		return -ENOMEM;
++
+ 	dma_addr = dma_map_single(eth->dev,
+ 				  eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
+ 				  DMA_FROM_DEVICE);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0084-net-next-mediatek-fix-missing-free-of-scratch-memory.patch

@@ -0,0 +1,96 @@
+From 5207debf8825a8b6f2934b7d39ef76c163dfd794 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Sat, 23 Apr 2016 09:18:28 +0200
+Subject: [PATCH 84/91] net-next: mediatek: fix missing free of scratch memory
+
+Scratch memory gets allocated in mtk_init_fq_dma() but the corresponding
+code to free it is missing inside mtk_dma_free() causing a memory leak.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |   18 +++++++++++++-----
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |    2 ++
+ 2 files changed, 15 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 37e9260..6896d17 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -469,14 +469,14 @@ static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
+ /* the qdma core needs scratch memory to be setup */
+ static int mtk_init_fq_dma(struct mtk_eth *eth)
+ {
+-	dma_addr_t phy_ring_head, phy_ring_tail;
++	dma_addr_t phy_ring_tail;
+ 	int cnt = MTK_DMA_SIZE;
+ 	dma_addr_t dma_addr;
+ 	int i;
+ 
+ 	eth->scratch_ring = dma_alloc_coherent(eth->dev,
+ 					       cnt * sizeof(struct mtk_tx_dma),
+-					       &phy_ring_head,
++					       &eth->phy_scratch_ring,
+ 					       GFP_ATOMIC | __GFP_ZERO);
+ 	if (unlikely(!eth->scratch_ring))
+ 		return -ENOMEM;
+@@ -493,19 +493,19 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
+ 		return -ENOMEM;
+ 
+ 	memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
+-	phy_ring_tail = phy_ring_head +
++	phy_ring_tail = eth->phy_scratch_ring +
+ 			(sizeof(struct mtk_tx_dma) * (cnt - 1));
+ 
+ 	for (i = 0; i < cnt; i++) {
+ 		eth->scratch_ring[i].txd1 =
+ 					(dma_addr + (i * MTK_QDMA_PAGE_SIZE));
+ 		if (i < cnt - 1)
+-			eth->scratch_ring[i].txd2 = (phy_ring_head +
++			eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
+ 				((i + 1) * sizeof(struct mtk_tx_dma)));
+ 		eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
+ 	}
+ 
+-	mtk_w32(eth, phy_ring_head, MTK_QDMA_FQ_HEAD);
++	mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
+ 	mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
+ 	mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
+ 	mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
+@@ -1203,6 +1203,14 @@ static void mtk_dma_free(struct mtk_eth *eth)
+ 	for (i = 0; i < MTK_MAC_COUNT; i++)
+ 		if (eth->netdev[i])
+ 			netdev_reset_queue(eth->netdev[i]);
++	if (eth->scratch_ring) {
++		dma_free_coherent(eth->dev,
++				  MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
++				  eth->scratch_ring,
++				  eth->phy_scratch_ring);
++		eth->scratch_ring = NULL;
++		eth->phy_scratch_ring = 0;
++	}
+ 	mtk_tx_clean(eth);
+ 	mtk_rx_clean(eth);
+ 	kfree(eth->scratch_head);
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+index eed626d..57f7e8a 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -357,6 +357,7 @@ struct mtk_rx_ring {
+  * @rx_ring:		Pointer to the memore holding info about the RX ring
+  * @rx_napi:		The NAPI struct
+  * @scratch_ring:	Newer SoCs need memory for a second HW managed TX ring
++ * @phy_scratch_ring:	physical address of scratch_ring
+  * @scratch_head:	The scratch memory that scratch_ring points to.
+  * @clk_ethif:		The ethif clock
+  * @clk_esw:		The switch clock
+@@ -384,6 +385,7 @@ struct mtk_eth {
+ 	struct mtk_rx_ring		rx_ring;
+ 	struct napi_struct		rx_napi;
+ 	struct mtk_tx_dma		*scratch_ring;
++	dma_addr_t			phy_scratch_ring;
+ 	void				*scratch_head;
+ 	struct clk			*clk_ethif;
+ 	struct clk			*clk_esw;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0085-net-next-mediatek-invalid-buffer-lookup-in-mtk_tx_ma.patch

@@ -0,0 +1,30 @@
+From e58c3912f08f71d9c3e2b09548c96dca8f6ea9d8 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Sat, 23 Apr 2016 09:25:00 +0200
+Subject: [PATCH 85/91] net-next: mediatek: invalid buffer lookup in
+ mtk_tx_map()
+
+The lookup of the tx_buffer in the error path inside mtk_tx_map() uses the
+wrong descriptor pointer. This looks like a copy & paste error.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 6896d17..2a4bbbb 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -670,7 +670,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
+ 
+ err_dma:
+ 	do {
+-		tx_buf = mtk_desc_to_tx_buf(ring, txd);
++		tx_buf = mtk_desc_to_tx_buf(ring, itxd);
+ 
+ 		/* unmap dma */
+ 		mtk_tx_unmap(&dev->dev, tx_buf);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0086-net-next-mediatek-dropped-rx-packets-are-not-being-c.patch

@@ -0,0 +1,38 @@
+From 78579ebd671ebdffdaa4691a0e91acd36f691575 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Sat, 23 Apr 2016 09:28:25 +0200
+Subject: [PATCH 86/91] net-next: mediatek: dropped rx packets are not being
+ counted properly
+
+There are 2 places inside mtk_poll_rx where rx_dropped is not being
+incremented properly. Fix this by adding the missing code to increment
+the counter.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 2a4bbbb..679cefd 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -825,6 +825,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
+ 					  DMA_FROM_DEVICE);
+ 		if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
+ 			skb_free_frag(new_data);
++			netdev->stats.rx_dropped++;
+ 			goto release_desc;
+ 		}
+ 
+@@ -832,6 +833,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
+ 		skb = build_skb(data, ring->frag_size);
+ 		if (unlikely(!skb)) {
+ 			put_page(virt_to_head_page(new_data));
++			netdev->stats.rx_dropped++;
+ 			goto release_desc;
+ 		}
+ 		skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0087-net-next-mediatek-add-IRQ-locking.patch

@@ -0,0 +1,74 @@
+From 8aa53beda6ad6c8154e4f7b8a7ca9815412fa95a Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Wed, 20 Apr 2016 16:18:07 +0200
+Subject: [PATCH 87/91] net-next: mediatek: add IRQ locking
+
+The code that enables and disables IRQs is missing proper locking. After
+adding the IRQ separation patch and routing the putting the RX and TX IRQs
+on different cores we experienced IRQ stalls. Fix this by adding proper
+locking. We use a dedicated lock to reduce the latency if the IRQ code.
+Otherwise it might wait for bottom code to finish before reenabling or
+disabling IRQs.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    7 +++++++
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |    1 +
+ 2 files changed, 8 insertions(+)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 679cefd..f821820 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -316,22 +316,28 @@ static void mtk_mdio_cleanup(struct mtk_eth *eth)
+ 
+ static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
+ {
++	unsigned long flags;
+ 	u32 val;
+ 
++	spin_lock_irqsave(&eth->irq_lock, flags);
+ 	val = mtk_r32(eth, MTK_QDMA_INT_MASK);
+ 	mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
+ 	/* flush write */
+ 	mtk_r32(eth, MTK_QDMA_INT_MASK);
++	spin_unlock_irqrestore(&eth->irq_lock, flags);
+ }
+ 
+ static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
+ {
++	unsigned long flags;
+ 	u32 val;
+ 
++	spin_lock_irqsave(&eth->irq_lock, flags);
+ 	val = mtk_r32(eth, MTK_QDMA_INT_MASK);
+ 	mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
+ 	/* flush write */
+ 	mtk_r32(eth, MTK_QDMA_INT_MASK);
++	spin_unlock_irqrestore(&eth->irq_lock, flags);
+ }
+ 
+ static int mtk_set_mac_address(struct net_device *dev, void *p)
+@@ -1750,6 +1756,7 @@ static int mtk_probe(struct platform_device *pdev)
+ 		return -EADDRNOTAVAIL;
+ 
+ 	spin_lock_init(&eth->page_lock);
++	spin_lock_init(&eth->irq_lock);
+ 
+ 	eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ 						      "mediatek,ethsys");
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+index 57f7e8a..8220275 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -372,6 +372,7 @@ struct mtk_eth {
+ 	void __iomem			*base;
+ 	struct reset_control		*rstc;
+ 	spinlock_t			page_lock;
++	spinlock_t			irq_lock;
+ 	struct net_device		dummy_dev;
+ 	struct net_device		*netdev[MTK_MAX_DEVS];
+ 	struct mtk_mac			*mac[MTK_MAX_DEVS];
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0088-net-next-mediatek-add-support-for-IRQ-grouping.patch

@@ -0,0 +1,403 @@
+From f43e3aaaacaaf0482f0aaa6fbad03572f3a0c614 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Wed, 23 Mar 2016 18:31:48 +0100
+Subject: [PATCH 88/91] net-next: mediatek: add support for IRQ grouping
+
+The ethernet core has 3 IRQs. using the IRQ grouping registers we are able
+to separate TX and RX IRQs, which allows us to service them on separate
+cores. This patch splits the irq handler into 2 separate functiosn, one for
+TX and another for RX. The TX housekeeping is split out of the NAPI handler.
+Instead we use a tasklet to handle housekeeping.
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |  165 ++++++++++++++++++---------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |   16 ++-
+ 2 files changed, 125 insertions(+), 56 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index f821820..b5e364c 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -789,7 +789,7 @@ drop:
+ }
+ 
+ static int mtk_poll_rx(struct napi_struct *napi, int budget,
+-		       struct mtk_eth *eth, u32 rx_intr)
++		       struct mtk_eth *eth)
+ {
+ 	struct mtk_rx_ring *ring = &eth->rx_ring;
+ 	int idx = ring->calc_idx;
+@@ -877,19 +877,18 @@ release_desc:
+ 	}
+ 
+ 	if (done < budget)
+-		mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS);
++		mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
+ 
+ 	return done;
+ }
+ 
+-static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
++static int mtk_poll_tx(struct mtk_eth *eth, int budget)
+ {
+ 	struct mtk_tx_ring *ring = &eth->tx_ring;
+ 	struct mtk_tx_dma *desc;
+ 	struct sk_buff *skb;
+ 	struct mtk_tx_buf *tx_buf;
+-	int total = 0, done = 0;
+-	unsigned int bytes = 0;
++	unsigned int bytes = 0, done = 0;
+ 	u32 cpu, dma;
+ 	static int condition;
+ 	int i;
+@@ -941,64 +940,82 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
+ 			continue;
+ 		netdev_completed_queue(eth->netdev[i], done, bytes);
+ 	}
++
+ 	/* read hw index again make sure no new tx packet */
+-	if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
+-		*tx_again = true;
+-	else
++	if (cpu == dma && cpu == mtk_r32(eth, MTK_QTX_DRX_PTR))
+ 		mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
+ 
+-	if (!total)
+-		return 0;
+-
+ 	if (atomic_read(&ring->free_count) > ring->thresh)
+ 		mtk_wake_queue(eth);
+ 
+-	return total;
++	return done;
+ }
+ 
+-static int mtk_poll(struct napi_struct *napi, int budget)
++static void mtk_handle_status_irq(struct mtk_eth *eth)
+ {
+-	struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
+-	u32 status, status2, mask, tx_intr, rx_intr, status_intr;
+-	int tx_done, rx_done;
+-	bool tx_again = false;
+-
+-	status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
+-	status2 = mtk_r32(eth, MTK_INT_STATUS2);
+-	tx_intr = MTK_TX_DONE_INT;
+-	rx_intr = MTK_RX_DONE_INT;
+-	status_intr = (MTK_GDM1_AF | MTK_GDM2_AF);
+-	tx_done = 0;
+-	rx_done = 0;
+-	tx_again = 0;
+-
+-	if (status & tx_intr)
+-		tx_done = mtk_poll_tx(eth, budget, &tx_again);
+-
+-	if (status & rx_intr)
+-		rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
++	u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
++	u32 status_intr = (MTK_GDM1_AF | MTK_GDM2_AF);
+ 
+ 	if (unlikely(status2 & status_intr)) {
+ 		mtk_stats_update(eth);
+ 		mtk_w32(eth, status_intr, MTK_INT_STATUS2);
+ 	}
++}
++
++static int mtk_napi_tx(struct napi_struct *napi, int budget)
++{
++	struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
++	u32 status, mask;
++	int tx_done = 0;
++
++	mtk_handle_status_irq(eth);
++
++	status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
++	tx_done = mtk_poll_tx(eth, budget);
++	if (unlikely(netif_msg_intr(eth))) {
++		mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
++		dev_info(eth->dev,
++			 "done tx %d, intr 0x%08x/0x%x\n",
++			 tx_done, status, mask);
++	}
++
++	if (tx_done == budget)
++		return budget;
++
++	status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
++	if (status & MTK_TX_DONE_INT)
++		return budget;
++
++	napi_complete(napi);
++	mtk_irq_enable(eth, MTK_TX_DONE_INT);
++
++	return tx_done;
++}
++
++static int mtk_napi_rx(struct napi_struct *napi, int budget)
++{
++	struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
++	u32 status, mask;
++	int rx_done = 0;
+ 
++	status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
++	rx_done = mtk_poll_rx(napi, budget, eth);
+ 	if (unlikely(netif_msg_intr(eth))) {
+ 		mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
+-		netdev_info(eth->netdev[0],
+-			    "done tx %d, rx %d, intr 0x%08x/0x%x\n",
+-			    tx_done, rx_done, status, mask);
++		dev_info(eth->dev,
++			 "done rx %d, intr 0x%08x/0x%x\n",
++			 rx_done, status, mask);
+ 	}
+ 
+-	if (tx_again || rx_done == budget)
++	if (rx_done == budget)
+ 		return budget;
+ 
+ 	status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
+-	if (status & (tx_intr | rx_intr))
++	if (status & MTK_RX_DONE_INT)
+ 		return budget;
+ 
+ 	napi_complete(napi);
+-	mtk_irq_enable(eth, tx_intr | rx_intr);
++	mtk_irq_enable(eth, MTK_RX_DONE_INT);
+ 
+ 	return rx_done;
+ }
+@@ -1235,22 +1252,44 @@ static void mtk_tx_timeout(struct net_device *dev)
+ 	schedule_work(&eth->pending_work);
+ }
+ 
+-static irqreturn_t mtk_handle_irq(int irq, void *_eth)
++static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
+ {
+ 	struct mtk_eth *eth = _eth;
+ 	u32 status;
+ 
+ 	status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
++	status &= ~MTK_TX_DONE_INT;
++
+ 	if (unlikely(!status))
+ 		return IRQ_NONE;
+ 
+-	if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) {
++	if (status & MTK_RX_DONE_INT) {
+ 		if (likely(napi_schedule_prep(&eth->rx_napi)))
+ 			__napi_schedule(&eth->rx_napi);
+-	} else {
+-		mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
++		mtk_irq_disable(eth, MTK_RX_DONE_INT);
+ 	}
+-	mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT));
++	mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
++{
++	struct mtk_eth *eth = _eth;
++	u32 status;
++
++	status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
++	status &= ~MTK_RX_DONE_INT;
++
++	if (unlikely(!status))
++		return IRQ_NONE;
++
++	if (status & MTK_TX_DONE_INT) {
++		if (likely(napi_schedule_prep(&eth->tx_napi)))
++			__napi_schedule(&eth->tx_napi);
++		mtk_irq_disable(eth, MTK_TX_DONE_INT);
++	}
++	mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
+ 
+ 	return IRQ_HANDLED;
+ }
+@@ -1263,7 +1302,7 @@ static void mtk_poll_controller(struct net_device *dev)
+ 	u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
+ 
+ 	mtk_irq_disable(eth, int_mask);
+-	mtk_handle_irq(dev->irq, dev);
++	mtk_handle_irq(dev->irq[0], dev);
+ 	mtk_irq_enable(eth, int_mask);
+ }
+ #endif
+@@ -1299,6 +1338,7 @@ static int mtk_open(struct net_device *dev)
+ 		if (err)
+ 			return err;
+ 
++		napi_enable(&eth->tx_napi);
+ 		napi_enable(&eth->rx_napi);
+ 		mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
+ 	}
+@@ -1347,6 +1387,7 @@ static int mtk_stop(struct net_device *dev)
+ 		return 0;
+ 
+ 	mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
++	napi_disable(&eth->tx_napi);
+ 	napi_disable(&eth->rx_napi);
+ 
+ 	mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
+@@ -1384,7 +1425,11 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
+ 	/* Enable RX VLan Offloading */
+ 	mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
+ 
+-	err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
++	err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
++			       dev_name(eth->dev), eth);
++	if (err)
++		return err;
++	err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
+ 			       dev_name(eth->dev), eth);
+ 	if (err)
+ 		return err;
+@@ -1400,7 +1445,11 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
+ 	mtk_w32(eth, 0, MTK_RST_GL);
+ 
+ 	/* FE int grouping */
+-	mtk_w32(eth, 0, MTK_FE_INT_GRP);
++	mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
++	mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
++	mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
++	mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
++	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+ 
+ 	for (i = 0; i < 2; i++) {
+ 		u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
+@@ -1448,7 +1497,9 @@ static void mtk_uninit(struct net_device *dev)
+ 	phy_disconnect(mac->phy_dev);
+ 	mtk_mdio_cleanup(eth);
+ 	mtk_irq_disable(eth, ~0);
+-	free_irq(dev->irq, dev);
++	free_irq(eth->irq[0], dev);
++	free_irq(eth->irq[1], dev);
++	free_irq(eth->irq[2], dev);
+ }
+ 
+ static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+@@ -1723,10 +1774,10 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+ 		dev_err(eth->dev, "error bringing up device\n");
+ 		goto free_netdev;
+ 	}
+-	eth->netdev[id]->irq = eth->irq;
++	eth->netdev[id]->irq = eth->irq[0];
+ 	netif_info(eth, probe, eth->netdev[id],
+ 		   "mediatek frame engine at 0x%08lx, irq %d\n",
+-		   eth->netdev[id]->base_addr, eth->netdev[id]->irq);
++		   eth->netdev[id]->base_addr, eth->irq[0]);
+ 
+ 	return 0;
+ 
+@@ -1743,6 +1794,7 @@ static int mtk_probe(struct platform_device *pdev)
+ 	struct mtk_soc_data *soc;
+ 	struct mtk_eth *eth;
+ 	int err;
++	int i;
+ 
+ 	match = of_match_device(of_mtk_match, &pdev->dev);
+ 	soc = (struct mtk_soc_data *)match->data;
+@@ -1778,10 +1830,12 @@ static int mtk_probe(struct platform_device *pdev)
+ 		return PTR_ERR(eth->rstc);
+ 	}
+ 
+-	eth->irq = platform_get_irq(pdev, 0);
+-	if (eth->irq < 0) {
+-		dev_err(&pdev->dev, "no IRQ resource found\n");
+-		return -ENXIO;
++	for (i = 0; i < 3; i++) {
++		eth->irq[i] = platform_get_irq(pdev, i);
++		if (eth->irq[i] < 0) {
++			dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
++			return -ENXIO;
++		}
+ 	}
+ 
+ 	eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
+@@ -1822,7 +1876,9 @@ static int mtk_probe(struct platform_device *pdev)
+ 	 * for NAPI to work
+ 	 */
+ 	init_dummy_netdev(&eth->dummy_dev);
+-	netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_poll,
++	netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
++		       MTK_NAPI_WEIGHT);
++	netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
+ 		       MTK_NAPI_WEIGHT);
+ 
+ 	platform_set_drvdata(pdev, eth);
+@@ -1843,6 +1899,7 @@ static int mtk_remove(struct platform_device *pdev)
+ 	clk_disable_unprepare(eth->clk_gp1);
+ 	clk_disable_unprepare(eth->clk_gp2);
+ 
++	netif_napi_del(&eth->tx_napi);
+ 	netif_napi_del(&eth->rx_napi);
+ 	mtk_cleanup(eth);
+ 	platform_set_drvdata(pdev, NULL);
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+index 8220275..bf158f8 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -68,6 +68,10 @@
+ /* Unicast Filter MAC Address Register - High */
+ #define MTK_GDMA_MAC_ADRH(x)	(0x50C + (x * 0x1000))
+ 
++/* PDMA Interrupt grouping registers */
++#define MTK_PDMA_INT_GRP1	0xa50
++#define MTK_PDMA_INT_GRP2	0xa54
++
+ /* QDMA TX Queue Configuration Registers */
+ #define MTK_QTX_CFG(x)		(0x1800 + (x * 0x10))
+ #define QDMA_RES_THRES		4
+@@ -124,6 +128,11 @@
+ #define MTK_TX_DONE_INT		(MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
+ 				 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
+ 
++/* QDMA Interrupt grouping registers */
++#define MTK_QDMA_INT_GRP1	0x1a20
++#define MTK_QDMA_INT_GRP2	0x1a24
++#define MTK_RLS_DONE_INT	BIT(0)
++
+ /* QDMA Interrupt Status Register */
+ #define MTK_QDMA_INT_MASK	0x1A1C
+ 
+@@ -355,7 +364,8 @@ struct mtk_rx_ring {
+  * @dma_refcnt:		track how many netdevs are using the DMA engine
+  * @tx_ring:		Pointer to the memore holding info about the TX ring
+  * @rx_ring:		Pointer to the memore holding info about the RX ring
+- * @rx_napi:		The NAPI struct
++ * @tx_napi:		The TX NAPI struct
++ * @rx_napi:		The RX NAPI struct
+  * @scratch_ring:	Newer SoCs need memory for a second HW managed TX ring
+  * @phy_scratch_ring:	physical address of scratch_ring
+  * @scratch_head:	The scratch memory that scratch_ring points to.
+@@ -376,7 +386,7 @@ struct mtk_eth {
+ 	struct net_device		dummy_dev;
+ 	struct net_device		*netdev[MTK_MAX_DEVS];
+ 	struct mtk_mac			*mac[MTK_MAX_DEVS];
+-	int				irq;
++	int				irq[3];
+ 	u32				msg_enable;
+ 	unsigned long			sysclk;
+ 	struct regmap			*ethsys;
+@@ -384,6 +394,7 @@ struct mtk_eth {
+ 	atomic_t			dma_refcnt;
+ 	struct mtk_tx_ring		tx_ring;
+ 	struct mtk_rx_ring		rx_ring;
++	struct napi_struct		tx_napi;
+ 	struct napi_struct		rx_napi;
+ 	struct mtk_tx_dma		*scratch_ring;
+ 	dma_addr_t			phy_scratch_ring;
+@@ -394,6 +405,7 @@ struct mtk_eth {
+ 	struct clk			*clk_gp2;
+ 	struct mii_bus			*mii_bus;
+ 	struct work_struct		pending_work;
++
+ };
+ 
+ /* struct mtk_mac -	the structure that holds the info about the MACs of the
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0089-net-mediatek-add-gsw-mt7530-driver.patch

@@ -0,0 +1,2377 @@
+From 4c23129f65d9bac10d9cf88c45fced58597400e6 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Mon, 11 Apr 2016 03:11:54 +0200
+Subject: [PATCH 89/91] net: mediatek add gsw/mt7530 driver
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/Makefile      |    2 +-
+ drivers/net/ethernet/mediatek/gsw_mt7620.h  |  251 +++++++
+ drivers/net/ethernet/mediatek/gsw_mt7623.c  | 1081 +++++++++++++++++++++++++++
+ drivers/net/ethernet/mediatek/mt7530.c      |  808 ++++++++++++++++++++
+ drivers/net/ethernet/mediatek/mt7530.h      |   20 +
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |   59 +-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |    4 +
+ 7 files changed, 2195 insertions(+), 30 deletions(-)
+ create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.h
+ create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7623.c
+ create mode 100644 drivers/net/ethernet/mediatek/mt7530.c
+ create mode 100644 drivers/net/ethernet/mediatek/mt7530.h
+
+diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile
+index aa3f1c8..82001c4 100644
+--- a/drivers/net/ethernet/mediatek/Makefile
++++ b/drivers/net/ethernet/mediatek/Makefile
+@@ -2,4 +2,4 @@
+ # Makefile for the Mediatek SoCs built-in ethernet macs
+ #
+ 
+-obj-$(CONFIG_NET_MEDIATEK_SOC)			+= mtk_eth_soc.o
++obj-$(CONFIG_NET_MEDIATEK_SOC)			+= mt7530.o gsw_mt7623.o mtk_eth_soc.o
+diff --git a/drivers/net/ethernet/mediatek/gsw_mt7620.h b/drivers/net/ethernet/mediatek/gsw_mt7620.h
+new file mode 100644
+index 0000000..6fca8f2
+--- /dev/null
++++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
+@@ -0,0 +1,251 @@
++/*   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   Copyright (C) 2009-2016 John Crispin <[email protected]>
++ *   Copyright (C) 2009-2016 Felix Fietkau <[email protected]>
++ *   Copyright (C) 2013-2016 Michael Lee <[email protected]>
++ */
++
++#ifndef _RALINK_GSW_MT7620_H__
++#define _RALINK_GSW_MT7620_H__
++
++#define GSW_REG_PHY_TIMEOUT	(5 * HZ)
++
++#define MT7620_GSW_REG_PIAC	0x0004
++
++#define GSW_NUM_VLANS		16
++#define GSW_NUM_VIDS		4096
++#define GSW_NUM_PORTS		7
++#define GSW_PORT6		6
++
++#define GSW_MDIO_ACCESS		BIT(31)
++#define GSW_MDIO_READ		BIT(19)
++#define GSW_MDIO_WRITE		BIT(18)
++#define GSW_MDIO_START		BIT(16)
++#define GSW_MDIO_ADDR_SHIFT	20
++#define GSW_MDIO_REG_SHIFT	25
++
++#define GSW_REG_PORT_PMCR(x)	(0x3000 + (x * 0x100))
++#define GSW_REG_PORT_STATUS(x)	(0x3008 + (x * 0x100))
++#define GSW_REG_SMACCR0		0x3fE4
++#define GSW_REG_SMACCR1		0x3fE8
++#define GSW_REG_CKGCR		0x3ff0
++
++#define GSW_REG_IMR		0x7008
++#define GSW_REG_ISR		0x700c
++#define GSW_REG_GPC1		0x7014
++
++#define SYSC_REG_CHIP_REV_ID	0x0c
++#define SYSC_REG_CFG		0x10
++#define SYSC_REG_CFG1		0x14
++#define RST_CTRL_MCM		BIT(2)
++#define SYSC_PAD_RGMII2_MDIO	0x58
++#define SYSC_GPIO_MODE		0x60
++
++#define PORT_IRQ_ST_CHG		0x7f
++
++#define MT7621_ESW_PHY_POLLING	0x0000
++#define MT7620_ESW_PHY_POLLING	0x7000
++
++#define	PMCR_IPG		BIT(18)
++#define	PMCR_MAC_MODE		BIT(16)
++#define	PMCR_FORCE		BIT(15)
++#define	PMCR_TX_EN		BIT(14)
++#define	PMCR_RX_EN		BIT(13)
++#define	PMCR_BACKOFF		BIT(9)
++#define	PMCR_BACKPRES		BIT(8)
++#define	PMCR_RX_FC		BIT(5)
++#define	PMCR_TX_FC		BIT(4)
++#define	PMCR_SPEED(_x)		(_x << 2)
++#define	PMCR_DUPLEX		BIT(1)
++#define	PMCR_LINK		BIT(0)
++
++#define PHY_AN_EN		BIT(31)
++#define PHY_PRE_EN		BIT(30)
++#define PMY_MDC_CONF(_x)	((_x & 0x3f) << 24)
++
++/* ethernet subsystem config register */
++#define ETHSYS_SYSCFG0		0x14
++/* ethernet subsystem clock register */
++#define ETHSYS_CLKCFG0		0x2c
++#define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
++
++/* p5 RGMII wrapper TX clock control register */
++#define MT7530_P5RGMIITXCR	0x7b04
++/* p5 RGMII wrapper RX clock control register */
++#define MT7530_P5RGMIIRXCR	0x7b00
++/* TRGMII TDX ODT registers */
++#define MT7530_TRGMII_TD0_ODT	0x7a54
++#define MT7530_TRGMII_TD1_ODT	0x7a5c
++#define MT7530_TRGMII_TD2_ODT	0x7a64
++#define MT7530_TRGMII_TD3_ODT	0x7a6c
++#define MT7530_TRGMII_TD4_ODT	0x7a74
++#define MT7530_TRGMII_TD5_ODT	0x7a7c
++/* TRGMII TCK ctrl register */
++#define MT7530_TRGMII_TCK_CTRL	0x7a78
++/* TRGMII Tx ctrl register */
++#define MT7530_TRGMII_TXCTRL	0x7a40
++/* port 6 extended control register */
++#define MT7530_P6ECR            0x7830
++/* IO driver control register */
++#define MT7530_IO_DRV_CR	0x7810
++/* top signal control register */
++#define MT7530_TOP_SIG_CTRL	0x7808
++/* modified hwtrap register */
++#define MT7530_MHWTRAP		0x7804
++/* hwtrap status register */
++#define MT7530_HWTRAP		0x7800
++/* status interrupt register */
++#define MT7530_SYS_INT_STS	0x700c
++/* system nterrupt register */
++#define MT7530_SYS_INT_EN	0x7008
++/* system control register */
++#define MT7530_SYS_CTRL		0x7000
++/* port MAC status register */
++#define MT7530_PMSR_P(x)	(0x3008 + (x * 0x100))
++/* port MAC control register */
++#define MT7530_PMCR_P(x)	(0x3000 + (x * 0x100))
++
++#define MT7621_XTAL_SHIFT	6
++#define MT7621_XTAL_MASK	0x7
++#define MT7621_XTAL_25		6
++#define MT7621_XTAL_40		3
++#define MT7621_MDIO_DRV_MASK	(3 << 4)
++#define MT7621_GE1_MODE_MASK	(3 << 12)
++
++#define TRGMII_TXCTRL_TXC_INV	BIT(30)
++#define P6ECR_INTF_MODE_RGMII	BIT(1)
++#define P5RGMIIRXCR_C_ALIGN	BIT(8)
++#define P5RGMIIRXCR_DELAY_2	BIT(1)
++#define P5RGMIITXCR_DELAY_2	(BIT(8) | BIT(2))
++
++/* TOP_SIG_CTRL bits */
++#define TOP_SIG_CTRL_NORMAL	(BIT(17) | BIT(16))
++
++/* MHWTRAP bits */
++#define MHWTRAP_MANUAL		BIT(16)
++#define MHWTRAP_P5_MAC_SEL	BIT(13)
++#define MHWTRAP_P6_DIS		BIT(8)
++#define MHWTRAP_P5_RGMII_MODE	BIT(7)
++#define MHWTRAP_P5_DIS		BIT(6)
++#define MHWTRAP_PHY_ACCESS	BIT(5)
++
++/* HWTRAP bits */
++#define HWTRAP_XTAL_SHIFT	9
++#define HWTRAP_XTAL_MASK	0x3
++
++/* SYS_CTRL bits */
++#define SYS_CTRL_SW_RST		BIT(1)
++#define SYS_CTRL_REG_RST	BIT(0)
++
++/* PMCR bits */
++#define PMCR_IFG_XMIT_96	BIT(18)
++#define PMCR_MAC_MODE		BIT(16)
++#define PMCR_FORCE_MODE		BIT(15)
++#define PMCR_TX_EN		BIT(14)
++#define PMCR_RX_EN		BIT(13)
++#define PMCR_BACK_PRES_EN	BIT(9)
++#define PMCR_BACKOFF_EN		BIT(8)
++#define PMCR_TX_FC_EN		BIT(5)
++#define PMCR_RX_FC_EN		BIT(4)
++#define PMCR_FORCE_SPEED_1000	BIT(3)
++#define PMCR_FORCE_FDX		BIT(1)
++#define PMCR_FORCE_LNK		BIT(0)
++#define PMCR_FIXED_LINK		(PMCR_IFG_XMIT_96 | PMCR_MAC_MODE | \
++				 PMCR_FORCE_MODE | PMCR_TX_EN | PMCR_RX_EN | \
++				 PMCR_BACK_PRES_EN | PMCR_BACKOFF_EN | \
++				 PMCR_FORCE_SPEED_1000 | PMCR_FORCE_FDX | \
++				 PMCR_FORCE_LNK)
++
++#define PMCR_FIXED_LINK_FC	(PMCR_FIXED_LINK | \
++				 PMCR_TX_FC_EN | PMCR_RX_FC_EN)
++
++/* TRGMII control registers */
++#define GSW_INTF_MODE		0x390
++#define GSW_TRGMII_TD0_ODT	0x354
++#define GSW_TRGMII_TD1_ODT	0x35c
++#define GSW_TRGMII_TD2_ODT	0x364
++#define GSW_TRGMII_TD3_ODT	0x36c
++#define GSW_TRGMII_TXCTL_ODT	0x374
++#define GSW_TRGMII_TCK_ODT	0x37c
++#define GSW_TRGMII_RCK_CTRL	0x300
++
++#define INTF_MODE_TRGMII	BIT(1)
++#define TRGMII_RCK_CTRL_RX_RST	BIT(31)
++
++
++/* possible XTAL speed */
++#define	MT7623_XTAL_40		0
++#define MT7623_XTAL_20		1
++#define MT7623_XTAL_25		3
++
++/* GPIO port control registers */
++#define	GPIO_OD33_CTRL8		0x4c0
++#define	GPIO_BIAS_CTRL		0xed0
++#define GPIO_DRV_SEL10		0xf00
++
++/* on MT7620 the functio of port 4 can be software configured */
++enum {
++	PORT4_EPHY = 0,
++	PORT4_EXT,
++};
++
++/* struct mt7620_gsw -	the structure that holds the SoC specific data
++ * @dev:		The Device struct
++ * @base:		The base address
++ * @piac_offset:	The PIAC base may change depending on SoC
++ * @irq:		The IRQ we are using
++ * @port4:		The port4 mode on MT7620
++ * @autopoll:		Is MDIO autopolling enabled
++ * @ethsys:		The ethsys register map
++ * @pctl:		The pin control register map
++ * @clk_trgpll:		The trgmii pll clock
++ */
++struct mt7620_gsw {
++	struct mtk_eth		*eth;
++	struct device		*dev;
++	void __iomem		*base;
++	u32			piac_offset;
++	int			irq;
++	int			port4;
++	unsigned long int	autopoll;
++
++	struct regmap		*ethsys;
++	struct regmap		*pctl;
++
++	struct clk		*clk_trgpll;
++
++	int			trgmii_force;
++	bool			wllll;
++};
++
++/* switch register I/O wrappers */
++void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
++u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
++
++/* the callback used by the driver core to bringup the switch */
++int mtk_gsw_init(struct mtk_eth *eth);
++
++/* MDIO access wrappers */
++int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
++int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
++void mt7620_mdio_link_adjust(struct mtk_eth *eth, int port);
++int mt7620_has_carrier(struct mtk_eth *eth);
++void mt7620_print_link_state(struct mtk_eth *eth, int port, int link,
++			     int speed, int duplex);
++void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
++u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
++void mt7530_mdio_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, u32 reg);
++
++u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
++		      u32 phy_register, u32 write_data);
++u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg);
++void mt7620_handle_carrier(struct mtk_eth *eth);
++
++#endif
+diff --git a/drivers/net/ethernet/mediatek/gsw_mt7623.c b/drivers/net/ethernet/mediatek/gsw_mt7623.c
+new file mode 100644
+index 0000000..28df15a
+--- /dev/null
++++ b/drivers/net/ethernet/mediatek/gsw_mt7623.c
+@@ -0,0 +1,1081 @@
++/*   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   Copyright (C) 2009-2016 John Crispin <[email protected]>
++ *   Copyright (C) 2009-2016 Felix Fietkau <[email protected]>
++ *   Copyright (C) 2013-2016 Michael Lee <[email protected]>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/platform_device.h>
++#include <linux/of_device.h>
++#include <linux/of_irq.h>
++#include <linux/of_gpio.h>
++#include <linux/of_mdio.h>
++#include <linux/clk.h>
++#include <linux/mfd/syscon.h>
++#include <linux/regulator/consumer.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/mii.h>
++#include <linux/interrupt.h>
++#include <linux/netdevice.h>
++#include <linux/dma-mapping.h>
++#include <linux/phy.h>
++#include <linux/ethtool.h>
++#include <linux/version.h>
++#include <linux/atomic.h>
++
++#include "mtk_eth_soc.h"
++#include "gsw_mt7620.h"
++#include "mt7530.h"
++
++#define ETHSYS_CLKCFG0			0x2c
++#define ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
++
++void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
++{
++	_mtk_mdio_write(gsw->eth, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
++	_mtk_mdio_write(gsw->eth, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
++	_mtk_mdio_write(gsw->eth, 0x1f, 0x10, val >> 16);
++}
++
++u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
++{
++	u16 high, low;
++
++	_mtk_mdio_write(gsw->eth, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
++	low = _mtk_mdio_read(gsw->eth, 0x1f, (reg >> 2) & 0xf);
++	high = _mtk_mdio_read(gsw->eth, 0x1f, 0x10);
++
++	return (high << 16) | (low & 0xffff);
++}
++
++void mt7530_mdio_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, u32 reg)
++{
++	u32 val = mt7530_mdio_r32(gsw, reg);
++
++	val &= mask;
++	val |= set;
++	mt7530_mdio_w32(gsw, reg, val);
++}
++
++void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
++{
++	mtk_w32(gsw->eth, val, reg + 0x10000);
++}
++
++u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
++{
++	return mtk_r32(gsw->eth, reg + 0x10000);
++}
++
++void mtk_switch_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, unsigned reg)
++{
++	u32 val = mtk_switch_r32(gsw, reg);
++
++	val &= mask;
++	val |= set;
++
++	mtk_switch_w32(gsw, val, reg);
++}
++
++int mt7623_gsw_config(struct mtk_eth *eth)
++{
++	if (eth->mii_bus && eth->mii_bus->phy_map[0x1f])
++		mt7530_probe(eth->dev, NULL, eth->mii_bus, 1);
++
++	return 0;
++}
++
++static irqreturn_t gsw_interrupt_mt7623(int irq, void *_eth)
++{
++	struct mtk_eth *eth = (struct mtk_eth *)_eth;
++	struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
++	u32 reg, i;
++
++	reg = mt7530_mdio_r32(gsw, 0x700c);
++
++	for (i = 0; i < 5; i++)
++		if (reg & BIT(i)) {
++			unsigned int link;
++
++			link = mt7530_mdio_r32(gsw,
++					       0x3008 + (i * 0x100)) & 0x1;
++
++			if (link)
++				dev_info(gsw->dev,
++					 "port %d link up\n", i);
++			else
++				dev_info(gsw->dev,
++					 "port %d link down\n", i);
++		}
++
++//	mt7620_handle_carrier(eth);
++	mt7530_mdio_w32(gsw, 0x700c, 0x1f);
++
++	return IRQ_HANDLED;
++}
++
++static void wait_loop(struct mt7620_gsw *gsw)
++{
++	int i;
++	int read_data;
++
++	for (i = 0; i < 320; i = i + 1)
++		read_data = mtk_switch_r32(gsw, 0x610);
++}
++
++static void trgmii_calibration_7623(struct mt7620_gsw *gsw)
++{
++
++	unsigned int tap_a[5] = { 0, 0, 0, 0, 0 };	/* minumum delay for all correct */
++	unsigned int tap_b[5] = { 0, 0, 0, 0, 0 };	/* maximum delay for all correct */
++	unsigned int final_tap[5];
++	unsigned int rxc_step_size;
++	unsigned int rxd_step_size;
++	unsigned int read_data;
++	unsigned int tmp;
++	unsigned int rd_wd;
++	int i;
++	unsigned int err_cnt[5];
++	unsigned int init_toggle_data;
++	unsigned int err_flag[5];
++	unsigned int err_total_flag;
++	unsigned int training_word;
++	unsigned int rd_tap;
++	u32 val;
++
++	u32 TRGMII_7623_base;
++	u32 TRGMII_7623_RD_0;
++	u32 TRGMII_RCK_CTRL;
++
++	TRGMII_7623_base = 0x300;	/* 0xFB110300 */
++	TRGMII_7623_RD_0 = TRGMII_7623_base + 0x10;
++	TRGMII_RCK_CTRL = TRGMII_7623_base;
++	rxd_step_size = 0x1;
++	rxc_step_size = 0x4;
++	init_toggle_data = 0x00000055;
++	training_word = 0x000000AC;
++
++	/* RX clock gating in MT7623 */
++	mtk_switch_m32(gsw, 0x3fffffff, 0, TRGMII_7623_base + 0x04);
++
++	/* Assert RX  reset in MT7623 */
++	mtk_switch_m32(gsw, 0, 0x80000000, TRGMII_7623_base + 0x00);
++
++	/* Set TX OE edge in  MT7623 */
++	mtk_switch_m32(gsw, 0, 0x00002000, TRGMII_7623_base + 0x78);
++
++	/* Disable RX clock gating in MT7623 */
++	mtk_switch_m32(gsw, 0, 0xC0000000, TRGMII_7623_base + 0x04);
++
++	/* Release RX reset in MT7623 */
++	mtk_switch_m32(gsw, 0x7fffffff, 0, TRGMII_7623_base);
++
++	for (i = 0; i < 5; i++)
++		mtk_switch_m32(gsw, 0, 0x80000000, TRGMII_7623_RD_0 + i * 8);
++
++	pr_err("Enable Training Mode in MT7530\n");
++	read_data = mt7530_mdio_r32(gsw, 0x7A40);
++	read_data |= 0xC0000000;
++	mt7530_mdio_w32(gsw, 0x7A40, read_data);	/* Enable Training Mode in MT7530 */
++	err_total_flag = 0;
++	pr_err("Adjust RXC delay in MT7623\n");
++	read_data = 0x0;
++	while (err_total_flag == 0 && read_data != 0x68) {
++		pr_err("2nd Enable EDGE CHK in MT7623\n");
++		/* Enable EDGE CHK in MT7623 */
++		for (i = 0; i < 5; i++)
++			    mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
++
++		wait_loop(gsw);
++		err_total_flag = 1;
++		for (i = 0; i < 5; i++) {
++			err_cnt[i] =
++			    mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8) >> 8;
++			err_cnt[i] &= 0x0000000f;
++			rd_wd = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8) >> 16;
++			rd_wd &= 0x000000ff;
++			val = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8);
++			pr_err("ERR_CNT = %d, RD_WD =%x, TRGMII_7623_RD_0=%x\n",
++			       err_cnt[i], rd_wd, val);
++			if (err_cnt[i] != 0) {
++				err_flag[i] = 1;
++			} else if (rd_wd != 0x55) {
++				err_flag[i] = 1;
++			} else {
++				err_flag[i] = 0;
++			}
++			err_total_flag = err_flag[i] & err_total_flag;
++		}
++
++		pr_err("2nd Disable EDGE CHK in MT7623\n");
++		/* Disable EDGE CHK in MT7623 */
++		for (i = 0; i < 5; i++)
++			    mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
++		wait_loop(gsw);
++		pr_err("2nd Disable EDGE CHK in MT7623\n");
++		/* Adjust RXC delay */
++		/* RX clock gating in MT7623 */
++		mtk_switch_m32(gsw, 0x3fffffff, 0, TRGMII_7623_base + 0x04);
++		read_data = mtk_switch_r32(gsw, TRGMII_7623_base);
++		if (err_total_flag == 0) {
++			tmp = (read_data & 0x0000007f) + rxc_step_size;
++			pr_err(" RXC delay = %d\n", tmp); 
++			read_data >>= 8;
++			read_data &= 0xffffff80;
++			read_data |= tmp;
++			read_data <<= 8;
++			read_data &= 0xffffff80;
++			read_data |= tmp;
++			mtk_switch_w32(gsw, read_data, TRGMII_7623_base);
++		} else {
++			tmp = (read_data & 0x0000007f) + 16;
++			pr_err(" RXC delay = %d\n", tmp); 
++			read_data >>= 8;
++			read_data &= 0xffffff80;
++			read_data |= tmp;
++			read_data <<= 8;
++			read_data &= 0xffffff80;
++			read_data |= tmp;
++			mtk_switch_w32(gsw, read_data, TRGMII_7623_base);
++		}
++		read_data &= 0x000000ff;
++
++		/* Disable RX clock gating in MT7623 */
++		mtk_switch_m32(gsw, 0, 0xC0000000, TRGMII_7623_base + 0x04);
++		for (i = 0; i < 5; i++)
++			mtk_switch_m32(gsw, 0, 0x80000000, TRGMII_7623_RD_0 + i * 8);
++	}
++
++	/* Read RD_WD MT7623 */
++	for (i = 0; i < 5; i++) {
++		rd_tap = 0;
++		while (err_flag[i] != 0 && rd_tap != 128) {
++			/* Enable EDGE CHK in MT7623 */
++			mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
++			wait_loop(gsw);
++
++			read_data = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8);
++			err_cnt[i] = (read_data >> 8) & 0x0000000f;	/* Read MT7623 Errcnt */
++			rd_wd = (read_data >> 16) & 0x000000ff;
++			if (err_cnt[i] != 0 || rd_wd != 0x55) {
++				err_flag[i] = 1;
++			} else {
++				err_flag[i] = 0;
++			}
++			/* Disable EDGE CHK in MT7623 */
++			mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
++			wait_loop(gsw);
++			if (err_flag[i] != 0) {
++				rd_tap = (read_data & 0x0000007f) + rxd_step_size;	/* Add RXD delay in MT7623 */
++				read_data = (read_data & 0xffffff80) | rd_tap;
++				mtk_switch_w32(gsw, read_data,
++					TRGMII_7623_RD_0 + i * 8);
++				tap_a[i] = rd_tap;
++			} else {
++				rd_tap = (read_data & 0x0000007f) + 48;
++				read_data = (read_data & 0xffffff80) | rd_tap;
++				mtk_switch_w32(gsw, read_data,
++					TRGMII_7623_RD_0 + i * 8);
++			}
++
++		}
++		pr_err("MT7623 %dth bit  Tap_a = %d\n", i, tap_a[i]);
++	}
++	/* pr_err("Last While Loop\n"); */
++	for (i = 0; i < 5; i++) {
++		while ((err_flag[i] == 0) && (rd_tap != 128)) {
++			read_data = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8);
++			rd_tap = (read_data & 0x0000007f) + rxd_step_size;	/* Add RXD delay in MT7623 */
++			read_data = (read_data & 0xffffff80) | rd_tap;
++			mtk_switch_w32(gsw, read_data, TRGMII_7623_RD_0 + i * 8);
++			/* Enable EDGE CHK in MT7623 */
++			val =
++			    mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8) | 0x40000000;
++			val &= 0x4fffffff;
++			mtk_switch_w32(gsw, val, TRGMII_7623_RD_0 + i * 8);
++			wait_loop(gsw);
++			read_data = mtk_switch_r32(gsw, TRGMII_7623_RD_0 + i * 8);
++			err_cnt[i] = (read_data >> 8) & 0x0000000f;	/* Read MT7623 Errcnt */
++			rd_wd = (read_data >> 16) & 0x000000ff;
++			if (err_cnt[i] != 0 || rd_wd != 0x55) {
++				err_flag[i] = 1;
++			} else {
++				err_flag[i] = 0;
++			}
++
++			/* Disable EDGE CHK in MT7623 */
++			mtk_switch_m32(gsw, 0x4fffffff, 0x40000000, TRGMII_7623_RD_0 + i * 8);
++			wait_loop(gsw);
++
++		}
++
++		tap_b[i] = rd_tap;	/* -rxd_step_size; */
++		pr_err("MT7623 %dth bit  Tap_b = %d\n", i, tap_b[i]);
++		final_tap[i] = (tap_a[i] + tap_b[i]) / 2;	/* Calculate RXD delay = (TAP_A + TAP_B)/2 */
++		read_data = (read_data & 0xffffff80) | final_tap[i];
++		mtk_switch_w32(gsw, read_data, TRGMII_7623_RD_0 + i * 8);
++	}
++
++	read_data = mt7530_mdio_r32(gsw, 0x7A40);
++	read_data &= 0x3fffffff;
++	mt7530_mdio_w32(gsw, 0x7A40, read_data);
++}
++
++static void trgmii_calibration_7530(struct mt7620_gsw *gsw)
++{
++
++	unsigned int tap_a[5] = { 0, 0, 0, 0, 0 };
++	unsigned int tap_b[5] = { 0, 0, 0, 0, 0 };
++	unsigned int final_tap[5];
++	unsigned int rxc_step_size;
++	unsigned int rxd_step_size;
++	unsigned int read_data;
++	unsigned int tmp = 0;
++	int i;
++	unsigned int err_cnt[5];
++	unsigned int rd_wd;
++	unsigned int init_toggle_data;
++	unsigned int err_flag[5];
++	unsigned int err_total_flag;
++	unsigned int training_word;
++	unsigned int rd_tap;
++
++	u32 TRGMII_7623_base;
++	u32 TRGMII_7530_RD_0;
++	u32 TRGMII_RCK_CTRL;
++	u32 TRGMII_7530_base;
++	u32 TRGMII_7530_TX_base;
++	u32 val;
++
++	TRGMII_7623_base = 0x300;
++	TRGMII_7530_base = 0x7A00;
++	TRGMII_7530_RD_0 = TRGMII_7530_base + 0x10;
++	TRGMII_RCK_CTRL = TRGMII_7623_base;
++	rxd_step_size = 0x1;
++	rxc_step_size = 0x8;
++	init_toggle_data = 0x00000055;
++	training_word = 0x000000AC;
++
++	TRGMII_7530_TX_base = TRGMII_7530_base + 0x50;
++
++	/* pr_err("Calibration begin ........\n"); */
++	val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x40) | 0x80000000;
++	mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x40);
++	read_data = mt7530_mdio_r32(gsw, 0x7a10);
++	/* pr_err("TRGMII_7530_RD_0 is %x\n", read_data); */
++
++	read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base + 0x04);
++	read_data &= 0x3fffffff;
++	mt7530_mdio_w32(gsw, TRGMII_7530_base + 0x04, read_data);	/* RX clock gating in MT7530 */
++
++	read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base + 0x78);
++	read_data |= 0x00002000;
++	mt7530_mdio_w32(gsw, TRGMII_7530_base + 0x78, read_data);	/* Set TX OE edge in  MT7530 */
++
++	read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base);
++	read_data |= 0x80000000;
++	mt7530_mdio_w32(gsw, TRGMII_7530_base, read_data);	/* Assert RX  reset in MT7530 */
++
++	read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base);
++	read_data &= 0x7fffffff;
++	mt7530_mdio_w32(gsw, TRGMII_7530_base, read_data);	/* Release RX reset in MT7530 */
++
++	read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base + 0x04);
++	read_data |= 0xC0000000;
++	mt7530_mdio_w32(gsw, TRGMII_7530_base + 0x04, read_data);	/* Disable RX clock gating in MT7530 */
++
++	/* pr_err("Enable Training Mode in MT7623\n"); */
++	/*Enable Training Mode in MT7623 */
++	val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x40) | 0x80000000;
++	mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x40);
++	if (gsw->trgmii_force == 2000) {
++		val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x40) | 0xC0000000;
++		mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x40);
++	} else {
++		val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x40) | 0x80000000;
++		mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x40);
++	}
++	val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x078) & 0xfffff0ff;
++	mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x078);
++	val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x50) & 0xfffff0ff;
++	mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x50);
++	val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x58) & 0xfffff0ff;
++	mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x58);
++	val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x60) & 0xfffff0ff;
++	mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x60);
++	val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x68) & 0xfffff0ff;
++	mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x68);
++	val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x70) & 0xfffff0ff;
++	mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x70);
++	val = mtk_switch_r32(gsw, TRGMII_7623_base + 0x78) & 0x00000800;
++	mtk_switch_w32(gsw, val, TRGMII_7623_base + 0x78);
++	err_total_flag = 0;
++	/* pr_err("Adjust RXC delay in MT7530\n"); */
++	read_data = 0x0;
++	while (err_total_flag == 0 && (read_data != 0x68)) {
++		/* pr_err("2nd Enable EDGE CHK in MT7530\n"); */
++		/* Enable EDGE CHK in MT7530 */
++		for (i = 0; i < 5; i++) {
++			read_data =
++			    mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
++			read_data |= 0x40000000;
++			read_data &= 0x4fffffff;
++			mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
++					read_data);
++			wait_loop(gsw);
++			/* pr_err("2nd Disable EDGE CHK in MT7530\n"); */
++			err_cnt[i] =
++			    mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
++			/* pr_err("***** MT7530 %dth bit ERR_CNT =%x\n",i, err_cnt[i]); */
++			/* pr_err("MT7530 %dth bit ERR_CNT =%x\n",i, err_cnt[i]); */
++			err_cnt[i] >>= 8;
++			err_cnt[i] &= 0x0000ff0f;
++			rd_wd = err_cnt[i] >> 8;
++			rd_wd &= 0x000000ff;
++			err_cnt[i] &= 0x0000000f;
++			/* read_data = mt7530_mdio_r32(gsw,0x7a10,&read_data); */
++			if (err_cnt[i] != 0) {
++				err_flag[i] = 1;
++			} else if (rd_wd != 0x55) {
++				err_flag[i] = 1;
++			} else {
++				err_flag[i] = 0;
++			}
++			if (i == 0) {
++				err_total_flag = err_flag[i];
++			} else {
++				err_total_flag = err_flag[i] & err_total_flag;
++			}
++			/* Disable EDGE CHK in MT7530 */
++			read_data =
++			    mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
++			read_data |= 0x40000000;
++			read_data &= 0x4fffffff;
++			mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
++					read_data);
++			wait_loop(gsw);
++		}
++		/*Adjust RXC delay */
++		if (err_total_flag == 0) {
++			read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base);
++			read_data |= 0x80000000;
++			mt7530_mdio_w32(gsw, TRGMII_7530_base, read_data);	/* Assert RX  reset in MT7530 */
++
++			read_data =
++			    mt7530_mdio_r32(gsw, TRGMII_7530_base + 0x04);
++			read_data &= 0x3fffffff;
++			mt7530_mdio_w32(gsw, TRGMII_7530_base + 0x04, read_data);	/* RX clock gating in MT7530 */
++
++			read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base);
++			tmp = read_data;
++			tmp &= 0x0000007f;
++			tmp += rxc_step_size;
++			/* pr_err("Current rxc delay = %d\n", tmp); */
++			read_data &= 0xffffff80;
++			read_data |= tmp;
++			mt7530_mdio_w32(gsw, TRGMII_7530_base, read_data);
++			read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base);
++			/* pr_err("Current RXC delay = %x\n", read_data); */
++
++			read_data = mt7530_mdio_r32(gsw, TRGMII_7530_base);
++			read_data &= 0x7fffffff;
++			mt7530_mdio_w32(gsw, TRGMII_7530_base, read_data);	/* Release RX reset in MT7530 */
++
++			read_data =
++			    mt7530_mdio_r32(gsw, TRGMII_7530_base + 0x04);
++			read_data |= 0xc0000000;
++			mt7530_mdio_w32(gsw, TRGMII_7530_base + 0x04, read_data);	/* Disable RX clock gating in MT7530 */
++			pr_err("####### MT7530 RXC delay is %d\n", tmp);
++		}
++		read_data = tmp;
++	}
++	pr_err("Finish RXC Adjustment while loop\n");
++
++	/* pr_err("Read RD_WD MT7530\n"); */
++	/* Read RD_WD MT7530 */
++	for (i = 0; i < 5; i++) {
++		rd_tap = 0;
++		while (err_flag[i] != 0 && rd_tap != 128) {
++			/* Enable EDGE CHK in MT7530 */
++			read_data =
++			    mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
++			read_data |= 0x40000000;
++			read_data &= 0x4fffffff;
++			mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
++					read_data);
++			wait_loop(gsw);
++			err_cnt[i] = (read_data >> 8) & 0x0000000f;
++			rd_wd = (read_data >> 16) & 0x000000ff;
++			if (err_cnt[i] != 0 || rd_wd != 0x55) {
++				err_flag[i] = 1;
++			} else {
++				err_flag[i] = 0;
++			}
++			if (err_flag[i] != 0) {
++				rd_tap = (read_data & 0x0000007f) + rxd_step_size;	/* Add RXD delay in MT7530 */
++				read_data = (read_data & 0xffffff80) | rd_tap;
++				mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
++						read_data);
++				tap_a[i] = rd_tap;
++			} else {
++				tap_a[i] = (read_data & 0x0000007f);	/* Record the min delay TAP_A */
++				rd_tap = tap_a[i] + 0x4;
++				read_data = (read_data & 0xffffff80) | rd_tap;
++				mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
++						read_data);
++			}
++
++			/* Disable EDGE CHK in MT7530 */
++			read_data =
++			    mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
++			read_data |= 0x40000000;
++			read_data &= 0x4fffffff;
++			mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
++					read_data);
++			wait_loop(gsw);
++
++		}
++		pr_err("MT7530 %dth bit  Tap_a = %d\n", i, tap_a[i]);
++	}
++
++	/* pr_err("Last While Loop\n"); */
++	for (i = 0; i < 5; i++) {
++		rd_tap = 0;
++		while (err_flag[i] == 0 && (rd_tap != 128)) {
++			/* Enable EDGE CHK in MT7530 */
++			read_data = mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
++			read_data |= 0x40000000;
++			read_data &= 0x4fffffff;
++			mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
++					read_data);
++			wait_loop(gsw);
++			err_cnt[i] = (read_data >> 8) & 0x0000000f;
++			rd_wd = (read_data >> 16) & 0x000000ff;
++			if (err_cnt[i] != 0 || rd_wd != 0x55)
++				err_flag[i] = 1;
++			else
++				err_flag[i] = 0;
++
++			if (err_flag[i] == 0 && (rd_tap != 128)) {
++				/* Add RXD delay in MT7530 */
++				rd_tap = (read_data & 0x0000007f) + rxd_step_size;
++				read_data = (read_data & 0xffffff80) | rd_tap;
++				mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
++						read_data);
++			}
++			/* Disable EDGE CHK in MT7530 */
++			read_data =
++			    mt7530_mdio_r32(gsw, TRGMII_7530_RD_0 + i * 8);
++			read_data |= 0x40000000;
++			read_data &= 0x4fffffff;
++			mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8,
++					read_data);
++			wait_loop(gsw);
++		}
++		tap_b[i] = rd_tap;	/* - rxd_step_size; */
++		pr_err("MT7530 %dth bit  Tap_b = %d\n", i, tap_b[i]);
++		/* Calculate RXD delay = (TAP_A + TAP_B)/2 */
++		final_tap[i] = (tap_a[i] + tap_b[i]) / 2;	
++		/* pr_err("########****** MT7530 %dth bit Final Tap = %d\n", i, final_tap[i]); */
++
++		read_data = (read_data & 0xffffff80) | final_tap[i];
++		mt7530_mdio_w32(gsw, TRGMII_7530_RD_0 + i * 8, read_data);
++	}
++
++	if (gsw->trgmii_force == 2000)
++		mtk_switch_m32(gsw, 0x7fffffff, 0, TRGMII_7623_base + 0x40);
++	else
++		mtk_switch_m32(gsw, 0x3fffffff, 0, TRGMII_7623_base + 0x40);
++
++}
++
++static void mt7530_trgmii_clock_setting(struct mt7620_gsw *gsw, u32 xtal_mode)
++{
++
++	u32 regValue;
++
++	/* TRGMII Clock */
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x410);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x1);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x404);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++
++	if (xtal_mode == 1) {
++		/* 25MHz */
++		if (gsw->trgmii_force == 2600)
++			/* 325MHz */
++			_mtk_mdio_write(gsw->eth, 0, 14, 0x1a00);
++		else if (gsw->trgmii_force == 2000)
++			/* 250MHz */
++			_mtk_mdio_write(gsw->eth, 0, 14, 0x1400);
++	} else if (xtal_mode == 2) {
++		/* 40MHz */
++		if (gsw->trgmii_force == 2600)
++			/* 325MHz */
++			_mtk_mdio_write(gsw->eth, 0, 14, 0x1040);
++		else if (gsw->trgmii_force == 2000)
++			/* 250MHz */
++			_mtk_mdio_write(gsw->eth, 0, 14, 0x0c80);
++	}
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x405);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x0);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x409);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	if (xtal_mode == 1)
++		/* 25MHz */
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x0057);
++	else
++		/* 40MHz */
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x0087);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x40a);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	if (xtal_mode == 1)
++		/* 25MHz */
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x0057);
++	else
++		/* 40MHz */
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x0087);
++
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x403);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x1800);
++
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x403);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x1c00);
++
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x401);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0xc020);
++
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x406);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0xa030);
++
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x406);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0xa038);
++
++//	udelay(120);		/* for MT7623 bring up test */
++
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x410);
++	_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x3);
++
++	regValue = mt7530_mdio_r32(gsw, 0x7830);
++	regValue &= 0xFFFFFFFC;
++	regValue |= 0x00000001;
++	mt7530_mdio_w32(gsw, 0x7830, regValue);
++
++	regValue = mt7530_mdio_r32(gsw, 0x7a40);
++	regValue &= ~(0x1 << 30);
++	regValue &= ~(0x1 << 28);
++	mt7530_mdio_w32(gsw, 0x7a40, regValue);
++
++	mt7530_mdio_w32(gsw, 0x7a78, 0x55);
++//	udelay(100);		/* for mt7623 bring up test */
++
++	mtk_switch_m32(gsw, 0x7fffffff, 0, 0x300);
++
++	trgmii_calibration_7623(gsw);
++	trgmii_calibration_7530(gsw);
++
++	mtk_switch_m32(gsw, 0, 0x80000000, 0x300);
++	mtk_switch_m32(gsw, 0, 0x7fffffff, 0x300);
++
++	/*MT7530 RXC reset */
++	regValue = mt7530_mdio_r32(gsw, 0x7a00);
++	regValue |= (0x1 << 31);
++	mt7530_mdio_w32(gsw, 0x7a00, regValue);
++	mdelay(1);
++	regValue &= ~(0x1 << 31);
++	mt7530_mdio_w32(gsw, 0x7a00, regValue);
++	mdelay(100);
++}
++
++static void mt7623_hw_init(struct mtk_eth *eth, struct mt7620_gsw *gsw, struct device_node *np)
++{
++       u32     i;
++       u32     val;
++       u32     xtal_mode;
++
++	regmap_update_bits(gsw->ethsys, ETHSYS_CLKCFG0,
++			   ETHSYS_TRGMII_CLK_SEL362_5,
++			   ETHSYS_TRGMII_CLK_SEL362_5);
++
++	/* reset the TRGMII core */
++	mtk_switch_m32(gsw, 0, INTF_MODE_TRGMII, GSW_INTF_MODE);
++	/* Assert MT7623 RXC reset */
++	mtk_switch_m32(gsw, 0, TRGMII_RCK_CTRL_RX_RST, GSW_TRGMII_RCK_CTRL);
++
++	/* Hardware reset Switch */
++	device_reset(eth->dev);
++
++	/* Wait for Switch Reset Completed*/
++	for (i = 0; i < 100; i++) {
++		mdelay(10);
++		if (mt7530_mdio_r32(gsw, MT7530_HWTRAP))
++			break;
++	}
++
++	/* turn off all PHYs */
++	for (i = 0; i <= 4; i++) {
++		val = _mtk_mdio_read(gsw->eth, i, 0x0);
++		val |= BIT(11);
++		_mtk_mdio_write(gsw->eth, i, 0x0, val);
++	}
++
++	/* reset the switch */
++	mt7530_mdio_w32(gsw, MT7530_SYS_CTRL,
++			SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
++	udelay(100);
++
++	/* GE1, Force 1000M/FD, FC ON */
++	mt7530_mdio_w32(gsw, MT7530_PMCR_P(6), PMCR_FIXED_LINK_FC);
++
++	/* GE2, Force 1000M/FD, FC ON */
++	mt7530_mdio_w32(gsw, MT7530_PMCR_P(5), PMCR_FIXED_LINK_FC);
++
++	/* Enable Port 6, P5 as GMAC5, P5 disable */
++	val = mt7530_mdio_r32(gsw, MT7530_MHWTRAP);
++	if (gsw->eth->mac[0] &&
++	    of_phy_is_fixed_link(gsw->eth->mac[0]->of_node))
++		/* Enable Port 6 */
++		val &= ~MHWTRAP_P6_DIS;
++	else
++		/* Disable Port 6 */
++		val |= MHWTRAP_P6_DIS;
++	if (gsw->eth->mac[1] &&
++	    of_phy_is_fixed_link(gsw->eth->mac[1]->of_node)) {
++		/* Enable Port 5 */
++		val &= ~MHWTRAP_P5_DIS;
++		/* Port 5 as PHY */
++		val &= ~MHWTRAP_P5_MAC_SEL;
++	} else {
++		/* Disable Port 5 */
++		val |= MHWTRAP_P5_DIS;
++		/* Port 5 as GMAC */
++		val |= MHWTRAP_P5_MAC_SEL;
++		val |= BIT(7);
++		mt7530_mdio_w32(gsw, MT7530_PMCR_P(5), 0x8000);
++	}
++	/* gphy to port 0/4 */
++	if (gsw->wllll)
++		val |= BIT(20);
++	else
++		val &= ~BIT(20);
++
++	/* Set MT7530 phy direct access mode**/
++	val &= ~MHWTRAP_PHY_ACCESS;
++	/* manual override of HW-Trap */
++	val |= MHWTRAP_MANUAL;
++	mt7530_mdio_w32(gsw, MT7530_MHWTRAP, val);
++	dev_info(gsw->dev, "Setting MHWTRAP to 0x%08x\n", val);
++
++	val = mt7530_mdio_r32(gsw, 0x7800);
++	val = (val >> 9) & 0x3;
++	if (val == 0x3) {
++		xtal_mode = 1;
++		/* 25Mhz Xtal - do nothing */
++	} else if (val == 0x2) {
++		/* 40Mhz */
++		xtal_mode = 2;
++
++		/* disable MT7530 core clock */
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x410);
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x0);
++
++		/* disable MT7530 PLL */
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x40d);
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x2020);
++
++		/* for MT7530 core clock = 500Mhz */
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x40e);
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x119);
++
++		/* enable MT7530 PLL */
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x40d);
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x2820);
++
++		udelay(20);
++
++		/* enable MT7530 core clock */
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x1f);
++		_mtk_mdio_write(gsw->eth, 0, 14, 0x410);
++		_mtk_mdio_write(gsw->eth, 0, 13, 0x401f);
++	} else {
++		xtal_mode = 3;
++		/* 20Mhz Xtal - TODO */
++	}
++
++	/* RGMII */
++	_mtk_mdio_write(gsw->eth, 0, 14, 0x1);
++
++	/* set MT7530 central align */
++	val = mt7530_mdio_r32(gsw, 0x7830);
++	val &= ~1;
++	val |= 1<<1;
++	mt7530_mdio_w32(gsw, 0x7830, val);
++
++	val = mt7530_mdio_r32(gsw, 0x7a40);
++	val &= ~(1<<30);
++	mt7530_mdio_w32(gsw, 0x7a40, val);
++
++	mt7530_mdio_w32(gsw, 0x7a78, 0x855);
++
++	/* delay setting for 10/1000M */
++	mt7530_mdio_w32(gsw, 0x7b00, 0x104);
++	mt7530_mdio_w32(gsw, 0x7b04, 0x10);
++
++	/* lower Tx Driving */
++	mt7530_mdio_w32(gsw, 0x7a54, 0x88);
++	mt7530_mdio_w32(gsw, 0x7a5c, 0x88);
++	mt7530_mdio_w32(gsw, 0x7a64, 0x88);
++	mt7530_mdio_w32(gsw, 0x7a6c, 0x88);
++	mt7530_mdio_w32(gsw, 0x7a74, 0x88);
++	mt7530_mdio_w32(gsw, 0x7a7c, 0x88);
++	mt7530_mdio_w32(gsw, 0x7810, 0x11);
++
++	/* Set MT7623/MT7683 TX Driving */
++	mtk_switch_w32(gsw, 0x88, 0x354);
++	mtk_switch_w32(gsw, 0x88, 0x35c);
++	mtk_switch_w32(gsw, 0x88, 0x364);
++	mtk_switch_w32(gsw, 0x88, 0x36c);
++	mtk_switch_w32(gsw, 0x88, 0x374);
++	mtk_switch_w32(gsw, 0x88, 0x37c);
++
++	/* Set GE2 driving and slew rate */
++	regmap_write(gsw->pctl, 0xF00, 0xe00);
++	/* set GE2 TDSEL */
++	regmap_write(gsw->pctl, 0x4C0, 0x5);
++	/* set GE2 TUNE */
++	regmap_write(gsw->pctl, 0xED0, 0x0);
++
++	regmap_write(gsw->pctl, 0xb70, 0);
++	regmap_write(gsw->pctl, 0x250, 0xffff);
++	regmap_write(gsw->pctl, 0x260, 0xff);
++	regmap_write(gsw->pctl, 0x380, 0x37);
++	regmap_write(gsw->pctl, 0x390, 0x40);
++
++	mt7530_trgmii_clock_setting(gsw, xtal_mode);
++
++	//LANWANPartition(gsw);
++
++	/* disable EEE */
++	for (i = 0; i <= 4; i++) {
++		_mtk_mdio_write(gsw->eth, i, 13, 0x7);
++		_mtk_mdio_write(gsw->eth, i, 14, 0x3C);
++		_mtk_mdio_write(gsw->eth, i, 13, 0x4007);
++		_mtk_mdio_write(gsw->eth, i, 14, 0x0);
++
++		/* Increase SlvDPSready time */
++		_mtk_mdio_write(gsw->eth, i, 31, 0x52b5);
++		_mtk_mdio_write(gsw->eth, i, 16, 0xafae);
++		_mtk_mdio_write(gsw->eth, i, 18, 0x2f);
++		_mtk_mdio_write(gsw->eth, i, 16, 0x8fae);
++
++		/* Incease post_update_timer */
++		_mtk_mdio_write(gsw->eth, i, 31, 0x3);
++		_mtk_mdio_write(gsw->eth, i, 17, 0x4b);
++
++		/* Adjust 100_mse_threshold */
++		_mtk_mdio_write(gsw->eth, i, 13, 0x1e);
++		_mtk_mdio_write(gsw->eth, i, 14, 0x123);
++		_mtk_mdio_write(gsw->eth, i, 13, 0x401e);
++		_mtk_mdio_write(gsw->eth, i, 14, 0xffff);
++
++		/* Disable mcc */
++		_mtk_mdio_write(gsw->eth, i, 13, 0x1e);
++		_mtk_mdio_write(gsw->eth, i, 14, 0xa6);
++		_mtk_mdio_write(gsw->eth, i, 13, 0x401e);
++		_mtk_mdio_write(gsw->eth, i, 14, 0x300);
++
++		/* Disable HW auto downshift*/
++		_mtk_mdio_write(gsw->eth, i, 31, 0x1);
++		val = _mtk_mdio_read(gsw->eth, i, 0x14);
++		val &= ~(1<<4);
++		_mtk_mdio_write(gsw->eth, i, 0x14, val);
++	}
++
++	/* turn on all PHYs */
++	for (i = 0; i <= 4; i++) {
++		val = _mtk_mdio_read(gsw->eth, i, 0);
++		val &= ~BIT(11);
++		_mtk_mdio_write(gsw->eth, i, 0, val);
++	}
++
++	/* enable irq */
++	mt7530_mdio_m32(gsw, 0, TOP_SIG_CTRL_NORMAL, MT7530_TOP_SIG_CTRL);
++}
++
++static const struct of_device_id mediatek_gsw_match[] = {
++	{ .compatible = "mediatek,mt7623-gsw" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
++
++int mtk_gsw_init(struct mtk_eth *eth)
++{
++	struct device_node *np = eth->switch_np;
++	struct platform_device *pdev = of_find_device_by_node(np);
++	struct mt7620_gsw *gsw;
++
++	if (!pdev)
++		return -ENODEV;
++
++	if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
++		return -EINVAL;
++
++	gsw = platform_get_drvdata(pdev);
++	if (!gsw)
++		return -ENODEV;
++	gsw->eth = eth;
++	eth->sw_priv = gsw;
++
++	mt7623_hw_init(eth, gsw, np);
++
++	if (request_threaded_irq(gsw->irq, gsw_interrupt_mt7623, NULL, 0,
++				 "gsw", eth))
++		pr_err("fail to request irq\n");
++	mt7530_mdio_w32(gsw, 0x7008, 0x1f);
++
++	return 0;
++}
++
++static int mt7623_gsw_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct device_node *pctl;
++	int reset_pin, ret;
++	struct mt7620_gsw *gsw;
++	struct regulator *supply;
++
++	gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
++	if (!gsw)
++		return -ENOMEM;
++
++	gsw->dev = &pdev->dev;
++	gsw->trgmii_force = 2000;
++	gsw->irq = irq_of_parse_and_map(np, 0);
++	if (gsw->irq < 0)
++		return -EINVAL;
++
++	gsw->ethsys = syscon_regmap_lookup_by_phandle(np, "mediatek,ethsys");
++	if (IS_ERR(gsw->ethsys))
++		return PTR_ERR(gsw->ethsys);
++
++	reset_pin = of_get_named_gpio(np, "mediatek,reset-pin", 0);
++	if (reset_pin < 0)
++		return reset_pin;
++
++	pctl = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
++	if (IS_ERR(pctl))
++		return PTR_ERR(pctl);
++
++	gsw->pctl = syscon_node_to_regmap(pctl);
++	if (IS_ERR(pctl))
++		return PTR_ERR(pctl);
++
++	ret = devm_gpio_request(&pdev->dev, reset_pin, "mt7530-reset");
++	if (ret)
++		return ret;
++
++	gsw->clk_trgpll = devm_clk_get(&pdev->dev, "trgpll");
++
++	if (IS_ERR(gsw->clk_trgpll))
++		return -ENODEV;
++
++	supply = devm_regulator_get(&pdev->dev, "mt7530");
++	if (IS_ERR(supply))
++		return PTR_ERR(supply);
++
++	regulator_set_voltage(supply, 1000000, 1000000);
++	ret = regulator_enable(supply);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to enable reg-7530: %d\n", ret);
++		return ret;
++	}
++
++	gsw->wllll = of_property_read_bool(np, "mediatek,wllll");
++
++	pm_runtime_enable(&pdev->dev);
++	pm_runtime_get_sync(&pdev->dev);
++
++	ret = clk_set_rate(gsw->clk_trgpll, 500000000);
++	if (ret)
++		return ret;
++
++	clk_prepare_enable(gsw->clk_trgpll);
++
++	gpio_direction_output(reset_pin, 0);
++	udelay(1000);
++	gpio_set_value(reset_pin, 1);
++	mdelay(100);
++
++	platform_set_drvdata(pdev, gsw);
++
++	return 0;
++}
++
++static int mt7623_gsw_remove(struct platform_device *pdev)
++{
++	struct mt7620_gsw *gsw = platform_get_drvdata(pdev);
++
++	clk_disable_unprepare(gsw->clk_trgpll);
++
++	pm_runtime_put_sync(&pdev->dev);
++        pm_runtime_disable(&pdev->dev);
++
++	platform_set_drvdata(pdev, NULL);
++
++	return 0;
++}
++
++static struct platform_driver gsw_driver = {
++	.probe = mt7623_gsw_probe,
++	.remove = mt7623_gsw_remove,
++	.driver = {
++		.name = "mt7623-gsw",
++		.owner = THIS_MODULE,
++		.of_match_table = mediatek_gsw_match,
++	},
++};
++
++module_platform_driver(gsw_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("John Crispin <[email protected]>");
++MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7623 SoC");
+diff --git a/drivers/net/ethernet/mediatek/mt7530.c b/drivers/net/ethernet/mediatek/mt7530.c
+new file mode 100644
+index 0000000..2e9d280
+--- /dev/null
++++ b/drivers/net/ethernet/mediatek/mt7530.c
+@@ -0,0 +1,808 @@
++/*
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * Copyright (C) 2013 John Crispin <[email protected]>
++ */
++
++#include <linux/if.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/if_ether.h>
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#include <linux/netlink.h>
++#include <linux/bitops.h>
++#include <net/genetlink.h>
++#include <linux/switch.h>
++#include <linux/delay.h>
++#include <linux/phy.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/lockdep.h>
++#include <linux/workqueue.h>
++#include <linux/of_device.h>
++
++#include "mt7530.h"
++
++#define MT7530_CPU_PORT		6
++#define MT7530_NUM_PORTS	8
++#define MT7530_NUM_VLANS	16
++#define MT7530_MAX_VID		4095
++#define MT7530_MIN_VID		0
++
++/* registers */
++#define REG_ESW_VLAN_VTCR		0x90
++#define REG_ESW_VLAN_VAWD1		0x94
++#define REG_ESW_VLAN_VAWD2		0x98
++#define REG_ESW_VLAN_VTIM(x)	(0x100 + 4 * ((x) / 2))
++
++#define REG_ESW_VLAN_VAWD1_IVL_MAC	BIT(30)
++#define REG_ESW_VLAN_VAWD1_VTAG_EN	BIT(28)
++#define REG_ESW_VLAN_VAWD1_VALID	BIT(0)
++
++/* vlan egress mode */
++enum {
++	ETAG_CTRL_UNTAG	= 0,
++	ETAG_CTRL_TAG	= 2,
++	ETAG_CTRL_SWAP	= 1,
++	ETAG_CTRL_STACK	= 3,
++};
++
++#define REG_ESW_PORT_PCR(x)	(0x2004 | ((x) << 8))
++#define REG_ESW_PORT_PVC(x)	(0x2010 | ((x) << 8))
++#define REG_ESW_PORT_PPBV1(x)	(0x2014 | ((x) << 8))
++
++#define REG_HWTRAP		0x7804
++
++#define MIB_DESC(_s , _o, _n)   \
++	{                       \
++		.size = (_s),   \
++		.offset = (_o), \
++		.name = (_n),   \
++	}
++
++struct mt7xxx_mib_desc {
++	unsigned int size;
++	unsigned int offset;
++	const char *name;
++};
++
++#define MT7621_MIB_COUNTER_BASE	0x4000
++#define MT7621_MIB_COUNTER_PORT_OFFSET	0x100
++#define MT7621_STATS_TDPC	0x00
++#define MT7621_STATS_TCRC	0x04
++#define MT7621_STATS_TUPC	0x08
++#define MT7621_STATS_TMPC	0x0C
++#define MT7621_STATS_TBPC	0x10
++#define MT7621_STATS_TCEC	0x14
++#define MT7621_STATS_TSCEC	0x18
++#define MT7621_STATS_TMCEC	0x1C
++#define MT7621_STATS_TDEC	0x20
++#define MT7621_STATS_TLCEC	0x24
++#define MT7621_STATS_TXCEC	0x28
++#define MT7621_STATS_TPPC	0x2C
++#define MT7621_STATS_TL64PC	0x30
++#define MT7621_STATS_TL65PC	0x34
++#define MT7621_STATS_TL128PC	0x38
++#define MT7621_STATS_TL256PC	0x3C
++#define MT7621_STATS_TL512PC	0x40
++#define MT7621_STATS_TL1024PC	0x44
++#define MT7621_STATS_TOC	0x48
++#define MT7621_STATS_RDPC	0x60
++#define MT7621_STATS_RFPC	0x64
++#define MT7621_STATS_RUPC	0x68
++#define MT7621_STATS_RMPC	0x6C
++#define MT7621_STATS_RBPC	0x70
++#define MT7621_STATS_RAEPC	0x74
++#define MT7621_STATS_RCEPC	0x78
++#define MT7621_STATS_RUSPC	0x7C
++#define MT7621_STATS_RFEPC	0x80
++#define MT7621_STATS_ROSPC	0x84
++#define MT7621_STATS_RJEPC	0x88
++#define MT7621_STATS_RPPC	0x8C
++#define MT7621_STATS_RL64PC	0x90
++#define MT7621_STATS_RL65PC	0x94
++#define MT7621_STATS_RL128PC	0x98
++#define MT7621_STATS_RL256PC	0x9C
++#define MT7621_STATS_RL512PC	0xA0
++#define MT7621_STATS_RL1024PC	0xA4
++#define MT7621_STATS_ROC	0xA8
++#define MT7621_STATS_RDPC_CTRL	0xB0
++#define MT7621_STATS_RDPC_ING	0xB4
++#define MT7621_STATS_RDPC_ARL	0xB8
++
++static const struct mt7xxx_mib_desc mt7621_mibs[] = {
++	MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
++	MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
++	MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
++	MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
++	MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
++	MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
++	MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
++	MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
++	MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
++	MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
++	MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
++	MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
++	MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
++	MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
++	MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
++	MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
++	MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
++	MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
++	MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
++	MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
++	MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
++	MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
++	MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
++	MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
++	MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
++	MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
++	MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
++	MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
++	MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
++	MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
++	MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
++	MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
++	MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
++	MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
++	MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
++	MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
++	MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
++	MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
++	MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
++	MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
++	MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
++};
++
++enum {
++	/* Global attributes. */
++	MT7530_ATTR_ENABLE_VLAN,
++};
++
++struct mt7530_port_entry {
++	u16	pvid;
++};
++
++struct mt7530_vlan_entry {
++	u16	vid;
++	u8	member;
++	u8	etags;
++};
++
++struct mt7530_priv {
++	void __iomem		*base;
++	struct mii_bus		*bus;
++	struct switch_dev	swdev;
++
++	bool			global_vlan_enable;
++	struct mt7530_vlan_entry	vlan_entries[MT7530_NUM_VLANS];
++	struct mt7530_port_entry	port_entries[MT7530_NUM_PORTS];
++};
++
++struct mt7530_mapping {
++	char	*name;
++	u16	pvids[MT7530_NUM_PORTS];
++	u8	members[MT7530_NUM_VLANS];
++	u8	etags[MT7530_NUM_VLANS];
++	u16	vids[MT7530_NUM_VLANS];
++} mt7530_defaults[] = {
++	{
++		.name = "llllw",
++		.pvids = { 1, 1, 1, 1, 2, 1, 1 },
++		.members = { 0, 0x6f, 0x50 },
++		.etags = { 0, 0x40, 0x40 },
++		.vids = { 0, 1, 2 },
++	}, {
++		.name = "wllll",
++		.pvids = { 2, 1, 1, 1, 1, 1, 1 },
++		.members = { 0, 0x7e, 0x41 },
++		.etags = { 0, 0x40, 0x40 },
++		.vids = { 0, 1, 2 },
++	},
++};
++
++struct mt7530_mapping*
++mt7530_find_mapping(struct device_node *np)
++{
++	const char *map;
++	int i;
++
++	if (of_property_read_string(np, "mediatek,portmap", &map))
++		return NULL;
++
++	for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
++		if (!strcmp(map, mt7530_defaults[i].name))
++			return &mt7530_defaults[i];
++
++	return NULL;
++}
++
++static void
++mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
++{
++	int i = 0;
++
++	for (i = 0; i < MT7530_NUM_PORTS; i++)
++		mt7530->port_entries[i].pvid = map->pvids[i];
++
++	for (i = 0; i < MT7530_NUM_VLANS; i++) {
++		mt7530->vlan_entries[i].member = map->members[i];
++		mt7530->vlan_entries[i].etags = map->etags[i];
++		mt7530->vlan_entries[i].vid = map->vids[i];
++	}
++}
++
++static int
++mt7530_reset_switch(struct switch_dev *dev)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++	int i;
++
++	memset(eth->port_entries, 0, sizeof(eth->port_entries));
++	memset(eth->vlan_entries, 0, sizeof(eth->vlan_entries));
++
++	/* set default vid of each vlan to the same number of vlan, so the vid
++	 * won't need be set explicitly.
++	 */
++	for (i = 0; i < MT7530_NUM_VLANS; i++) {
++		eth->vlan_entries[i].vid = i;
++	}
++
++	return 0;
++}
++
++static int
++mt7530_get_vlan_enable(struct switch_dev *dev,
++			   const struct switch_attr *attr,
++			   struct switch_val *val)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++
++	val->value.i = eth->global_vlan_enable;
++
++	return 0;
++}
++
++static int
++mt7530_set_vlan_enable(struct switch_dev *dev,
++			   const struct switch_attr *attr,
++			   struct switch_val *val)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++
++	eth->global_vlan_enable = val->value.i != 0;
++
++	return 0;
++}
++
++static u32
++mt7530_r32(struct mt7530_priv *eth, u32 reg)
++{
++	u32 val;
++	if (eth->bus) {
++		u16 high, low;
++
++		mdiobus_write(eth->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
++		low = mdiobus_read(eth->bus, 0x1f, (reg >> 2) & 0xf);
++		high = mdiobus_read(eth->bus, 0x1f, 0x10);
++
++		return (high << 16) | (low & 0xffff);
++	}
++
++	val = ioread32(eth->base + reg);
++	pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
++
++	return val;
++}
++
++static void
++mt7530_w32(struct mt7530_priv *eth, u32 reg, u32 val)
++{
++	if (eth->bus) {
++		mdiobus_write(eth->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
++		mdiobus_write(eth->bus, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
++		mdiobus_write(eth->bus, 0x1f, 0x10, val >> 16);
++		return;
++	}
++
++	pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
++	iowrite32(val, eth->base + reg);
++}
++
++static void
++mt7530_vtcr(struct mt7530_priv *eth, u32 cmd, u32 val)
++{
++	int i;
++
++	mt7530_w32(eth, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
++
++	for (i = 0; i < 20; i++) {
++		u32 val = mt7530_r32(eth, REG_ESW_VLAN_VTCR);
++
++		if ((val & BIT(31)) == 0)
++			break;
++
++		udelay(1000);
++	}
++	if (i == 20)
++		printk("mt7530: vtcr timeout\n");
++}
++
++static int
++mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++
++	if (port >= MT7530_NUM_PORTS)
++		return -EINVAL;
++
++	*val = mt7530_r32(eth, REG_ESW_PORT_PPBV1(port));
++	*val &= 0xfff;
++
++	return 0;
++}
++
++static int
++mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++
++	if (port >= MT7530_NUM_PORTS)
++		return -EINVAL;
++
++	if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
++		return -EINVAL;
++
++	eth->port_entries[port].pvid = pvid;
++
++	return 0;
++}
++
++static int
++mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++	u32 member;
++	u32 etags;
++	int i;
++
++	val->len = 0;
++
++	if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
++		return -EINVAL;
++
++	mt7530_vtcr(eth, 0, val->port_vlan);
++
++	member = mt7530_r32(eth, REG_ESW_VLAN_VAWD1);
++	member >>= 16;
++	member &= 0xff;
++
++	etags = mt7530_r32(eth, REG_ESW_VLAN_VAWD2);
++
++	for (i = 0; i < MT7530_NUM_PORTS; i++) {
++		struct switch_port *p;
++		int etag;
++
++		if (!(member & BIT(i)))
++			continue;
++
++		p = &val->value.ports[val->len++];
++		p->id = i;
++
++		etag = (etags >> (i * 2)) & 0x3;
++
++		if (etag == ETAG_CTRL_TAG)
++			p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
++		else if (etag != ETAG_CTRL_UNTAG)
++			printk("vlan egress tag control neither untag nor tag.\n");
++	}
++
++	return 0;
++}
++
++static int
++mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++	u8 member = 0;
++	u8 etags = 0;
++	int i;
++
++	if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
++			val->len > MT7530_NUM_PORTS)
++		return -EINVAL;
++
++	for (i = 0; i < val->len; i++) {
++		struct switch_port *p = &val->value.ports[i];
++
++		if (p->id >= MT7530_NUM_PORTS)
++			return -EINVAL;
++
++		member |= BIT(p->id);
++
++		if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
++			etags |= BIT(p->id);
++	}
++	eth->vlan_entries[val->port_vlan].member = member;
++	eth->vlan_entries[val->port_vlan].etags = etags;
++
++	return 0;
++}
++
++static int
++mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
++		struct switch_val *val)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++	int vlan;
++	u16 vid;
++
++	vlan = val->port_vlan;
++	vid = (u16)val->value.i;
++
++	if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
++		return -EINVAL;
++
++	if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
++		return -EINVAL;
++
++	eth->vlan_entries[vlan].vid = vid;
++	return 0;
++}
++
++static int
++mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
++		struct switch_val *val)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++	u32 vid;
++	int vlan;
++
++	vlan = val->port_vlan;
++
++	vid = mt7530_r32(eth, REG_ESW_VLAN_VTIM(vlan));
++	if (vlan & 1)
++		vid = vid >> 12;
++	vid &= 0xfff;
++
++	val->value.i = vid;
++	return 0;
++}
++
++static int
++mt7530_apply_config(struct switch_dev *dev)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++	int i, j;
++	u8 tag_ports;
++	u8 untag_ports;
++
++	if (!eth->global_vlan_enable) {
++		for (i = 0; i < MT7530_NUM_PORTS; i++)
++			mt7530_w32(eth, REG_ESW_PORT_PCR(i), 0x00ff0000);
++
++		for (i = 0; i < MT7530_NUM_PORTS; i++)
++			mt7530_w32(eth, REG_ESW_PORT_PVC(i), 0x810000c0);
++
++		return 0;
++	}
++
++	/* set all ports as security mode */
++	for (i = 0; i < MT7530_NUM_PORTS; i++)
++		mt7530_w32(eth, REG_ESW_PORT_PCR(i), 0x00ff0003);
++
++	/* check if a port is used in tag/untag vlan egress mode */
++	tag_ports = 0;
++	untag_ports = 0;
++
++	for (i = 0; i < MT7530_NUM_VLANS; i++) {
++		u8 member = eth->vlan_entries[i].member;
++		u8 etags = eth->vlan_entries[i].etags;
++
++		if (!member)
++			continue;
++
++		for (j = 0; j < MT7530_NUM_PORTS; j++) {
++			if (!(member & BIT(j)))
++				continue;
++
++			if (etags & BIT(j))
++				tag_ports |= 1u << j;
++			else
++				untag_ports |= 1u << j;
++		}
++	}
++
++	/* set all untag-only ports as transparent and the rest as user port */
++	for (i = 0; i < MT7530_NUM_PORTS; i++) {
++		u32 pvc_mode = 0x81000000;
++
++		if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
++			pvc_mode = 0x810000c0;
++
++		mt7530_w32(eth, REG_ESW_PORT_PVC(i), pvc_mode);
++	}
++
++	for (i = 0; i < MT7530_NUM_VLANS; i++) {
++		u16 vid = eth->vlan_entries[i].vid;
++		u8 member = eth->vlan_entries[i].member;
++		u8 etags = eth->vlan_entries[i].etags;
++		u32 val;
++
++		/* vid of vlan */
++		val = mt7530_r32(eth, REG_ESW_VLAN_VTIM(i));
++		if (i % 2 == 0) {
++			val &= 0xfff000;
++			val |= vid;
++		} else {
++			val &= 0xfff;
++			val |= (vid << 12);
++		}
++		mt7530_w32(eth, REG_ESW_VLAN_VTIM(i), val);
++
++		/* vlan port membership */
++		if (member)
++			mt7530_w32(eth, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
++				REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
++				REG_ESW_VLAN_VAWD1_VALID);
++		else
++			mt7530_w32(eth, REG_ESW_VLAN_VAWD1, 0);
++
++		/* egress mode */
++		val = 0;
++		for (j = 0; j < MT7530_NUM_PORTS; j++) {
++			if (etags & BIT(j))
++				val |= ETAG_CTRL_TAG << (j * 2);
++			else
++				val |= ETAG_CTRL_UNTAG << (j * 2);
++		}
++		mt7530_w32(eth, REG_ESW_VLAN_VAWD2, val);
++
++		/* write to vlan table */
++		mt7530_vtcr(eth, 1, i);
++	}
++
++	/* Port Default PVID */
++	for (i = 0; i < MT7530_NUM_PORTS; i++) {
++		u32 val;
++		val = mt7530_r32(eth, REG_ESW_PORT_PPBV1(i));
++		val &= ~0xfff;
++		val |= eth->port_entries[i].pvid;
++		mt7530_w32(eth, REG_ESW_PORT_PPBV1(i), val);
++	}
++
++	return 0;
++}
++
++static int
++mt7530_get_port_link(struct switch_dev *dev,  int port,
++			struct switch_port_link *link)
++{
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++	u32 speed, pmsr;
++
++	if (port < 0 || port >= MT7530_NUM_PORTS)
++		return -EINVAL;
++
++	pmsr = mt7530_r32(eth, 0x3008 + (0x100 * port));
++
++	link->link = pmsr & 1;
++	link->duplex = (pmsr >> 1) & 1;
++	speed = (pmsr >> 2) & 3;
++
++	switch (speed) {
++	case 0:
++		link->speed = SWITCH_PORT_SPEED_10;
++		break;
++	case 1:
++		link->speed = SWITCH_PORT_SPEED_100;
++		break;
++	case 2:
++	case 3: /* forced gige speed can be 2 or 3 */
++		link->speed = SWITCH_PORT_SPEED_1000;
++		break;
++	default:
++		link->speed = SWITCH_PORT_SPEED_UNKNOWN;
++		break;
++	}
++
++	return 0;
++}
++
++static const struct switch_attr mt7530_global[] = {
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "enable_vlan",
++		.description = "VLAN mode (1:enabled)",
++		.max = 1,
++		.id = MT7530_ATTR_ENABLE_VLAN,
++		.get = mt7530_get_vlan_enable,
++		.set = mt7530_set_vlan_enable,
++	},
++};
++
++static u64 get_mib_counter(struct mt7530_priv *eth, int i, int port)
++{
++	unsigned int port_base;
++	u64 t;
++
++	port_base = MT7621_MIB_COUNTER_BASE +
++		    MT7621_MIB_COUNTER_PORT_OFFSET * port;
++
++	t = mt7530_r32(eth, port_base + mt7621_mibs[i].offset);
++	if (mt7621_mibs[i].size == 2) {
++		u64 hi;
++
++		hi = mt7530_r32(eth, port_base + mt7621_mibs[i].offset + 4);
++		t |= hi << 32;
++	}
++
++	return t;
++}
++
++static int mt7621_sw_get_port_mib(struct switch_dev *dev,
++				  const struct switch_attr *attr,
++				  struct switch_val *val)
++{
++	static char buf[4096];
++	struct mt7530_priv *eth = container_of(dev, struct mt7530_priv, swdev);
++	int i, len = 0;
++
++	if (val->port_vlan >= MT7530_NUM_PORTS)
++		return -EINVAL;
++
++	len += snprintf(buf + len, sizeof(buf) - len,
++			"Port %d MIB counters\n", val->port_vlan);
++
++	for (i = 0; i < sizeof(mt7621_mibs) / sizeof(*mt7621_mibs); ++i) {
++		u64 counter;
++		len += snprintf(buf + len, sizeof(buf) - len,
++				"%-11s: ", mt7621_mibs[i].name);
++		counter = get_mib_counter(eth, i, val->port_vlan);
++		len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
++				counter);
++	}
++
++	val->value.s = buf;
++	val->len = len;
++	return 0;
++}
++
++static const struct switch_attr mt7621_port[] = {
++	{
++		.type = SWITCH_TYPE_STRING,
++		.name = "mib",
++		.description = "Get MIB counters for port",
++		.get = mt7621_sw_get_port_mib,
++		.set = NULL,
++	},
++};
++
++static const struct switch_attr mt7530_port[] = {
++};
++
++static const struct switch_attr mt7530_vlan[] = {
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "vid",
++		.description = "VLAN ID (0-4094)",
++		.set = mt7530_set_vid,
++		.get = mt7530_get_vid,
++		.max = 4094,
++	},
++};
++
++static const struct switch_dev_ops mt7621_ops = {
++	.attr_global = {
++		.attr = mt7530_global,
++		.n_attr = ARRAY_SIZE(mt7530_global),
++	},
++/*	.attr_port = {
++		.attr = mt7621_port,
++		.n_attr = ARRAY_SIZE(mt7621_port),
++	},*/
++	.attr_vlan = {
++		.attr = mt7530_vlan,
++		.n_attr = ARRAY_SIZE(mt7530_vlan),
++	},
++	.get_vlan_ports = mt7530_get_vlan_ports,
++	.set_vlan_ports = mt7530_set_vlan_ports,
++	.get_port_pvid = mt7530_get_port_pvid,
++	.set_port_pvid = mt7530_set_port_pvid,
++	.get_port_link = mt7530_get_port_link,
++	.apply_config = mt7530_apply_config,
++	.reset_switch = mt7530_reset_switch,
++};
++
++static const struct switch_dev_ops mt7530_ops = {
++	.attr_global = {
++		.attr = mt7530_global,
++		.n_attr = ARRAY_SIZE(mt7530_global),
++	},
++	.attr_port = {
++		.attr = mt7530_port,
++		.n_attr = ARRAY_SIZE(mt7530_port),
++	},
++	.attr_vlan = {
++		.attr = mt7530_vlan,
++		.n_attr = ARRAY_SIZE(mt7530_vlan),
++	},
++	.get_vlan_ports = mt7530_get_vlan_ports,
++	.set_vlan_ports = mt7530_set_vlan_ports,
++	.get_port_pvid = mt7530_get_port_pvid,
++	.set_port_pvid = mt7530_set_port_pvid,
++	.get_port_link = mt7530_get_port_link,
++	.apply_config = mt7530_apply_config,
++	.reset_switch = mt7530_reset_switch,
++};
++
++int
++mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
++{
++	struct switch_dev *swdev;
++	struct mt7530_priv *mt7530;
++	struct mt7530_mapping *map;
++	int ret;
++
++	mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
++	if (!mt7530)
++		return -ENOMEM;
++
++	mt7530->base = base;
++	mt7530->bus = bus;
++	mt7530->global_vlan_enable = vlan;
++
++	swdev = &mt7530->swdev;
++	if (bus) {
++		swdev->alias = "mt7530";
++		swdev->name = "mt7530";
++	} else if (IS_ENABLED(CONFIG_MACH_MT7623)) {
++		swdev->alias = "mt7623";
++		swdev->name = "mt7623";
++	} else if (IS_ENABLED(CONFIG_SOC_MT7621)) {
++		swdev->alias = "mt7621";
++		swdev->name = "mt7621";
++	} else {
++		swdev->alias = "mt7620";
++		swdev->name = "mt7620";
++	}
++	swdev->cpu_port = MT7530_CPU_PORT;
++	swdev->ports = MT7530_NUM_PORTS;
++	swdev->vlans = MT7530_NUM_VLANS;
++	if (IS_ENABLED(CONFIG_SOC_MT7621) || IS_ENABLED(CONFIG_MACH_MT7623))
++		swdev->ops = &mt7621_ops;
++	else
++		swdev->ops = &mt7530_ops;
++
++	ret = register_switch(swdev, NULL);
++	if (ret) {
++		dev_err(dev, "failed to register mt7530\n");
++		return ret;
++	}
++
++	mt7530_reset_switch(swdev);
++
++	map = mt7530_find_mapping(dev->of_node);
++	if (map)
++		mt7530_apply_mapping(mt7530, map);
++	mt7530_apply_config(swdev);
++
++	/* magic vodoo */
++	if (!(IS_ENABLED(CONFIG_SOC_MT7621) || IS_ENABLED(CONFIG_MACH_MT7623)) && bus && mt7530_r32(mt7530, REG_HWTRAP) !=  0x1117edf) {
++	        dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
++		mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
++	}
++	dev_info(dev, "loaded %s driver\n", swdev->name);
++
++	return 0;
++}
+diff --git a/drivers/net/ethernet/mediatek/mt7530.h b/drivers/net/ethernet/mediatek/mt7530.h
+new file mode 100644
+index 0000000..1fc8c62
+--- /dev/null
++++ b/drivers/net/ethernet/mediatek/mt7530.h
+@@ -0,0 +1,20 @@
++/*
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * Copyright (C) 2013 John Crispin <[email protected]>
++ */
++
++#ifndef _MT7530_H__
++#define _MT7530_H__
++
++int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
++
++#endif
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index b5e364c..eee4324a 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -24,6 +24,9 @@
+ 
+ #include "mtk_eth_soc.h"
+ 
++/* the callback used by the driver core to bringup the switch */
++int mtk_gsw_init(struct mtk_eth *eth);
++
+ static int mtk_msg_level = -1;
+ module_param_named(msg_level, mtk_msg_level, int, 0);
+ MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
+@@ -69,7 +72,7 @@ static int mtk_mdio_busy_wait(struct mtk_eth *eth)
+ 			return 0;
+ 		if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
+ 			break;
+-		usleep_range(10, 20);
++//		usleep_range(10, 20);
+ 	}
+ 
+ 	dev_err(eth->dev, "mdio: MDIO timeout\n");
+@@ -1407,15 +1410,6 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
+ 	reset_control_deassert(eth->rstc);
+ 	usleep_range(10, 20);
+ 
+-	/* Set GE2 driving and slew rate */
+-	regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
+-
+-	/* set GE2 TDSEL */
+-	regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
+-
+-	/* set GE2 TUNE */
+-	regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
+-
+ 	/* GE1, Force 1000M/FD, FC ON */
+ 	mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
+ 
+@@ -1438,6 +1432,8 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
+ 	if (err)
+ 		return err;
+ 
++	mtk_gsw_init(eth);
++
+ 	/* disable delay and normal interrupt */
+ 	mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
+ 	mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
+@@ -1465,6 +1461,8 @@ static int __init mtk_hw_init(struct mtk_eth *eth)
+ 		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
+ 	}
+ 
++	mt7623_gsw_config(eth);
++
+ 	return 0;
+ }
+ 
+@@ -1720,7 +1718,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+ {
+ 	struct mtk_mac *mac;
+ 	const __be32 *_id = of_get_property(np, "reg", NULL);
+-	int id, err;
++	int id;
+ 
+ 	if (!_id) {
+ 		dev_err(eth->dev, "missing mac id\n");
+@@ -1754,8 +1752,8 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+ 				     GFP_KERNEL);
+ 	if (!mac->hw_stats) {
+ 		dev_err(eth->dev, "failed to allocate counter memory\n");
+-		err = -ENOMEM;
+-		goto free_netdev;
++		free_netdev(eth->netdev[id]);
++		return -ENOMEM;
+ 	}
+ 	spin_lock_init(&mac->hw_stats->stats_lock);
+ 	mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
+@@ -1769,21 +1767,9 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+ 	eth->netdev[id]->features |= MTK_HW_FEATURES;
+ 	eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
+ 
+-	err = register_netdev(eth->netdev[id]);
+-	if (err) {
+-		dev_err(eth->dev, "error bringing up device\n");
+-		goto free_netdev;
+-	}
+ 	eth->netdev[id]->irq = eth->irq[0];
+-	netif_info(eth, probe, eth->netdev[id],
+-		   "mediatek frame engine at 0x%08lx, irq %d\n",
+-		   eth->netdev[id]->base_addr, eth->irq[0]);
+ 
+ 	return 0;
+-
+-free_netdev:
+-	free_netdev(eth->netdev[id]);
+-	return err;
+ }
+ 
+ static int mtk_probe(struct platform_device *pdev)
+@@ -1851,14 +1837,13 @@ static int mtk_probe(struct platform_device *pdev)
+ 	clk_prepare_enable(eth->clk_gp1);
+ 	clk_prepare_enable(eth->clk_gp2);
+ 
++	eth->switch_np = of_parse_phandle(pdev->dev.of_node,
++					  "mediatek,switch", 0);
++
+ 	eth->dev = &pdev->dev;
+ 	eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
+ 	INIT_WORK(&eth->pending_work, mtk_pending_work);
+ 
+-	err = mtk_hw_init(eth);
+-	if (err)
+-		return err;
+-
+ 	for_each_child_of_node(pdev->dev.of_node, mac_np) {
+ 		if (!of_device_is_compatible(mac_np,
+ 					     "mediatek,eth-mac"))
+@@ -1872,6 +1857,22 @@ static int mtk_probe(struct platform_device *pdev)
+ 			goto err_free_dev;
+ 	}
+ 
++	err = mtk_hw_init(eth);
++	if (err)
++		return err;
++
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		if (!eth->netdev[i])
++			continue;
++		err = register_netdev(eth->netdev[i]);
++		if (err)
++			dev_err(eth->dev, "error bringing up device\n");
++		else
++			netif_info(eth, probe, eth->netdev[i],
++				   "mediatek frame engine at 0x%08lx, irq %d\n",
++				   eth->netdev[i]->base_addr, eth->irq[0]);
++	}
++
+ 	/* we run 2 devices on the same DMA ring so we need a dummy device
+ 	 * for NAPI to work
+ 	 */
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+index bf158f8..5093518 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -406,6 +406,8 @@ struct mtk_eth {
+ 	struct mii_bus			*mii_bus;
+ 	struct work_struct		pending_work;
+ 
++	struct device_node		*switch_np;
++	void				*sw_priv;
+ };
+ 
+ /* struct mtk_mac -	the structure that holds the info about the MACs of the
+@@ -433,4 +435,6 @@ void mtk_stats_update_mac(struct mtk_mac *mac);
+ void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
+ u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
+ 
++int mt7623_gsw_config(struct mtk_eth *eth);
++
+ #endif /* MTK_ETH_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0090-net-mediatek-v4.4-backports.patch

@@ -0,0 +1,77 @@
+From 65f0d87a26f7cec860b89b40eebc48a4eb71acf8 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Mon, 11 Apr 2016 06:00:23 +0200
+Subject: [PATCH 90/91] net: mediatek: v4.4 backports
+
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |   23 ++++++++++++++---------
+ 1 file changed, 14 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index eee4324a..b466f45 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -207,7 +207,7 @@ static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
+ 
+ 	dev_info(eth->dev,
+ 		 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
+-		 mac->id, phydev_name(phydev), phydev->phy_id,
++		 mac->id, dev_name(&phydev->dev), phydev->phy_id,
+ 		 phydev->drv->name);
+ 
+ 	mac->phy_dev = phydev;
+@@ -1267,9 +1267,10 @@ static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
+ 		return IRQ_NONE;
+ 
+ 	if (status & MTK_RX_DONE_INT) {
+-		if (likely(napi_schedule_prep(&eth->rx_napi)))
++		if (likely(napi_schedule_prep(&eth->rx_napi))) {
++			mtk_irq_disable(eth, MTK_RX_DONE_INT);
+ 			__napi_schedule(&eth->rx_napi);
+-		mtk_irq_disable(eth, MTK_RX_DONE_INT);
++		}
+ 	}
+ 	mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
+ 
+@@ -1288,9 +1289,10 @@ static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
+ 		return IRQ_NONE;
+ 
+ 	if (status & MTK_TX_DONE_INT) {
+-		if (likely(napi_schedule_prep(&eth->tx_napi)))
++		if (likely(napi_schedule_prep(&eth->tx_napi))) {
++			mtk_irq_disable(eth, MTK_TX_DONE_INT);
+ 			__napi_schedule(&eth->tx_napi);
+-		mtk_irq_disable(eth, MTK_TX_DONE_INT);
++		}
+ 	}
+ 	mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
+ 
+@@ -1382,6 +1384,7 @@ static int mtk_stop(struct net_device *dev)
+ 	struct mtk_mac *mac = netdev_priv(dev);
+ 	struct mtk_eth *eth = mac->hw;
+ 
++	netif_carrier_off(dev);
+ 	netif_tx_disable(dev);
+ 	phy_stop(mac->phy_dev);
+ 
+@@ -1581,11 +1584,13 @@ static int mtk_set_settings(struct net_device *dev,
+ {
+ 	struct mtk_mac *mac = netdev_priv(dev);
+ 
+-	if (cmd->phy_address != mac->phy_dev->mdio.addr) {
+-		mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
+-					       cmd->phy_address);
+-		if (!mac->phy_dev)
++	if (cmd->phy_address != mac->phy_dev->addr) {
++		if (mac->hw->mii_bus->phy_map[cmd->phy_address]) {
++			mac->phy_dev =
++				mac->hw->mii_bus->phy_map[cmd->phy_address];
++		} else {
+ 			return -ENODEV;
++		}
+ 	}
+ 
+ 	return phy_ethtool_sset(mac->phy_dev, cmd);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0091-net-next-mediatek-remove-BQL.patch

@@ -0,0 +1,57 @@
+From 1e1f2c5ea2af34017a398ab11cffac142adea87e Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Sat, 23 Apr 2016 12:57:21 +0200
+Subject: [PATCH 91/91] net-next: mediatek: remove BQL
+
+Signed-off-by: John Crispin <[email protected]>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |   19 -------------------
+ 1 file changed, 19 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index b466f45..68f39ed 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -653,15 +653,6 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
+ 	WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
+ 				(!nr_frags * TX_DMA_LS0)));
+ 
+-	/* we have a single DMA ring so BQL needs to be updated for all devices
+-	 * sitting on this ring
+-	 */
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
+-		if (!eth->netdev[i])
+-			continue;
+-		netdev_sent_queue(dev, skb->len);
+-	}
+-
+ 	skb_tx_timestamp(skb);
+ 
+ 	ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
+@@ -894,7 +885,6 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget)
+ 	unsigned int bytes = 0, done = 0;
+ 	u32 cpu, dma;
+ 	static int condition;
+-	int i;
+ 
+ 	cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
+ 	dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
+@@ -935,15 +925,6 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget)
+ 
+ 	mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
+ 
+-	/* we have a single DMA ring so BQL needs to be updated for all devices
+-	 * sitting on this ring
+-	 */
+-	for (i = 0; i < MTK_MAC_COUNT; i++) {
+-		if (!eth->netdev[i])
+-			continue;
+-		netdev_completed_queue(eth->netdev[i], done, bytes);
+-	}
+-
+ 	/* read hw index again make sure no new tx packet */
+ 	if (cpu == dma && cpu == mtk_r32(eth, MTK_QTX_DRX_PTR))
+ 		mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
+-- 
+1.7.10.4
+