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@@ -19,40 +19,7 @@
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/regmap.h>
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-
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-/* bit numbers of reset control register */
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-#define SYS_CTRL_RST_SCU 0
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-#define SYS_CTRL_RST_COPRO 1
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-#define SYS_CTRL_RST_ARM0 2
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-#define SYS_CTRL_RST_ARM1 3
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-#define SYS_CTRL_RST_USBHS 4
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-#define SYS_CTRL_RST_USBHSPHYA 5
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-#define SYS_CTRL_RST_MACA 6
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-#define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
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-#define SYS_CTRL_RST_PCIEA 7
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-#define SYS_CTRL_RST_SGDMA 8
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-#define SYS_CTRL_RST_CIPHER 9
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-#define SYS_CTRL_RST_DDR 10
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-#define SYS_CTRL_RST_SATA 11
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-#define SYS_CTRL_RST_SATA_LINK 12
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-#define SYS_CTRL_RST_SATA_PHY 13
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-#define SYS_CTRL_RST_PCIEPHY 14
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-#define SYS_CTRL_RST_STATIC 15
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-#define SYS_CTRL_RST_GPIO 16
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-#define SYS_CTRL_RST_UART1 17
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-#define SYS_CTRL_RST_UART2 18
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-#define SYS_CTRL_RST_MISC 19
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-#define SYS_CTRL_RST_I2S 20
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-#define SYS_CTRL_RST_SD 21
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-#define SYS_CTRL_RST_MACB 22
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-#define SYS_CTRL_RST_PCIEB 23
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-#define SYS_CTRL_RST_VIDEO 24
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-#define SYS_CTRL_RST_DDR_PHY 25
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-#define SYS_CTRL_RST_USBHSPHYB 26
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-#define SYS_CTRL_RST_USBDEV 27
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-#define SYS_CTRL_RST_ARMDBG 29
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-#define SYS_CTRL_RST_PLLA 30
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-#define SYS_CTRL_RST_PLLB 31
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+#include <dt-bindings/reset/oxsemi,ox820.h>
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/* bit numbers of clock control register */
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#define SYS_CTRL_CLK_COPRO 0
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@@ -110,33 +77,33 @@ static int oxnas_restart_handle(struct notifier_block *this,
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* Don't touch the DDR interface as things will come to an impromptu stop
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* NB Possibly should be asserting reset for PLLB, but there are timing
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* concerns here according to the docs */
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- value = BIT(SYS_CTRL_RST_COPRO) |
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- BIT(SYS_CTRL_RST_USBHS) |
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- BIT(SYS_CTRL_RST_USBHSPHYA) |
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- BIT(SYS_CTRL_RST_MACA) |
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- BIT(SYS_CTRL_RST_PCIEA) |
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- BIT(SYS_CTRL_RST_SGDMA) |
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- BIT(SYS_CTRL_RST_CIPHER) |
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- BIT(SYS_CTRL_RST_SATA) |
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- BIT(SYS_CTRL_RST_SATA_LINK) |
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- BIT(SYS_CTRL_RST_SATA_PHY) |
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- BIT(SYS_CTRL_RST_PCIEPHY) |
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- BIT(SYS_CTRL_RST_STATIC) |
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- BIT(SYS_CTRL_RST_UART1) |
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- BIT(SYS_CTRL_RST_UART2) |
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- BIT(SYS_CTRL_RST_MISC) |
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- BIT(SYS_CTRL_RST_I2S) |
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- BIT(SYS_CTRL_RST_SD) |
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- BIT(SYS_CTRL_RST_MACB) |
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- BIT(SYS_CTRL_RST_PCIEB) |
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- BIT(SYS_CTRL_RST_VIDEO) |
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- BIT(SYS_CTRL_RST_USBHSPHYB) |
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- BIT(SYS_CTRL_RST_USBDEV);
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+ value = BIT(RESET_LEON) |
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+ BIT(RESET_USBHS) |
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+ BIT(RESET_USBPHYA) |
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+ BIT(RESET_MAC) |
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+ BIT(RESET_PCIEA) |
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+ BIT(RESET_SGDMA) |
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+ BIT(RESET_CIPHER) |
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+ BIT(RESET_SATA) |
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+ BIT(RESET_SATA_LINK) |
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+ BIT(RESET_SATA_PHY) |
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+ BIT(RESET_PCIEPHY) |
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+ BIT(RESET_NAND) |
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+ BIT(RESET_UART1) |
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+ BIT(RESET_UART2) |
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+ BIT(RESET_MISC) |
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+ BIT(RESET_I2S) |
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+ BIT(RESET_SD) |
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+ BIT(RESET_MAC_2) |
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+ BIT(RESET_PCIEB) |
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+ BIT(RESET_VIDEO) |
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+ BIT(RESET_USBPHYB) |
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+ BIT(RESET_USBDEV);
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regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
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/* Release reset to cores as per power on defaults */
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- regmap_write(ctx->sys_ctrl, RST_CLR_REGOFFSET, BIT(SYS_CTRL_RST_GPIO));
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+ regmap_write(ctx->sys_ctrl, RST_CLR_REGOFFSET, BIT(RESET_GPIO));
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/* Disable clocks to cores as per power-on defaults - must leave DDR
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* related clocks enabled otherwise we'll stop rather abruptly. */
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@@ -179,9 +146,9 @@ static int oxnas_restart_handle(struct notifier_block *this,
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* reset is due to power cycling or programatic action, just hit the
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* (self-clearing) CPU reset bit of the block reset register */
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value =
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- BIT(SYS_CTRL_RST_SCU) |
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- BIT(SYS_CTRL_RST_ARM0) |
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- BIT(SYS_CTRL_RST_ARM1);
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+ BIT(RESET_SCU) |
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+ BIT(RESET_ARM0) |
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+ BIT(RESET_ARM1);
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regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
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Daniel Golle