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@@ -10,3 +10,75 @@
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NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
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NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
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#define ATH9K_5GHZ_5470_5850 REG_RULE(5470-10, 5850+10, 40, 0, 30,\
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#define ATH9K_5GHZ_5470_5850 REG_RULE(5470-10, 5850+10, 40, 0, 30,\
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NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
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NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
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+@@ -55,57 +56,56 @@
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+ #define ATH9K_5GHZ_NO_MIDBAND ATH9K_5GHZ_5150_5350, \
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+ ATH9K_5GHZ_5725_5850
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+
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++#define REGD_RULES(...) \
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++ .reg_rules = { __VA_ARGS__ }, \
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++ .n_reg_rules = ARRAY_SIZE(((struct ieee80211_reg_rule[]) { __VA_ARGS__ }))
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++
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+ /* Can be used for:
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+ * 0x60, 0x61, 0x62 */
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+ static const struct ieee80211_regdomain ath_world_regdom_60_61_62 = {
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+- .n_reg_rules = 5,
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+ .alpha2 = "99",
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+- .reg_rules = {
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++ REGD_RULES(
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+ ATH9K_2GHZ_ALL,
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+ ATH9K_5GHZ_ALL,
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+- }
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++ )
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+ };
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+
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+ /* Can be used by 0x63 and 0x65 */
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+ static const struct ieee80211_regdomain ath_world_regdom_63_65 = {
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+- .n_reg_rules = 4,
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+ .alpha2 = "99",
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+- .reg_rules = {
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++ REGD_RULES(
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+ ATH9K_2GHZ_CH01_11,
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+ ATH9K_2GHZ_CH12_13,
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+ ATH9K_5GHZ_NO_MIDBAND,
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+- }
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++ )
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+ };
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+
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+ /* Can be used by 0x64 only */
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+ static const struct ieee80211_regdomain ath_world_regdom_64 = {
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+- .n_reg_rules = 3,
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+ .alpha2 = "99",
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+- .reg_rules = {
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++ REGD_RULES(
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+ ATH9K_2GHZ_CH01_11,
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+ ATH9K_5GHZ_NO_MIDBAND,
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+- }
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++ )
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+ };
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+
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+ /* Can be used by 0x66 and 0x69 */
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+ static const struct ieee80211_regdomain ath_world_regdom_66_69 = {
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+- .n_reg_rules = 3,
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+ .alpha2 = "99",
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+- .reg_rules = {
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++ REGD_RULES(
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+ ATH9K_2GHZ_CH01_11,
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+ ATH9K_5GHZ_ALL,
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+- }
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++ )
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+ };
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+
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+ /* Can be used by 0x67, 0x6A and 0x68 */
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+ static const struct ieee80211_regdomain ath_world_regdom_67_68_6A = {
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+- .n_reg_rules = 4,
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+ .alpha2 = "99",
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+- .reg_rules = {
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++ REGD_RULES(
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+ ATH9K_2GHZ_CH01_11,
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+ ATH9K_2GHZ_CH12_13,
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+ ATH9K_5GHZ_ALL,
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+- }
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++ )
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+ };
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+
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+ static inline bool is_wwr_sku(u16 regd)
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