rockchip: add Orange Pi R1 Plus LTS support

The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
identical to OrangePi R1 Plus.

Tested-by: Volkan Yetik <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>

target/linux/rockchip/armv8/base-files/etc/board.d/01_leds

@@ -11,7 +11,8 @@ case $board in
 friendlyarm,nanopi-r2c|\
 friendlyarm,nanopi-r2s|\
 friendlyarm,nanopi-r4s|\
-xunlong,orangepi-r1-plus)
+xunlong,orangepi-r1-plus|\
+xunlong,orangepi-r1-plus-lts)
 	ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
 	ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1"
 	;;

target/linux/rockchip/armv8/base-files/etc/board.d/02_network

@@ -9,7 +9,8 @@ rockchip_setup_interfaces()
 	case "$board" in
 	friendlyarm,nanopi-r2s|\
 	friendlyarm,nanopi-r4s|\
-	xunlong,orangepi-r1-plus)
+	xunlong,orangepi-r1-plus|\
+	xunlong,orangepi-r1-plus-lts)
 		ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
 		;;
 	*)
@@ -56,7 +57,8 @@ rockchip_setup_macs()
 		wan_mac=$(nanopi_r4s_get_mac wan)
 		lan_mac=$(nanopi_r4s_get_mac lan)
 		;;
-	xunlong,orangepi-r1-plus)
+	xunlong,orangepi-r1-plus|\
+	xunlong,orangepi-r1-plus-lts)
 		wan_mac=$(macaddr_add "$(cat /sys/class/net/eth1/address)" -1)
 		;;
 	esac

target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity

@@ -31,7 +31,8 @@ set_interface_core() {
 case "$(board_name)" in
 friendlyarm,nanopi-r2c|\
 friendlyarm,nanopi-r2s|\
-xunlong,orangepi-r1-plus)
+xunlong,orangepi-r1-plus|\
+xunlong,orangepi-r1-plus-lts)
 	set_interface_core 2 "eth0"
 	set_interface_core 4 "eth1" "xhci-hcd:usb3"
 	;;

target/linux/rockchip/image/armv8.mk

@@ -69,3 +69,12 @@ define Device/xunlong_orangepi-r1-plus
   DEVICE_PACKAGES := kmod-usb-net-rtl8152
 endef
 TARGET_DEVICES += xunlong_orangepi-r1-plus
+
+define Device/xunlong_orangepi-r1-plus-lts
+  DEVICE_VENDOR := Xunlong
+  DEVICE_MODEL := Orange Pi R1 Plus LTS
+  SOC := rk3328
+  IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
+  DEVICE_PACKAGES := kmod-usb-net-rtl8152
+endef
+TARGET_DEVICES += xunlong_orangepi-r1-plus-lts

target/linux/rockchip/patches-5.15/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch

@@ -0,0 +1,71 @@
+From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <[email protected]>
+Date: Sat, 25 Mar 2023 15:40:22 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
+
+The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
+the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
+identical to OrangePi R1 Plus.
+
+Signed-off-by: Tianling Shen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Heiko Stuebner <[email protected]>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../rockchip/rk3328-orangepi-r1-plus-lts.dts  | 40 +++++++++++++++++++
+ 2 files changed, 41 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+@@ -0,0 +1,40 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
++ * (http://www.orangepi.org)
++ *
++ * Copyright (c) 2021-2023 Tianling Shen <[email protected]>
++ */
++
++/dts-v1/;
++#include "rk3328-orangepi-r1-plus.dts"
++
++/ {
++	model = "Xunlong Orange Pi R1 Plus LTS";
++	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
++};
++
++&gmac2io {
++	phy-handle = <&yt8531c>;
++	tx_delay = <0x19>;
++	rx_delay = <0x05>;
++
++	mdio {
++		/delete-node/ ethernet-phy@1;
++
++		yt8531c: ethernet-phy@0 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			reg = <0>;
++
++			motorcomm,clk-out-frequency-hz = <125000000>;
++			motorcomm,keep-pll-enabled;
++			motorcomm,auto-sleep-disabled;
++
++			pinctrl-0 = <&eth_phy_reset_pin>;
++			pinctrl-names = "default";
++			reset-assert-us = <15000>;
++			reset-deassert-us = <50000>;
++			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++		};
++	};
++};

target/linux/rockchip/patches-6.1/008-v6.4-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch

@@ -0,0 +1,71 @@
+From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <[email protected]>
+Date: Sat, 25 Mar 2023 15:40:22 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
+
+The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
+the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
+identical to OrangePi R1 Plus.
+
+Signed-off-by: Tianling Shen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Heiko Stuebner <[email protected]>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../rockchip/rk3328-orangepi-r1-plus-lts.dts  | 40 +++++++++++++++++++
+ 2 files changed, 41 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+@@ -0,0 +1,40 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
++ * (http://www.orangepi.org)
++ *
++ * Copyright (c) 2021-2023 Tianling Shen <[email protected]>
++ */
++
++/dts-v1/;
++#include "rk3328-orangepi-r1-plus.dts"
++
++/ {
++	model = "Xunlong Orange Pi R1 Plus LTS";
++	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
++};
++
++&gmac2io {
++	phy-handle = <&yt8531c>;
++	tx_delay = <0x19>;
++	rx_delay = <0x05>;
++
++	mdio {
++		/delete-node/ ethernet-phy@1;
++
++		yt8531c: ethernet-phy@0 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			reg = <0>;
++
++			motorcomm,clk-out-frequency-hz = <125000000>;
++			motorcomm,keep-pll-enabled;
++			motorcomm,auto-sleep-disabled;
++
++			pinctrl-0 = <&eth_phy_reset_pin>;
++			pinctrl-names = "default";
++			reset-assert-us = <15000>;
++			reset-deassert-us = <50000>;
++			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++		};
++	};
++};