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+/*
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+ * DO NOT MODIFY
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+ *
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+ * Declares the U_BOOT_DRIVER() records and platform data.
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+ * This was generated by dtoc from a .dtb (device tree binary) file.
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+ */
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+
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+/* Allow use of U_BOOT_DRVINFO() in this file */
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+#define DT_PLAT_C
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <dt-structs.h>
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+
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+/*
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+ * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
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+ *
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+ * idx driver_info driver
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+ * --- -------------------- --------------------
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+ * 0: clock_controller_at_ff440000 rockchip_rk3328_cru
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+ * 1: dmc rockchip_rk3328_dmc
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+ * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
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+ * 3: serial_at_ff130000 ns16550_serial
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+ * 4: spi_at_ff190000 rockchip_rk3328_spi
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+ * 5: syscon_at_ff100000 rockchip_rk3328_grf
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+ * --- -------------------- --------------------
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+ */
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+
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+/*
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+ * Node /clock-controller@ff440000 index 0
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+ * driver rockchip_rk3328_cru parent None
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+ */
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+static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
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+ .reg = {0xff440000, 0x1000},
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+ .rockchip_grf = 0x38,
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+};
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+U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
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+ .name = "rockchip_rk3328_cru",
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+ .plat = &dtv_clock_controller_at_ff440000,
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+ .plat_size = sizeof(dtv_clock_controller_at_ff440000),
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+ .parent_idx = -1,
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+};
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+
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+/*
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+ * Node /dmc index 1
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+ * driver rockchip_rk3328_dmc parent None
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+ */
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+static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
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+ .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
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+ 0xff720000, 0x1000, 0xff798000, 0x1000},
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+ .rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
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+ 0x10, 0x10, 0x0, 0x8c48a18a, 0x0, 0x21, 0x482, 0x15,
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+ 0x21a, 0xff, 0x14d, 0x6, 0x1, 0x0, 0x0, 0x0,
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+ 0x43041008, 0x64, 0x140023, 0xd0, 0x220002, 0xd4, 0x10000, 0xd8,
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+ 0x703, 0xdc, 0x830004, 0xe0, 0x10000, 0xe4, 0x70003, 0xf4,
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+ 0xf011f, 0x100, 0x6090b07, 0x104, 0x2020b, 0x108, 0x2030506, 0x10c,
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+ 0x505000, 0x110, 0x3020204, 0x114, 0x1010303, 0x118, 0x2020003, 0x120,
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+ 0x303, 0x138, 0x25, 0x180, 0x3c000f, 0x184, 0x900000, 0x190,
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+ 0x7020000, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0x900090c, 0x244,
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+ 0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
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+ 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0x6, 0x2c,
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+ 0x0, 0x30, 0x3, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
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+ 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
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+ 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
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+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
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+ 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
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+ 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
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+ 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
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+ 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
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+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
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+ 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
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+ 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
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+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
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+ 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
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+ 0x77, 0x77, 0x79, 0x9},
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+};
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+U_BOOT_DRVINFO(dmc) = {
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+ .name = "rockchip_rk3328_dmc",
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+ .plat = &dtv_dmc,
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+ .plat_size = sizeof(dtv_dmc),
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+ .parent_idx = -1,
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+};
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+
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+/*
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+ * Node /mmc@ff500000 index 2
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+ * driver rockchip_rk3288_dw_mshc parent None
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+ */
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+static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
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+ .bus_width = 0x4,
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+ .cap_sd_highspeed = true,
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+ .clocks = {
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+ {0, {317}},
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+ {0, {33}},
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+ {0, {74}},
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+ {0, {78}},},
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+ .disable_wp = true,
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+ .fifo_depth = 0x100,
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+ .interrupts = {0x0, 0xc, 0x4},
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+ .max_frequency = 0x8f0d180,
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+ .pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
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+ .pinctrl_names = "default",
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+ .reg = {0xff500000, 0x4000},
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+ .u_boot_spl_fifo_mode = true,
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+ .vmmc_supply = 0x49,
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+};
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+U_BOOT_DRVINFO(mmc_at_ff500000) = {
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+ .name = "rockchip_rk3288_dw_mshc",
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+ .plat = &dtv_mmc_at_ff500000,
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+ .plat_size = sizeof(dtv_mmc_at_ff500000),
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+ .parent_idx = -1,
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+};
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+
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+/*
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+ * Node /serial@ff130000 index 3
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+ * driver ns16550_serial parent None
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+ */
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+static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
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+ .clock_frequency = 0x16e3600,
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+ .clocks = {
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+ {0, {40}},
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+ {0, {212}},},
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+ .dma_names = {"tx", "rx"},
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+ .dmas = {0x10, 0x6, 0x10, 0x7},
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+ .interrupts = {0x0, 0x39, 0x4},
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+ .pinctrl_0 = 0x24,
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+ .pinctrl_names = "default",
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+ .reg = {0xff130000, 0x100},
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+ .reg_io_width = 0x4,
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+ .reg_shift = 0x2,
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+};
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+U_BOOT_DRVINFO(serial_at_ff130000) = {
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+ .name = "ns16550_serial",
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+ .plat = &dtv_serial_at_ff130000,
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+ .plat_size = sizeof(dtv_serial_at_ff130000),
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+ .parent_idx = -1,
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+};
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+
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+/* Node /spi@ff190000 index 4 */
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+static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
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+ .clocks = {
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+ {0, {32}},
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+ {0, {209}},},
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+ .dma_names = {"tx", "rx"},
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+ .dmas = {0x10, 0x8, 0x10, 0x9},
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+ .interrupts = {0x0, 0x31, 0x4},
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+ .pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f},
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+ .pinctrl_names = "default",
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+ .reg = {0xff190000, 0x1000},
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+};
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+U_BOOT_DRVINFO(spi_at_ff190000) = {
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+ .name = "rockchip_rk3328_spi",
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+ .plat = &dtv_spi_at_ff190000,
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+ .plat_size = sizeof(dtv_spi_at_ff190000),
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+ .parent_idx = -1,
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+};
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+
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+/*
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+ * Node /syscon@ff100000 index 5
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+ * driver rockchip_rk3328_grf parent None
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+ */
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+static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
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+ .reg = {0xff100000, 0x1000},
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+};
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+U_BOOT_DRVINFO(syscon_at_ff100000) = {
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+ .name = "rockchip_rk3328_grf",
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+ .plat = &dtv_syscon_at_ff100000,
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+ .plat_size = sizeof(dtv_syscon_at_ff100000),
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+ .parent_idx = -1,
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+};
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+
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Tianling Shen