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@@ -0,0 +1,741 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/* Copyright (c) 2024, Robert Marko <[email protected]> */
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+
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+/dts-v1/;
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+
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+#include "ipq8074.dtsi"
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+#include "ipq8074-hk-cpu.dtsi"
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+#include "ipq8074-ess.dtsi"
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/leds/common.h>
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+
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+/ {
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+ model = "Asus RT-AX89X";
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+ compatible = "asus,rt-ax89x", "qcom,ipq8074";
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+
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+ aliases {
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+ serial0 = &blsp1_uart5;
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+ mdio-gpio0 = &mdio1;
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+ ethernet0 = &dp1;
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+ ethernet1 = &dp2;
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+ ethernet2 = &dp3;
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+ ethernet3 = &dp4;
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+ ethernet4 = &dp5_syn;
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+ ethernet5 = &dp6_syn;
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+ led-boot = &led_pwr;
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+ led-failsafe = &led_pwr;
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+ led-running = &led_pwr;
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+ led-upgrade = &led_pwr;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ /* We have to override root and ubi device passed by bootloader */
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+ bootargs-append = " ubi.block=0,jffs2 root=/dev/ubiblock0_4";
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+ };
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+
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+ keys {
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+ compatible = "gpio-keys";
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+ pinctrl-0 = <&button_pins>;
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+ pinctrl-names = "default";
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+
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+ wifi-button {
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+ label = "wifi";
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+ gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_WLAN>;
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+ };
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+
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+ reset-button {
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+ label = "reset";
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+ gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_RESTART>;
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+ };
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+
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+ wps-button {
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+ label = "wps";
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+ gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_WPS_BUTTON>;
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+ };
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+
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+ led-button {
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+ label = "led";
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+ gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_LIGHTS_TOGGLE>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ pinctrl-0 = <&led_pins>;
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+ pinctrl-names = "default";
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+
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+ led_pwr: led-pwr {
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+ function = LED_FUNCTION_POWER;
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+ gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
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+ color = <LED_COLOR_ID_WHITE>;
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+ };
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+
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+ led-2g {
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+ function = LED_FUNCTION_WLAN_2GHZ;
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+ gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
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+ color = <LED_COLOR_ID_WHITE>;
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+ linux,default-trigger = "phy0radio";
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+ };
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+
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+ led-5g {
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+ function = LED_FUNCTION_WLAN_5GHZ;
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+ gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
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+ color = <LED_COLOR_ID_WHITE>;
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+ linux,default-trigger = "phy1radio";
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+ };
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+
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+ led-10g-copper {
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+ function = "aqr10g";
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+ gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
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+ color = <LED_COLOR_ID_WHITE>;
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+ };
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+
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+ led-lan {
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+ function = LED_FUNCTION_LAN;
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+ gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
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+ color = <LED_COLOR_ID_WHITE>;
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+ };
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+
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+ led-sfp {
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+ function = "sfp";
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+ gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
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+ color = <LED_COLOR_ID_WHITE>;
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+ };
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+
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+ led-wan-red {
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+ function = LED_FUNCTION_WAN;
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+ gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
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+ color = <LED_COLOR_ID_RED>;
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+ };
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+
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+ led-wan-white {
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+ function = LED_FUNCTION_WAN;
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+ gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
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+ color = <LED_COLOR_ID_WHITE>;
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+ };
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+ };
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+
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+ gpio_fan: gpio-fan {
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+ compatible = "gpio-fan";
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+ pinctrl-0 = <&fan_pins>;
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+ pinctrl-names = "default";
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+ gpios = <&tlmm 64 GPIO_ACTIVE_HIGH
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+ &tlmm 66 GPIO_ACTIVE_HIGH>;
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+ /*
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+ * Not supported upstream, but good to document for
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+ * future uses.
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+ * It seems that Delta AFB0712VHB fan has its tacho
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+ * output connected to GPIO 65.
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+ */
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+ //rpm-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
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+ gpio-fan,speed-map = < 0 0
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+ 1600 1
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+ 1850 2
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+ 2100 3 >;
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+ #cooling-cells = <2>;
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+ };
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+
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+ usb0_vbus: regulator-usb0-vbus {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb0_vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ gpio = <&tlmm 30 GPIO_ACTIVE_HIGH>;
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+ enable-active-high;
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+ regulator-boot-on;
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+ };
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+
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+ usb1_vbus: regulator-usb1-vbus {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb1_vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
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+ enable-active-high;
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+ regulator-boot-on;
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+ };
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+
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+ output-usb0-power {
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+ compatible = "regulator-output";
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+ vout-supply = <&usb0_vbus>;
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+ };
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+
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+ output-usb1-power {
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+ compatible = "regulator-output";
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+ vout-supply = <&usb1_vbus>;
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+ };
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+};
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+
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+&cpu0_thermal {
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+ trips {
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+ cpu0_active: cpu-active {
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+ temperature = <70000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map2 {
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+ trip = <&cpu0_active>;
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+ cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+};
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+
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+&cpu1_thermal {
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+ trips {
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+ cpu1_active: cpu-active {
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+ temperature = <70000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map2 {
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+ trip = <&cpu1_active>;
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+ cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+};
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+
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+&cpu2_thermal {
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+ trips {
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+ cpu2_active: cpu-active {
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+ temperature = <70000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map2 {
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+ trip = <&cpu2_active>;
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+ cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+};
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+
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+&cpu3_thermal {
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+ trips {
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+ cpu3_active: cpu-active {
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+ temperature = <70000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map2 {
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+ trip = <&cpu3_active>;
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+ cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+};
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+
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+&cluster_thermal {
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+ trips {
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+ cluster_active: cluster-active {
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+ temperature = <70000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map2 {
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+ trip = <&cluster_active>;
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+ cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+};
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+
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+&tlmm {
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+ button_pins: button-state {
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+ pins = "gpio25", "gpio26", "gpio34", "gpio61";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+
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+ i2c_pins: i2c-pins {
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+ pins = "gpio42", "gpio43";
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+ function = "blsp1_i2c";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ mdio_pins: mdio-pins {
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+ mdc {
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+ pins = "gpio68";
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+ function = "mdc";
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+ drive-strength = <16>;
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+ bias-pull-up;
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+ };
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+
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+ mdio {
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+ pins = "gpio69";
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+ function = "mdio";
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+ drive-strength = <16>;
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+ bias-pull-up;
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+ };
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+ };
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+
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+ mdio_gpio_pins: mdio-gpio-pins {
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+ pins = "gpio54", "gpio56";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+
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+ uniphy_pins: uniphy_pinmux {
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+ mux {
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+ pins = "gpio60";
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+ function = "rx2";
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+ bias-disable;
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+ };
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+
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+ sfp_tx_disable {
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+ pins = "gpio48";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ output-low;
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+ };
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+
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+ sfp_tx_fault {
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+ pins = "gpio62";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ output-high;
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+ };
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+
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+ sfp_mod_def0 {
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+ pins = "gpio46";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+ };
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+
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+ led_pins: led-state {
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+ power {
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+ pins = "gpio21";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+
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+ default_off {
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+ pins = "gpio18", "gpio19", "gpio20", "gpio47",
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+ "gpio44", "gpio35", "gpio36";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+ };
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+
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+ fan_pins: fan-state {
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+ pins = "gpio64", "gpio66";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-disable;
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+ output-high;
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+ };
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+};
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+
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+&blsp1_uart5 {
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+ status = "okay";
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+};
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+
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+&prng {
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+ status = "okay";
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+};
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+
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+&cryptobam {
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+ status = "okay";
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+};
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+
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+&crypto {
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+ status = "okay";
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+};
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+
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+&ssphy_0 {
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+ status = "okay";
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+};
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+
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+&qusb_phy_0 {
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+ status = "okay";
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+};
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+
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+&ssphy_1 {
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+ status = "okay";
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+};
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+
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+&qusb_phy_1 {
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+ status = "okay";
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+};
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+
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+&usb_0 {
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+ status = "okay";
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+};
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+
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+&usb_1 {
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+ status = "okay";
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+};
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+
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+&qpic_bam {
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+ status = "okay";
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+};
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+
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+&qpic_nand {
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+ status = "okay";
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+
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+ nand@0 {
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+ reg = <0>;
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ nand-bus-width = <8>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "0:sbl1";
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+ reg = <0x0 0x60000>;
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+ read-only;
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+ };
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+
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+ partition@60000 {
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+ label = "0:mibib";
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+ reg = <0x00060000 0x40000>;
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+ read-only;
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+ };
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+
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+ partition@a0000 {
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+ label = "0:qsee";
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+ reg = <0x000a0000 0x1e0000>;
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+ read-only;
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+ };
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+
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+ partition@280000 {
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+ label = "0:devcfg";
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+ reg = <0x00280000 0x20000>;
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+ read-only;
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+ };
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+
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+ partition@2a0000 {
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+ label = "0:apdp";
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+ reg = <0x002a0000 0x20000>;
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+ read-only;
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+ };
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+
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+ partition@2c0000 {
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+ label = "0:rpm";
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+ reg = <0x002c0000 0x40000>;
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+ read-only;
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+ };
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+
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+ partition@300000 {
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+ label = "0:cdt";
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+ reg = <0x00300000 0x20000>;
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+ read-only;
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+ };
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+
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+ partition@320000 {
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+ label = "0:appsbl";
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+ reg = <0x00320000 0xc0000>;
|
|
|
+ read-only;
|
|
|
+ };
|
|
|
+
|
|
|
+ partition@3e0000 {
|
|
|
+ label = "0:appsblenv";
|
|
|
+ reg = <0x003e0000 0x20000>;
|
|
|
+ };
|
|
|
+
|
|
|
+ partition@400000 {
|
|
|
+ compatible = "linux,ubi";
|
|
|
+ label = "UBI_DEV";
|
|
|
+ reg = <0x00400000 0xfc00000>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&blsp1_i2c2 {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&mdio {
|
|
|
+ status = "okay";
|
|
|
+
|
|
|
+ pinctrl-0 = <&mdio_pins>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
|
|
|
+
|
|
|
+ qca8337_0: ethernet-phy@0 {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0x0>;
|
|
|
+ };
|
|
|
+
|
|
|
+ qca8337_1: ethernet-phy@1 {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0x1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ qca8337_2: ethernet-phy@2 {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0x2>;
|
|
|
+ };
|
|
|
+
|
|
|
+ qca8337_3: ethernet-phy@3 {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0x3>;
|
|
|
+ };
|
|
|
+
|
|
|
+ qca8337_4: ethernet-phy@4 {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0x4>;
|
|
|
+ };
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Vendor bootloader has path for ethernet-phy@5 hardcoded
|
|
|
+ * and if its there it will delete the node, but since we
|
|
|
+ * need the QCA8035 for DSA lets fool the bootloader by using
|
|
|
+ * ethernet-phy@05 even though it causes DTC to print a warning.
|
|
|
+ */
|
|
|
+ qca8035: ethernet-phy@05 {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0x5>;
|
|
|
+ };
|
|
|
+
|
|
|
+ qca8033: ethernet-phy@6 {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0x6>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ethernet-phy-package@8 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ compatible = "qcom,qca8075-package";
|
|
|
+ reg = <8>;
|
|
|
+
|
|
|
+ qcom,package-mode = "qsgmii";
|
|
|
+
|
|
|
+ qca8075_8: ethernet-phy@8 {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0x8>;
|
|
|
+ };
|
|
|
+
|
|
|
+ qca8075_9: ethernet-phy@9 {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0x9>;
|
|
|
+ };
|
|
|
+
|
|
|
+ qca8075_a: ethernet-phy@a {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0xa>;
|
|
|
+ };
|
|
|
+
|
|
|
+ qca8075_b: ethernet-phy@b {
|
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
+ reg = <0xb>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qca8337: switch@10 {
|
|
|
+ compatible = "qca,qca8337";
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ reg = <0x10>;
|
|
|
+
|
|
|
+ ports {
|
|
|
+ port@0 {
|
|
|
+ reg = <0>;
|
|
|
+ label = "cpu";
|
|
|
+ ethernet = <&dp1>;
|
|
|
+ phy-mode = "rgmii-rxid";
|
|
|
+ phy-handle = <&qca8035>;
|
|
|
+ };
|
|
|
+
|
|
|
+ port@1 {
|
|
|
+ reg = <1>;
|
|
|
+ label = "lan7";
|
|
|
+ phy-handle = <&qca8337_0>;
|
|
|
+ };
|
|
|
+
|
|
|
+ port@2 {
|
|
|
+ reg = <2>;
|
|
|
+ label = "lan6";
|
|
|
+ phy-handle = <&qca8337_1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ port@3 {
|
|
|
+ reg = <3>;
|
|
|
+ label = "lan5";
|
|
|
+ phy-handle = <&qca8337_2>;
|
|
|
+ };
|
|
|
+
|
|
|
+ port@4 {
|
|
|
+ reg = <4>;
|
|
|
+ label = "lan4";
|
|
|
+ phy-handle = <&qca8337_3>;
|
|
|
+ };
|
|
|
+
|
|
|
+ port@5 {
|
|
|
+ reg = <5>;
|
|
|
+ label = "lan3";
|
|
|
+ phy-handle = <&qca8337_4>;
|
|
|
+ };
|
|
|
+
|
|
|
+ port@6 {
|
|
|
+ reg = <6>;
|
|
|
+ label = "lan8";
|
|
|
+ phy-mode = "sgmii";
|
|
|
+ phy-handle = <&qca8033>;
|
|
|
+ managed = "in-band-status";
|
|
|
+ qca,sgmii-enable-pll;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&soc {
|
|
|
+ /*
|
|
|
+ * This is techically incorrect and will cause a DTC warning as
|
|
|
+ * all nodes under a bus are supposed to have addresses as well
|
|
|
+ * but its required as bootloader has this path hardcoded in
|
|
|
+ * order to enable AQR113C on newer revisions.
|
|
|
+ */
|
|
|
+ mdio1: mdio1 {
|
|
|
+ compatible = "virtual,mdio-gpio";
|
|
|
+ pinctrl-0 = <&mdio_gpio_pins>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>,
|
|
|
+ <&tlmm 54 GPIO_ACTIVE_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * PCB R5.00, AQR113C
|
|
|
+ * No idea why the bitbanged this one.
|
|
|
+ * @5 is wrong, but their bootloader has it hardcoded in
|
|
|
+ * order to dynamically enable the PHY for newer HW.
|
|
|
+ */
|
|
|
+ aqr113c: ethernet-phy@5 {
|
|
|
+ status = "disabled";
|
|
|
+ compatible ="ethernet-phy-ieee802.3-c45";
|
|
|
+ reg = <8>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&switch {
|
|
|
+ status = "okay";
|
|
|
+
|
|
|
+ pinctrl-0 = <&uniphy_pins>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+
|
|
|
+ switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT5 | ESS_PORT6)>; /* lan port bitmap */
|
|
|
+ switch_wan_bmp = <ESS_PORT4>; /* wan port bitmap */
|
|
|
+ switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
|
|
|
+ switch_mac_mode1 = <MAC_MODE_10GBASE_R>; /* mac mode for uniphy instance1*/
|
|
|
+ switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
|
|
|
+
|
|
|
+ qcom,port_phyinfo {
|
|
|
+ port@0 {
|
|
|
+ port_id = <1>;
|
|
|
+ phy_address = <0x8>;
|
|
|
+ };
|
|
|
+ port@1 {
|
|
|
+ port_id = <2>;
|
|
|
+ phy_address = <0x9>;
|
|
|
+ };
|
|
|
+ port@2 {
|
|
|
+ port_id = <3>;
|
|
|
+ phy_address = <0xa>;
|
|
|
+ };
|
|
|
+ port@3 {
|
|
|
+ port_id = <4>;
|
|
|
+ phy_address = <0xb>;
|
|
|
+ };
|
|
|
+
|
|
|
+ sfp: port@4 {
|
|
|
+ port_id = <5>;
|
|
|
+ phy_address = <30>;
|
|
|
+ phy_i2c_address = <30>;
|
|
|
+ phy-i2c-mode; /*i2c access phy */
|
|
|
+ media-type = "sfp"; /* fiber mode */
|
|
|
+ sfp_tx_dis_pin = <&tlmm 48 GPIO_ACTIVE_HIGH>;
|
|
|
+ sfp_mod_present_pin = <&tlmm 46 GPIO_ACTIVE_LOW>;
|
|
|
+ };
|
|
|
+
|
|
|
+ /* PCB R5.00, AQR113C */
|
|
|
+ port@5_113c {
|
|
|
+ status = "disabled";
|
|
|
+ port_id = <6>;
|
|
|
+ phy_address = <8>;
|
|
|
+ ethernet-phy-ieee802.3-c45;
|
|
|
+ mdiobus = <&mdio1>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+&edma {
|
|
|
+ status = "okay";
|
|
|
+};
|
|
|
+
|
|
|
+&dp1 {
|
|
|
+ status = "okay";
|
|
|
+ phy-mode = "qsgmii";
|
|
|
+ phy-handle = <&qca8075_8>;
|
|
|
+ label = "switch";
|
|
|
+};
|
|
|
+
|
|
|
+&dp2 {
|
|
|
+ status = "okay";
|
|
|
+ phy-mode = "qsgmii";
|
|
|
+ phy-handle = <&qca8075_9>;
|
|
|
+ label = "lan2";
|
|
|
+};
|
|
|
+
|
|
|
+&dp3 {
|
|
|
+ status = "okay";
|
|
|
+ phy-mode = "qsgmii";
|
|
|
+ phy-handle = <&qca8075_a>;
|
|
|
+ label = "lan1";
|
|
|
+};
|
|
|
+
|
|
|
+&dp4 {
|
|
|
+ status = "okay";
|
|
|
+ phy-mode = "qsgmii";
|
|
|
+ phy-handle = <&qca8075_b>;
|
|
|
+ label = "wan";
|
|
|
+};
|
|
|
+
|
|
|
+&dp5_syn {
|
|
|
+ status = "okay";
|
|
|
+ phy-handle = <&sfp>;
|
|
|
+ label = "10g-sfp";
|
|
|
+};
|
|
|
+
|
|
|
+&dp6_syn {
|
|
|
+ status = "okay";
|
|
|
+ phy-handle = <&aqr113c>;
|
|
|
+ label = "10g-copper";
|
|
|
+};
|
|
|
+
|
|
|
+&wifi {
|
|
|
+ status = "okay";
|
|
|
+ qcom,ath11k-calibration-variant = "Asus-RT-AX89X";
|
|
|
+};
|