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@@ -0,0 +1,328 @@
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+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
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+/*
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+ * WatchGuard Firebox M300 Device Tree Source
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+ * Based on t2081qds.dts from Linux 5.10
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+ *
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+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
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+ * Copyright 2020 - 2021 Stijn Tintel <[email protected]>
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+ */
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+
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+/include/ "t208xsi-pre.dtsi"
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+/include/ "t208xqds.dtsi"
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+
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+/ {
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+ model = "WatchGuard Firebox M300";
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+ compatible = "watchguard,firebox-m300", "fsl,T2081QDS";
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+
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+ interrupt-parent = <&mpic>;
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+
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+ aliases {
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+ /delete-property/ ethernet0;
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+ /delete-property/ ethernet1;
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+ /delete-property/ ethernet2;
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+ /delete-property/ ethernet3;
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+ /delete-property/ ethernet4;
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+ /delete-property/ ethernet5;
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+ /delete-property/ ethernet6;
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+ /delete-property/ ethernet7;
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+
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+ ethernet0 = &enet7;
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+ ethernet1 = &enet0;
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+ ethernet2 = &enet1;
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+ ethernet3 = &enet2;
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+ ethernet4 = &enet3;
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+ };
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+};
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+
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+&soc {
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+// Include first to make this the first interface
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+/include/ "qoriq-fman3-0-10g-1.dtsi"
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+};
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+
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+// mdio-mux under &boardctrl + its aliases removed. causes crash:
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+// Oops: Machine check, sig: 7 [#1]
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+
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+/include/ "t2081si-post.dtsi"
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+
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+// add stuff below the include to make sure we override whatever is there
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+
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+&enet0 {
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+ phy-connection-type = "sgmii";
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+ phy-handle = <&phy1>;
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+};
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+
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+&enet1 {
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+ phy-connection-type = "sgmii";
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+ phy-handle = <&phy2>;
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+};
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+
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+&enet2 {
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+ phy-connection-type = "rgmii";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+};
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+
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+&enet3 {
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+ phy-connection-type = "rgmii";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+};
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+
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+&enet4 {
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+ status = "disabled";
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+};
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+
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+&enet5 {
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+ status = "disabled";
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+};
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+
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+&enet6 {
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+ status = "disabled";
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+};
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+
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+&enet7 {
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+ phy-connection-type = "sgmii";
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+ phy-handle = <&phy0>;
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+};
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+
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+&ifc {
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+ ranges = <0x00 0x00 0x0f 0xefc00000 0x400000>;
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+
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+ nor@0,0 {
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+ reg = <0x00 0x00 0x400000>;
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+
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+ partition@0{
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+ reg = <0x0 0x10000>;
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+ label = "qoriq-rcw";
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+ read-only;
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+ };
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+
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+ partition@10000 {
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+ reg = <0x10000 0x20000>;
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+ label = "wg_cfg0";
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+ read-only;
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+ };
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+
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+ partition@30000 {
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+ reg = <0x30000 0x10000>;
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+ label = "wg_cfg1";
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+ read-only;
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+ };
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+
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+ partition@40000 {
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+ reg = <0x40000 0x10000>;
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+ label = "wg_mfg_data";
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+ read-only;
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+ };
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+
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+ partition@50000 {
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+ reg = <0x50000 0xb0000>;
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+ label = "wg_bootopt_data_and_reserved";
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+ read-only;
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+ };
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+
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+ partition@100000 {
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+ reg = <0x100000 0xb0000>;
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+ label = "wg_extra_reserved_1";
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+ read-only;
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+ };
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+
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+ partition@1B0000 {
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+ reg = <0x1b0000 0xb0000>;
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+ label = "wg_extra_reserved_2";
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+ read-only;
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+ };
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+
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+ partition@260000 {
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+ reg = <0x260000 0xc0000>;
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+ label = "wg_u-boot_failsafe";
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+ read-only;
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+ };
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+
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+ partition@320000 {
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+ reg = <0x320000 0x10000>;
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+ label = "qoriq-fman";
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+ read-only;
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+ };
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+
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+ partition@330000 {
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+ reg = <0x330000 0x10000>;
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+ label = "u-boot-env";
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+ };
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+
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+ partition@340000 {
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+ reg = <0x340000 0xc0000>;
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+ label = "u-boot";
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+ read-only;
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+ };
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+ };
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+
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+ nand@2,0 {
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+ status = "disabled";
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+ };
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+};
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+
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+&mdio0 {
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+ // m300 ethernet port 0
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+ phy0: ethernet-phy@0 {
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+ reg = <0x00>;
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+ };
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+
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+ // m300 ethernet port 1
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+ phy1: ethernet-phy@1 {
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+ reg = <0x01>;
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+ };
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+
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+ phy2: ethernet-phy@2 {
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+ reg = <0x02>;
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+ };
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+
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+ phy3: ethernet-phy@3 {
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+ reg = <0x03>;
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+ };
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+
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+ switch0: switch@10 {
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+ compatible = "marvell,mv88e6085";
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+ reg = <0x10>;
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ switch0phy0: switch0phy0@0 {
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+ reg = <0x00>;
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+ interrupt-parent = <&switch0>;
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+ };
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+
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+ switch0phy1: switch0phy1@1 {
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+ reg = <0x01>;
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+ interrupt-parent = <&switch0>;
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+ };
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+
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+ switch0phy2: switch0phy2@2 {
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+ reg = <0x02>;
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+ interrupt-parent = <&switch0>;
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+ };
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+
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+ switch0phy3: switch0phy3@3 {
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+ reg = <0x03>;
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+ interrupt-parent = <&switch0>;
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+ };
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+
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+ switch0phy4: switch0phy4@4 {
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+ reg = <0x04>;
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+ interrupt-parent = <&switch0>;
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+ };
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+ };
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "sweth3";
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+ phy-handle = <&switch0phy0>;
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "sweth4";
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+ phy-handle = <&switch0phy1>;
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "sweth5";
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+ phy-handle = <&switch0phy2>;
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "sweth6";
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+ phy-handle = <&switch0phy3>;
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "sweth7";
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+ phy-handle = <&switch0phy4>;
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+ };
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+
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+ // OEM bootlog suggests multiple ports are attached to switch
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+ // Keep this until OEM supplies GPL sources
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+ port@5 {
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+ status = "disabled";
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+
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+ reg = "<5>";
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+ label = "cpu";
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+ ethernet = <&enet2>;
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+ phy-mode = "rgmii-id";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ label = "cpu";
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+ ethernet = <&enet3>;
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+ phy-mode = "rgmii-id";
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+ };
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+ };
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+};
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+
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+&soc {
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+ i2c@118000 {
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+ tpm@29 {
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+ compatible = "tpm,tpm_i2c_atmel";
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+ reg = <0x29>;
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+ };
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+ hwmon@2c {
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+ compatible = "winbond,w83793";
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+ reg = <0x2c>;
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+ };
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+ hwmon@2d {
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+ compatible = "winbond,w83793";
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+ reg = <0x2d>;
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+ };
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+ rtc@32 {
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+ compatible = "ricoh,rs5c372a";
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+ reg = <0x32>;
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+ };
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+ pca9547@77 {
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+ status = "disabled";
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+ };
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+ };
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+
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+ spi@110000 {
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+ // DTS decompiled from OEM DTB contains flash@0 but doesn't work
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+ // spi-nor spi0.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff
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+ // disable for now
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+ flash@0 {
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+ status = "disabled";
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+ };
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+
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+ flash@1 {
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+ status = "disabled";
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+ };
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+
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+ flash@2 {
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+ status = "disabled";
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+ };
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+ };
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+};
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