qualcommax: ipq50xx: backport upstreamed patch for adding ipq5018 UART2 node

Add node to support the second UART node controller in IPQ5018.

Signed-off-by: George Moussalem <[email protected]>
Link: https://github.com/openwrt/openwrt/pull/20090
Signed-off-by: Robert Marko <[email protected]>

target/linux/qualcommax/patches-6.12/0070-arm64-dts-qcom-ipq5018-add-QUP1-UART2-node.patch

@@ -0,0 +1,36 @@
+From b410d25fb349bc32132749bd2cb17aa17054287d Mon Sep 17 00:00:00 2001
+From: Manikanta Mylavarapu <[email protected]>
+Date: Wed, 17 Sep 2025 15:49:00 +0400
+Subject: arm64: dts: qcom: ipq5018: add QUP1 UART2 node
+
+Add node to support the second UART node controller in IPQ5018.
+
+Signed-off-by: Manikanta Mylavarapu <[email protected]>
+Signed-off-by: George Moussalem <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Bjorn Andersson <[email protected]>
+---
+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
+
+--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+@@ -490,6 +490,16 @@
+ 			status = "disabled";
+ 		};
+ 
++		blsp1_uart2: serial@78b0000 {
++			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
++			reg = <0x078b0000 0x200>;
++			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
++				 <&gcc GCC_BLSP1_AHB_CLK>;
++			clock-names = "core", "iface";
++			status = "disabled";
++		};
++
+ 		blsp1_spi1: spi@78b5000 {
+ 			compatible = "qcom,spi-qup-v2.2.1";
+ 			#address-cells = <1>;

target/linux/qualcommax/patches-6.12/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch

@@ -1,27 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add QUP1-UART2 node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add QUP1-UART2 node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -500,6 +500,16 @@
- 			status = "disabled";
- 		};
- 
-+		blsp1_uart2: serial@78b0000 {
-+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+			reg = <0x078b0000 0x200>;
-+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
-+					<&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			status = "disabled";
-+		};
-+
- 		blsp1_spi1: spi@78b5000 {
- 			compatible = "qcom,spi-qup-v2.2.1";
- 			#address-cells = <1>;