realtek: add support for D-Link DGS-1250-28X

Hardware specification
----------------------

* RTL9301 SoC, 1 MIPS 34KEc core @ 800MHz
* 512MB DRAM
* 64MB NAND Flash
* 24 x 10/100/1000BASE-T ports
* 4 x 10G SFP+ ports
* Power LED, Console LED, Fan Fault LED
* Reset button on front panel
* LM75 temperature sensor
* Atmel AT24C02 2kb eeprom
* fan (controllable via gpio for on/off and LM75 for low/high speed)
* UART (115200 8N1) via RJ45

Installation using serial interface
-----------------------------------

 1. Prepare TFTP server & connect to serial port.
 2. Connect DGS-1250 to your computer or network with one of the
    1G ports. All of them will be fine.
 3. Power on DGS-1250 and interrupt autoboot with "&".
 4. Change U-Boot startup sequence
	> setenv silent
	> setenv bootcmd 'cp.l 0xb4200000 0x84000000 0x300000; bootm 0x84000000'
	> saveenv
 5. Enable networking within U-Boot.
	> rtk network on
 6. Set switch IP and TFTP server IP (optional, adjust to your setup).
	> setenv ipaddr <ip>
	> setenv serverip <ip>
 7. Download initramfs image from TFTP server.
	> tftpboot 0x84000000 <image name>
 8. Boot with the downloaded image.
	> bootm 0x84000000
 9. With rambooted OpenWrt, backup the stock firmware.
    THIS IS CRITICAL! /dev/mtd3 contains data that is not provided
    in the downloadable vendor firmware images.
10. Copy sysupgrade image to the device.
11. Perform sysupgrade with the sysupgrade image.
12. After reboot, you should have functional OpenWrt.

Installation using OEM webinterface
-----------------------------------

This is not possible because the vendor image uses a ubifs based
loading technique with encrypted images. To be precise the boot
sequence basically runs as follows.

 1. U-Boot starts
 2. U-Boot mounts 62MB ubifs from mtd3
 3. U-Boot reads Linux kernel from file uImage inside ubifs
 4. Linux starts (this is a initramfs image)
 5. Linux mounts ubifs
 6. Linux calls a loader binary
 7. Depending on current configuration first (file Image1) or
    second firmware image (file Image2) is loaded and decrypted
 8. Inside the decrpyted firmware image there is a executable
    named “switch”
 9. "switch" executable is run and the switch comes alive

Reverting to stock firmware
---------------------------

 1. Boot OpenWrt from initramfs (like in installation section above)
 2. Restore partition /dev/mtd3 from backup
 3. Erase Openwrt special U-Boot env
	# mtd erase mtd1
 4. reboot

Further information
-------------------

Wiki: https://openwrt.org/toh/d-link/dgs-1250
Forum: https://forum.openwrt.org/t/support-for-d-link-dgs-1250-switches
Partition dumps: https://github.com/plappermaul/realtek-doc/tree/main/DGS-1250

Signed-off-by: Markus Stockhausen <[email protected]>
Link: https://github.com/openwrt/openwrt/pull/22530
Signed-off-by: Hauke Mehrtens <[email protected]>

target/linux/realtek/base-files/etc/board.d/02_network

@@ -74,6 +74,7 @@ realtek_setup_macs()
 		lan_mac=$(get_mac_label)
 		lan_mac_start=$lan_mac
 		;;
+	d-link,dgs-1250-28x|\
 	hasivo,s1100wp-8gt-se|\
 	hpe,1920-8g|\
 	hpe,1920-8g-poe-65w|\

target/linux/realtek/base-files/etc/init.d/hwmon_fancontrol

@@ -35,11 +35,25 @@ plasmacloud_common() {
 	echo 2 > "$path_to_hwmon/pwm2_enable"
 }
 
+dlink_dgs_1250() {
+	local path_temp_hwmon="$(find /sys/devices/platform/i2c-gpio-4/i2c-4/4-0048/hwmon/ -type d -maxdepth 1 -mindepth 1 -name 'hwmon*')"
+	local path_fan_hwmon="$(find /sys/devices/platform/gpio-fan/hwmon/ -type d -maxdepth 1 -mindepth 1 -name 'hwmon*')"
+
+	# Activate fan and let LM75 steer high/low speed via alert pin
+	# vendor defaults for DGS-1250-28X are 69C low->high and 57C high->low
+	echo 1 > "$path_fan_hwmon/fan1_target"
+	echo 69000 > "$path_temp_hwmon/temp1_max"
+	echo 57000 > "$path_temp_hwmon/temp1_max_hyst"
+}
+
 boot() {
 	case $(board_name) in
 	plasmacloud,esx28|\
 	plasmacloud,psx28)
 		plasmacloud_common
 		;;
+	d-link,dgs-1250-28x)
+		dlink_dgs_1250
+		;;
 	esac
 }

target/linux/realtek/dts/rtl9301_d-link_dgs-1250-28x.dts

@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later or MIT)
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "rtl930x.dtsi"
+
+/ {
+	compatible = "d-link,dgs-1250-28x", "realtek,rtl9301-soc";
+	model = "D-Link DGS-1250-28X";
+
+	aliases {
+		label-mac-device = &ethernet0;
+		led-boot = &led_power;
+		led-failsafe = &led_console;
+		led-running = &led_power;
+		led-upgrade = &led_console;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	fan: gpio-fan {
+		compatible = "gpio-fan";
+		gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+		alarm-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+		/* simple on/off values as LM75 alert pin steers fan high/low speed */
+		gpio-fan,speed-map = <0 0>, <1 1>;
+		#cooling-cells = <2>;
+	};
+
+	i2c-gpio-shared {
+		compatible = "i2c-gpio-shared";
+		scl-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c0: i2c@0 {
+			sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+			i2c-gpio,delay-us = <5>;
+		};
+
+		i2c1: i2c@1 {
+			sda-gpios = <&gpio0 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+			i2c-gpio,delay-us = <5>;
+		};
+
+		i2c2: i2c@2 {
+			sda-gpios = <&gpio0 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+			i2c-gpio,delay-us = <5>;
+		};
+
+		i2c3: i2c@3 {
+			sda-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+			i2c-gpio,delay-us = <5>;
+		};
+	};
+
+	i2c4: i2c-gpio-4 {
+		compatible = "i2c-gpio";
+		sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		i2c-gpio,delay-us = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		gpio1: gpio-expander@20 {
+			compatible = "nxp,pca9555";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		temperature_sensor: temperature-sensor@48 {
+			compatible = "microchip,tcn75";
+			reg = <0x48>;
+			#thermal-sensor-cells = <0>;
+			alert-polarity-active-high;
+		};
+
+		eeprom@50 {
+			compatible = "atmel,24c02";
+			reg = <0x50>;
+			read-only;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				mac_address: mac-address@10 {
+					reg = <0x10 0x6>;
+				};
+			};
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	led_set {
+		compatible = "realtek,rtl9300-leds";
+		active-low;
+
+		/*
+		 * 1G Ports LED0 (green): 1G/LINK/ACT
+		 * 1G Ports LED1 (orange): 10M/100M/LINK/ACT
+		 */
+		led_set0 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
+			    (RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M |
+			     RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
+
+		/*
+		 * 10G Ports LED0 (green): 10G/LINK/ACT
+		 * 10G Ports LED1 (orange): 10M/100M/1G/2.5G/5G/LINK/ACT
+		 */
+		led_set1 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
+			    (RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_1G |
+			     RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_5G |
+			     RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
+	};
+
+	leds: leds {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinmux_disable_sys_led>;
+		compatible = "gpio-leds";
+
+		led_power: led-0 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+
+		led_console: led-1 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		};
+
+		led_fault: led-2 {
+			function = LED_FUNCTION_FAULT;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	sfp0: sfp-p24 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c0>;
+		mod-def0-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
+		tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+		los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+	};
+	sfp1: sfp-p25 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c1>;
+		mod-def0-gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
+		tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+		los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+	};
+	sfp2: sfp-p26 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c2>;
+		mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+		tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+	};
+	sfp3: sfp-p27 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c3>;
+		mod-def0-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
+		tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		los-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x100000>;
+				read-only;
+			};
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x100000 0x80000>;
+			};
+			partition@180000 {
+				label = "u-boot-env2";
+				reg = <0x180000 0x80000>;
+			};
+			partition@200000 {
+				label = "firmware";
+				compatible = "openwrt,uimage";
+				reg = <0x200000 0x3e00000>;
+			};
+		};
+	};
+};
+
+&mdio_bus0 {
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy2: ethernet-phy@2 {
+		reg = <2>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy3: ethernet-phy@3 {
+		reg = <3>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy4: ethernet-phy@4 {
+		reg = <4>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy5: ethernet-phy@5 {
+		reg = <5>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy6: ethernet-phy@6 {
+		reg = <6>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy7: ethernet-phy@7 {
+		reg = <7>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+};
+
+&mdio_bus1 {
+	phy8: ethernet-phy@8 {
+		reg = <8>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy9: ethernet-phy@9 {
+		reg = <9>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy10: ethernet-phy@10 {
+		reg = <10>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy11: ethernet-phy@11 {
+		reg = <11>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy12: ethernet-phy@12 {
+		reg = <12>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy13: ethernet-phy@13 {
+		reg = <13>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy14: ethernet-phy@14 {
+		reg = <14>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy15: ethernet-phy@15 {
+		reg = <15>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+};
+
+&mdio_bus2 {
+	phy16: ethernet-phy@16 {
+		reg = <16>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy17: ethernet-phy@17 {
+		reg = <17>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy18: ethernet-phy@18 {
+		reg = <18>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy19: ethernet-phy@19 {
+		reg = <19>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy20: ethernet-phy@20 {
+		reg = <20>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy21: ethernet-phy@21 {
+		reg = <21>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy22: ethernet-phy@22 {
+		reg = <22>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+	phy23: ethernet-phy@23 {
+		reg = <23>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+	};
+};
+
+&switch0 {
+	ethernet-ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		SWITCH_PORT_LED(0, 1, 0, 0, qsgmii)
+		SWITCH_PORT_LED(1, 2, 0, 0, qsgmii)
+		SWITCH_PORT_LED(2, 3, 0, 0, qsgmii)
+		SWITCH_PORT_LED(3, 4, 0, 0, qsgmii)
+		SWITCH_PORT_LED(4, 5, 1, 0, qsgmii)
+		SWITCH_PORT_LED(5, 6, 1, 0, qsgmii)
+		SWITCH_PORT_LED(6, 7, 1, 0, qsgmii)
+		SWITCH_PORT_LED(7, 8, 1, 0, qsgmii)
+
+		SWITCH_PORT_LED(8, 9, 2, 0, usxgmii)
+		SWITCH_PORT_LED(9, 10, 2, 0, usxgmii)
+		SWITCH_PORT_LED(10, 11, 2, 0, usxgmii)
+		SWITCH_PORT_LED(11, 12, 2, 0, usxgmii)
+		SWITCH_PORT_LED(12, 13, 2, 0, usxgmii)
+		SWITCH_PORT_LED(13, 14, 2, 0, usxgmii)
+		SWITCH_PORT_LED(14, 15, 2, 0, usxgmii)
+		SWITCH_PORT_LED(15, 16, 2, 0, usxgmii)
+
+		SWITCH_PORT_LED(16, 17, 3, 0, usxgmii)
+		SWITCH_PORT_LED(17, 18, 3, 0, usxgmii)
+		SWITCH_PORT_LED(18, 19, 3, 0, usxgmii)
+		SWITCH_PORT_LED(19, 20, 3, 0, usxgmii)
+		SWITCH_PORT_LED(20, 21, 3, 0, usxgmii)
+		SWITCH_PORT_LED(21, 22, 3, 0, usxgmii)
+		SWITCH_PORT_LED(22, 23, 3, 0, usxgmii)
+		SWITCH_PORT_LED(23, 24, 3, 0, usxgmii)
+
+		port@24 {
+			reg = <24>;
+			label = "lan25";
+			led-set = <1>;
+			pcs-handle = <&serdes4>;
+			phy-mode = "1000base-x";
+			managed = "in-band-status";
+			sfp = <&sfp0>;
+		};
+		port@25 {
+			reg = <25>;
+			label = "lan26";
+			led-set = <1>;
+			pcs-handle = <&serdes6>;
+			phy-mode = "1000base-x";
+			managed = "in-band-status";
+			sfp = <&sfp1>;
+		};
+		port@26 {
+			reg = <26>;
+			label = "lan27";
+			led-set = <1>;
+			pcs-handle = <&serdes8>;
+			phy-mode = "1000base-x";
+			managed = "in-band-status";
+			sfp = <&sfp2>;
+		};
+		port@27 {
+			reg = <27>;
+			label = "lan28";
+			led-set = <1>;
+			pcs-handle = <&serdes9>;
+			phy-mode = "1000base-x";
+			managed = "in-band-status";
+			sfp = <&sfp3>;
+		};
+
+		port@28 {
+			reg = <28>;
+			ethernet = <&ethernet0>;
+			phy-mode = "internal";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+	};
+};
+
+&ethernet0 {
+	nvmem-cells = <&mac_address>;
+	nvmem-cell-names = "mac-address";
+};

target/linux/realtek/image/rtl930x.mk

@@ -2,6 +2,16 @@
 
 include ./common.mk
 
+define Device/d-link_dgs-1250-28x
+  SOC := rtl9301
+  DEVICE_VENDOR := D-Link
+  DEVICE_MODEL := DGS-1250-28X
+  DEVICE_PACKAGES += kmod-hwmon-lm75
+  IMAGE_SIZE := 24576k
+  $(Device/kernel-lzma)
+endef
+TARGET_DEVICES += d-link_dgs-1250-28x
+
 define Device/hasivo_s1100w-8xgt-se
   SOC := rtl9303
   DEVICE_VENDOR := Hasivo