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@@ -0,0 +1,86 @@
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+From e379c2199de4280243e43118dceb4ea5e97059a3 Mon Sep 17 00:00:00 2001
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+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <[email protected]>
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+Date: Tue, 23 Feb 2021 09:00:42 +0100
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+Subject: [PATCH] watchdog: bcm7038_wdt: add big endian support
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+MIME-Version: 1.0
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+Content-Type: text/plain; charset=UTF-8
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+Content-Transfer-Encoding: 8bit
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+
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+bcm7038_wdt can be used on bmips big endian (bcm63xx) devices too.
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+
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+Signed-off-by: Álvaro Fernández Rojas <[email protected]>
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+Reviewed-by: Guenter Roeck <[email protected]>
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+Link: https://lore.kernel.org/r/[email protected]
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+Signed-off-by: Guenter Roeck <[email protected]>
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+Signed-off-by: Wim Van Sebroeck <[email protected]>
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+---
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+ drivers/watchdog/bcm7038_wdt.c | 31 +++++++++++++++++++++++++------
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+ 1 file changed, 25 insertions(+), 6 deletions(-)
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+
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+--- a/drivers/watchdog/bcm7038_wdt.c
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++++ b/drivers/watchdog/bcm7038_wdt.c
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+@@ -34,6 +34,25 @@ struct bcm7038_watchdog {
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+
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+ static bool nowayout = WATCHDOG_NOWAYOUT;
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+
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++static inline void bcm7038_wdt_write(u32 value, void __iomem *addr)
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++{
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++ /* MIPS chips strapped for BE will automagically configure the
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++ * peripheral registers for CPU-native byte order.
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++ */
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++ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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++ __raw_writel(value, addr);
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++ else
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++ writel_relaxed(value, addr);
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++}
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++
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++static inline u32 bcm7038_wdt_read(void __iomem *addr)
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++{
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++ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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++ return __raw_readl(addr);
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++ else
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++ return readl_relaxed(addr);
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++}
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++
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+ static void bcm7038_wdt_set_timeout_reg(struct watchdog_device *wdog)
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+ {
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+ struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
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+@@ -41,15 +60,15 @@ static void bcm7038_wdt_set_timeout_reg(
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+
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+ timeout = wdt->rate * wdog->timeout;
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+
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+- writel(timeout, wdt->base + WDT_TIMEOUT_REG);
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++ bcm7038_wdt_write(timeout, wdt->base + WDT_TIMEOUT_REG);
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+ }
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+
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+ static int bcm7038_wdt_ping(struct watchdog_device *wdog)
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+ {
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+ struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
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+
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+- writel(WDT_START_1, wdt->base + WDT_CMD_REG);
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+- writel(WDT_START_2, wdt->base + WDT_CMD_REG);
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++ bcm7038_wdt_write(WDT_START_1, wdt->base + WDT_CMD_REG);
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++ bcm7038_wdt_write(WDT_START_2, wdt->base + WDT_CMD_REG);
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+
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+ return 0;
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+ }
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+@@ -66,8 +85,8 @@ static int bcm7038_wdt_stop(struct watch
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+ {
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+ struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
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+
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+- writel(WDT_STOP_1, wdt->base + WDT_CMD_REG);
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+- writel(WDT_STOP_2, wdt->base + WDT_CMD_REG);
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++ bcm7038_wdt_write(WDT_STOP_1, wdt->base + WDT_CMD_REG);
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++ bcm7038_wdt_write(WDT_STOP_2, wdt->base + WDT_CMD_REG);
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+
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+ return 0;
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+ }
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+@@ -88,7 +107,7 @@ static unsigned int bcm7038_wdt_get_time
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+ struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);
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+ u32 time_left;
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+
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+- time_left = readl(wdt->base + WDT_CMD_REG);
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++ time_left = bcm7038_wdt_read(wdt->base + WDT_CMD_REG);
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+
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+ return time_left / wdt->rate;
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+ }
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