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@@ -1,4 +1,4 @@
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-From 693f0ff3dbc53f910dff57ac15c324f7a94cc0ad Mon Sep 17 00:00:00 2001
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+From 107ff718dad1c8f6abbf6247d6796a4535b71276 Mon Sep 17 00:00:00 2001
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From: John Crispin <[email protected]>
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Date: Mon, 14 Dec 2015 23:50:53 +0100
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Subject: [PATCH 509/513] net-next: mediatek: add support for mt7621
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@@ -15,16 +15,16 @@ Signed-off-by: John Crispin <[email protected]>
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Signed-off-by: Felix Fietkau <[email protected]>
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Signed-off-by: Michael Lee <[email protected]>
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---
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- drivers/net/ethernet/mediatek/soc_mt7621.c | 184 ++++++++++++++++++++++++++++
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- 1 file changed, 184 insertions(+)
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+ drivers/net/ethernet/mediatek/soc_mt7621.c | 186 ++++++++++++++++++++++++++++
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+ 1 file changed, 186 insertions(+)
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create mode 100644 drivers/net/ethernet/mediatek/soc_mt7621.c
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diff --git a/drivers/net/ethernet/mediatek/soc_mt7621.c b/drivers/net/ethernet/mediatek/soc_mt7621.c
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new file mode 100644
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-index 0000000..d6f7f23
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+index 0000000..1609a3e
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/soc_mt7621.c
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-@@ -0,0 +1,184 @@
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+@@ -0,0 +1,186 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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@@ -52,18 +52,13 @@ index 0000000..d6f7f23
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+#include "mdio.h"
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+
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+#define MT7620A_CDMA_CSG_CFG 0x400
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-+#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
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+#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00)
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+#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04)
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-+#define MT7620A_RESET_FE BIT(21)
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+#define MT7621_RESET_FE BIT(6)
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-+#define MT7620A_RESET_ESW BIT(23)
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-+#define MT7620_L4_VALID BIT(23)
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+#define MT7621_L4_VALID BIT(24)
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+
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-+#define MT7620_TX_DMA_UDF BIT(15)
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+#define MT7621_TX_DMA_UDF BIT(19)
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-+#define TX_DMA_FP_BMAP ((0xff) << 19)
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++#define MT7621_TX_DMA_FPORT BIT(25)
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+
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+#define CDMA_ICS_EN BIT(2)
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+#define CDMA_UCS_EN BIT(1)
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@@ -74,11 +69,6 @@ index 0000000..d6f7f23
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+#define GDMA_UCS_EN BIT(20)
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+
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+/* frame engine counters */
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-+#define MT7620_REG_MIB_OFFSET 0x1000
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-+#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
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-+#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
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-+#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
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-+
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+#define MT7621_REG_MIB_OFFSET 0x2000
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+#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
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+#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
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@@ -130,6 +120,18 @@ index 0000000..d6f7f23
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+ fe_reset(MT7621_RESET_FE);
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+}
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+
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++static void mt7621_rxcsum_config(bool enable)
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++{
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++ if (enable)
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++ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
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++ GDMA_TCS_EN | GDMA_UCS_EN),
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++ MT7620A_GDMA1_FWD_CFG);
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++ else
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++ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
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++ GDMA_TCS_EN | GDMA_UCS_EN),
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++ MT7620A_GDMA1_FWD_CFG);
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++}
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++
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+static void mt7621_rxvlan_config(bool enable)
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+{
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+ if (enable)
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@@ -145,8 +147,8 @@ index 0000000..d6f7f23
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+ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff,
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+ MT7620A_GDMA1_FWD_CFG);
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+
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-+ /* mt7621 don't have txcsum config */
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-+ mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
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++ /* mt7621 doesn't have txcsum config */
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++ mt7621_rxcsum_config((dev->features & NETIF_F_RXCSUM));
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+ mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
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+ (priv->flags & FE_FLAG_RX_VLAN_CTAG));
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+
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@@ -155,7 +157,7 @@ index 0000000..d6f7f23
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+
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+static void mt7621_tx_dma(struct fe_tx_dma *txd)
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+{
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-+ txd->txd4 = BIT(25);
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++ txd->txd4 = MT7621_TX_DMA_FPORT;
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+}
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+
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+static void mt7621_init_data(struct fe_soc_data *data,
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John Crispin