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@@ -1,6 +1,6 @@
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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-@@ -139,6 +139,9 @@ config MACH_DECSTATION
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+@@ -139,6 +139,9 @@
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otherwise choose R3000.
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@@ -10,7 +10,7 @@
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config MACH_JAZZ
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bool "Jazz family of machines"
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select ARC
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-@@ -693,6 +696,7 @@ source "arch/mips/txx9/Kconfig"
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+@@ -695,6 +698,7 @@
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source "arch/mips/vr41xx/Kconfig"
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source "arch/mips/cavium-octeon/Kconfig"
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source "arch/mips/loongson/Kconfig"
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@@ -20,7 +20,7 @@
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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-@@ -317,6 +317,17 @@ cflags-$(CONFIG_MIPS_COBALT) += -I$(srct
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+@@ -339,6 +339,17 @@
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load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
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#
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@@ -83,6 +83,227 @@
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+obj-y := irq.o setup.o clk.o prom.o
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+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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--- /dev/null
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++++ b/arch/mips/lantiq/irq.c
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+@@ -0,0 +1,218 @@
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++/*
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++ * This program is free software; you can redistribute it and/or modify it
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++ * under the terms of the GNU General Public License version 2 as published
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++ * by the Free Software Foundation.
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++ *
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++ * Copyright (C) 2010 John Crispin <[email protected]>
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++ */
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++
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++#include <linux/module.h>
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++#include <linux/interrupt.h>
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++
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++#include <asm/bootinfo.h>
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++#include <asm/irq_cpu.h>
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++
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++#include <lantiq.h>
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++#include <irq.h>
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++
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++#define LQ_ICU_BASE_ADDR (KSEG1 | 0x1F880200)
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++
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++#define LQ_ICU_IM0_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0000))
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++#define LQ_ICU_IM0_IER ((u32 *)(LQ_ICU_BASE_ADDR + 0x0008))
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++#define LQ_ICU_IM0_IOSR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0010))
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++#define LQ_ICU_IM0_IRSR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0018))
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++#define LQ_ICU_IM0_IMR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0020))
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++
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++#define LQ_ICU_IM1_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0028))
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++#define LQ_ICU_IM2_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0050))
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++#define LQ_ICU_IM3_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0078))
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++#define LQ_ICU_IM4_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x00A0))
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++
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++#define LQ_ICU_OFFSET (LQ_ICU_IM1_ISR - LQ_ICU_IM0_ISR)
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++
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++#define LQ_EBU_BASE_ADDR 0xBE105300
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++#define LQ_EBU_PCC_ISTAT ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A0))
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++
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++void
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++lq_disable_irq(unsigned int irq_nr)
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++{
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++ u32 *ier = LQ_ICU_IM0_IER;
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++ irq_nr -= INT_NUM_IRQ0;
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++ ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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++ irq_nr %= INT_NUM_IM_OFFSET;
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++ lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
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++}
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++EXPORT_SYMBOL(lq_disable_irq);
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++
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++void
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++lq_mask_and_ack_irq(unsigned int irq_nr)
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++{
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++ u32 *ier = LQ_ICU_IM0_IER;
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++ u32 *isr = LQ_ICU_IM0_ISR;
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++ irq_nr -= INT_NUM_IRQ0;
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++ ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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++ isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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++ irq_nr %= INT_NUM_IM_OFFSET;
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++ lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
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++ lq_w32((1 << irq_nr), isr);
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++}
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++EXPORT_SYMBOL(lq_mask_and_ack_irq);
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++
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++static void
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++lq_ack_irq(unsigned int irq_nr)
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++{
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++ u32 *isr = LQ_ICU_IM0_ISR;
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++ irq_nr -= INT_NUM_IRQ0;
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++ isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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++ irq_nr %= INT_NUM_IM_OFFSET;
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++ lq_w32((1 << irq_nr), isr);
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++}
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++
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++void
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++lq_enable_irq(unsigned int irq_nr)
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++{
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++ u32 *ier = LQ_ICU_IM0_IER;
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++ irq_nr -= INT_NUM_IRQ0;
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++ ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
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++ irq_nr %= INT_NUM_IM_OFFSET;
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++ lq_w32(lq_r32(ier) | (1 << irq_nr), ier);
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++}
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++EXPORT_SYMBOL(lq_enable_irq);
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++
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++static unsigned int
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++lq_startup_irq(unsigned int irq)
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++{
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++ lq_enable_irq(irq);
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++ return 0;
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++}
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++
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++static void
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++lq_end_irq(unsigned int irq)
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++{
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++ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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++ lq_enable_irq(irq);
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++}
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++
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++static struct irq_chip
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++lq_irq_type = {
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++ "lq_irq",
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++ .startup = lq_startup_irq,
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++ .enable = lq_enable_irq,
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++ .disable = lq_disable_irq,
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++ .unmask = lq_enable_irq,
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++ .ack = lq_ack_irq,
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++ .mask = lq_disable_irq,
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++ .mask_ack = lq_mask_and_ack_irq,
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++ .end = lq_end_irq,
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++};
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++
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++static void
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++lq_hw_irqdispatch(int module)
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++{
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++ u32 irq;
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++
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++ irq = lq_r32(LQ_ICU_IM0_IOSR + (module * LQ_ICU_OFFSET));
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++ if (irq == 0)
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++ return;
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++
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++ /* silicon bug causes only the msb set to 1 to be valid. all
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++ other bits might be bogus */
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++ irq = __fls(irq);
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++ do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
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++ if ((irq == 22) && (module == 0))
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++ lq_w32(lq_r32(LQ_EBU_PCC_ISTAT) | 0x10,
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++ LQ_EBU_PCC_ISTAT);
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++}
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++
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++#define DEFINE_HWx_IRQDISPATCH(x) \
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++static void lq_hw ## x ## _irqdispatch(void)\
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++{\
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++ lq_hw_irqdispatch(x); \
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++}
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++static void lq_hw5_irqdispatch(void)
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++{
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++ do_IRQ(MIPS_CPU_TIMER_IRQ);
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++}
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++DEFINE_HWx_IRQDISPATCH(0)
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++DEFINE_HWx_IRQDISPATCH(1)
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++DEFINE_HWx_IRQDISPATCH(2)
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++DEFINE_HWx_IRQDISPATCH(3)
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++DEFINE_HWx_IRQDISPATCH(4)
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++/*DEFINE_HWx_IRQDISPATCH(5)*/
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++
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++asmlinkage void
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++plat_irq_dispatch(void)
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++{
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++ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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++ unsigned int i;
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++
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++ if (pending & CAUSEF_IP7)
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++ {
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++ do_IRQ(MIPS_CPU_TIMER_IRQ);
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++ goto out;
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++ } else {
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++ for (i = 0; i < 5; i++)
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++ {
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++ if (pending & (CAUSEF_IP2 << i))
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++ {
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++ lq_hw_irqdispatch(i);
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++ goto out;
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++ }
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++ }
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++ }
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++ printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
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++
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++out:
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++ return;
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++}
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++
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++static struct irqaction
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++cascade = {
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++ .handler = no_action,
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++ .flags = IRQF_DISABLED,
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++ .name = "cascade",
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++};
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++
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++void __init
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++arch_init_irq(void)
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++{
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++ int i;
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++
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++ for (i = 0; i < 5; i++)
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++ lq_w32(0, LQ_ICU_IM0_IER + (i * LQ_ICU_OFFSET));
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++
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++ mips_cpu_irq_init();
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++
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++ for (i = 2; i <= 6; i++)
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++ setup_irq(i, &cascade);
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++
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++ if (cpu_has_vint) {
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++ printk(KERN_INFO "Setting up vectored interrupts\n");
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++ set_vi_handler(2, lq_hw0_irqdispatch);
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++ set_vi_handler(3, lq_hw1_irqdispatch);
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++ set_vi_handler(4, lq_hw2_irqdispatch);
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++ set_vi_handler(5, lq_hw3_irqdispatch);
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++ set_vi_handler(6, lq_hw4_irqdispatch);
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++ set_vi_handler(7, lq_hw5_irqdispatch);
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++ }
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++
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++ for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
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++ set_irq_chip_and_handler(i, &lq_irq_type,
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++ handle_level_irq);
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++
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++ #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
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++ set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
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++ IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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++ #else
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++ set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
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++ IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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++ #endif
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++}
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++
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++void __cpuinit
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++arch_fixup_c0_irqs(void)
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++{
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++ /* FIXME: check for CPUID and only do fix for specific chips/versions */
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++ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
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++ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
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++}
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+--- /dev/null
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+++ b/arch/mips/lantiq/setup.c
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@@ -0,0 +1,47 @@
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+/*
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John Crispin