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@@ -1,5017 +0,0 @@
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-From 3924d0442771e17c26ab10ad53a1807e800ab3f1 Mon Sep 17 00:00:00 2001
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-From: Ivo van Doorn <[email protected]>
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-Date: Sat, 28 Mar 2009 20:48:56 +0100
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-Subject: [PATCH 9/9] rt2x00: Implement support for rt2800usb
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-
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-Add support for the rt2800usb chipset.
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-
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-Includes various patches from Mattias, Felix, Xose and Axel.
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-
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-Signed-off-by: Mattias Nissler <[email protected]>
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-Signed-off-by: Felix Fietkau <[email protected]>
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-Signed-off-by: Xose Vazquez Perez <[email protected]>
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-Signed-off-by: Axel Kollhofer <[email protected]>
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-Signed-off-by: Ivo van Doorn <[email protected]>
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----
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- drivers/net/wireless/rt2x00/Kconfig | 14 +
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- drivers/net/wireless/rt2x00/Makefile | 1 +
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- drivers/net/wireless/rt2x00/rt2800usb.c | 3036 +++++++++++++++++++++++++++++++
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- drivers/net/wireless/rt2x00/rt2800usb.h | 1934 ++++++++++++++++++++
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- drivers/net/wireless/rt2x00/rt2x00.h | 1 +
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- 5 files changed, 4986 insertions(+), 0 deletions(-)
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- create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.c
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- create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.h
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-
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---- a/drivers/net/wireless/rt2x00/Makefile
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-+++ b/drivers/net/wireless/rt2x00/Makefile
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-@@ -20,3 +20,4 @@ obj-$(CONFIG_RT61PCI) += rt61pci.o
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- obj-$(CONFIG_RT2800PCI) += rt2800pci.o
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- obj-$(CONFIG_RT2500USB) += rt2500usb.o
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- obj-$(CONFIG_RT73USB) += rt73usb.o
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-+obj-$(CONFIG_RT2800USB) += rt2800usb.o
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---- /dev/null
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-+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
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-@@ -0,0 +1,3036 @@
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-+/*
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-+ Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
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-+ <http://rt2x00.serialmonkey.com>
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-+
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-+ This program is free software; you can redistribute it and/or modify
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-+ it under the terms of the GNU General Public License as published by
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-+ the Free Software Foundation; either version 2 of the License, or
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-+ (at your option) any later version.
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-+
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-+ This program is distributed in the hope that it will be useful,
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-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-+ GNU General Public License for more details.
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-+
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-+ You should have received a copy of the GNU General Public License
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-+ along with this program; if not, write to the
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-+ Free Software Foundation, Inc.,
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-+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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-+ */
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-+
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-+/*
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-+ Module: rt2800usb
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-+ Abstract: rt2800usb device specific routines.
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-+ Supported chipsets: RT2800U.
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-+ */
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-+
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-+#include <linux/crc-ccitt.h>
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-+#include <linux/delay.h>
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-+#include <linux/etherdevice.h>
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-+#include <linux/init.h>
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-+#include <linux/kernel.h>
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-+#include <linux/module.h>
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-+#include <linux/usb.h>
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-+
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-+#include "rt2x00.h"
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-+#include "rt2x00usb.h"
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-+#include "rt2800usb.h"
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-+
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-+/*
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-+ * Allow hardware encryption to be disabled.
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-+ */
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-+static int modparam_nohwcrypt = 0;
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-+module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
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-+MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
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-+
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-+/*
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-+ * Register access.
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-+ * All access to the CSR registers will go through the methods
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-+ * rt2x00usb_register_read and rt2x00usb_register_write.
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-+ * BBP and RF register require indirect register access,
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-+ * and use the CSR registers BBPCSR and RFCSR to achieve this.
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-+ * These indirect registers work with busy bits,
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-+ * and we will try maximal REGISTER_BUSY_COUNT times to access
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-+ * the register while taking a REGISTER_BUSY_DELAY us delay
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-+ * between each attampt. When the busy bit is still set at that time,
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-+ * the access attempt is considered to have failed,
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-+ * and we will print an error.
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-+ * The _lock versions must be used if you already hold the csr_mutex
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-+ */
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-+#define WAIT_FOR_BBP(__dev, __reg) \
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-+ rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
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-+#define WAIT_FOR_RFCSR(__dev, __reg) \
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-+ rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
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-+#define WAIT_FOR_RF(__dev, __reg) \
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-+ rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
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-+#define WAIT_FOR_MCU(__dev, __reg) \
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-+ rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
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-+ H2M_MAILBOX_CSR_OWNER, (__reg))
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-+
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-+static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
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-+ const unsigned int word, const u8 value)
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-+{
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-+ u32 reg;
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-+
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-+ mutex_lock(&rt2x00dev->csr_mutex);
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-+
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-+ /*
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-+ * Wait until the BBP becomes available, afterwards we
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-+ * can safely write the new data into the register.
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-+ */
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-+ if (WAIT_FOR_BBP(rt2x00dev, ®)) {
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-+ reg = 0;
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-+ rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value);
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-+ rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
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-+ rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
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-+ rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0);
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-+
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-+ rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
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-+ }
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-+
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-+ mutex_unlock(&rt2x00dev->csr_mutex);
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-+}
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-+
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-+static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
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-+ const unsigned int word, u8 *value)
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-+{
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-+ u32 reg;
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-+
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-+ mutex_lock(&rt2x00dev->csr_mutex);
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-+
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-+ /*
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-+ * Wait until the BBP becomes available, afterwards we
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-+ * can safely write the read request into the register.
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-+ * After the data has been written, we wait until hardware
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-+ * returns the correct value, if at any time the register
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-+ * doesn't become available in time, reg will be 0xffffffff
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-+ * which means we return 0xff to the caller.
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-+ */
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-+ if (WAIT_FOR_BBP(rt2x00dev, ®)) {
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-+ reg = 0;
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-+ rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
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-+ rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
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-+ rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1);
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-+
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-+ rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
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-+
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-+ WAIT_FOR_BBP(rt2x00dev, ®);
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-+ }
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-+
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-+ *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
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-+
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-+ mutex_unlock(&rt2x00dev->csr_mutex);
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-+}
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-+
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-+static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
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-+ const unsigned int word, const u8 value)
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-+{
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-+ u32 reg;
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-+
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-+ mutex_lock(&rt2x00dev->csr_mutex);
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-+
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-+ /*
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-+ * Wait until the RFCSR becomes available, afterwards we
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-+ * can safely write the new data into the register.
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-+ */
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-+ if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
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-+ reg = 0;
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-+ rt2x00_set_field32(®, RF_CSR_CFG_DATA, value);
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-+ rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
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-+ rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1);
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-+ rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
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-+
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-+ rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
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-+ }
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-+
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-+ mutex_unlock(&rt2x00dev->csr_mutex);
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-+}
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-+
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-+static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
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-+ const unsigned int word, u8 *value)
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-+{
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-+ u32 reg;
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-+
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-+ mutex_lock(&rt2x00dev->csr_mutex);
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-+
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-+ /*
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-+ * Wait until the RFCSR becomes available, afterwards we
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-+ * can safely write the read request into the register.
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-+ * After the data has been written, we wait until hardware
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-+ * returns the correct value, if at any time the register
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-+ * doesn't become available in time, reg will be 0xffffffff
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-+ * which means we return 0xff to the caller.
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-+ */
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-+ if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
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-+ reg = 0;
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-+ rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
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-+ rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0);
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-+ rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
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-+
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-+ rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
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-+
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-+ WAIT_FOR_RFCSR(rt2x00dev, ®);
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-+ }
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-+
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-+ *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
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-+
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-+ mutex_unlock(&rt2x00dev->csr_mutex);
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-+}
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-+
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-+static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
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-+ const unsigned int word, const u32 value)
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-+{
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-+ u32 reg;
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-+
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-+ mutex_lock(&rt2x00dev->csr_mutex);
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-+
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-+ /*
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-+ * Wait until the RF becomes available, afterwards we
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-+ * can safely write the new data into the register.
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-+ */
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-+ if (WAIT_FOR_RF(rt2x00dev, ®)) {
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-+ reg = 0;
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-+ rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value);
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-+ rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0);
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-+ rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0);
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-+ rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1);
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-+
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-+ rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
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-+ rt2x00_rf_write(rt2x00dev, word, value);
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-+ }
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-+
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-+ mutex_unlock(&rt2x00dev->csr_mutex);
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-+}
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-+
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-+static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
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-+ const u8 command, const u8 token,
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-+ const u8 arg0, const u8 arg1)
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-+{
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-+ u32 reg;
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-+
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-+ mutex_lock(&rt2x00dev->csr_mutex);
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-+
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-+ /*
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-+ * Wait until the MCU becomes available, afterwards we
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-+ * can safely write the new data into the register.
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-+ */
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-+ if (WAIT_FOR_MCU(rt2x00dev, ®)) {
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-+ rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
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-+ rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
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-+ rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
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-+ rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
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-+ rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
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-+
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-+ reg = 0;
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-+ rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
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-+ rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
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-+ }
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-+
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-+ mutex_unlock(&rt2x00dev->csr_mutex);
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-+}
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-+
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-+#ifdef CONFIG_RT2X00_LIB_DEBUGFS
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-+static const struct rt2x00debug rt2800usb_rt2x00debug = {
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-+ .owner = THIS_MODULE,
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-+ .csr = {
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-+ .read = rt2x00usb_register_read,
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-+ .write = rt2x00usb_register_write,
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-+ .flags = RT2X00DEBUGFS_OFFSET,
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-+ .word_base = CSR_REG_BASE,
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-+ .word_size = sizeof(u32),
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-+ .word_count = CSR_REG_SIZE / sizeof(u32),
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-+ },
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-+ .eeprom = {
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-+ .read = rt2x00_eeprom_read,
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-+ .write = rt2x00_eeprom_write,
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-+ .word_base = EEPROM_BASE,
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-+ .word_size = sizeof(u16),
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-+ .word_count = EEPROM_SIZE / sizeof(u16),
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-+ },
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-+ .bbp = {
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-+ .read = rt2800usb_bbp_read,
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-+ .write = rt2800usb_bbp_write,
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-+ .word_base = BBP_BASE,
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-+ .word_size = sizeof(u8),
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-+ .word_count = BBP_SIZE / sizeof(u8),
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-+ },
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-+ .rf = {
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-+ .read = rt2x00_rf_read,
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-+ .write = rt2800usb_rf_write,
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-+ .word_base = RF_BASE,
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-+ .word_size = sizeof(u32),
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-+ .word_count = RF_SIZE / sizeof(u32),
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-+ },
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-+};
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-+#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
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-+
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-+#ifdef CONFIG_RT2X00_LIB_RFKILL
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-+static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
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-+{
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-+ u32 reg;
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-+
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-+ rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
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-+ return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
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-+}
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-+#else
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-+#define rt2800usb_rfkill_poll NULL
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-+#endif /* CONFIG_RT2X00_LIB_RFKILL */
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-+
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-+#ifdef CONFIG_RT2X00_LIB_LEDS
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-+static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
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-+ enum led_brightness brightness)
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-+{
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-+ struct rt2x00_led *led =
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-+ container_of(led_cdev, struct rt2x00_led, led_dev);
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-+ unsigned int enabled = brightness != LED_OFF;
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-+ unsigned int bg_mode =
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-+ (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
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-+ unsigned int polarity =
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-+ rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
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-+ EEPROM_FREQ_LED_POLARITY);
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-+ unsigned int ledmode =
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-+ rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
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-+ EEPROM_FREQ_LED_MODE);
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-+
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-+ if (led->type == LED_TYPE_RADIO) {
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-+ rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
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-+ enabled ? 0x20 : 0);
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-+ } else if (led->type == LED_TYPE_ASSOC) {
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-+ rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
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-+ enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
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-+ } else if (led->type == LED_TYPE_QUALITY) {
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-+ /*
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-+ * The brightness is divided into 6 levels (0 - 5),
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-+ * The specs tell us the following levels:
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-+ * 0, 1 ,3, 7, 15, 31
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|
|
-+ * to determine the level in a simple way we can simply
|
|
|
-+ * work with bitshifting:
|
|
|
-+ * (1 << level) - 1
|
|
|
-+ */
|
|
|
-+ rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
|
|
|
-+ (1 << brightness / (LED_FULL / 6)) - 1,
|
|
|
-+ polarity);
|
|
|
-+ }
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_blink_set(struct led_classdev *led_cdev,
|
|
|
-+ unsigned long *delay_on,
|
|
|
-+ unsigned long *delay_off)
|
|
|
-+{
|
|
|
-+ struct rt2x00_led *led =
|
|
|
-+ container_of(led_cdev, struct rt2x00_led, led_dev);
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(led->rt2x00dev, LED_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, LED_CFG_ON_PERIOD, *delay_on);
|
|
|
-+ rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, *delay_off);
|
|
|
-+ rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3);
|
|
|
-+ rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3);
|
|
|
-+ rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 12);
|
|
|
-+ rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3);
|
|
|
-+ rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1);
|
|
|
-+ rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00_led *led,
|
|
|
-+ enum led_type type)
|
|
|
-+{
|
|
|
-+ led->rt2x00dev = rt2x00dev;
|
|
|
-+ led->type = type;
|
|
|
-+ led->led_dev.brightness_set = rt2800usb_brightness_set;
|
|
|
-+ led->led_dev.blink_set = rt2800usb_blink_set;
|
|
|
-+ led->flags = LED_INITIALIZED;
|
|
|
-+}
|
|
|
-+#endif /* CONFIG_RT2X00_LIB_LEDS */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Configuration handlers.
|
|
|
-+ */
|
|
|
-+static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00lib_crypto *crypto,
|
|
|
-+ struct ieee80211_key_conf *key)
|
|
|
-+{
|
|
|
-+ struct mac_wcid_entry wcid_entry;
|
|
|
-+ struct mac_iveiv_entry iveiv_entry;
|
|
|
-+ u32 offset;
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, offset, ®);
|
|
|
-+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
|
|
|
-+ !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
|
|
|
-+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER,
|
|
|
-+ (crypto->cmd == SET_KEY) * crypto->cipher);
|
|
|
-+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX,
|
|
|
-+ (crypto->cmd == SET_KEY) * crypto->bssidx);
|
|
|
-+ rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, offset, reg);
|
|
|
-+
|
|
|
-+ offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
|
|
|
-+
|
|
|
-+ memset(&iveiv_entry, 0, sizeof(iveiv_entry));
|
|
|
-+ if ((crypto->cipher == CIPHER_TKIP) ||
|
|
|
-+ (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
|
|
|
-+ (crypto->cipher == CIPHER_AES))
|
|
|
-+ iveiv_entry.iv[3] |= 0x20;
|
|
|
-+ iveiv_entry.iv[3] |= key->keyidx << 6;
|
|
|
-+ rt2x00usb_register_multiwrite(rt2x00dev, offset,
|
|
|
-+ &iveiv_entry, sizeof(iveiv_entry));
|
|
|
-+
|
|
|
-+ offset = MAC_WCID_ENTRY(key->hw_key_idx);
|
|
|
-+
|
|
|
-+ memset(&wcid_entry, 0, sizeof(wcid_entry));
|
|
|
-+ if (crypto->cmd == SET_KEY)
|
|
|
-+ memcpy(&wcid_entry, crypto->address, ETH_ALEN);
|
|
|
-+ rt2x00usb_register_multiwrite(rt2x00dev, offset,
|
|
|
-+ &wcid_entry, sizeof(wcid_entry));
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00lib_crypto *crypto,
|
|
|
-+ struct ieee80211_key_conf *key)
|
|
|
-+{
|
|
|
-+ struct hw_key_entry key_entry;
|
|
|
-+ struct rt2x00_field32 field;
|
|
|
-+ int timeout;
|
|
|
-+ u32 offset;
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ if (crypto->cmd == SET_KEY) {
|
|
|
-+ key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
|
|
|
-+
|
|
|
-+ memcpy(key_entry.key, crypto->key,
|
|
|
-+ sizeof(key_entry.key));
|
|
|
-+ memcpy(key_entry.tx_mic, crypto->tx_mic,
|
|
|
-+ sizeof(key_entry.tx_mic));
|
|
|
-+ memcpy(key_entry.rx_mic, crypto->rx_mic,
|
|
|
-+ sizeof(key_entry.rx_mic));
|
|
|
-+
|
|
|
-+ offset = SHARED_KEY_ENTRY(key->hw_key_idx);
|
|
|
-+ timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
|
|
|
-+ rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
|
|
|
-+ USB_VENDOR_REQUEST_OUT,
|
|
|
-+ offset, &key_entry,
|
|
|
-+ sizeof(key_entry),
|
|
|
-+ timeout);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * The cipher types are stored over multiple registers
|
|
|
-+ * starting with SHARED_KEY_MODE_BASE each word will have
|
|
|
-+ * 32 bits and contains the cipher types for 2 bssidx each.
|
|
|
-+ * Using the correct defines correctly will cause overhead,
|
|
|
-+ * so just calculate the correct offset.
|
|
|
-+ */
|
|
|
-+ field.bit_offset = 4 * (key->hw_key_idx % 8);
|
|
|
-+ field.bit_mask = 0x7 << field.bit_offset;
|
|
|
-+
|
|
|
-+ offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, offset, ®);
|
|
|
-+ rt2x00_set_field32(®, field,
|
|
|
-+ (crypto->cmd == SET_KEY) * crypto->cipher);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, offset, reg);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Update WCID information
|
|
|
-+ */
|
|
|
-+ rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00lib_crypto *crypto,
|
|
|
-+ struct ieee80211_key_conf *key)
|
|
|
-+{
|
|
|
-+ struct hw_key_entry key_entry;
|
|
|
-+ int timeout;
|
|
|
-+ u32 offset;
|
|
|
-+
|
|
|
-+ if (crypto->cmd == SET_KEY) {
|
|
|
-+ /*
|
|
|
-+ * 1 pairwise key is possible per AID, this means that the AID
|
|
|
-+ * equals our hw_key_idx. Make sure the WCID starts _after_ the
|
|
|
-+ * last possible shared key entry.
|
|
|
-+ */
|
|
|
-+ if (crypto->aid > (256 - 32))
|
|
|
-+ return -ENOSPC;
|
|
|
-+
|
|
|
-+ key->hw_key_idx = 32 + crypto->aid;
|
|
|
-+
|
|
|
-+ memcpy(key_entry.key, crypto->key,
|
|
|
-+ sizeof(key_entry.key));
|
|
|
-+ memcpy(key_entry.tx_mic, crypto->tx_mic,
|
|
|
-+ sizeof(key_entry.tx_mic));
|
|
|
-+ memcpy(key_entry.rx_mic, crypto->rx_mic,
|
|
|
-+ sizeof(key_entry.rx_mic));
|
|
|
-+
|
|
|
-+ offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
|
|
|
-+ timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
|
|
|
-+ rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
|
|
|
-+ USB_VENDOR_REQUEST_OUT,
|
|
|
-+ offset, &key_entry,
|
|
|
-+ sizeof(key_entry),
|
|
|
-+ timeout);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Update WCID information
|
|
|
-+ */
|
|
|
-+ rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ const unsigned int filter_flags)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Start configuration steps.
|
|
|
-+ * Note that the version error will always be dropped
|
|
|
-+ * and broadcast frames will always be accepted since
|
|
|
-+ * there is no filter for it at this time.
|
|
|
-+ */
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR,
|
|
|
-+ !(filter_flags & FIF_FCSFAIL));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR,
|
|
|
-+ !(filter_flags & FIF_PLCPFAIL));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME,
|
|
|
-+ !(filter_flags & FIF_PROMISC_IN_BSS));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1);
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST,
|
|
|
-+ !(filter_flags & FIF_ALLMULTI));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0);
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1);
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK,
|
|
|
-+ !(filter_flags & FIF_CONTROL));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END,
|
|
|
-+ !(filter_flags & FIF_CONTROL));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK,
|
|
|
-+ !(filter_flags & FIF_CONTROL));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS,
|
|
|
-+ !(filter_flags & FIF_CONTROL));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS,
|
|
|
-+ !(filter_flags & FIF_CONTROL));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL,
|
|
|
-+ !(filter_flags & FIF_CONTROL));
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 1);
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 0);
|
|
|
-+ rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL,
|
|
|
-+ !(filter_flags & FIF_CONTROL));
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00_intf *intf,
|
|
|
-+ struct rt2x00intf_conf *conf,
|
|
|
-+ const unsigned int flags)
|
|
|
-+{
|
|
|
-+ unsigned int beacon_base;
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ if (flags & CONFIG_UPDATE_TYPE) {
|
|
|
-+ /*
|
|
|
-+ * Clear current synchronisation setup.
|
|
|
-+ * For the Beacon base registers we only need to clear
|
|
|
-+ * the first byte since that byte contains the VALID and OWNER
|
|
|
-+ * bits which (when set to 0) will invalidate the entire beacon.
|
|
|
-+ */
|
|
|
-+ beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Enable synchronisation.
|
|
|
-+ */
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (flags & CONFIG_UPDATE_MAC) {
|
|
|
-+ reg = le32_to_cpu(conf->mac[1]);
|
|
|
-+ rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
|
|
|
-+ conf->mac[1] = cpu_to_le32(reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
|
|
|
-+ conf->mac, sizeof(conf->mac));
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (flags & CONFIG_UPDATE_BSSID) {
|
|
|
-+ reg = le32_to_cpu(conf->bssid[1]);
|
|
|
-+ rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 0);
|
|
|
-+ rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
|
|
|
-+ conf->bssid[1] = cpu_to_le32(reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
|
|
|
-+ conf->bssid, sizeof(conf->bssid));
|
|
|
-+ }
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00lib_erp *erp)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
|
|
|
-+ DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY,
|
|
|
-+ !!erp->short_preamble);
|
|
|
-+ rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE,
|
|
|
-+ !!erp->short_preamble);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL,
|
|
|
-+ erp->cts_protection ? 2 : 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
|
|
|
-+ erp->basic_rates);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
|
|
|
-+ rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
|
|
|
-+ rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
|
|
|
-+ rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
|
|
|
-+ rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs);
|
|
|
-+ rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct antenna_setup *ant)
|
|
|
-+{
|
|
|
-+ u16 eeprom;
|
|
|
-+ u8 r1;
|
|
|
-+ u8 r3;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * FIXME: Use requested antenna configuration.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
|
|
|
-+
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 1, &r1);
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 3, &r3);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Configure the TX antenna.
|
|
|
-+ */
|
|
|
-+ switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
|
|
|
-+ case 1:
|
|
|
-+ rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
|
|
|
-+ break;
|
|
|
-+ case 2:
|
|
|
-+ rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
|
|
|
-+ break;
|
|
|
-+ case 3:
|
|
|
-+ /* Do nothing */
|
|
|
-+ break;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Configure the RX antenna.
|
|
|
-+ */
|
|
|
-+ switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
|
|
|
-+ case 1:
|
|
|
-+ rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
|
|
|
-+ break;
|
|
|
-+ case 2:
|
|
|
-+ rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
|
|
|
-+ break;
|
|
|
-+ case 3:
|
|
|
-+ rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
|
|
|
-+ break;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 3, r3);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 1, r1);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00lib_conf *libconf)
|
|
|
-+{
|
|
|
-+ u16 eeprom;
|
|
|
-+ short lna_gain;
|
|
|
-+
|
|
|
-+ if (libconf->rf.channel <= 14) {
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
|
|
|
-+ lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
|
|
|
-+ } else if (libconf->rf.channel <= 64) {
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
|
|
|
-+ lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
|
|
|
-+ } else if (libconf->rf.channel <= 128) {
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
|
|
|
-+ lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
|
|
|
-+ } else {
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
|
|
|
-+ lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00dev->lna_gain = lna_gain;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct ieee80211_conf *conf,
|
|
|
-+ struct rf_channel *rf,
|
|
|
-+ struct channel_info *info)
|
|
|
-+{
|
|
|
-+ u16 eeprom;
|
|
|
-+
|
|
|
-+ rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Determine antenna settings from EEPROM
|
|
|
-+ */
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
|
|
|
-+
|
|
|
-+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
|
|
|
-+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
|
|
|
-+
|
|
|
-+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
|
|
|
-+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
|
|
|
-+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
|
|
|
-+ } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
|
|
|
-+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
|
|
|
-+
|
|
|
-+ if (rf->channel > 14) {
|
|
|
-+ /*
|
|
|
-+ * When TX power is below 0, we should increase it by 7 to
|
|
|
-+ * make it a positive value (Minumum value is -7).
|
|
|
-+ * However this means that values between 0 and 7 have
|
|
|
-+ * double meaning, and we should set a 7DBm boost flag.
|
|
|
-+ */
|
|
|
-+ rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
|
|
|
-+ (info->tx_power1 >= 0));
|
|
|
-+
|
|
|
-+ if (info->tx_power1 < 0)
|
|
|
-+ info->tx_power1 += 7;
|
|
|
-+
|
|
|
-+ rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
|
|
|
-+ TXPOWER_A_TO_DEV(info->tx_power1));
|
|
|
-+
|
|
|
-+ rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
|
|
|
-+ (info->tx_power2 >= 0));
|
|
|
-+
|
|
|
-+ if (info->tx_power2 < 0)
|
|
|
-+ info->tx_power2 += 7;
|
|
|
-+
|
|
|
-+ rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
|
|
|
-+ TXPOWER_A_TO_DEV(info->tx_power2));
|
|
|
-+ } else {
|
|
|
-+ rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
|
|
|
-+ TXPOWER_G_TO_DEV(info->tx_power1));
|
|
|
-+ rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
|
|
|
-+ TXPOWER_G_TO_DEV(info->tx_power2));
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
|
|
|
-+
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
|
|
|
-+
|
|
|
-+ udelay(200);
|
|
|
-+
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
|
|
|
-+
|
|
|
-+ udelay(200);
|
|
|
-+
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
|
|
|
-+ rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct ieee80211_conf *conf,
|
|
|
-+ struct rf_channel *rf,
|
|
|
-+ struct channel_info *info)
|
|
|
-+{
|
|
|
-+ u8 rfcsr;
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
|
|
|
-+ rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
|
|
|
-+ rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
|
|
|
-+ TXPOWER_G_TO_DEV(info->tx_power1));
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
|
|
|
-+ rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
|
|
|
-+
|
|
|
-+ if (conf_is_ht40(conf))
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 24,
|
|
|
-+ rt2x00dev->calibration_bw40);
|
|
|
-+ else
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 24,
|
|
|
-+ rt2x00dev->calibration_bw20);
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
|
|
|
-+ rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct ieee80211_conf *conf,
|
|
|
-+ struct rf_channel *rf,
|
|
|
-+ struct channel_info *info)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+ unsigned int tx_pin;
|
|
|
-+ u16 eeprom;
|
|
|
-+ u8 bbp;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Determine antenna settings from EEPROM
|
|
|
-+ */
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
|
|
|
-+
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
|
|
|
-+ rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
|
|
|
-+ else
|
|
|
-+ rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Change BBP settings
|
|
|
-+ */
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 86, 0);
|
|
|
-+
|
|
|
-+ if (rf->channel <= 14) {
|
|
|
-+ if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
|
|
|
-+ } else {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
|
|
|
-+ }
|
|
|
-+ } else {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
|
|
|
-+
|
|
|
-+ if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
|
|
|
-+ else
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
|
|
|
-+ rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
|
|
|
-+ rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
|
|
|
-+
|
|
|
-+ tx_pin = 0;
|
|
|
-+
|
|
|
-+ /* Turn on unused PA or LNA when not using 1T or 1R */
|
|
|
-+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /* Turn on unused PA or LNA when not using 1T or 1R */
|
|
|
-+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
|
|
|
-+ rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
|
|
|
-+
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
|
|
|
-+ rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 4, bbp);
|
|
|
-+
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
|
|
|
-+ rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 3, bbp);
|
|
|
-+
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
|
|
|
-+ if (conf_is_ht40(conf)) {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
|
|
|
-+ } else {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
|
|
|
-+ }
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ msleep(1);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ const int txpower)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+ u32 value = TXPOWER_G_TO_DEV(txpower);
|
|
|
-+ u8 r1;
|
|
|
-+
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 1, &r1);
|
|
|
-+ rt2x00_set_field8(®, BBP1_TX_POWER, 0);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 1, r1);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_0_1MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_0_2MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_0_55MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_0_11MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_0_6MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_0_9MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_0_12MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_0_18MBS, value);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_1_24MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_1_36MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_1_48MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_1_54MBS, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_1_MCS0, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_1_MCS1, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_1_MCS2, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_1_MCS3, value);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_2_MCS4, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_2_MCS5, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_2_MCS6, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_2_MCS7, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_2_MCS8, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_2_MCS9, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_2_MCS10, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_2_MCS11, value);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_3_MCS12, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_3_MCS13, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_3_MCS14, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_3_MCS15, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN1, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN2, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN3, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN4, value);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN5, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN6, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN7, value);
|
|
|
-+ rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN8, value);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00lib_conf *libconf)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT,
|
|
|
-+ libconf->conf->short_frame_max_tx_count);
|
|
|
-+ rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT,
|
|
|
-+ libconf->conf->long_frame_max_tx_count);
|
|
|
-+ rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000);
|
|
|
-+ rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
|
|
|
-+ rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0);
|
|
|
-+ rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00lib_conf *libconf)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
|
|
|
-+ libconf->conf->beacon_int * 16);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00lib_conf *libconf)
|
|
|
-+{
|
|
|
-+ enum dev_state state =
|
|
|
-+ (libconf->conf->flags & IEEE80211_CONF_PS) ?
|
|
|
-+ STATE_SLEEP : STATE_AWAKE;
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ if (state == STATE_SLEEP) {
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
|
|
|
-+ rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
|
|
|
-+ libconf->conf->listen_interval - 1);
|
|
|
-+ rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
|
|
|
-+ } else {
|
|
|
-+ rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
|
|
|
-+ rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
|
|
|
-+ rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
|
|
|
-+ }
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct rt2x00lib_conf *libconf,
|
|
|
-+ const unsigned int flags)
|
|
|
-+{
|
|
|
-+ /* Always recalculate LNA gain before changing configuration */
|
|
|
-+ rt2800usb_config_lna_gain(rt2x00dev, libconf);
|
|
|
-+
|
|
|
-+ if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
|
|
|
-+ rt2800usb_config_channel(rt2x00dev, libconf->conf,
|
|
|
-+ &libconf->rf, &libconf->channel);
|
|
|
-+ if (flags & IEEE80211_CONF_CHANGE_POWER)
|
|
|
-+ rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
|
|
|
-+ if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
|
|
|
-+ rt2800usb_config_retry_limit(rt2x00dev, libconf);
|
|
|
-+ if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
|
|
|
-+ rt2800usb_config_duration(rt2x00dev, libconf);
|
|
|
-+ if (flags & IEEE80211_CONF_CHANGE_PS)
|
|
|
-+ rt2800usb_config_ps(rt2x00dev, libconf);
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Link tuning
|
|
|
-+ */
|
|
|
-+static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct link_qual *qual)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Update FCS error count from register.
|
|
|
-+ */
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, ®);
|
|
|
-+ qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
|
|
|
-+ return 0x1c + (2 * rt2x00dev->lna_gain);
|
|
|
-+ else
|
|
|
-+ return 0x2e + rt2x00dev->lna_gain;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
|
|
|
-+ return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
|
|
|
-+ else
|
|
|
-+ return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct link_qual *qual, u8 vgc_level)
|
|
|
-+{
|
|
|
-+ if (qual->vgc_level != vgc_level) {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
|
|
|
-+ qual->vgc_level = vgc_level;
|
|
|
-+ qual->vgc_level_reg = vgc_level;
|
|
|
-+ }
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct link_qual *qual)
|
|
|
-+{
|
|
|
-+ rt2800usb_set_vgc(rt2x00dev, qual,
|
|
|
-+ rt2800usb_get_default_vgc(rt2x00dev));
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct link_qual *qual, const u32 count)
|
|
|
-+{
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
|
|
|
-+ return;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * When RSSI is better then -80 increase VGC level with 0x10
|
|
|
-+ */
|
|
|
-+ rt2800usb_set_vgc(rt2x00dev, qual,
|
|
|
-+ rt2800usb_get_default_vgc(rt2x00dev) +
|
|
|
-+ ((qual->rssi > -80) * 0x10));
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Firmware functions
|
|
|
-+ */
|
|
|
-+static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ return FIRMWARE_RT2870;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static bool rt2800usb_check_crc(const u8 *data, const size_t len)
|
|
|
-+{
|
|
|
-+ u16 fw_crc;
|
|
|
-+ u16 crc;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * The last 2 bytes in the firmware array are the crc checksum itself,
|
|
|
-+ * this means that we should never pass those 2 bytes to the crc
|
|
|
-+ * algorithm.
|
|
|
-+ */
|
|
|
-+ fw_crc = (data[len - 2] << 8 | data[len - 1]);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Use the crc ccitt algorithm.
|
|
|
-+ * This will return the same value as the legacy driver which
|
|
|
-+ * used bit ordering reversion on the both the firmware bytes
|
|
|
-+ * before input input as well as on the final output.
|
|
|
-+ * Obviously using crc ccitt directly is much more efficient.
|
|
|
-+ */
|
|
|
-+ crc = crc_ccitt(~0, data, len - 2);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * There is a small difference between the crc-itu-t + bitrev and
|
|
|
-+ * the crc-ccitt crc calculation. In the latter method the 2 bytes
|
|
|
-+ * will be swapped, use swab16 to convert the crc to the correct
|
|
|
-+ * value.
|
|
|
-+ */
|
|
|
-+ crc = swab16(crc);
|
|
|
-+
|
|
|
-+ return fw_crc == crc;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ const u8 *data, const size_t len)
|
|
|
-+{
|
|
|
-+ u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
|
|
|
-+ size_t offset = 0;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Firmware files:
|
|
|
-+ * There are 2 variations of the rt2870 firmware.
|
|
|
-+ * a) size: 4kb
|
|
|
-+ * b) size: 8kb
|
|
|
-+ * Note that (b) contains 2 seperate firmware blobs of 4k
|
|
|
-+ * within the file. The first blob is the same firmware as (a),
|
|
|
-+ * but the second blob is for the additional chipsets.
|
|
|
-+ */
|
|
|
-+ if (len != 4096 && len != 8192)
|
|
|
-+ return FW_BAD_LENGTH;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Check if we need the upper 4kb firmware data or not.
|
|
|
-+ */
|
|
|
-+ if ((len == 4096) &&
|
|
|
-+ (chipset != 0x2860) &&
|
|
|
-+ (chipset != 0x2872) &&
|
|
|
-+ (chipset != 0x3070))
|
|
|
-+ return FW_BAD_VERSION;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * 8kb firmware files must be checked as if it were
|
|
|
-+ * 2 seperate firmware files.
|
|
|
-+ */
|
|
|
-+ while (offset < len) {
|
|
|
-+ if (!rt2800usb_check_crc(data + offset, 4096))
|
|
|
-+ return FW_BAD_CRC;
|
|
|
-+
|
|
|
-+ offset += 4096;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ return FW_OK;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ const u8 *data, const size_t len)
|
|
|
-+{
|
|
|
-+ unsigned int i;
|
|
|
-+ int status;
|
|
|
-+ u32 reg;
|
|
|
-+ u32 offset;
|
|
|
-+ u32 length;
|
|
|
-+ u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Check which section of the firmware we need.
|
|
|
-+ */
|
|
|
-+ if ((chipset == 0x2860) || (chipset == 0x2872) || (chipset == 0x3070)) {
|
|
|
-+ offset = 0;
|
|
|
-+ length = 4096;
|
|
|
-+ } else {
|
|
|
-+ offset = 4096;
|
|
|
-+ length = 4096;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Wait for stable hardware.
|
|
|
-+ */
|
|
|
-+ for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®);
|
|
|
-+ if (reg && reg != ~0)
|
|
|
-+ break;
|
|
|
-+ msleep(1);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (i == REGISTER_BUSY_COUNT) {
|
|
|
-+ ERROR(rt2x00dev, "Unstable hardware.\n");
|
|
|
-+ return -EBUSY;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Write firmware to device.
|
|
|
-+ */
|
|
|
-+ rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
|
|
|
-+ USB_VENDOR_REQUEST_OUT,
|
|
|
-+ FIRMWARE_IMAGE_BASE,
|
|
|
-+ data + offset, length,
|
|
|
-+ REGISTER_TIMEOUT32(length));
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Send firmware request to device to load firmware,
|
|
|
-+ * we need to specify a long timeout time.
|
|
|
-+ */
|
|
|
-+ status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
|
|
|
-+ 0, USB_MODE_FIRMWARE,
|
|
|
-+ REGISTER_TIMEOUT_FIRMWARE);
|
|
|
-+ if (status < 0) {
|
|
|
-+ ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
|
|
|
-+ return status;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Wait for device to stabilize.
|
|
|
-+ */
|
|
|
-+ for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, ®);
|
|
|
-+ if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
|
|
|
-+ break;
|
|
|
-+ msleep(1);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (i == REGISTER_BUSY_COUNT) {
|
|
|
-+ ERROR(rt2x00dev, "PBF system register not ready.\n");
|
|
|
-+ return -EBUSY;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Initialize firmware.
|
|
|
-+ */
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
|
|
|
-+ msleep(1);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Initialization functions.
|
|
|
-+ */
|
|
|
-+static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+ unsigned int i;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Wait untill BBP and RF are ready.
|
|
|
-+ */
|
|
|
-+ for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®);
|
|
|
-+ if (reg && reg != ~0)
|
|
|
-+ break;
|
|
|
-+ msleep(1);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (i == REGISTER_BUSY_COUNT) {
|
|
|
-+ ERROR(rt2x00dev, "Unstable hardware.\n");
|
|
|
-+ return -EBUSY;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, ®);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
|
|
|
-+ rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
|
|
|
-+ rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
|
|
|
-+
|
|
|
-+ rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
|
|
|
-+ USB_MODE_RESET, REGISTER_TIMEOUT);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, ®);
|
|
|
-+ rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
|
|
|
-+ rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
|
|
|
-+ rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
|
|
|
-+ rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, ®);
|
|
|
-+ rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
|
|
|
-+ rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
|
|
|
-+ rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
|
|
|
-+ rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 0);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
|
|
-+
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
|
|
|
-+ } else {
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
|
|
|
-+ rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0);
|
|
|
-+ rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
|
|
|
-+ rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0);
|
|
|
-+ rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0);
|
|
|
-+ rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1);
|
|
|
-+ rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0);
|
|
|
-+ rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
|
|
|
-+ rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
|
|
|
-+ rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
|
|
|
-+ rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2);
|
|
|
-+ else
|
|
|
-+ rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1);
|
|
|
-+ rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0);
|
|
|
-+ rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1);
|
|
|
-+ rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0);
|
|
|
-+ rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0);
|
|
|
-+ rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
|
|
|
-+ rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 8);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV, 1);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 8);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV, 1);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV, 1);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV, 1);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV, 1);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV, 1);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
|
|
|
-+ rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
|
|
|
-+ IEEE80211_MAX_RTS_THRESHOLD);
|
|
|
-+ rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * ASIC will keep garbage value after boot, clear encryption keys.
|
|
|
-+ */
|
|
|
-+ for (i = 0; i < 256; i++) {
|
|
|
-+ u32 wcid[2] = { 0xffffffff, 0x00ffffff };
|
|
|
-+ rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
|
|
|
-+ wcid, sizeof(wcid));
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ for (i = 0; i < 16; i++)
|
|
|
-+ rt2x00usb_register_write(rt2x00dev,
|
|
|
-+ SHARED_KEY_MODE_ENTRY(i), 0);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Clear all beacons
|
|
|
-+ * For the Beacon base registers we only need to clear
|
|
|
-+ * the first byte since that byte contains the VALID and OWNER
|
|
|
-+ * bits which (when set to 0) will invalidate the entire beacon.
|
|
|
-+ */
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, USB_CYC_CFG_CLOCK_CYCLE, 30);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, ®);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, ®);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13);
|
|
|
-+ rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, ®);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 3);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, ®);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1);
|
|
|
-+ rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * We must clear the error counters.
|
|
|
-+ * These registers are cleared on read,
|
|
|
-+ * so we may pass a useless variable to store the value.
|
|
|
-+ */
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, ®);
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, ®);
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, ®);
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, ®);
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, ®);
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, ®);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ unsigned int i;
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, ®);
|
|
|
-+ if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
|
|
|
-+ return 0;
|
|
|
-+
|
|
|
-+ udelay(REGISTER_BUSY_DELAY);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
|
|
|
-+ return -EACCES;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ unsigned int i;
|
|
|
-+ u8 value;
|
|
|
-+
|
|
|
-+ for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 0, &value);
|
|
|
-+ if ((value != 0xff) && (value != 0x00))
|
|
|
-+ return 0;
|
|
|
-+ udelay(REGISTER_BUSY_DELAY);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
|
|
|
-+ return -EACCES;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ unsigned int i;
|
|
|
-+ u16 eeprom;
|
|
|
-+ u8 reg_id;
|
|
|
-+ u8 value;
|
|
|
-+
|
|
|
-+ if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
|
|
|
-+ rt2800usb_wait_bbp_ready(rt2x00dev)))
|
|
|
-+ return -EACCES;
|
|
|
-+
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
|
|
|
-+
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ for (i = 0; i < EEPROM_BBP_SIZE; i++) {
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
|
|
|
-+
|
|
|
-+ if (eeprom != 0xffff && eeprom != 0x0000) {
|
|
|
-+ reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
|
|
|
-+ value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, reg_id, value);
|
|
|
-+ }
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ bool bw40, u8 rfcsr24, u8 filter_target)
|
|
|
-+{
|
|
|
-+ unsigned int i;
|
|
|
-+ u8 bbp;
|
|
|
-+ u8 rfcsr;
|
|
|
-+ u8 passband;
|
|
|
-+ u8 stopband;
|
|
|
-+ u8 overtuned = 0;
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
|
|
|
-+
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
|
|
|
-+ rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 4, bbp);
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
|
|
|
-+ rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Set power & frequency of passband test tone
|
|
|
-+ */
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 24, 0);
|
|
|
-+
|
|
|
-+ for (i = 0; i < 100; i++) {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
|
|
|
-+ msleep(1);
|
|
|
-+
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 55, &passband);
|
|
|
-+ if (passband)
|
|
|
-+ break;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Set power & frequency of stopband test tone
|
|
|
-+ */
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
|
|
|
-+
|
|
|
-+ for (i = 0; i < 100; i++) {
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
|
|
|
-+ msleep(1);
|
|
|
-+
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
|
|
|
-+
|
|
|
-+ if ((passband - stopband) <= filter_target) {
|
|
|
-+ rfcsr24++;
|
|
|
-+ overtuned += ((passband - stopband) == filter_target);
|
|
|
-+ } else
|
|
|
-+ break;
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rfcsr24 -= !!overtuned;
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
|
|
|
-+ return rfcsr24;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ u8 rfcsr;
|
|
|
-+ u8 bbp;
|
|
|
-+
|
|
|
-+ if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
|
|
|
-+ return 0;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Init RF calibration.
|
|
|
-+ */
|
|
|
-+ rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
|
|
|
-+ rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
|
|
|
-+ msleep(1);
|
|
|
-+ rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Set RX Filter calibration for 20MHz and 40MHz
|
|
|
-+ */
|
|
|
-+ rt2x00dev->calibration_bw20 =
|
|
|
-+ rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
|
|
|
-+ rt2x00dev->calibration_bw40 =
|
|
|
-+ rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Set back to initial state
|
|
|
-+ */
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 24, 0);
|
|
|
-+
|
|
|
-+ rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
|
|
|
-+ rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
|
|
|
-+ rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * set BBP back to BW20
|
|
|
-+ */
|
|
|
-+ rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
|
|
|
-+ rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
|
|
|
-+ rt2800usb_bbp_write(rt2x00dev, 4, bbp);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Device state switch handlers.
|
|
|
-+ */
|
|
|
-+static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ enum dev_state state)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
|
|
|
-+ rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX,
|
|
|
-+ (state == STATE_RADIO_RX_ON) ||
|
|
|
-+ (state == STATE_RADIO_RX_ON_LINK));
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ unsigned int i;
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
|
|
|
-+ if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
|
|
|
-+ !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
|
|
|
-+ return 0;
|
|
|
-+
|
|
|
-+ msleep(1);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
|
|
|
-+ return -EACCES;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+ u16 word;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Initialize all registers.
|
|
|
-+ */
|
|
|
-+ if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
|
|
|
-+ rt2800usb_init_registers(rt2x00dev) ||
|
|
|
-+ rt2800usb_init_bbp(rt2x00dev) ||
|
|
|
-+ rt2800usb_init_rfcsr(rt2x00dev)))
|
|
|
-+ return -EIO;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
|
|
|
-+ rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
|
|
|
-+
|
|
|
-+ udelay(50);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
|
|
|
-+
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, USB_DMA_CFG_PHY_CLEAR, 0);
|
|
|
-+ /* Don't use bulk in aggregation when working with USB 1.1 */
|
|
|
-+ rt2x00_set_field32(®, USB_DMA_CFG_RX_BULK_AGG_EN,
|
|
|
-+ (rt2x00dev->rx->usb_maxpacket == 512));
|
|
|
-+ rt2x00_set_field32(®, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
|
|
|
-+ /* FIXME: Calculate this value based on Aggregation defines */
|
|
|
-+ rt2x00_set_field32(®, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
|
|
|
-+ rt2x00_set_field32(®, USB_DMA_CFG_RX_BULK_EN, 1);
|
|
|
-+ rt2x00_set_field32(®, USB_DMA_CFG_TX_BULK_EN, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
|
|
|
-+ rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
|
|
|
-+ rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Send signal to firmware during boot time.
|
|
|
-+ */
|
|
|
-+ rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Initialize LED control
|
|
|
-+ */
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
|
|
|
-+ rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
|
|
|
-+ word & 0xff, (word >> 8) & 0xff);
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
|
|
|
-+ rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
|
|
|
-+ word & 0xff, (word >> 8) & 0xff);
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
|
|
|
-+ rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
|
|
|
-+ word & 0xff, (word >> 8) & 0xff);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
|
|
|
-+ rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
|
|
|
-+
|
|
|
-+ /* Wait for DMA, ignore error */
|
|
|
-+ rt2800usb_wait_wpdma_ready(rt2x00dev);
|
|
|
-+
|
|
|
-+ rt2x00usb_disable_radio(rt2x00dev);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ enum dev_state state)
|
|
|
-+{
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
|
|
|
-+
|
|
|
-+ if (state == STATE_AWAKE)
|
|
|
-+ rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
|
|
|
-+ else
|
|
|
-+ rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ enum dev_state state)
|
|
|
-+{
|
|
|
-+ int retval = 0;
|
|
|
-+
|
|
|
-+ switch (state) {
|
|
|
-+ case STATE_RADIO_ON:
|
|
|
-+ /*
|
|
|
-+ * Before the radio can be enabled, the device first has
|
|
|
-+ * to be woken up. After that it needs a bit of time
|
|
|
-+ * to be fully awake and the radio can be enabled.
|
|
|
-+ */
|
|
|
-+ rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
|
|
|
-+ msleep(1);
|
|
|
-+ retval = rt2800usb_enable_radio(rt2x00dev);
|
|
|
-+ break;
|
|
|
-+ case STATE_RADIO_OFF:
|
|
|
-+ /*
|
|
|
-+ * After the radio has been disablee, the device should
|
|
|
-+ * be put to sleep for powersaving.
|
|
|
-+ */
|
|
|
-+ rt2800usb_disable_radio(rt2x00dev);
|
|
|
-+ rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
|
|
|
-+ break;
|
|
|
-+ case STATE_RADIO_RX_ON:
|
|
|
-+ case STATE_RADIO_RX_ON_LINK:
|
|
|
-+ case STATE_RADIO_RX_OFF:
|
|
|
-+ case STATE_RADIO_RX_OFF_LINK:
|
|
|
-+ rt2800usb_toggle_rx(rt2x00dev, state);
|
|
|
-+ break;
|
|
|
-+ case STATE_RADIO_IRQ_ON:
|
|
|
-+ case STATE_RADIO_IRQ_OFF:
|
|
|
-+ /* No support, but no error either */
|
|
|
-+ break;
|
|
|
-+ case STATE_DEEP_SLEEP:
|
|
|
-+ case STATE_SLEEP:
|
|
|
-+ case STATE_STANDBY:
|
|
|
-+ case STATE_AWAKE:
|
|
|
-+ retval = rt2800usb_set_state(rt2x00dev, state);
|
|
|
-+ break;
|
|
|
-+ default:
|
|
|
-+ retval = -ENOTSUPP;
|
|
|
-+ break;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (unlikely(retval))
|
|
|
-+ ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
|
|
|
-+ state, retval);
|
|
|
-+
|
|
|
-+ return retval;
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX descriptor initialization
|
|
|
-+ */
|
|
|
-+static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ struct sk_buff *skb,
|
|
|
-+ struct txentry_desc *txdesc)
|
|
|
-+{
|
|
|
-+ struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
|
|
|
-+ __le32 *txi = skbdesc->desc;
|
|
|
-+ __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
|
|
|
-+ u32 word;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Initialize TX Info descriptor
|
|
|
-+ */
|
|
|
-+ rt2x00_desc_read(txwi, 0, &word);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_FRAG,
|
|
|
-+ test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_TS,
|
|
|
-+ test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_AMPDU,
|
|
|
-+ test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_BW,
|
|
|
-+ test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
|
|
|
-+ test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
|
|
|
-+ rt2x00_desc_write(txwi, 0, word);
|
|
|
-+
|
|
|
-+ rt2x00_desc_read(txwi, 1, &word);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W1_ACK,
|
|
|
-+ test_bit(ENTRY_TXD_ACK, &txdesc->flags));
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W1_NSEQ,
|
|
|
-+ test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
|
|
|
-+ test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
|
|
|
-+ txdesc->key_idx : 0xff);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
|
|
|
-+ rt2x00_set_field32(&word, TXWI_W1_PACKETID,
|
|
|
-+ skbdesc->entry->entry_idx);
|
|
|
-+ rt2x00_desc_write(txwi, 1, word);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Always write 0 to IV/EIV fields, hardware will insert the IV
|
|
|
-+ * from the IVEIV register when TXINFO_W0_WIV is set to 0.
|
|
|
-+ * When TXINFO_W0_WIV is set to 1 it will use the IV data
|
|
|
-+ * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
|
|
|
-+ * crypto entry in the registers should be used to encrypt the frame.
|
|
|
-+ */
|
|
|
-+ _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
|
|
|
-+ _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Initialize TX descriptor
|
|
|
-+ */
|
|
|
-+ rt2x00_desc_read(txi, 0, &word);
|
|
|
-+ rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
|
|
|
-+ skb->len + TXWI_DESC_SIZE);
|
|
|
-+ rt2x00_set_field32(&word, TXINFO_W0_WIV,
|
|
|
-+ !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
|
|
|
-+ rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
|
|
|
-+ rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
|
|
|
-+ rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
|
|
|
-+ rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
|
|
|
-+ test_bit(ENTRY_TXD_BURST, &txdesc->flags));
|
|
|
-+ rt2x00_desc_write(txi, 0, word);
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX data initialization
|
|
|
-+ */
|
|
|
-+static void rt2800usb_write_beacon(struct queue_entry *entry)
|
|
|
-+{
|
|
|
-+ struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
|
|
|
-+ struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
|
|
|
-+ unsigned int beacon_base;
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Add the descriptor in front of the skb.
|
|
|
-+ */
|
|
|
-+ skb_push(entry->skb, entry->queue->desc_size);
|
|
|
-+ memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
|
|
|
-+ skbdesc->desc = entry->skb->data;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Disable beaconing while we are reloading the beacon data,
|
|
|
-+ * otherwise we might be sending out invalid data.
|
|
|
-+ */
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Write entire beacon with descriptor to register.
|
|
|
-+ */
|
|
|
-+ beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
|
|
|
-+ rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
|
|
|
-+ USB_VENDOR_REQUEST_OUT, beacon_base,
|
|
|
-+ entry->skb->data, entry->skb->len,
|
|
|
-+ REGISTER_TIMEOUT32(entry->skb->len));
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Clean up the beacon skb.
|
|
|
-+ */
|
|
|
-+ dev_kfree_skb(entry->skb);
|
|
|
-+ entry->skb = NULL;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
|
|
|
-+{
|
|
|
-+ int length;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * The length _must_ include 4 bytes padding,
|
|
|
-+ * it should always be multiple of 4,
|
|
|
-+ * but it must _not_ be a multiple of the USB packet size.
|
|
|
-+ */
|
|
|
-+ length = roundup(entry->skb->len + 4, 4);
|
|
|
-+ length += (4 * !(length % entry->queue->usb_maxpacket));
|
|
|
-+
|
|
|
-+ return length;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
|
|
|
-+ const enum data_queue_qid queue)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ if (queue != QID_BEACON) {
|
|
|
-+ rt2x00usb_kick_tx_queue(rt2x00dev, queue);
|
|
|
-+ return;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
|
|
-+ if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
|
|
|
-+ rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
|
|
-+ }
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX control handlers
|
|
|
-+ */
|
|
|
-+static void rt2800usb_fill_rxdone(struct queue_entry *entry,
|
|
|
-+ struct rxdone_entry_desc *rxdesc)
|
|
|
-+{
|
|
|
-+ struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
|
|
|
-+ struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
|
|
|
-+ __le32 *rxd = (__le32 *)entry->skb->data;
|
|
|
-+ __le32 *rxwi;
|
|
|
-+ u32 rxd0;
|
|
|
-+ u32 rxwi0;
|
|
|
-+ u32 rxwi1;
|
|
|
-+ u32 rxwi2;
|
|
|
-+ u32 rxwi3;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Copy descriptor to the skbdesc->desc buffer, making it safe from
|
|
|
-+ * moving of frame data in rt2x00usb.
|
|
|
-+ */
|
|
|
-+ memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
|
|
|
-+ rxd = (__le32 *)skbdesc->desc;
|
|
|
-+ rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * It is now safe to read the descriptor on all architectures.
|
|
|
-+ */
|
|
|
-+ rt2x00_desc_read(rxd, 0, &rxd0);
|
|
|
-+ rt2x00_desc_read(rxwi, 0, &rxwi0);
|
|
|
-+ rt2x00_desc_read(rxwi, 1, &rxwi1);
|
|
|
-+ rt2x00_desc_read(rxwi, 2, &rxwi2);
|
|
|
-+ rt2x00_desc_read(rxwi, 3, &rxwi3);
|
|
|
-+
|
|
|
-+ if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
|
|
|
-+ rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
|
|
|
-+
|
|
|
-+ if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
|
|
|
-+ rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
|
|
|
-+ rxdesc->cipher_status =
|
|
|
-+ rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
|
|
|
-+ /*
|
|
|
-+ * Hardware has stripped IV/EIV data from 802.11 frame during
|
|
|
-+ * decryption. Unfortunately the descriptor doesn't contain
|
|
|
-+ * any fields with the EIV/IV data either, so they can't
|
|
|
-+ * be restored by rt2x00lib.
|
|
|
-+ */
|
|
|
-+ rxdesc->flags |= RX_FLAG_IV_STRIPPED;
|
|
|
-+
|
|
|
-+ if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
|
|
|
-+ rxdesc->flags |= RX_FLAG_DECRYPTED;
|
|
|
-+ else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
|
|
|
-+ rxdesc->flags |= RX_FLAG_MMIC_ERROR;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
|
|
|
-+ rxdesc->dev_flags |= RXDONE_MY_BSS;
|
|
|
-+
|
|
|
-+ if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
|
|
|
-+ rxdesc->flags |= RX_FLAG_SHORT_GI;
|
|
|
-+
|
|
|
-+ if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
|
|
|
-+ rxdesc->flags |= RX_FLAG_40MHZ;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Detect RX rate, always use MCS as signal type.
|
|
|
-+ */
|
|
|
-+ rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
|
|
|
-+ rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
|
|
|
-+ rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Mask of 0x8 bit to remove the short preamble flag.
|
|
|
-+ */
|
|
|
-+ if (rxdesc->rate_mode == RATE_MODE_CCK)
|
|
|
-+ rxdesc->signal &= ~0x8;
|
|
|
-+
|
|
|
-+ rxdesc->rssi =
|
|
|
-+ (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
|
|
|
-+ rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
|
|
|
-+
|
|
|
-+ rxdesc->noise =
|
|
|
-+ (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
|
|
|
-+ rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
|
|
|
-+
|
|
|
-+ rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Remove RXWI descriptor from start of buffer.
|
|
|
-+ */
|
|
|
-+ skb_pull(entry->skb, skbdesc->desc_len);
|
|
|
-+ skb_trim(entry->skb, rxdesc->size);
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Device probe functions.
|
|
|
-+ */
|
|
|
-+static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ u16 word;
|
|
|
-+ u8 *mac;
|
|
|
-+ u8 default_lna_gain;
|
|
|
-+
|
|
|
-+ rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Start validation of the data that has been read.
|
|
|
-+ */
|
|
|
-+ mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
|
|
|
-+ if (!is_valid_ether_addr(mac)) {
|
|
|
-+ DECLARE_MAC_BUF(macbuf);
|
|
|
-+
|
|
|
-+ random_ether_addr(mac);
|
|
|
-+ EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
|
|
|
-+ if (word == 0xffff) {
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
|
|
|
-+ EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
|
|
|
-+ } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
|
|
|
-+ /*
|
|
|
-+ * There is a max of 2 RX streams for RT2860 series
|
|
|
-+ */
|
|
|
-+ if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
|
|
|
-+ if (word == 0xffff) {
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
|
|
|
-+ EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
|
|
|
-+ if ((word & 0x00ff) == 0x00ff) {
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
|
|
|
-+ LED_MODE_TXRX_ACTIVITY);
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
|
|
|
-+ EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * During the LNA validation we are going to use
|
|
|
-+ * lna0 as correct value. Note that EEPROM_LNA
|
|
|
-+ * is never validated.
|
|
|
-+ */
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
|
|
|
-+ default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
|
|
|
-+ if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
|
|
|
-+ if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
|
|
|
-+ if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
|
|
|
-+ if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
|
|
|
-+ rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
|
|
|
-+ default_lna_gain);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
|
|
|
-+ if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
|
|
|
-+ if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
|
|
|
-+ if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
|
|
|
-+ if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
|
|
|
-+ rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
|
|
|
-+ rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
|
|
|
-+ default_lna_gain);
|
|
|
-+ rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ u32 reg;
|
|
|
-+ u16 value;
|
|
|
-+ u16 eeprom;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Read EEPROM word for configuration.
|
|
|
-+ */
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Identify RF chipset.
|
|
|
-+ */
|
|
|
-+ value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®);
|
|
|
-+ rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * The check for rt2860 is not a typo, some rt2870 hardware
|
|
|
-+ * identifies itself as rt2860 in the CSR register.
|
|
|
-+ */
|
|
|
-+ if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
|
|
|
-+ (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870) &&
|
|
|
-+ (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x3070)) {
|
|
|
-+ ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
|
|
|
-+ return -ENODEV;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
|
|
|
-+ !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
|
|
|
-+ !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
|
|
|
-+ !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
|
|
|
-+ !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
|
|
|
-+ !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
|
|
|
-+ ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
|
|
|
-+ return -ENODEV;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Read frequency offset and RF programming sequence.
|
|
|
-+ */
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
|
|
|
-+ rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Read external LNA informations.
|
|
|
-+ */
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
|
|
|
-+
|
|
|
-+ if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
|
|
|
-+ __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
|
|
|
-+ if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
|
|
|
-+ __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Detect if this device has an hardware controlled radio.
|
|
|
-+ */
|
|
|
-+#ifdef CONFIG_RT2X00_LIB_RFKILL
|
|
|
-+ if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
|
|
|
-+ __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
|
|
|
-+#endif /* CONFIG_RT2X00_LIB_RFKILL */
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Store led settings, for correct led behaviour.
|
|
|
-+ */
|
|
|
-+#ifdef CONFIG_RT2X00_LIB_LEDS
|
|
|
-+ rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
|
|
|
-+ rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
|
|
|
-+ rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
|
|
|
-+ &rt2x00dev->led_mcu_reg);
|
|
|
-+#endif /* CONFIG_RT2X00_LIB_LEDS */
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF value list for rt2870
|
|
|
-+ * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
|
|
|
-+ */
|
|
|
-+static const struct rf_channel rf_vals[] = {
|
|
|
-+ { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
|
|
|
-+ { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
|
|
|
-+ { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
|
|
|
-+ { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
|
|
|
-+ { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
|
|
|
-+ { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
|
|
|
-+ { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
|
|
|
-+ { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
|
|
|
-+ { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
|
|
|
-+ { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
|
|
|
-+ { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
|
|
|
-+ { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
|
|
|
-+ { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
|
|
|
-+ { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
|
|
|
-+
|
|
|
-+ /* 802.11 UNI / HyperLan 2 */
|
|
|
-+ { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
|
|
|
-+ { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
|
|
|
-+ { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
|
|
|
-+ { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
|
|
|
-+ { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
|
|
|
-+ { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
|
|
|
-+ { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
|
|
|
-+ { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
|
|
|
-+ { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
|
|
|
-+ { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
|
|
|
-+ { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
|
|
|
-+ { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
|
|
|
-+
|
|
|
-+ /* 802.11 HyperLan 2 */
|
|
|
-+ { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
|
|
|
-+ { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
|
|
|
-+ { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
|
|
|
-+ { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
|
|
|
-+ { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
|
|
|
-+ { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
|
|
|
-+ { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
|
|
|
-+ { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
|
|
|
-+ { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
|
|
|
-+ { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
|
|
|
-+ { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
|
|
|
-+ { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
|
|
|
-+ { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
|
|
|
-+ { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
|
|
|
-+ { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
|
|
|
-+ { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
|
|
|
-+
|
|
|
-+ /* 802.11 UNII */
|
|
|
-+ { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
|
|
|
-+ { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
|
|
|
-+ { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
|
|
|
-+ { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
|
|
|
-+ { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
|
|
|
-+ { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
|
|
|
-+ { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
|
|
|
-+ { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
|
|
|
-+ { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
|
|
|
-+ { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
|
|
|
-+ { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
|
|
|
-+
|
|
|
-+ /* 802.11 Japan */
|
|
|
-+ { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
|
|
|
-+ { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
|
|
|
-+ { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
|
|
|
-+ { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
|
|
|
-+ { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
|
|
|
-+ { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
|
|
|
-+ { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
|
|
|
-+};
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF value list for rt3070
|
|
|
-+ * Supports: 2.4 GHz
|
|
|
-+ */
|
|
|
-+static const struct rf_channel rf_vals_3070[] = {
|
|
|
-+ {1, 241, 2, 2 },
|
|
|
-+ {2, 241, 2, 7 },
|
|
|
-+ {3, 242, 2, 2 },
|
|
|
-+ {4, 242, 2, 7 },
|
|
|
-+ {5, 243, 2, 2 },
|
|
|
-+ {6, 243, 2, 7 },
|
|
|
-+ {7, 244, 2, 2 },
|
|
|
-+ {8, 244, 2, 7 },
|
|
|
-+ {9, 245, 2, 2 },
|
|
|
-+ {10, 245, 2, 7 },
|
|
|
-+ {11, 246, 2, 2 },
|
|
|
-+ {12, 246, 2, 7 },
|
|
|
-+ {13, 247, 2, 2 },
|
|
|
-+ {14, 248, 2, 4 },
|
|
|
-+};
|
|
|
-+
|
|
|
-+static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ struct hw_mode_spec *spec = &rt2x00dev->spec;
|
|
|
-+ struct channel_info *info;
|
|
|
-+ char *tx_power1;
|
|
|
-+ char *tx_power2;
|
|
|
-+ unsigned int i;
|
|
|
-+ u16 eeprom;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Initialize all hw fields.
|
|
|
-+ */
|
|
|
-+ rt2x00dev->hw->flags =
|
|
|
-+ IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
|
|
|
-+ IEEE80211_HW_SIGNAL_DBM |
|
|
|
-+ IEEE80211_HW_SUPPORTS_PS |
|
|
|
-+ IEEE80211_HW_PS_NULLFUNC_STACK;
|
|
|
-+ rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
|
|
|
-+
|
|
|
-+ SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
|
|
|
-+ SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
|
|
|
-+ rt2x00_eeprom_addr(rt2x00dev,
|
|
|
-+ EEPROM_MAC_ADDR_0));
|
|
|
-+
|
|
|
-+ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Initialize HT information.
|
|
|
-+ */
|
|
|
-+ spec->ht.ht_supported = true;
|
|
|
-+ spec->ht.cap =
|
|
|
-+ IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
|
|
|
-+ IEEE80211_HT_CAP_GRN_FLD |
|
|
|
-+ IEEE80211_HT_CAP_SGI_20 |
|
|
|
-+ IEEE80211_HT_CAP_SGI_40 |
|
|
|
-+ IEEE80211_HT_CAP_TX_STBC |
|
|
|
-+ IEEE80211_HT_CAP_RX_STBC |
|
|
|
-+ IEEE80211_HT_CAP_PSMP_SUPPORT;
|
|
|
-+ spec->ht.ampdu_factor = 3;
|
|
|
-+ spec->ht.ampdu_density = 4;
|
|
|
-+ spec->ht.mcs.tx_params =
|
|
|
-+ IEEE80211_HT_MCS_TX_DEFINED |
|
|
|
-+ IEEE80211_HT_MCS_TX_RX_DIFF |
|
|
|
-+ ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
|
|
|
-+ IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
|
|
|
-+
|
|
|
-+ switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
|
|
|
-+ case 3:
|
|
|
-+ spec->ht.mcs.rx_mask[2] = 0xff;
|
|
|
-+ case 2:
|
|
|
-+ spec->ht.mcs.rx_mask[1] = 0xff;
|
|
|
-+ case 1:
|
|
|
-+ spec->ht.mcs.rx_mask[0] = 0xff;
|
|
|
-+ spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
|
|
|
-+ break;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Initialize hw_mode information.
|
|
|
-+ */
|
|
|
-+ spec->supported_bands = SUPPORT_BAND_2GHZ;
|
|
|
-+ spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
|
|
|
-+
|
|
|
-+ if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
|
|
|
-+ rt2x00_rf(&rt2x00dev->chip, RF2720)) {
|
|
|
-+ spec->num_channels = 14;
|
|
|
-+ spec->channels = rf_vals;
|
|
|
-+ } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
|
|
|
-+ rt2x00_rf(&rt2x00dev->chip, RF2750)) {
|
|
|
-+ spec->supported_bands |= SUPPORT_BAND_5GHZ;
|
|
|
-+ spec->num_channels = ARRAY_SIZE(rf_vals);
|
|
|
-+ spec->channels = rf_vals;
|
|
|
-+ } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
|
|
|
-+ rt2x00_rf(&rt2x00dev->chip, RF2020)) {
|
|
|
-+ spec->num_channels = ARRAY_SIZE(rf_vals_3070);
|
|
|
-+ spec->channels = rf_vals_3070;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Create channel information array
|
|
|
-+ */
|
|
|
-+ info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
|
|
|
-+ if (!info)
|
|
|
-+ return -ENOMEM;
|
|
|
-+
|
|
|
-+ spec->channels_info = info;
|
|
|
-+
|
|
|
-+ tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
|
|
|
-+ tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
|
|
|
-+
|
|
|
-+ for (i = 0; i < 14; i++) {
|
|
|
-+ info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
|
|
|
-+ info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ if (spec->num_channels > 14) {
|
|
|
-+ tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
|
|
|
-+ tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
|
|
|
-+
|
|
|
-+ for (i = 14; i < spec->num_channels; i++) {
|
|
|
-+ info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
|
|
|
-+ info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
|
|
|
-+ }
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ int retval;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Allocate eeprom data.
|
|
|
-+ */
|
|
|
-+ retval = rt2800usb_validate_eeprom(rt2x00dev);
|
|
|
-+ if (retval)
|
|
|
-+ return retval;
|
|
|
-+
|
|
|
-+ retval = rt2800usb_init_eeprom(rt2x00dev);
|
|
|
-+ if (retval)
|
|
|
-+ return retval;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Initialize hw specifications.
|
|
|
-+ */
|
|
|
-+ retval = rt2800usb_probe_hw_mode(rt2x00dev);
|
|
|
-+ if (retval)
|
|
|
-+ return retval;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * This device requires firmware.
|
|
|
-+ */
|
|
|
-+ __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
|
|
|
-+ __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
|
|
|
-+ if (!modparam_nohwcrypt)
|
|
|
-+ __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Set the rssi offset.
|
|
|
-+ */
|
|
|
-+ rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * IEEE80211 stack callback functions.
|
|
|
-+ */
|
|
|
-+static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
|
|
|
-+ u32 *iv32, u16 *iv16)
|
|
|
-+{
|
|
|
-+ struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
-+ struct mac_iveiv_entry iveiv_entry;
|
|
|
-+ u32 offset;
|
|
|
-+
|
|
|
-+ offset = MAC_IVEIV_ENTRY(hw_key_idx);
|
|
|
-+ rt2x00usb_register_multiread(rt2x00dev, offset,
|
|
|
-+ &iveiv_entry, sizeof(iveiv_entry));
|
|
|
-+
|
|
|
-+ memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
|
|
|
-+ memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
|
|
|
-+{
|
|
|
-+ struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
-+ u32 reg;
|
|
|
-+ bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
|
|
|
-+ const struct ieee80211_tx_queue_params *params)
|
|
|
-+{
|
|
|
-+ struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
-+ struct data_queue *queue;
|
|
|
-+ struct rt2x00_field32 field;
|
|
|
-+ int retval;
|
|
|
-+ u32 reg;
|
|
|
-+ u32 offset;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * First pass the configuration through rt2x00lib, that will
|
|
|
-+ * update the queue settings and validate the input. After that
|
|
|
-+ * we are free to update the registers based on the value
|
|
|
-+ * in the queue parameter.
|
|
|
-+ */
|
|
|
-+ retval = rt2x00mac_conf_tx(hw, queue_idx, params);
|
|
|
-+ if (retval)
|
|
|
-+ return retval;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * We only need to perform additional register initialization
|
|
|
-+ * for WMM queues/
|
|
|
-+ */
|
|
|
-+ if (queue_idx >= 4)
|
|
|
-+ return 0;
|
|
|
-+
|
|
|
-+ queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
|
|
|
-+
|
|
|
-+ /* Update WMM TXOP register */
|
|
|
-+ offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
|
|
|
-+ field.bit_offset = (queue_idx & 1) * 16;
|
|
|
-+ field.bit_mask = 0xffff << field.bit_offset;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, offset, ®);
|
|
|
-+ rt2x00_set_field32(®, field, queue->txop);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, offset, reg);
|
|
|
-+
|
|
|
-+ /* Update WMM registers */
|
|
|
-+ field.bit_offset = queue_idx * 4;
|
|
|
-+ field.bit_mask = 0xf << field.bit_offset;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, field, queue->aifs);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, field, queue->cw_min);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, ®);
|
|
|
-+ rt2x00_set_field32(®, field, queue->cw_max);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
|
|
|
-+
|
|
|
-+ /* Update EDCA registers */
|
|
|
-+ offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, offset, ®);
|
|
|
-+ rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
|
|
|
-+ rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
|
|
|
-+ rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
|
|
|
-+ rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
|
|
|
-+ rt2x00usb_register_write(rt2x00dev, offset, reg);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
|
|
|
-+{
|
|
|
-+ struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
-+ u64 tsf;
|
|
|
-+ u32 reg;
|
|
|
-+
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, ®);
|
|
|
-+ tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
|
|
|
-+ rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, ®);
|
|
|
-+ tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
|
|
|
-+
|
|
|
-+ return tsf;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static const struct ieee80211_ops rt2800usb_mac80211_ops = {
|
|
|
-+ .tx = rt2x00mac_tx,
|
|
|
-+ .start = rt2x00mac_start,
|
|
|
-+ .stop = rt2x00mac_stop,
|
|
|
-+ .add_interface = rt2x00mac_add_interface,
|
|
|
-+ .remove_interface = rt2x00mac_remove_interface,
|
|
|
-+ .config = rt2x00mac_config,
|
|
|
-+ .config_interface = rt2x00mac_config_interface,
|
|
|
-+ .configure_filter = rt2x00mac_configure_filter,
|
|
|
-+ .set_key = rt2x00mac_set_key,
|
|
|
-+ .get_stats = rt2x00mac_get_stats,
|
|
|
-+ .get_tkip_seq = rt2800usb_get_tkip_seq,
|
|
|
-+ .set_rts_threshold = rt2800usb_set_rts_threshold,
|
|
|
-+ .bss_info_changed = rt2x00mac_bss_info_changed,
|
|
|
-+ .conf_tx = rt2800usb_conf_tx,
|
|
|
-+ .get_tx_stats = rt2x00mac_get_tx_stats,
|
|
|
-+ .get_tsf = rt2800usb_get_tsf,
|
|
|
-+};
|
|
|
-+
|
|
|
-+static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
|
|
|
-+ .probe_hw = rt2800usb_probe_hw,
|
|
|
-+ .get_firmware_name = rt2800usb_get_firmware_name,
|
|
|
-+ .check_firmware = rt2800usb_check_firmware,
|
|
|
-+ .load_firmware = rt2800usb_load_firmware,
|
|
|
-+ .initialize = rt2x00usb_initialize,
|
|
|
-+ .uninitialize = rt2x00usb_uninitialize,
|
|
|
-+ .clear_entry = rt2x00usb_clear_entry,
|
|
|
-+ .set_device_state = rt2800usb_set_device_state,
|
|
|
-+ .rfkill_poll = rt2800usb_rfkill_poll,
|
|
|
-+ .link_stats = rt2800usb_link_stats,
|
|
|
-+ .reset_tuner = rt2800usb_reset_tuner,
|
|
|
-+ .link_tuner = rt2800usb_link_tuner,
|
|
|
-+ .write_tx_desc = rt2800usb_write_tx_desc,
|
|
|
-+ .write_tx_data = rt2x00usb_write_tx_data,
|
|
|
-+ .write_beacon = rt2800usb_write_beacon,
|
|
|
-+ .get_tx_data_len = rt2800usb_get_tx_data_len,
|
|
|
-+ .kick_tx_queue = rt2800usb_kick_tx_queue,
|
|
|
-+ .kill_tx_queue = rt2x00usb_kill_tx_queue,
|
|
|
-+ .fill_rxdone = rt2800usb_fill_rxdone,
|
|
|
-+ .config_shared_key = rt2800usb_config_shared_key,
|
|
|
-+ .config_pairwise_key = rt2800usb_config_pairwise_key,
|
|
|
-+ .config_filter = rt2800usb_config_filter,
|
|
|
-+ .config_intf = rt2800usb_config_intf,
|
|
|
-+ .config_erp = rt2800usb_config_erp,
|
|
|
-+ .config_ant = rt2800usb_config_ant,
|
|
|
-+ .config = rt2800usb_config,
|
|
|
-+};
|
|
|
-+
|
|
|
-+static const struct data_queue_desc rt2800usb_queue_rx = {
|
|
|
-+ .entry_num = RX_ENTRIES,
|
|
|
-+ .data_size = AGGREGATION_SIZE,
|
|
|
-+ .desc_size = RXD_DESC_SIZE + RXWI_DESC_SIZE,
|
|
|
-+ .priv_size = sizeof(struct queue_entry_priv_usb),
|
|
|
-+};
|
|
|
-+
|
|
|
-+static const struct data_queue_desc rt2800usb_queue_tx = {
|
|
|
-+ .entry_num = TX_ENTRIES,
|
|
|
-+ .data_size = AGGREGATION_SIZE,
|
|
|
-+ .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
|
|
|
-+ .priv_size = sizeof(struct queue_entry_priv_usb),
|
|
|
-+};
|
|
|
-+
|
|
|
-+static const struct data_queue_desc rt2800usb_queue_bcn = {
|
|
|
-+ .entry_num = 8 * BEACON_ENTRIES,
|
|
|
-+ .data_size = MGMT_FRAME_SIZE,
|
|
|
-+ .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
|
|
|
-+ .priv_size = sizeof(struct queue_entry_priv_usb),
|
|
|
-+};
|
|
|
-+
|
|
|
-+static const struct rt2x00_ops rt2800usb_ops = {
|
|
|
-+ .name = KBUILD_MODNAME,
|
|
|
-+ .max_sta_intf = 1,
|
|
|
-+ .max_ap_intf = 8,
|
|
|
-+ .eeprom_size = EEPROM_SIZE,
|
|
|
-+ .rf_size = RF_SIZE,
|
|
|
-+ .tx_queues = NUM_TX_QUEUES,
|
|
|
-+ .rx = &rt2800usb_queue_rx,
|
|
|
-+ .tx = &rt2800usb_queue_tx,
|
|
|
-+ .bcn = &rt2800usb_queue_bcn,
|
|
|
-+ .lib = &rt2800usb_rt2x00_ops,
|
|
|
-+ .hw = &rt2800usb_mac80211_ops,
|
|
|
-+#ifdef CONFIG_RT2X00_LIB_DEBUGFS
|
|
|
-+ .debugfs = &rt2800usb_rt2x00debug,
|
|
|
-+#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
|
|
|
-+};
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * rt2800usb module information.
|
|
|
-+ */
|
|
|
-+static struct usb_device_id rt2800usb_device_table[] = {
|
|
|
-+ /* Abocom */
|
|
|
-+ { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* AirTies */
|
|
|
-+ { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Amigo */
|
|
|
-+ { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Amit */
|
|
|
-+ { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* ASUS */
|
|
|
-+ { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* AzureWave */
|
|
|
-+ { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Belkin */
|
|
|
-+ { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Buffalo */
|
|
|
-+ { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Conceptronic */
|
|
|
-+ { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Corega */
|
|
|
-+ { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* D-Link */
|
|
|
-+ { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x2001, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x2001, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Edimax */
|
|
|
-+ { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* EnGenius */
|
|
|
-+ { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Gemtek */
|
|
|
-+ { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Gigabyte */
|
|
|
-+ { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Hawking */
|
|
|
-+ { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* LevelOne */
|
|
|
-+ { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Linksys */
|
|
|
-+ { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Logitec */
|
|
|
-+ { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Pegatron */
|
|
|
-+ { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Philips */
|
|
|
-+ { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Planex */
|
|
|
-+ { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Qcom */
|
|
|
-+ { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Quanta */
|
|
|
-+ { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Ralink */
|
|
|
-+ { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Samsung */
|
|
|
-+ { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Siemens */
|
|
|
-+ { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Sitecom */
|
|
|
-+ { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* SMC */
|
|
|
-+ { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Sparklan */
|
|
|
-+ { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* U-Media*/
|
|
|
-+ { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* ZCOM */
|
|
|
-+ { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Zinwell */
|
|
|
-+ { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ /* Zyxel */
|
|
|
-+ { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
|
|
|
-+ { 0, }
|
|
|
-+};
|
|
|
-+
|
|
|
-+MODULE_AUTHOR(DRV_PROJECT);
|
|
|
-+MODULE_VERSION(DRV_VERSION);
|
|
|
-+MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
|
|
|
-+MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
|
|
|
-+MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
|
|
|
-+MODULE_FIRMWARE(FIRMWARE_RT2870);
|
|
|
-+MODULE_LICENSE("GPL");
|
|
|
-+
|
|
|
-+static struct usb_driver rt2800usb_driver = {
|
|
|
-+ .name = KBUILD_MODNAME,
|
|
|
-+ .id_table = rt2800usb_device_table,
|
|
|
-+ .probe = rt2x00usb_probe,
|
|
|
-+ .disconnect = rt2x00usb_disconnect,
|
|
|
-+ .suspend = rt2x00usb_suspend,
|
|
|
-+ .resume = rt2x00usb_resume,
|
|
|
-+};
|
|
|
-+
|
|
|
-+static int __init rt2800usb_init(void)
|
|
|
-+{
|
|
|
-+ return usb_register(&rt2800usb_driver);
|
|
|
-+}
|
|
|
-+
|
|
|
-+static void __exit rt2800usb_exit(void)
|
|
|
-+{
|
|
|
-+ usb_deregister(&rt2800usb_driver);
|
|
|
-+}
|
|
|
-+
|
|
|
-+module_init(rt2800usb_init);
|
|
|
-+module_exit(rt2800usb_exit);
|
|
|
---- /dev/null
|
|
|
-+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
|
|
|
-@@ -0,0 +1,1934 @@
|
|
|
-+/*
|
|
|
-+ Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
|
|
|
-+ <http://rt2x00.serialmonkey.com>
|
|
|
-+
|
|
|
-+ This program is free software; you can redistribute it and/or modify
|
|
|
-+ it under the terms of the GNU General Public License as published by
|
|
|
-+ the Free Software Foundation; either version 2 of the License, or
|
|
|
-+ (at your option) any later version.
|
|
|
-+
|
|
|
-+ This program is distributed in the hope that it will be useful,
|
|
|
-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
-+ GNU General Public License for more details.
|
|
|
-+
|
|
|
-+ You should have received a copy of the GNU General Public License
|
|
|
-+ along with this program; if not, write to the
|
|
|
-+ Free Software Foundation, Inc.,
|
|
|
-+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ Module: rt2800usb
|
|
|
-+ Abstract: Data structures and registers for the rt2800usb module.
|
|
|
-+ Supported chipsets: RT2800U.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+#ifndef RT2800USB_H
|
|
|
-+#define RT2800USB_H
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF chip defines.
|
|
|
-+ *
|
|
|
-+ * RF2820 2.4G 2T3R
|
|
|
-+ * RF2850 2.4G/5G 2T3R
|
|
|
-+ * RF2720 2.4G 1T2R
|
|
|
-+ * RF2750 2.4G/5G 1T2R
|
|
|
-+ * RF3020 2.4G 1T1R
|
|
|
-+ * RF2020 2.4G B/G
|
|
|
-+ */
|
|
|
-+#define RF2820 0x0001
|
|
|
-+#define RF2850 0x0002
|
|
|
-+#define RF2720 0x0003
|
|
|
-+#define RF2750 0x0004
|
|
|
-+#define RF3020 0x0005
|
|
|
-+#define RF2020 0x0006
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RT2870 version
|
|
|
-+ */
|
|
|
-+#define RT2860C_VERSION 0x28600100
|
|
|
-+#define RT2860D_VERSION 0x28600101
|
|
|
-+#define RT2880E_VERSION 0x28720200
|
|
|
-+#define RT2883_VERSION 0x28830300
|
|
|
-+#define RT3070_VERSION 0x30700200
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Signal information.
|
|
|
-+ * Defaul offset is required for RSSI <-> dBm conversion.
|
|
|
-+ */
|
|
|
-+#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Register layout information.
|
|
|
-+ */
|
|
|
-+#define CSR_REG_BASE 0x1000
|
|
|
-+#define CSR_REG_SIZE 0x0800
|
|
|
-+#define EEPROM_BASE 0x0000
|
|
|
-+#define EEPROM_SIZE 0x0110
|
|
|
-+#define BBP_BASE 0x0000
|
|
|
-+#define BBP_SIZE 0x0080
|
|
|
-+#define RF_BASE 0x0004
|
|
|
-+#define RF_SIZE 0x0010
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Number of TX queues.
|
|
|
-+ */
|
|
|
-+#define NUM_TX_QUEUES 4
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * USB registers.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HOST-MCU shared memory
|
|
|
-+ */
|
|
|
-+#define HOST_CMD_CSR 0x0404
|
|
|
-+#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * INT_SOURCE_CSR: Interrupt source register.
|
|
|
-+ * Write one to clear corresponding bit.
|
|
|
-+ * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
|
|
|
-+ */
|
|
|
-+#define INT_SOURCE_CSR 0x0200
|
|
|
-+#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
|
|
|
-+#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
|
|
|
-+#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
|
|
|
-+#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
|
|
|
-+#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
|
|
|
-+#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
|
|
|
-+#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
|
|
|
-+#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
|
|
|
-+#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
|
|
|
-+#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
|
|
|
-+#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
|
|
|
-+#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
|
|
|
-+#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
|
|
|
-+#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
|
|
|
-+#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
|
|
|
-+#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
|
|
|
-+#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
|
|
|
-+#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
|
|
|
-+ */
|
|
|
-+#define INT_MASK_CSR 0x0204
|
|
|
-+#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
|
|
|
-+#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
|
|
|
-+#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
|
|
|
-+#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
|
|
|
-+#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
|
|
|
-+#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
|
|
|
-+#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
|
|
|
-+#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
|
|
|
-+#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
|
|
|
-+#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
|
|
|
-+#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
|
|
|
-+#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
|
|
|
-+#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
|
|
|
-+#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
|
|
|
-+#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
|
|
|
-+#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
|
|
|
-+#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
|
|
|
-+#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * WPDMA_GLO_CFG
|
|
|
-+ */
|
|
|
-+#define WPDMA_GLO_CFG 0x0208
|
|
|
-+#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
|
|
|
-+#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
|
|
|
-+#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
|
|
|
-+#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
|
|
|
-+#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
|
|
|
-+#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
|
|
|
-+#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
|
|
|
-+#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
|
|
|
-+#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * WPDMA_RST_IDX
|
|
|
-+ */
|
|
|
-+#define WPDMA_RST_IDX 0x020c
|
|
|
-+#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
|
|
|
-+#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
|
|
|
-+#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
|
|
|
-+#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
|
|
|
-+#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
|
|
|
-+#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
|
|
|
-+#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * DELAY_INT_CFG
|
|
|
-+ */
|
|
|
-+#define DELAY_INT_CFG 0x0210
|
|
|
-+#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
|
|
|
-+#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
|
|
|
-+#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
|
|
|
-+#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
|
|
|
-+#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
|
|
|
-+#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * WMM_AIFSN_CFG: Aifsn for each EDCA AC
|
|
|
-+ * AIFSN0: AC_BE
|
|
|
-+ * AIFSN1: AC_BK
|
|
|
-+ * AIFSN1: AC_VI
|
|
|
-+ * AIFSN1: AC_VO
|
|
|
-+ */
|
|
|
-+#define WMM_AIFSN_CFG 0x0214
|
|
|
-+#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
|
|
|
-+#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
|
|
|
-+#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
|
|
|
-+#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * WMM_CWMIN_CSR: CWmin for each EDCA AC
|
|
|
-+ * CWMIN0: AC_BE
|
|
|
-+ * CWMIN1: AC_BK
|
|
|
-+ * CWMIN1: AC_VI
|
|
|
-+ * CWMIN1: AC_VO
|
|
|
-+ */
|
|
|
-+#define WMM_CWMIN_CFG 0x0218
|
|
|
-+#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
|
|
|
-+#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
|
|
|
-+#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
|
|
|
-+#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * WMM_CWMAX_CSR: CWmax for each EDCA AC
|
|
|
-+ * CWMAX0: AC_BE
|
|
|
-+ * CWMAX1: AC_BK
|
|
|
-+ * CWMAX1: AC_VI
|
|
|
-+ * CWMAX1: AC_VO
|
|
|
-+ */
|
|
|
-+#define WMM_CWMAX_CFG 0x021c
|
|
|
-+#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
|
|
|
-+#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
|
|
|
-+#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
|
|
|
-+#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * AC_TXOP0: AC_BK/AC_BE TXOP register
|
|
|
-+ * AC0TXOP: AC_BK in unit of 32us
|
|
|
-+ * AC1TXOP: AC_BE in unit of 32us
|
|
|
-+ */
|
|
|
-+#define WMM_TXOP0_CFG 0x0220
|
|
|
-+#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
|
|
|
-+#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * AC_TXOP1: AC_VO/AC_VI TXOP register
|
|
|
-+ * AC2TXOP: AC_VI in unit of 32us
|
|
|
-+ * AC3TXOP: AC_VO in unit of 32us
|
|
|
-+ */
|
|
|
-+#define WMM_TXOP1_CFG 0x0224
|
|
|
-+#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
|
|
|
-+#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * GPIO_CTRL_CFG:
|
|
|
-+ */
|
|
|
-+#define GPIO_CTRL_CFG 0x0228
|
|
|
-+#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
|
|
|
-+#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
|
|
|
-+#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
|
|
|
-+#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
|
|
|
-+#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
|
|
|
-+#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
|
|
|
-+#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
|
|
|
-+#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
|
|
|
-+#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MCU_CMD_CFG
|
|
|
-+ */
|
|
|
-+#define MCU_CMD_CFG 0x022c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * AC_BK register offsets
|
|
|
-+ */
|
|
|
-+#define TX_BASE_PTR0 0x0230
|
|
|
-+#define TX_MAX_CNT0 0x0234
|
|
|
-+#define TX_CTX_IDX0 0x0238
|
|
|
-+#define TX_DTX_IDX0 0x023c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * AC_BE register offsets
|
|
|
-+ */
|
|
|
-+#define TX_BASE_PTR1 0x0240
|
|
|
-+#define TX_MAX_CNT1 0x0244
|
|
|
-+#define TX_CTX_IDX1 0x0248
|
|
|
-+#define TX_DTX_IDX1 0x024c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * AC_VI register offsets
|
|
|
-+ */
|
|
|
-+#define TX_BASE_PTR2 0x0250
|
|
|
-+#define TX_MAX_CNT2 0x0254
|
|
|
-+#define TX_CTX_IDX2 0x0258
|
|
|
-+#define TX_DTX_IDX2 0x025c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * AC_VO register offsets
|
|
|
-+ */
|
|
|
-+#define TX_BASE_PTR3 0x0260
|
|
|
-+#define TX_MAX_CNT3 0x0264
|
|
|
-+#define TX_CTX_IDX3 0x0268
|
|
|
-+#define TX_DTX_IDX3 0x026c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HCCA register offsets
|
|
|
-+ */
|
|
|
-+#define TX_BASE_PTR4 0x0270
|
|
|
-+#define TX_MAX_CNT4 0x0274
|
|
|
-+#define TX_CTX_IDX4 0x0278
|
|
|
-+#define TX_DTX_IDX4 0x027c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MGMT register offsets
|
|
|
-+ */
|
|
|
-+#define TX_BASE_PTR5 0x0280
|
|
|
-+#define TX_MAX_CNT5 0x0284
|
|
|
-+#define TX_CTX_IDX5 0x0288
|
|
|
-+#define TX_DTX_IDX5 0x028c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX register offsets
|
|
|
-+ */
|
|
|
-+#define RX_BASE_PTR 0x0290
|
|
|
-+#define RX_MAX_CNT 0x0294
|
|
|
-+#define RX_CRX_IDX 0x0298
|
|
|
-+#define RX_DRX_IDX 0x029c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * USB_DMA_CFG
|
|
|
-+ * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
|
|
|
-+ * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
|
|
|
-+ * PHY_CLEAR: phy watch dog enable.
|
|
|
-+ * TX_CLEAR: Clear USB DMA TX path.
|
|
|
-+ * TXOP_HALT: Halt TXOP count down when TX buffer is full.
|
|
|
-+ * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
|
|
|
-+ * RX_BULK_EN: Enable USB DMA Rx.
|
|
|
-+ * TX_BULK_EN: Enable USB DMA Tx.
|
|
|
-+ * EP_OUT_VALID: OUT endpoint data valid.
|
|
|
-+ * RX_BUSY: USB DMA RX FSM busy.
|
|
|
-+ * TX_BUSY: USB DMA TX FSM busy.
|
|
|
-+ */
|
|
|
-+#define USB_DMA_CFG 0x02a0
|
|
|
-+#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
|
|
|
-+#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
|
|
|
-+#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
|
|
|
-+#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
|
|
|
-+#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
|
|
|
-+#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
|
|
|
-+#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
|
|
|
-+#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
|
|
|
-+#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
|
|
|
-+#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
|
|
|
-+#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * USB_CYC_CFG
|
|
|
-+ */
|
|
|
-+#define USB_CYC_CFG 0x02a4
|
|
|
-+#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * PBF_SYS_CTRL
|
|
|
-+ * HOST_RAM_WRITE: enable Host program ram write selection
|
|
|
-+ */
|
|
|
-+#define PBF_SYS_CTRL 0x0400
|
|
|
-+#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
|
|
|
-+#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * PBF registers
|
|
|
-+ * Most are for debug. Driver doesn't touch PBF register.
|
|
|
-+ */
|
|
|
-+#define PBF_CFG 0x0408
|
|
|
-+#define PBF_MAX_PCNT 0x040c
|
|
|
-+#define PBF_CTRL 0x0410
|
|
|
-+#define PBF_INT_STA 0x0414
|
|
|
-+#define PBF_INT_ENA 0x0418
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * BCN_OFFSET0:
|
|
|
-+ */
|
|
|
-+#define BCN_OFFSET0 0x042c
|
|
|
-+#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
|
|
|
-+#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
|
|
|
-+#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
|
|
|
-+#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * BCN_OFFSET1:
|
|
|
-+ */
|
|
|
-+#define BCN_OFFSET1 0x0430
|
|
|
-+#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
|
|
|
-+#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
|
|
|
-+#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
|
|
|
-+#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * PBF registers
|
|
|
-+ * Most are for debug. Driver doesn't touch PBF register.
|
|
|
-+ */
|
|
|
-+#define TXRXQ_PCNT 0x0438
|
|
|
-+#define PBF_DBG 0x043c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF registers
|
|
|
-+ */
|
|
|
-+#define RF_CSR_CFG 0x0500
|
|
|
-+#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
|
|
|
-+#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
|
|
|
-+#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
|
|
|
-+#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAC Control/Status Registers(CSR).
|
|
|
-+ * Some values are set in TU, whereas 1 TU == 1024 us.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAC_CSR0: ASIC revision number.
|
|
|
-+ * ASIC_REV: 0
|
|
|
-+ * ASIC_VER: 2870
|
|
|
-+ */
|
|
|
-+#define MAC_CSR0 0x1000
|
|
|
-+#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
|
|
|
-+#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAC_SYS_CTRL:
|
|
|
-+ */
|
|
|
-+#define MAC_SYS_CTRL 0x1004
|
|
|
-+#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
|
|
|
-+#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
|
|
|
-+#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
|
|
|
-+#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
|
|
|
-+#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
|
|
|
-+#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
|
|
|
-+#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
|
|
|
-+#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAC_ADDR_DW0: STA MAC register 0
|
|
|
-+ */
|
|
|
-+#define MAC_ADDR_DW0 0x1008
|
|
|
-+#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
|
|
|
-+#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
|
|
|
-+#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
|
|
|
-+#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAC_ADDR_DW1: STA MAC register 1
|
|
|
-+ * UNICAST_TO_ME_MASK:
|
|
|
-+ * Used to mask off bits from byte 5 of the MAC address
|
|
|
-+ * to determine the UNICAST_TO_ME bit for RX frames.
|
|
|
-+ * The full mask is complemented by BSS_ID_MASK:
|
|
|
-+ * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
|
|
|
-+ */
|
|
|
-+#define MAC_ADDR_DW1 0x100c
|
|
|
-+#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
|
|
|
-+#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
|
|
|
-+#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAC_BSSID_DW0: BSSID register 0
|
|
|
-+ */
|
|
|
-+#define MAC_BSSID_DW0 0x1010
|
|
|
-+#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
|
|
|
-+#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
|
|
|
-+#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
|
|
|
-+#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAC_BSSID_DW1: BSSID register 1
|
|
|
-+ * BSS_ID_MASK:
|
|
|
-+ * 0: 1-BSSID mode (BSS index = 0)
|
|
|
-+ * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
|
|
|
-+ * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
|
|
|
-+ * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
|
|
|
-+ * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
|
|
|
-+ * BSSID. This will make sure that those bits will be ignored
|
|
|
-+ * when determining the MY_BSS of RX frames.
|
|
|
-+ */
|
|
|
-+#define MAC_BSSID_DW1 0x1014
|
|
|
-+#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
|
|
|
-+#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
|
|
|
-+#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
|
|
|
-+#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAX_LEN_CFG: Maximum frame length register.
|
|
|
-+ * MAX_MPDU: rt2860b max 16k bytes
|
|
|
-+ * MAX_PSDU: Maximum PSDU length
|
|
|
-+ * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
|
|
|
-+ */
|
|
|
-+#define MAX_LEN_CFG 0x1018
|
|
|
-+#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
|
|
|
-+#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
|
|
|
-+#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
|
|
|
-+#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * BBP_CSR_CFG: BBP serial control register
|
|
|
-+ * VALUE: Register value to program into BBP
|
|
|
-+ * REG_NUM: Selected BBP register
|
|
|
-+ * READ_CONTROL: 0 write BBP, 1 read BBP
|
|
|
-+ * BUSY: ASIC is busy executing BBP commands
|
|
|
-+ * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
|
|
|
-+ * BBP_RW_MODE: 0 serial, 1 paralell
|
|
|
-+ */
|
|
|
-+#define BBP_CSR_CFG 0x101c
|
|
|
-+#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
|
|
|
-+#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
|
|
|
-+#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
|
|
|
-+#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
|
|
|
-+#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
|
|
|
-+#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF_CSR_CFG0: RF control register
|
|
|
-+ * REGID_AND_VALUE: Register value to program into RF
|
|
|
-+ * BITWIDTH: Selected RF register
|
|
|
-+ * STANDBYMODE: 0 high when standby, 1 low when standby
|
|
|
-+ * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
|
|
|
-+ * BUSY: ASIC is busy executing RF commands
|
|
|
-+ */
|
|
|
-+#define RF_CSR_CFG0 0x1020
|
|
|
-+#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
|
|
|
-+#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
|
|
|
-+#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
|
|
|
-+#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
|
|
|
-+#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
|
|
|
-+#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF_CSR_CFG1: RF control register
|
|
|
-+ * REGID_AND_VALUE: Register value to program into RF
|
|
|
-+ * RFGAP: Gap between BB_CONTROL_RF and RF_LE
|
|
|
-+ * 0: 3 system clock cycle (37.5usec)
|
|
|
-+ * 1: 5 system clock cycle (62.5usec)
|
|
|
-+ */
|
|
|
-+#define RF_CSR_CFG1 0x1024
|
|
|
-+#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
|
|
|
-+#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF_CSR_CFG2: RF control register
|
|
|
-+ * VALUE: Register value to program into RF
|
|
|
-+ * RFGAP: Gap between BB_CONTROL_RF and RF_LE
|
|
|
-+ * 0: 3 system clock cycle (37.5usec)
|
|
|
-+ * 1: 5 system clock cycle (62.5usec)
|
|
|
-+ */
|
|
|
-+#define RF_CSR_CFG2 0x1028
|
|
|
-+#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * LED_CFG: LED control
|
|
|
-+ * color LED's:
|
|
|
-+ * 0: off
|
|
|
-+ * 1: blinking upon TX2
|
|
|
-+ * 2: periodic slow blinking
|
|
|
-+ * 3: always on
|
|
|
-+ * LED polarity:
|
|
|
-+ * 0: active low
|
|
|
-+ * 1: active high
|
|
|
-+ */
|
|
|
-+#define LED_CFG 0x102c
|
|
|
-+#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
|
|
|
-+#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
|
|
|
-+#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
|
|
|
-+#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
|
|
|
-+#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
|
|
|
-+#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
|
|
|
-+#define LED_CFG_LED_POLAR FIELD32(0x40000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * XIFS_TIME_CFG: MAC timing
|
|
|
-+ * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
|
|
|
-+ * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
|
|
|
-+ * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
|
|
|
-+ * when MAC doesn't reference BBP signal BBRXEND
|
|
|
-+ * EIFS: unit 1us
|
|
|
-+ * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
|
|
|
-+ *
|
|
|
-+ */
|
|
|
-+#define XIFS_TIME_CFG 0x1100
|
|
|
-+#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
|
|
|
-+#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
|
|
|
-+#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
|
|
|
-+#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
|
|
|
-+#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * BKOFF_SLOT_CFG:
|
|
|
-+ */
|
|
|
-+#define BKOFF_SLOT_CFG 0x1104
|
|
|
-+#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
|
|
|
-+#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * NAV_TIME_CFG:
|
|
|
-+ */
|
|
|
-+#define NAV_TIME_CFG 0x1108
|
|
|
-+#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
|
|
|
-+#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
|
|
|
-+#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
|
|
|
-+#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * CH_TIME_CFG: count as channel busy
|
|
|
-+ */
|
|
|
-+#define CH_TIME_CFG 0x110c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
|
|
|
-+ */
|
|
|
-+#define PBF_LIFE_TIMER 0x1110
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * BCN_TIME_CFG:
|
|
|
-+ * BEACON_INTERVAL: in unit of 1/16 TU
|
|
|
-+ * TSF_TICKING: Enable TSF auto counting
|
|
|
-+ * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
|
|
|
-+ * BEACON_GEN: Enable beacon generator
|
|
|
-+ */
|
|
|
-+#define BCN_TIME_CFG 0x1114
|
|
|
-+#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
|
|
|
-+#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
|
|
|
-+#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
|
|
|
-+#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
|
|
|
-+#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
|
|
|
-+#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TBTT_SYNC_CFG:
|
|
|
-+ */
|
|
|
-+#define TBTT_SYNC_CFG 0x1118
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TSF_TIMER_DW0: Local lsb TSF timer, read-only
|
|
|
-+ */
|
|
|
-+#define TSF_TIMER_DW0 0x111c
|
|
|
-+#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TSF_TIMER_DW1: Local msb TSF timer, read-only
|
|
|
-+ */
|
|
|
-+#define TSF_TIMER_DW1 0x1120
|
|
|
-+#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TBTT_TIMER: TImer remains till next TBTT, read-only
|
|
|
-+ */
|
|
|
-+#define TBTT_TIMER 0x1124
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * INT_TIMER_CFG:
|
|
|
-+ */
|
|
|
-+#define INT_TIMER_CFG 0x1128
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
|
|
|
-+ */
|
|
|
-+#define INT_TIMER_EN 0x112c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * CH_IDLE_STA: channel idle time
|
|
|
-+ */
|
|
|
-+#define CH_IDLE_STA 0x1130
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * CH_BUSY_STA: channel busy time
|
|
|
-+ */
|
|
|
-+#define CH_BUSY_STA 0x1134
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAC_STATUS_CFG:
|
|
|
-+ * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
|
|
|
-+ * if 1 or higher one of the 2 registers is busy.
|
|
|
-+ */
|
|
|
-+#define MAC_STATUS_CFG 0x1200
|
|
|
-+#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * PWR_PIN_CFG:
|
|
|
-+ */
|
|
|
-+#define PWR_PIN_CFG 0x1204
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * AUTOWAKEUP_CFG: Manual power control / status register
|
|
|
-+ * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
|
|
|
-+ * AUTOWAKE: 0:sleep, 1:awake
|
|
|
-+ */
|
|
|
-+#define AUTOWAKEUP_CFG 0x1208
|
|
|
-+#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
|
|
|
-+#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
|
|
|
-+#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EDCA_AC0_CFG:
|
|
|
-+ */
|
|
|
-+#define EDCA_AC0_CFG 0x1300
|
|
|
-+#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
|
|
|
-+#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
|
|
|
-+#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
|
|
|
-+#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EDCA_AC1_CFG:
|
|
|
-+ */
|
|
|
-+#define EDCA_AC1_CFG 0x1304
|
|
|
-+#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
|
|
|
-+#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
|
|
|
-+#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
|
|
|
-+#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EDCA_AC2_CFG:
|
|
|
-+ */
|
|
|
-+#define EDCA_AC2_CFG 0x1308
|
|
|
-+#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
|
|
|
-+#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
|
|
|
-+#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
|
|
|
-+#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EDCA_AC3_CFG:
|
|
|
-+ */
|
|
|
-+#define EDCA_AC3_CFG 0x130c
|
|
|
-+#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
|
|
|
-+#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
|
|
|
-+#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
|
|
|
-+#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EDCA_TID_AC_MAP:
|
|
|
-+ */
|
|
|
-+#define EDCA_TID_AC_MAP 0x1310
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_PWR_CFG_0:
|
|
|
-+ */
|
|
|
-+#define TX_PWR_CFG_0 0x1314
|
|
|
-+#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
|
|
|
-+#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
|
|
|
-+#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
|
|
|
-+#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
|
|
|
-+#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
|
|
|
-+#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
|
|
|
-+#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
|
|
|
-+#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_PWR_CFG_1:
|
|
|
-+ */
|
|
|
-+#define TX_PWR_CFG_1 0x1318
|
|
|
-+#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
|
|
|
-+#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
|
|
|
-+#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
|
|
|
-+#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
|
|
|
-+#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
|
|
|
-+#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
|
|
|
-+#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
|
|
|
-+#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_PWR_CFG_2:
|
|
|
-+ */
|
|
|
-+#define TX_PWR_CFG_2 0x131c
|
|
|
-+#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
|
|
|
-+#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
|
|
|
-+#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
|
|
|
-+#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
|
|
|
-+#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
|
|
|
-+#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
|
|
|
-+#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
|
|
|
-+#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_PWR_CFG_3:
|
|
|
-+ */
|
|
|
-+#define TX_PWR_CFG_3 0x1320
|
|
|
-+#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
|
|
|
-+#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
|
|
|
-+#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
|
|
|
-+#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
|
|
|
-+#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
|
|
|
-+#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
|
|
|
-+#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
|
|
|
-+#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_PWR_CFG_4:
|
|
|
-+ */
|
|
|
-+#define TX_PWR_CFG_4 0x1324
|
|
|
-+#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
|
|
|
-+#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
|
|
|
-+#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
|
|
|
-+#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_PIN_CFG:
|
|
|
-+ */
|
|
|
-+#define TX_PIN_CFG 0x1328
|
|
|
-+#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
|
|
|
-+#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
|
|
|
-+#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
|
|
|
-+#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
|
|
|
-+#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
|
|
|
-+#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
|
|
|
-+#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
|
|
|
-+#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
|
|
|
-+#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
|
|
|
-+#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
|
|
|
-+#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
|
|
|
-+#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
|
|
|
-+#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
|
|
|
-+#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
|
|
|
-+#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
|
|
|
-+#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
|
|
|
-+#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
|
|
|
-+#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
|
|
|
-+#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
|
|
|
-+#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
|
|
|
-+ */
|
|
|
-+#define TX_BAND_CFG 0x132c
|
|
|
-+#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
|
|
|
-+#define TX_BAND_CFG_A FIELD32(0x00000002)
|
|
|
-+#define TX_BAND_CFG_BG FIELD32(0x00000004)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_SW_CFG0:
|
|
|
-+ */
|
|
|
-+#define TX_SW_CFG0 0x1330
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_SW_CFG1:
|
|
|
-+ */
|
|
|
-+#define TX_SW_CFG1 0x1334
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_SW_CFG2:
|
|
|
-+ */
|
|
|
-+#define TX_SW_CFG2 0x1338
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TXOP_THRES_CFG:
|
|
|
-+ */
|
|
|
-+#define TXOP_THRES_CFG 0x133c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TXOP_CTRL_CFG:
|
|
|
-+ */
|
|
|
-+#define TXOP_CTRL_CFG 0x1340
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_RTS_CFG:
|
|
|
-+ * RTS_THRES: unit:byte
|
|
|
-+ * RTS_FBK_EN: enable rts rate fallback
|
|
|
-+ */
|
|
|
-+#define TX_RTS_CFG 0x1344
|
|
|
-+#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
|
|
|
-+#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
|
|
|
-+#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_TIMEOUT_CFG:
|
|
|
-+ * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
|
|
|
-+ * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
|
|
|
-+ * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
|
|
|
-+ * it is recommended that:
|
|
|
-+ * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
|
|
|
-+ */
|
|
|
-+#define TX_TIMEOUT_CFG 0x1348
|
|
|
-+#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
|
|
|
-+#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
|
|
|
-+#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_RTY_CFG:
|
|
|
-+ * SHORT_RTY_LIMIT: short retry limit
|
|
|
-+ * LONG_RTY_LIMIT: long retry limit
|
|
|
-+ * LONG_RTY_THRE: Long retry threshoold
|
|
|
-+ * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
|
|
|
-+ * 0:expired by retry limit, 1: expired by mpdu life timer
|
|
|
-+ * AGG_RTY_MODE: Aggregate MPDU retry mode
|
|
|
-+ * 0:expired by retry limit, 1: expired by mpdu life timer
|
|
|
-+ * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
|
|
|
-+ */
|
|
|
-+#define TX_RTY_CFG 0x134c
|
|
|
-+#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
|
|
|
-+#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
|
|
|
-+#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
|
|
|
-+#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
|
|
|
-+#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
|
|
|
-+#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_LINK_CFG:
|
|
|
-+ * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
|
|
|
-+ * MFB_ENABLE: TX apply remote MFB 1:enable
|
|
|
-+ * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
|
|
|
-+ * 0: not apply remote remote unsolicit (MFS=7)
|
|
|
-+ * TX_MRQ_EN: MCS request TX enable
|
|
|
-+ * TX_RDG_EN: RDG TX enable
|
|
|
-+ * TX_CF_ACK_EN: Piggyback CF-ACK enable
|
|
|
-+ * REMOTE_MFB: remote MCS feedback
|
|
|
-+ * REMOTE_MFS: remote MCS feedback sequence number
|
|
|
-+ */
|
|
|
-+#define TX_LINK_CFG 0x1350
|
|
|
-+#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
|
|
|
-+#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
|
|
|
-+#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
|
|
|
-+#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
|
|
|
-+#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
|
|
|
-+#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
|
|
|
-+#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
|
|
|
-+#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HT_FBK_CFG0:
|
|
|
-+ */
|
|
|
-+#define HT_FBK_CFG0 0x1354
|
|
|
-+#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
|
|
|
-+#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
|
|
|
-+#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
|
|
|
-+#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
|
|
|
-+#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
|
|
|
-+#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
|
|
|
-+#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
|
|
|
-+#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HT_FBK_CFG1:
|
|
|
-+ */
|
|
|
-+#define HT_FBK_CFG1 0x1358
|
|
|
-+#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
|
|
|
-+#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
|
|
|
-+#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
|
|
|
-+#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
|
|
|
-+#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
|
|
|
-+#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
|
|
|
-+#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
|
|
|
-+#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * LG_FBK_CFG0:
|
|
|
-+ */
|
|
|
-+#define LG_FBK_CFG0 0x135c
|
|
|
-+#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
|
|
|
-+#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
|
|
|
-+#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
|
|
|
-+#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
|
|
|
-+#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
|
|
|
-+#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
|
|
|
-+#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
|
|
|
-+#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * LG_FBK_CFG1:
|
|
|
-+ */
|
|
|
-+#define LG_FBK_CFG1 0x1360
|
|
|
-+#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
|
|
|
-+#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
|
|
|
-+#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
|
|
|
-+#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * CCK_PROT_CFG: CCK Protection
|
|
|
-+ * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
|
|
|
-+ * PROTECT_CTRL: Protection control frame type for CCK TX
|
|
|
-+ * 0:none, 1:RTS/CTS, 2:CTS-to-self
|
|
|
-+ * PROTECT_NAV: TXOP protection type for CCK TX
|
|
|
-+ * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
|
|
|
-+ * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
|
|
|
-+ * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
|
|
|
-+ * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
|
|
|
-+ * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
|
|
|
-+ * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
|
|
|
-+ * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
|
|
|
-+ * RTS_TH_EN: RTS threshold enable on CCK TX
|
|
|
-+ */
|
|
|
-+#define CCK_PROT_CFG 0x1364
|
|
|
-+#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
|
|
|
-+#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
|
|
|
-+#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
|
|
|
-+#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
|
|
|
-+#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
|
|
|
-+#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
|
|
|
-+#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
|
|
|
-+#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
|
|
|
-+#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
|
|
|
-+#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * OFDM_PROT_CFG: OFDM Protection
|
|
|
-+ */
|
|
|
-+#define OFDM_PROT_CFG 0x1368
|
|
|
-+#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
|
|
|
-+#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
|
|
|
-+#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
|
|
|
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
|
|
|
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
|
|
|
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
|
|
|
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
|
|
|
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
|
|
|
-+#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
|
|
|
-+#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MM20_PROT_CFG: MM20 Protection
|
|
|
-+ */
|
|
|
-+#define MM20_PROT_CFG 0x136c
|
|
|
-+#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
|
|
|
-+#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
|
|
|
-+#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
|
|
|
-+#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
|
|
|
-+#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
|
|
|
-+#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
|
|
|
-+#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
|
|
|
-+#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
|
|
|
-+#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
|
|
|
-+#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MM40_PROT_CFG: MM40 Protection
|
|
|
-+ */
|
|
|
-+#define MM40_PROT_CFG 0x1370
|
|
|
-+#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
|
|
|
-+#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
|
|
|
-+#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
|
|
|
-+#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
|
|
|
-+#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
|
|
|
-+#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
|
|
|
-+#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
|
|
|
-+#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
|
|
|
-+#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
|
|
|
-+#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * GF20_PROT_CFG: GF20 Protection
|
|
|
-+ */
|
|
|
-+#define GF20_PROT_CFG 0x1374
|
|
|
-+#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
|
|
|
-+#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
|
|
|
-+#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
|
|
|
-+#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
|
|
|
-+#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
|
|
|
-+#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
|
|
|
-+#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
|
|
|
-+#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
|
|
|
-+#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
|
|
|
-+#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * GF40_PROT_CFG: GF40 Protection
|
|
|
-+ */
|
|
|
-+#define GF40_PROT_CFG 0x1378
|
|
|
-+#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
|
|
|
-+#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
|
|
|
-+#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
|
|
|
-+#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
|
|
|
-+#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
|
|
|
-+#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
|
|
|
-+#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
|
|
|
-+#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
|
|
|
-+#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
|
|
|
-+#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EXP_CTS_TIME:
|
|
|
-+ */
|
|
|
-+#define EXP_CTS_TIME 0x137c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EXP_ACK_TIME:
|
|
|
-+ */
|
|
|
-+#define EXP_ACK_TIME 0x1380
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX_FILTER_CFG: RX configuration register.
|
|
|
-+ */
|
|
|
-+#define RX_FILTER_CFG 0x1400
|
|
|
-+#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
|
|
|
-+#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
|
|
|
-+#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
|
|
|
-+#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
|
|
|
-+#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
|
|
|
-+#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
|
|
|
-+#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
|
|
|
-+#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
|
|
|
-+#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
|
|
|
-+#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
|
|
|
-+#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
|
|
|
-+#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
|
|
|
-+#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
|
|
|
-+#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
|
|
|
-+#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
|
|
|
-+#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
|
|
|
-+#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * AUTO_RSP_CFG:
|
|
|
-+ * AUTORESPONDER: 0: disable, 1: enable
|
|
|
-+ * BAC_ACK_POLICY: 0:long, 1:short preamble
|
|
|
-+ * CTS_40_MMODE: Response CTS 40MHz duplicate mode
|
|
|
-+ * CTS_40_MREF: Response CTS 40MHz duplicate mode
|
|
|
-+ * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
|
|
|
-+ * DUAL_CTS_EN: Power bit value in control frame
|
|
|
-+ * ACK_CTS_PSM_BIT:Power bit value in control frame
|
|
|
-+ */
|
|
|
-+#define AUTO_RSP_CFG 0x1404
|
|
|
-+#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
|
|
|
-+#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
|
|
|
-+#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
|
|
|
-+#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
|
|
|
-+#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
|
|
|
-+#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
|
|
|
-+#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * LEGACY_BASIC_RATE:
|
|
|
-+ */
|
|
|
-+#define LEGACY_BASIC_RATE 0x1408
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HT_BASIC_RATE:
|
|
|
-+ */
|
|
|
-+#define HT_BASIC_RATE 0x140c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HT_CTRL_CFG:
|
|
|
-+ */
|
|
|
-+#define HT_CTRL_CFG 0x1410
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * SIFS_COST_CFG:
|
|
|
-+ */
|
|
|
-+#define SIFS_COST_CFG 0x1414
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX_PARSER_CFG:
|
|
|
-+ * Set NAV for all received frames
|
|
|
-+ */
|
|
|
-+#define RX_PARSER_CFG 0x1418
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_SEC_CNT0:
|
|
|
-+ */
|
|
|
-+#define TX_SEC_CNT0 0x1500
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX_SEC_CNT0:
|
|
|
-+ */
|
|
|
-+#define RX_SEC_CNT0 0x1504
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * CCMP_FC_MUTE:
|
|
|
-+ */
|
|
|
-+#define CCMP_FC_MUTE 0x1508
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TXOP_HLDR_ADDR0:
|
|
|
-+ */
|
|
|
-+#define TXOP_HLDR_ADDR0 0x1600
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TXOP_HLDR_ADDR1:
|
|
|
-+ */
|
|
|
-+#define TXOP_HLDR_ADDR1 0x1604
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TXOP_HLDR_ET:
|
|
|
-+ */
|
|
|
-+#define TXOP_HLDR_ET 0x1608
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * QOS_CFPOLL_RA_DW0:
|
|
|
-+ */
|
|
|
-+#define QOS_CFPOLL_RA_DW0 0x160c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * QOS_CFPOLL_RA_DW1:
|
|
|
-+ */
|
|
|
-+#define QOS_CFPOLL_RA_DW1 0x1610
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * QOS_CFPOLL_QC:
|
|
|
-+ */
|
|
|
-+#define QOS_CFPOLL_QC 0x1614
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX_STA_CNT0: RX PLCP error count & RX CRC error count
|
|
|
-+ */
|
|
|
-+#define RX_STA_CNT0 0x1700
|
|
|
-+#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
|
|
|
-+#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX_STA_CNT1: RX False CCA count & RX LONG frame count
|
|
|
-+ */
|
|
|
-+#define RX_STA_CNT1 0x1704
|
|
|
-+#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
|
|
|
-+#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX_STA_CNT2:
|
|
|
-+ */
|
|
|
-+#define RX_STA_CNT2 0x1708
|
|
|
-+#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_STA_CNT0: TX Beacon count
|
|
|
-+ */
|
|
|
-+#define TX_STA_CNT0 0x170c
|
|
|
-+#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_STA_CNT1: TX tx count
|
|
|
-+ */
|
|
|
-+#define TX_STA_CNT1 0x1710
|
|
|
-+#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
|
|
|
-+#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_STA_CNT2: TX tx count
|
|
|
-+ */
|
|
|
-+#define TX_STA_CNT2 0x1714
|
|
|
-+#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_STA_FIFO: TX Result for specific PID status fifo register
|
|
|
-+ */
|
|
|
-+#define TX_STA_FIFO 0x1718
|
|
|
-+#define TX_STA_FIFO_VALID FIELD32(0x00000001)
|
|
|
-+#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
|
|
|
-+#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
|
|
|
-+#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
|
|
|
-+#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
|
|
|
-+#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
|
|
|
-+#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_AGG_CNT: Debug counter
|
|
|
-+ */
|
|
|
-+#define TX_AGG_CNT 0x171c
|
|
|
-+#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_AGG_CNT0:
|
|
|
-+ */
|
|
|
-+#define TX_AGG_CNT0 0x1720
|
|
|
-+#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_AGG_CNT1:
|
|
|
-+ */
|
|
|
-+#define TX_AGG_CNT1 0x1724
|
|
|
-+#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_AGG_CNT2:
|
|
|
-+ */
|
|
|
-+#define TX_AGG_CNT2 0x1728
|
|
|
-+#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_AGG_CNT3:
|
|
|
-+ */
|
|
|
-+#define TX_AGG_CNT3 0x172c
|
|
|
-+#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_AGG_CNT4:
|
|
|
-+ */
|
|
|
-+#define TX_AGG_CNT4 0x1730
|
|
|
-+#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_AGG_CNT5:
|
|
|
-+ */
|
|
|
-+#define TX_AGG_CNT5 0x1734
|
|
|
-+#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_AGG_CNT6:
|
|
|
-+ */
|
|
|
-+#define TX_AGG_CNT6 0x1738
|
|
|
-+#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX_AGG_CNT7:
|
|
|
-+ */
|
|
|
-+#define TX_AGG_CNT7 0x173c
|
|
|
-+#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
|
|
|
-+#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MPDU_DENSITY_CNT:
|
|
|
-+ * TX_ZERO_DEL: TX zero length delimiter count
|
|
|
-+ * RX_ZERO_DEL: RX zero length delimiter count
|
|
|
-+ */
|
|
|
-+#define MPDU_DENSITY_CNT 0x1740
|
|
|
-+#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
|
|
|
-+#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Security key table memory.
|
|
|
-+ * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
|
|
|
-+ * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
|
|
|
-+ * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
|
|
|
-+ * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
|
|
|
-+ * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
|
|
|
-+ * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
|
|
|
-+ */
|
|
|
-+#define MAC_WCID_BASE 0x1800
|
|
|
-+#define PAIRWISE_KEY_TABLE_BASE 0x4000
|
|
|
-+#define MAC_IVEIV_TABLE_BASE 0x6000
|
|
|
-+#define MAC_WCID_ATTRIBUTE_BASE 0x6800
|
|
|
-+#define SHARED_KEY_TABLE_BASE 0x6c00
|
|
|
-+#define SHARED_KEY_MODE_BASE 0x7000
|
|
|
-+
|
|
|
-+#define MAC_WCID_ENTRY(__idx) \
|
|
|
-+ ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
|
|
|
-+#define PAIRWISE_KEY_ENTRY(__idx) \
|
|
|
-+ ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
|
|
|
-+#define MAC_IVEIV_ENTRY(__idx) \
|
|
|
-+ ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
|
|
|
-+#define MAC_WCID_ATTR_ENTRY(__idx) \
|
|
|
-+ ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
|
|
|
-+#define SHARED_KEY_ENTRY(__idx) \
|
|
|
-+ ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
|
|
|
-+#define SHARED_KEY_MODE_ENTRY(__idx) \
|
|
|
-+ ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
|
|
|
-+
|
|
|
-+struct mac_wcid_entry {
|
|
|
-+ u8 mac[6];
|
|
|
-+ u8 reserved[2];
|
|
|
-+} __attribute__ ((packed));
|
|
|
-+
|
|
|
-+struct hw_key_entry {
|
|
|
-+ u8 key[16];
|
|
|
-+ u8 tx_mic[8];
|
|
|
-+ u8 rx_mic[8];
|
|
|
-+} __attribute__ ((packed));
|
|
|
-+
|
|
|
-+struct mac_iveiv_entry {
|
|
|
-+ u8 iv[8];
|
|
|
-+} __attribute__ ((packed));
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MAC_WCID_ATTRIBUTE:
|
|
|
-+ */
|
|
|
-+#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
|
|
|
-+#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
|
|
|
-+#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
|
|
|
-+#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * SHARED_KEY_MODE:
|
|
|
-+ */
|
|
|
-+#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
|
|
|
-+#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
|
|
|
-+#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
|
|
|
-+#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
|
|
|
-+#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
|
|
|
-+#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
|
|
|
-+#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
|
|
|
-+#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HOST-MCU communication
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
|
|
|
-+ */
|
|
|
-+#define H2M_MAILBOX_CSR 0x7010
|
|
|
-+#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
|
|
|
-+#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
|
|
|
-+#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
|
|
|
-+#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * H2M_MAILBOX_CID:
|
|
|
-+ */
|
|
|
-+#define H2M_MAILBOX_CID 0x7014
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * H2M_MAILBOX_STATUS:
|
|
|
-+ */
|
|
|
-+#define H2M_MAILBOX_STATUS 0x701c
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * H2M_INT_SRC:
|
|
|
-+ */
|
|
|
-+#define H2M_INT_SRC 0x7024
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * H2M_BBP_AGENT:
|
|
|
-+ */
|
|
|
-+#define H2M_BBP_AGENT 0x7028
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MCU_LEDCS: LED control for MCU Mailbox.
|
|
|
-+ */
|
|
|
-+#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
|
|
|
-+#define MCU_LEDCS_POLARITY FIELD8(0x01)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HW_CS_CTS_BASE:
|
|
|
-+ * Carrier-sense CTS frame base address.
|
|
|
-+ * It's where mac stores carrier-sense frame for carrier-sense function.
|
|
|
-+ */
|
|
|
-+#define HW_CS_CTS_BASE 0x7700
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HW_DFS_CTS_BASE:
|
|
|
-+ * FS CTS frame base address. It's where mac stores CTS frame for DFS.
|
|
|
-+ */
|
|
|
-+#define HW_DFS_CTS_BASE 0x7780
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TXRX control registers - base address 0x3000
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TXRX_CSR1:
|
|
|
-+ * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
|
|
|
-+ */
|
|
|
-+#define TXRX_CSR1 0x77d0
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HW_DEBUG_SETTING_BASE:
|
|
|
-+ * since NULL frame won't be that long (256 byte)
|
|
|
-+ * We steal 16 tail bytes to save debugging settings
|
|
|
-+ */
|
|
|
-+#define HW_DEBUG_SETTING_BASE 0x77f0
|
|
|
-+#define HW_DEBUG_SETTING_BASE2 0x7770
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HW_BEACON_BASE
|
|
|
-+ * In order to support maximum 8 MBSS and its maximum length
|
|
|
-+ * is 512 bytes for each beacon
|
|
|
-+ * Three section discontinue memory segments will be used.
|
|
|
-+ * 1. The original region for BCN 0~3
|
|
|
-+ * 2. Extract memory from FCE table for BCN 4~5
|
|
|
-+ * 3. Extract memory from Pair-wise key table for BCN 6~7
|
|
|
-+ * It occupied those memory of wcid 238~253 for BCN 6
|
|
|
-+ * and wcid 222~237 for BCN 7
|
|
|
-+ *
|
|
|
-+ * IMPORTANT NOTE: Not sure why legacy driver does this,
|
|
|
-+ * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
|
|
|
-+ */
|
|
|
-+#define HW_BEACON_BASE0 0x7800
|
|
|
-+#define HW_BEACON_BASE1 0x7a00
|
|
|
-+#define HW_BEACON_BASE2 0x7c00
|
|
|
-+#define HW_BEACON_BASE3 0x7e00
|
|
|
-+#define HW_BEACON_BASE4 0x7200
|
|
|
-+#define HW_BEACON_BASE5 0x7400
|
|
|
-+#define HW_BEACON_BASE6 0x5dc0
|
|
|
-+#define HW_BEACON_BASE7 0x5bc0
|
|
|
-+
|
|
|
-+#define HW_BEACON_OFFSET(__index) \
|
|
|
-+ ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
|
|
|
-+ (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
|
|
|
-+ (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * 8051 firmware image.
|
|
|
-+ */
|
|
|
-+#define FIRMWARE_RT2870 "rt2870.bin"
|
|
|
-+#define FIRMWARE_IMAGE_BASE 0x3000
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * BBP registers.
|
|
|
-+ * The wordsize of the BBP is 8 bits.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * BBP 1: TX Antenna
|
|
|
-+ */
|
|
|
-+#define BBP1_TX_POWER FIELD8(0x07)
|
|
|
-+#define BBP1_TX_ANTENNA FIELD8(0x18)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * BBP 3: RX Antenna
|
|
|
-+ */
|
|
|
-+#define BBP3_RX_ANTENNA FIELD8(0x18)
|
|
|
-+#define BBP3_HT40_PLUS FIELD8(0x20)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * BBP 4: Bandwidth
|
|
|
-+ */
|
|
|
-+#define BBP4_TX_BF FIELD8(0x01)
|
|
|
-+#define BBP4_BANDWIDTH FIELD8(0x18)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RFCSR registers
|
|
|
-+ * The wordsize of the RFCSR is 8 bits.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RFCSR 6:
|
|
|
-+ */
|
|
|
-+#define RFCSR6_R FIELD8(0x03)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RFCSR 7:
|
|
|
-+ */
|
|
|
-+#define RFCSR7_RF_TUNING FIELD8(0x01)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RFCSR 12:
|
|
|
-+ */
|
|
|
-+#define RFCSR12_TX_POWER FIELD8(0x1f)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RFCSR 22:
|
|
|
-+ */
|
|
|
-+#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RFCSR 23:
|
|
|
-+ */
|
|
|
-+#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RFCSR 30:
|
|
|
-+ */
|
|
|
-+#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF registers
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF 2
|
|
|
-+ */
|
|
|
-+#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
|
|
|
-+#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
|
|
|
-+#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF 3
|
|
|
-+ */
|
|
|
-+#define RF3_TXPOWER_G FIELD32(0x00003e00)
|
|
|
-+#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
|
|
|
-+#define RF3_TXPOWER_A FIELD32(0x00003c00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RF 4
|
|
|
-+ */
|
|
|
-+#define RF4_TXPOWER_G FIELD32(0x000007c0)
|
|
|
-+#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
|
|
|
-+#define RF4_TXPOWER_A FIELD32(0x00000780)
|
|
|
-+#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
|
|
|
-+#define RF4_HT40 FIELD32(0x00200000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM content.
|
|
|
-+ * The wordsize of the EEPROM is 16 bits.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM Version
|
|
|
-+ */
|
|
|
-+#define EEPROM_VERSION 0x0001
|
|
|
-+#define EEPROM_VERSION_FAE FIELD16(0x00ff)
|
|
|
-+#define EEPROM_VERSION_VERSION FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * HW MAC address.
|
|
|
-+ */
|
|
|
-+#define EEPROM_MAC_ADDR_0 0x0002
|
|
|
-+#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
|
|
|
-+#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
|
|
|
-+#define EEPROM_MAC_ADDR_1 0x0003
|
|
|
-+#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
|
|
|
-+#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
|
|
|
-+#define EEPROM_MAC_ADDR_2 0x0004
|
|
|
-+#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
|
|
|
-+#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM ANTENNA config
|
|
|
-+ * RXPATH: 1: 1R, 2: 2R, 3: 3R
|
|
|
-+ * TXPATH: 1: 1T, 2: 2T
|
|
|
-+ */
|
|
|
-+#define EEPROM_ANTENNA 0x001a
|
|
|
-+#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
|
|
|
-+#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
|
|
|
-+#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM NIC config
|
|
|
-+ * CARDBUS_ACCEL: 0 - enable, 1 - disable
|
|
|
-+ */
|
|
|
-+#define EEPROM_NIC 0x001b
|
|
|
-+#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
|
|
|
-+#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
|
|
|
-+#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
|
|
|
-+#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
|
|
|
-+#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
|
|
|
-+#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
|
|
|
-+#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
|
|
|
-+#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
|
|
|
-+#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
|
|
|
-+#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM frequency
|
|
|
-+ */
|
|
|
-+#define EEPROM_FREQ 0x001d
|
|
|
-+#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
|
|
|
-+#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
|
|
|
-+#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM LED
|
|
|
-+ * POLARITY_RDY_G: Polarity RDY_G setting.
|
|
|
-+ * POLARITY_RDY_A: Polarity RDY_A setting.
|
|
|
-+ * POLARITY_ACT: Polarity ACT setting.
|
|
|
-+ * POLARITY_GPIO_0: Polarity GPIO0 setting.
|
|
|
-+ * POLARITY_GPIO_1: Polarity GPIO1 setting.
|
|
|
-+ * POLARITY_GPIO_2: Polarity GPIO2 setting.
|
|
|
-+ * POLARITY_GPIO_3: Polarity GPIO3 setting.
|
|
|
-+ * POLARITY_GPIO_4: Polarity GPIO4 setting.
|
|
|
-+ * LED_MODE: Led mode.
|
|
|
-+ */
|
|
|
-+#define EEPROM_LED1 0x001e
|
|
|
-+#define EEPROM_LED2 0x001f
|
|
|
-+#define EEPROM_LED3 0x0020
|
|
|
-+#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
|
|
|
-+#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
|
|
|
-+#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
|
|
|
-+#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
|
|
|
-+#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
|
|
|
-+#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
|
|
|
-+#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
|
|
|
-+#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
|
|
|
-+#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM LNA
|
|
|
-+ */
|
|
|
-+#define EEPROM_LNA 0x0022
|
|
|
-+#define EEPROM_LNA_BG FIELD16(0x00ff)
|
|
|
-+#define EEPROM_LNA_A0 FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM RSSI BG offset
|
|
|
-+ */
|
|
|
-+#define EEPROM_RSSI_BG 0x0023
|
|
|
-+#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
|
|
|
-+#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM RSSI BG2 offset
|
|
|
-+ */
|
|
|
-+#define EEPROM_RSSI_BG2 0x0024
|
|
|
-+#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
|
|
|
-+#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM RSSI A offset
|
|
|
-+ */
|
|
|
-+#define EEPROM_RSSI_A 0x0025
|
|
|
-+#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
|
|
|
-+#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM RSSI A2 offset
|
|
|
-+ */
|
|
|
-+#define EEPROM_RSSI_A2 0x0026
|
|
|
-+#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
|
|
|
-+#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
|
|
|
-+ * This is delta in 40MHZ.
|
|
|
-+ * VALUE: Tx Power dalta value (MAX=4)
|
|
|
-+ * TYPE: 1: Plus the delta value, 0: minus the delta value
|
|
|
-+ * TXPOWER: Enable:
|
|
|
-+ */
|
|
|
-+#define EEPROM_TXPOWER_DELTA 0x0028
|
|
|
-+#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
|
|
|
-+#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
|
|
|
-+#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM TXPOWER 802.11BG
|
|
|
-+ */
|
|
|
-+#define EEPROM_TXPOWER_BG1 0x0029
|
|
|
-+#define EEPROM_TXPOWER_BG2 0x0030
|
|
|
-+#define EEPROM_TXPOWER_BG_SIZE 7
|
|
|
-+#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
|
|
|
-+#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM TXPOWER 802.11A
|
|
|
-+ */
|
|
|
-+#define EEPROM_TXPOWER_A1 0x003c
|
|
|
-+#define EEPROM_TXPOWER_A2 0x0053
|
|
|
-+#define EEPROM_TXPOWER_A_SIZE 6
|
|
|
-+#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
|
|
|
-+#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM TXpower byrate: 20MHZ power
|
|
|
-+ */
|
|
|
-+#define EEPROM_TXPOWER_BYRATE 0x006f
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * EEPROM BBP.
|
|
|
-+ */
|
|
|
-+#define EEPROM_BBP_START 0x0078
|
|
|
-+#define EEPROM_BBP_SIZE 16
|
|
|
-+#define EEPROM_BBP_VALUE FIELD16(0x00ff)
|
|
|
-+#define EEPROM_BBP_REG_ID FIELD16(0xff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * MCU mailbox commands.
|
|
|
-+ */
|
|
|
-+#define MCU_SLEEP 0x30
|
|
|
-+#define MCU_WAKEUP 0x31
|
|
|
-+#define MCU_RADIO_OFF 0x35
|
|
|
-+#define MCU_LED 0x50
|
|
|
-+#define MCU_LED_STRENGTH 0x51
|
|
|
-+#define MCU_LED_1 0x52
|
|
|
-+#define MCU_LED_2 0x53
|
|
|
-+#define MCU_LED_3 0x54
|
|
|
-+#define MCU_RADAR 0x60
|
|
|
-+#define MCU_BOOT_SIGNAL 0x72
|
|
|
-+#define MCU_BBP_SIGNAL 0x80
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * DMA descriptor defines.
|
|
|
-+ */
|
|
|
-+#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
|
|
|
-+#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
|
|
|
-+#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
|
|
|
-+#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
|
|
|
-+#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX descriptor format for TX, PRIO and Beacon Ring.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word0
|
|
|
-+ */
|
|
|
-+#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word1
|
|
|
-+ */
|
|
|
-+#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
|
|
|
-+#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
|
|
|
-+#define TXD_W1_BURST FIELD32(0x00008000)
|
|
|
-+#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
|
|
|
-+#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
|
|
|
-+#define TXD_W1_DMA_DONE FIELD32(0x80000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word2
|
|
|
-+ */
|
|
|
-+#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word3
|
|
|
-+ * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
|
|
|
-+ * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
|
|
|
-+ * 0:MGMT, 1:HCCA 2:EDCA
|
|
|
-+ */
|
|
|
-+#define TXD_W3_WIV FIELD32(0x01000000)
|
|
|
-+#define TXD_W3_QSEL FIELD32(0x06000000)
|
|
|
-+#define TXD_W3_TCO FIELD32(0x20000000)
|
|
|
-+#define TXD_W3_UCO FIELD32(0x40000000)
|
|
|
-+#define TXD_W3_ICO FIELD32(0x80000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX Info structure
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word0
|
|
|
-+ * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
|
|
|
-+ * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
|
|
|
-+ * 0:MGMT, 1:HCCA 2:EDCA
|
|
|
-+ * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
|
|
|
-+ * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
|
|
|
-+ * Force USB DMA transmit frame from current selected endpoint
|
|
|
-+ */
|
|
|
-+#define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
|
|
|
-+#define TXINFO_W0_WIV FIELD32(0x01000000)
|
|
|
-+#define TXINFO_W0_QSEL FIELD32(0x06000000)
|
|
|
-+#define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000)
|
|
|
-+#define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
|
|
|
-+#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * TX WI structure
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word0
|
|
|
-+ * FRAG: 1 To inform TKIP engine this is a fragment.
|
|
|
-+ * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
|
|
|
-+ * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
|
|
|
-+ * BW: Channel bandwidth 20MHz or 40 MHz
|
|
|
-+ * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
|
|
|
-+ */
|
|
|
-+#define TXWI_W0_FRAG FIELD32(0x00000001)
|
|
|
-+#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
|
|
|
-+#define TXWI_W0_CF_ACK FIELD32(0x00000004)
|
|
|
-+#define TXWI_W0_TS FIELD32(0x00000008)
|
|
|
-+#define TXWI_W0_AMPDU FIELD32(0x00000010)
|
|
|
-+#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
|
|
|
-+#define TXWI_W0_TX_OP FIELD32(0x00000300)
|
|
|
-+#define TXWI_W0_MCS FIELD32(0x007f0000)
|
|
|
-+#define TXWI_W0_BW FIELD32(0x00800000)
|
|
|
-+#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
|
|
|
-+#define TXWI_W0_STBC FIELD32(0x06000000)
|
|
|
-+#define TXWI_W0_IFS FIELD32(0x08000000)
|
|
|
-+#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word1
|
|
|
-+ */
|
|
|
-+#define TXWI_W1_ACK FIELD32(0x00000001)
|
|
|
-+#define TXWI_W1_NSEQ FIELD32(0x00000002)
|
|
|
-+#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
|
|
|
-+#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
|
|
|
-+#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
|
|
|
-+#define TXWI_W1_PACKETID FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word2
|
|
|
-+ */
|
|
|
-+#define TXWI_W2_IV FIELD32(0xffffffff)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word3
|
|
|
-+ */
|
|
|
-+#define TXWI_W3_EIV FIELD32(0xffffffff)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX descriptor format for RX Ring.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word0
|
|
|
-+ * UNICAST_TO_ME: This RX frame is unicast to me.
|
|
|
-+ * MULTICAST: This is a multicast frame.
|
|
|
-+ * BROADCAST: This is a broadcast frame.
|
|
|
-+ * MY_BSS: this frame belongs to the same BSSID.
|
|
|
-+ * CRC_ERROR: CRC error.
|
|
|
-+ * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
|
|
|
-+ * AMSDU: rx with 802.3 header, not 802.11 header.
|
|
|
-+ */
|
|
|
-+
|
|
|
-+#define RXD_W0_BA FIELD32(0x00000001)
|
|
|
-+#define RXD_W0_DATA FIELD32(0x00000002)
|
|
|
-+#define RXD_W0_NULLDATA FIELD32(0x00000004)
|
|
|
-+#define RXD_W0_FRAG FIELD32(0x00000008)
|
|
|
-+#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000010)
|
|
|
-+#define RXD_W0_MULTICAST FIELD32(0x00000020)
|
|
|
-+#define RXD_W0_BROADCAST FIELD32(0x00000040)
|
|
|
-+#define RXD_W0_MY_BSS FIELD32(0x00000080)
|
|
|
-+#define RXD_W0_CRC_ERROR FIELD32(0x00000100)
|
|
|
-+#define RXD_W0_CIPHER_ERROR FIELD32(0x00000600)
|
|
|
-+#define RXD_W0_AMSDU FIELD32(0x00000800)
|
|
|
-+#define RXD_W0_HTC FIELD32(0x00001000)
|
|
|
-+#define RXD_W0_RSSI FIELD32(0x00002000)
|
|
|
-+#define RXD_W0_L2PAD FIELD32(0x00004000)
|
|
|
-+#define RXD_W0_AMPDU FIELD32(0x00008000)
|
|
|
-+#define RXD_W0_DECRYPTED FIELD32(0x00010000)
|
|
|
-+#define RXD_W0_PLCP_RSSI FIELD32(0x00020000)
|
|
|
-+#define RXD_W0_CIPHER_ALG FIELD32(0x00040000)
|
|
|
-+#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
|
|
|
-+#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * RX WI structure
|
|
|
-+ */
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word0
|
|
|
-+ */
|
|
|
-+#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
|
|
|
-+#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
|
|
|
-+#define RXWI_W0_BSSID FIELD32(0x00001c00)
|
|
|
-+#define RXWI_W0_UDF FIELD32(0x0000e000)
|
|
|
-+#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
|
|
|
-+#define RXWI_W0_TID FIELD32(0xf0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word1
|
|
|
-+ */
|
|
|
-+#define RXWI_W1_FRAG FIELD32(0x0000000f)
|
|
|
-+#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
|
|
|
-+#define RXWI_W1_MCS FIELD32(0x007f0000)
|
|
|
-+#define RXWI_W1_BW FIELD32(0x00800000)
|
|
|
-+#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
|
|
|
-+#define RXWI_W1_STBC FIELD32(0x06000000)
|
|
|
-+#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word2
|
|
|
-+ */
|
|
|
-+#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
|
|
|
-+#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
|
|
|
-+#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Word3
|
|
|
-+ */
|
|
|
-+#define RXWI_W3_SNR0 FIELD32(0x000000ff)
|
|
|
-+#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Macro's for converting txpower from EEPROM to mac80211 value
|
|
|
-+ * and from mac80211 value to register value.
|
|
|
-+ */
|
|
|
-+#define MIN_G_TXPOWER 0
|
|
|
-+#define MIN_A_TXPOWER -7
|
|
|
-+#define MAX_G_TXPOWER 31
|
|
|
-+#define MAX_A_TXPOWER 15
|
|
|
-+#define DEFAULT_TXPOWER 5
|
|
|
-+
|
|
|
-+#define TXPOWER_G_FROM_DEV(__txpower) \
|
|
|
-+ ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
|
|
|
-+
|
|
|
-+#define TXPOWER_G_TO_DEV(__txpower) \
|
|
|
-+ clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
|
|
|
-+
|
|
|
-+#define TXPOWER_A_FROM_DEV(__txpower) \
|
|
|
-+ ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
|
|
|
-+
|
|
|
-+#define TXPOWER_A_TO_DEV(__txpower) \
|
|
|
-+ clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
|
|
|
-+
|
|
|
-+#endif /* RT2800USB_H */
|
|
|
---- a/drivers/net/wireless/rt2x00/rt2x00.h
|
|
|
-+++ b/drivers/net/wireless/rt2x00/rt2x00.h
|
|
|
-@@ -144,6 +144,7 @@ struct rt2x00_chip {
|
|
|
- #define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
|
|
|
- #define RT2880 0x2880 /* WSOC */
|
|
|
- #define RT3052 0x3052 /* WSOC */
|
|
|
-+#define RT2870 0x1600
|
|
|
-
|
|
|
- u16 rf;
|
|
|
- u32 rev;
|
Hauke Mehrtens