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@@ -0,0 +1,534 @@
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+diff -urN a/drivers/clk/clk-devres.c b/drivers/clk/clk-devres.c
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+--- a/drivers/clk/clk-devres.c 2019-08-29 16:59:26.540010395 +0800
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++++ b/drivers/clk/clk-devres.c 2019-08-29 17:02:09.215924786 +0800
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+@@ -34,6 +34,17 @@
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+ }
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+ EXPORT_SYMBOL(devm_clk_get);
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+
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++struct clk *devm_clk_get_optional(struct device *dev, const char *id)
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++{
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++ struct clk *clk = devm_clk_get(dev, id);
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++
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++ if (clk == ERR_PTR(-ENOENT))
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++ return NULL;
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++
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++ return clk;
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++}
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++EXPORT_SYMBOL(devm_clk_get_optional);
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++
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+ struct clk_bulk_devres {
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+ struct clk_bulk_data *clks;
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+ int num_clks;
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+diff -urN a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
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+--- a/drivers/pci/controller/pcie-mediatek.c 2019-08-29 16:59:10.520410188 +0800
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++++ b/drivers/pci/controller/pcie-mediatek.c 2019-08-29 17:01:58.340199243 +0800
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+@@ -15,6 +15,7 @@
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+ #include <linux/irqdomain.h>
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+ #include <linux/kernel.h>
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+ #include <linux/msi.h>
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++#include <linux/module.h>
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+ #include <linux/of_address.h>
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+ #include <linux/of_pci.h>
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+ #include <linux/of_platform.h>
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+@@ -162,6 +163,7 @@
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+ * @phy: pointer to PHY control block
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+ * @lane: lane count
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+ * @slot: port slot
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++ * @irq: GIC irq
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+ * @irq_domain: legacy INTx IRQ domain
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+ * @inner_domain: inner IRQ domain
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+ * @msi_domain: MSI IRQ domain
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+@@ -182,6 +184,7 @@
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+ struct phy *phy;
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+ u32 lane;
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+ u32 slot;
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++ int irq;
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+ struct irq_domain *irq_domain;
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+ struct irq_domain *inner_domain;
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+ struct irq_domain *msi_domain;
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+@@ -225,10 +228,8 @@
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+
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+ clk_disable_unprepare(pcie->free_ck);
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+
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+- if (dev->pm_domain) {
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+- pm_runtime_put_sync(dev);
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+- pm_runtime_disable(dev);
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+- }
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++ pm_runtime_put_sync(dev);
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++ pm_runtime_disable(dev);
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+ }
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+
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+ static void mtk_pcie_port_free(struct mtk_pcie_port *port)
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+@@ -394,75 +395,6 @@
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+ .write = mtk_pcie_config_write,
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+ };
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+
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+-static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
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+-{
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+- struct mtk_pcie *pcie = port->pcie;
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+- struct resource *mem = &pcie->mem;
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+- const struct mtk_pcie_soc *soc = port->pcie->soc;
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+- u32 val;
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+- size_t size;
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+- int err;
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+-
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+- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
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+- if (pcie->base) {
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+- val = readl(pcie->base + PCIE_SYS_CFG_V2);
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+- val |= PCIE_CSR_LTSSM_EN(port->slot) |
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+- PCIE_CSR_ASPM_L1_EN(port->slot);
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+- writel(val, pcie->base + PCIE_SYS_CFG_V2);
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+- }
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+-
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+- /* Assert all reset signals */
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+- writel(0, port->base + PCIE_RST_CTRL);
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+-
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+- /*
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+- * Enable PCIe link down reset, if link status changed from link up to
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+- * link down, this will reset MAC control registers and configuration
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+- * space.
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+- */
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+- writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
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+-
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+- /* De-assert PHY, PE, PIPE, MAC and configuration reset */
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+- val = readl(port->base + PCIE_RST_CTRL);
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+- val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
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+- PCIE_MAC_SRSTB | PCIE_CRSTB;
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+- writel(val, port->base + PCIE_RST_CTRL);
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+-
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+- /* Set up vendor ID and class code */
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+- if (soc->need_fix_class_id) {
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+- val = PCI_VENDOR_ID_MEDIATEK;
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+- writew(val, port->base + PCIE_CONF_VEND_ID);
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+-
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+- val = PCI_CLASS_BRIDGE_HOST;
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+- writew(val, port->base + PCIE_CONF_CLASS_ID);
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+- }
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+-
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+- /* 100ms timeout value should be enough for Gen1/2 training */
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+- err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
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+- !!(val & PCIE_PORT_LINKUP_V2), 20,
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+- 100 * USEC_PER_MSEC);
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+- if (err)
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+- return -ETIMEDOUT;
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+-
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+- /* Set INTx mask */
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+- val = readl(port->base + PCIE_INT_MASK);
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+- val &= ~INTX_MASK;
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+- writel(val, port->base + PCIE_INT_MASK);
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+-
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+- /* Set AHB to PCIe translation windows */
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+- size = mem->end - mem->start;
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+- val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
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+- writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
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+-
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+- val = upper_32_bits(mem->start);
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+- writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
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+-
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+- /* Set PCIe to AXI translation memory space.*/
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+- val = fls(0xffffffff) | WIN_ENABLE;
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+- writel(val, port->base + PCIE_AXI_WINDOW0);
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+-
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+- return 0;
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+-}
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+-
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+ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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+ {
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+ struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
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+@@ -601,6 +533,27 @@
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+ writel(val, port->base + PCIE_INT_MASK);
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+ }
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+
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++static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
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++{
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++ struct mtk_pcie_port *port, *tmp;
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++
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++ list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
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++ irq_set_chained_handler_and_data(port->irq, NULL, NULL);
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++
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++ if (port->irq_domain)
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++ irq_domain_remove(port->irq_domain);
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++
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++ if (IS_ENABLED(CONFIG_PCI_MSI)) {
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++ if (port->msi_domain)
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++ irq_domain_remove(port->msi_domain);
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++ if (port->inner_domain)
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++ irq_domain_remove(port->inner_domain);
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++ }
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++
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++ irq_dispose_mapping(port->irq);
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++ }
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++}
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++
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+ static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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+ irq_hw_number_t hwirq)
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+ {
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+@@ -630,6 +583,7 @@
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+
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+ port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
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+ &intx_domain_ops, port);
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++ of_node_put(pcie_intc_node);
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+ if (!port->irq_domain) {
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+ dev_err(dev, "failed to get INTx IRQ domain\n");
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+ return -ENODEV;
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+@@ -639,8 +593,6 @@
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+ ret = mtk_pcie_allocate_msi_domains(port);
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+ if (ret)
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+ return ret;
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+-
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+- mtk_pcie_enable_msi(port);
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+ }
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+
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+ return 0;
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+@@ -693,7 +645,7 @@
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+ struct mtk_pcie *pcie = port->pcie;
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+ struct device *dev = pcie->dev;
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+ struct platform_device *pdev = to_platform_device(dev);
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+- int err, irq;
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++ int err;
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+
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+ err = mtk_pcie_init_irq_domain(port, node);
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+ if (err) {
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+@@ -701,8 +653,81 @@
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+ return err;
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+ }
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+
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+- irq = platform_get_irq(pdev, port->slot);
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+- irq_set_chained_handler_and_data(irq, mtk_pcie_intr_handler, port);
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++ port->irq = platform_get_irq(pdev, port->slot);
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++ irq_set_chained_handler_and_data(port->irq,
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++ mtk_pcie_intr_handler, port);
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++
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++ return 0;
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++}
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++
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++static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
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++{
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++ struct mtk_pcie *pcie = port->pcie;
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++ struct resource *mem = &pcie->mem;
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++ const struct mtk_pcie_soc *soc = port->pcie->soc;
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++ u32 val;
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++ size_t size;
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++ int err;
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++
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++ /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
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++ if (pcie->base) {
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++ val = readl(pcie->base + PCIE_SYS_CFG_V2);
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++ val |= PCIE_CSR_LTSSM_EN(port->slot) |
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++ PCIE_CSR_ASPM_L1_EN(port->slot);
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++ writel(val, pcie->base + PCIE_SYS_CFG_V2);
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++ }
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++
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++ /* Assert all reset signals */
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++ writel(0, port->base + PCIE_RST_CTRL);
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++
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|
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++ /*
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|
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++ * Enable PCIe link down reset, if link status changed from link up to
|
|
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++ * link down, this will reset MAC control registers and configuration
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++ * space.
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++ */
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++ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
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++
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++ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
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++ val = readl(port->base + PCIE_RST_CTRL);
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++ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
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++ PCIE_MAC_SRSTB | PCIE_CRSTB;
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++ writel(val, port->base + PCIE_RST_CTRL);
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++
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++ /* Set up vendor ID and class code */
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++ if (soc->need_fix_class_id) {
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++ val = PCI_VENDOR_ID_MEDIATEK;
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++ writew(val, port->base + PCIE_CONF_VEND_ID);
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++
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++ val = PCI_CLASS_BRIDGE_PCI;
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++ writew(val, port->base + PCIE_CONF_CLASS_ID);
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++ }
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++
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++ /* 100ms timeout value should be enough for Gen1/2 training */
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++ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
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++ !!(val & PCIE_PORT_LINKUP_V2), 20,
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++ 100 * USEC_PER_MSEC);
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++ if (err)
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++ return -ETIMEDOUT;
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++
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|
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++ /* Set INTx mask */
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++ val = readl(port->base + PCIE_INT_MASK);
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++ val &= ~INTX_MASK;
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++ writel(val, port->base + PCIE_INT_MASK);
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++
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++ if (IS_ENABLED(CONFIG_PCI_MSI))
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++ mtk_pcie_enable_msi(port);
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++
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++ /* Set AHB to PCIe translation windows */
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++ size = mem->end - mem->start;
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++ val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
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++ writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
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++
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++ val = upper_32_bits(mem->start);
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++ writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
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++
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|
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++ /* Set PCIe to AXI translation memory space.*/
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++ val = fls(0xffffffff) | WIN_ENABLE;
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++ writel(val, port->base + PCIE_AXI_WINDOW0);
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+
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+ return 0;
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+ }
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+@@ -903,49 +928,29 @@
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+
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+ /* sys_ck might be divided into the following parts in some chips */
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+ snprintf(name, sizeof(name), "ahb_ck%d", slot);
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+- port->ahb_ck = devm_clk_get(dev, name);
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+- if (IS_ERR(port->ahb_ck)) {
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+- if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER)
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+- return -EPROBE_DEFER;
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+-
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|
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+- port->ahb_ck = NULL;
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+- }
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|
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++ port->ahb_ck = devm_clk_get_optional(dev, name);
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++ if (IS_ERR(port->ahb_ck))
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++ return PTR_ERR(port->ahb_ck);
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+
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+ snprintf(name, sizeof(name), "axi_ck%d", slot);
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|
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+- port->axi_ck = devm_clk_get(dev, name);
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+- if (IS_ERR(port->axi_ck)) {
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+- if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER)
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+- return -EPROBE_DEFER;
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|
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+-
|
|
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+- port->axi_ck = NULL;
|
|
|
+- }
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|
|
++ port->axi_ck = devm_clk_get_optional(dev, name);
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|
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++ if (IS_ERR(port->axi_ck))
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|
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++ return PTR_ERR(port->axi_ck);
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+
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+ snprintf(name, sizeof(name), "aux_ck%d", slot);
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|
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+- port->aux_ck = devm_clk_get(dev, name);
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+- if (IS_ERR(port->aux_ck)) {
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|
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+- if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER)
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+- return -EPROBE_DEFER;
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|
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+-
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|
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+- port->aux_ck = NULL;
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|
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+- }
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|
|
++ port->aux_ck = devm_clk_get_optional(dev, name);
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|
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++ if (IS_ERR(port->aux_ck))
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|
|
++ return PTR_ERR(port->aux_ck);
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+
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|
+ snprintf(name, sizeof(name), "obff_ck%d", slot);
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|
|
+- port->obff_ck = devm_clk_get(dev, name);
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|
|
+- if (IS_ERR(port->obff_ck)) {
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|
|
+- if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER)
|
|
|
+- return -EPROBE_DEFER;
|
|
|
+-
|
|
|
+- port->obff_ck = NULL;
|
|
|
+- }
|
|
|
++ port->obff_ck = devm_clk_get_optional(dev, name);
|
|
|
++ if (IS_ERR(port->obff_ck))
|
|
|
++ return PTR_ERR(port->obff_ck);
|
|
|
+
|
|
|
+ snprintf(name, sizeof(name), "pipe_ck%d", slot);
|
|
|
+- port->pipe_ck = devm_clk_get(dev, name);
|
|
|
+- if (IS_ERR(port->pipe_ck)) {
|
|
|
+- if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER)
|
|
|
+- return -EPROBE_DEFER;
|
|
|
+-
|
|
|
+- port->pipe_ck = NULL;
|
|
|
+- }
|
|
|
++ port->pipe_ck = devm_clk_get_optional(dev, name);
|
|
|
++ if (IS_ERR(port->pipe_ck))
|
|
|
++ return PTR_ERR(port->pipe_ck);
|
|
|
+
|
|
|
+ snprintf(name, sizeof(name), "pcie-rst%d", slot);
|
|
|
+ port->reset = devm_reset_control_get_optional_exclusive(dev, name);
|
|
|
+@@ -998,10 +1003,8 @@
|
|
|
+ pcie->free_ck = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+- if (dev->pm_domain) {
|
|
|
+- pm_runtime_enable(dev);
|
|
|
+- pm_runtime_get_sync(dev);
|
|
|
+- }
|
|
|
++ pm_runtime_enable(dev);
|
|
|
++ pm_runtime_get_sync(dev);
|
|
|
+
|
|
|
+ /* enable top level clock */
|
|
|
+ err = clk_prepare_enable(pcie->free_ck);
|
|
|
+@@ -1013,10 +1016,8 @@
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ err_free_ck:
|
|
|
+- if (dev->pm_domain) {
|
|
|
+- pm_runtime_put_sync(dev);
|
|
|
+- pm_runtime_disable(dev);
|
|
|
+- }
|
|
|
++ pm_runtime_put_sync(dev);
|
|
|
++ pm_runtime_disable(dev);
|
|
|
+
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+@@ -1125,34 +1126,6 @@
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+-static int mtk_pcie_register_host(struct pci_host_bridge *host)
|
|
|
+-{
|
|
|
+- struct mtk_pcie *pcie = pci_host_bridge_priv(host);
|
|
|
+- struct pci_bus *child;
|
|
|
+- int err;
|
|
|
+-
|
|
|
+- host->busnr = pcie->busn.start;
|
|
|
+- host->dev.parent = pcie->dev;
|
|
|
+- host->ops = pcie->soc->ops;
|
|
|
+- host->map_irq = of_irq_parse_and_map_pci;
|
|
|
+- host->swizzle_irq = pci_common_swizzle;
|
|
|
+- host->sysdata = pcie;
|
|
|
+-
|
|
|
+- err = pci_scan_root_bus_bridge(host);
|
|
|
+- if (err < 0)
|
|
|
+- return err;
|
|
|
+-
|
|
|
+- pci_bus_size_bridges(host->bus);
|
|
|
+- pci_bus_assign_resources(host->bus);
|
|
|
+-
|
|
|
+- list_for_each_entry(child, &host->bus->children, node)
|
|
|
+- pcie_bus_configure_settings(child);
|
|
|
+-
|
|
|
+- pci_bus_add_devices(host->bus);
|
|
|
+-
|
|
|
+- return 0;
|
|
|
+-}
|
|
|
+-
|
|
|
+ static int mtk_pcie_probe(struct platform_device *pdev)
|
|
|
+ {
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+@@ -1179,7 +1152,14 @@
|
|
|
+ if (err)
|
|
|
+ goto put_resources;
|
|
|
+
|
|
|
+- err = mtk_pcie_register_host(host);
|
|
|
++ host->busnr = pcie->busn.start;
|
|
|
++ host->dev.parent = pcie->dev;
|
|
|
++ host->ops = pcie->soc->ops;
|
|
|
++ host->map_irq = of_irq_parse_and_map_pci;
|
|
|
++ host->swizzle_irq = pci_common_swizzle;
|
|
|
++ host->sysdata = pcie;
|
|
|
++
|
|
|
++ err = pci_host_probe(host);
|
|
|
+ if (err)
|
|
|
+ goto put_resources;
|
|
|
+
|
|
|
+@@ -1192,6 +1172,80 @@
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
++
|
|
|
++static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
|
|
|
++{
|
|
|
++ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
|
|
|
++ struct list_head *windows = &host->windows;
|
|
|
++
|
|
|
++ pci_free_resource_list(windows);
|
|
|
++}
|
|
|
++
|
|
|
++static int mtk_pcie_remove(struct platform_device *pdev)
|
|
|
++{
|
|
|
++ struct mtk_pcie *pcie = platform_get_drvdata(pdev);
|
|
|
++ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
|
|
|
++
|
|
|
++ pci_stop_root_bus(host->bus);
|
|
|
++ pci_remove_root_bus(host->bus);
|
|
|
++ mtk_pcie_free_resources(pcie);
|
|
|
++
|
|
|
++ mtk_pcie_irq_teardown(pcie);
|
|
|
++
|
|
|
++ mtk_pcie_put_resources(pcie);
|
|
|
++
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
|
|
|
++{
|
|
|
++ struct mtk_pcie *pcie = dev_get_drvdata(dev);
|
|
|
++ struct mtk_pcie_port *port;
|
|
|
++
|
|
|
++ if (list_empty(&pcie->ports))
|
|
|
++ return 0;
|
|
|
++
|
|
|
++ list_for_each_entry(port, &pcie->ports, list) {
|
|
|
++ clk_disable_unprepare(port->pipe_ck);
|
|
|
++ clk_disable_unprepare(port->obff_ck);
|
|
|
++ clk_disable_unprepare(port->axi_ck);
|
|
|
++ clk_disable_unprepare(port->aux_ck);
|
|
|
++ clk_disable_unprepare(port->ahb_ck);
|
|
|
++ clk_disable_unprepare(port->sys_ck);
|
|
|
++ phy_power_off(port->phy);
|
|
|
++ phy_exit(port->phy);
|
|
|
++ }
|
|
|
++
|
|
|
++ clk_disable_unprepare(pcie->free_ck);
|
|
|
++
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
|
|
|
++{
|
|
|
++ struct mtk_pcie *pcie = dev_get_drvdata(dev);
|
|
|
++ struct mtk_pcie_port *port, *tmp;
|
|
|
++
|
|
|
++ if (list_empty(&pcie->ports))
|
|
|
++ return 0;
|
|
|
++
|
|
|
++ clk_prepare_enable(pcie->free_ck);
|
|
|
++
|
|
|
++ list_for_each_entry_safe(port, tmp, &pcie->ports, list)
|
|
|
++ mtk_pcie_enable_port(port);
|
|
|
++
|
|
|
++ /* In case of EP was removed while system suspend. */
|
|
|
++ if (list_empty(&pcie->ports))
|
|
|
++ clk_disable_unprepare(pcie->free_ck);
|
|
|
++
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static const struct dev_pm_ops mtk_pcie_pm_ops = {
|
|
|
++ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
|
|
|
++ mtk_pcie_resume_noirq)
|
|
|
++};
|
|
|
++
|
|
|
+ static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
|
|
|
+ .ops = &mtk_pcie_ops,
|
|
|
+ .startup = mtk_pcie_startup_port,
|
|
|
+@@ -1220,10 +1274,13 @@
|
|
|
+
|
|
|
+ static struct platform_driver mtk_pcie_driver = {
|
|
|
+ .probe = mtk_pcie_probe,
|
|
|
++ .remove = mtk_pcie_remove,
|
|
|
+ .driver = {
|
|
|
+ .name = "mtk-pcie",
|
|
|
+ .of_match_table = mtk_pcie_ids,
|
|
|
+ .suppress_bind_attrs = true,
|
|
|
++ .pm = &mtk_pcie_pm_ops,
|
|
|
+ },
|
|
|
+ };
|
|
|
+-builtin_platform_driver(mtk_pcie_driver);
|
|
|
++module_platform_driver(mtk_pcie_driver);
|
|
|
++MODULE_LICENSE("GPL v2");
|
|
|
+diff -urN a/include/linux/clk.h b/include/linux/clk.h
|
|
|
+--- a/include/linux/clk.h 2019-08-29 16:59:52.335365591 +0800
|
|
|
++++ b/include/linux/clk.h 2019-08-29 17:02:17.107725525 +0800
|
|
|
+@@ -349,6 +349,17 @@
|
|
|
+ struct clk *devm_clk_get(struct device *dev, const char *id);
|
|
|
+
|
|
|
+ /**
|
|
|
++ * devm_clk_get_optional - lookup and obtain a managed reference to an optional
|
|
|
++ * clock producer.
|
|
|
++ * @dev: device for clock "consumer"
|
|
|
++ * @id: clock consumer ID
|
|
|
++ *
|
|
|
++ * Behaves the same as devm_clk_get() except where there is no clock producer.
|
|
|
++ * In this case, instead of returning -ENOENT, the function returns NULL.
|
|
|
++ */
|
|
|
++struct clk *devm_clk_get_optional(struct device *dev, const char *id);
|
|
|
++
|
|
|
++/**
|
|
|
+ * devm_get_clk_from_child - lookup and obtain a managed reference to a
|
|
|
+ * clock producer from child node.
|
|
|
+ * @dev: device for clock "consumer"
|
John Crispin