layerscape: update patches-4.14 to LSDK 19.03

All patches of LSDK 19.03 were ported to Openwrt kernel.
We still used an all-in-one patch for each IP/feature for
OpenWrt.

Below are the changes this patch introduced.
- Updated original IP/feature patches to LSDK 19.03.
- Added new IP/feature patches for eTSEC/PTP/TMU.
- Squashed scattered patches into IP/feature patches.
- Updated config-4.14 correspondingly.
- Refreshed all patches.

More info about LSDK and the kernel:
- https://lsdk.github.io/components.html
- https://source.codeaurora.org/external/qoriq/qoriq-components/linux

Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Yangbo Lu <[email protected]>

target/linux/layerscape/armv7/config-4.14

@@ -73,6 +73,7 @@ CONFIG_ARM_TIMER_SP804=y
 CONFIG_ARM_UNWIND=y
 CONFIG_ARM_VIRT_EXT=y
 CONFIG_AT803X_PHY=y
+# CONFIG_AT803X_PHY_SMART_EEE is not set
 CONFIG_ATAGS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_AUTO_ZRELADDR=y
@@ -259,6 +260,7 @@ CONFIG_FSL_IFC=y
 # CONFIG_FSL_PPFE is not set
 CONFIG_FSL_PQ_MDIO=y
 # CONFIG_FSL_QDMA is not set
+# CONFIG_FSL_QIXIS is not set
 # CONFIG_FSL_SDK_DPA is not set
 CONFIG_FSL_XGMAC_MDIO=y
 CONFIG_FS_MBCACHE=y
@@ -279,6 +281,7 @@ CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IO=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 CONFIG_GENERIC_MSI_IRQ=y
@@ -393,6 +396,7 @@ CONFIG_IMX_DMA=y
 CONFIG_IMX_SDMA=y
 # CONFIG_IMX_WEIM is not set
 CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_INPHI_PHY is not set
 CONFIG_INPUT=y
 # CONFIG_INPUT_MISC is not set
 CONFIG_IOMMU_HELPER=y
@@ -430,6 +434,7 @@ CONFIG_MARVELL_PHY=y
 CONFIG_MCPM=y
 CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_BUS=y
+# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
 CONFIG_MDIO_DEVICE=y
 # CONFIG_MDIO_FSL_BACKPLANE is not set
 # CONFIG_MDIO_GPIO is not set
@@ -537,6 +542,7 @@ CONFIG_PCIEASPM_DEFAULT=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_DW=y
 CONFIG_PCIE_DW_HOST=y
+# CONFIG_PCIE_DW_PLAT_HOST is not set
 CONFIG_PCIE_PME=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_DOMAINS_GENERIC=y
@@ -588,7 +594,7 @@ CONFIG_PSTORE_PMSG=y
 CONFIG_PSTORE_RAM=y
 CONFIG_PSTORE_ZLIB_COMPRESS=y
 CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_GIANFAR=y
+CONFIG_PTP_1588_CLOCK_QORIQ=y
 CONFIG_QORIQ_CPUFREQ=y
 # CONFIG_QUICC_ENGINE is not set
 CONFIG_RAS=y
@@ -681,6 +687,7 @@ CONFIG_SPI_CADENCE=y
 # CONFIG_SPI_FSL_QUADSPI is not set
 # CONFIG_SPI_IMX is not set
 CONFIG_SPI_MASTER=y
+# CONFIG_SPI_NXP_FLEXSPI is not set
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPI_XILINX=y
 CONFIG_SPMI=y

target/linux/layerscape/armv8_64b/config-4.14

@@ -116,7 +116,6 @@ CONFIG_BLK_SCSI_REQUEST=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_BOUNCE=y
-CONFIG_BPF_JIT=y
 # CONFIG_BPF_SYSCALL is not set
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
@@ -188,7 +187,6 @@ CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_CRC32C=y
 CONFIG_CRYPTO_CRCT10DIF=y
 CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC is not set
 # CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM is not set
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
@@ -309,6 +307,7 @@ CONFIG_FSL_DPAA2_ETHSW=y
 CONFIG_FSL_DPAA2_EVB=y
 CONFIG_FSL_DPAA2_MAC=y
 # CONFIG_FSL_DPAA2_MAC_NETDEVS is not set
+CONFIG_FSL_DPAA2_PTP_CLOCK=y
 # CONFIG_FSL_DPAA2_QDMA is not set
 # CONFIG_FSL_DPAA_1588 is not set
 CONFIG_FSL_DPAA_ADVANCED_DRIVERS=y
@@ -321,7 +320,6 @@ CONFIG_FSL_DPAA_ETH_DEBUGFS=y
 # CONFIG_FSL_DPAA_ETH_JUMBO_FRAME is not set
 CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT=128
 CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD=80
-CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE=y
 # CONFIG_FSL_DPAA_HOOKS is not set
 CONFIG_FSL_DPAA_INGRESS_CS_THRESHOLD=0x10000000
 CONFIG_FSL_DPAA_OFFLINE_PORTS=y
@@ -347,6 +345,7 @@ CONFIG_FSL_PPFE=y
 CONFIG_FSL_PPFE_UTIL_DISABLED=y
 # CONFIG_FSL_QBMAN_DEBUG is not set
 # CONFIG_FSL_QDMA is not set
+CONFIG_FSL_QIXIS=y
 CONFIG_FSL_QMAN_CI_SCHED_CFG_BMAN_W=2
 CONFIG_FSL_QMAN_CI_SCHED_CFG_RW_W=2
 CONFIG_FSL_QMAN_CI_SCHED_CFG_SRCCIV=4
@@ -514,6 +513,7 @@ CONFIG_INET_DIAG=y
 # CONFIG_INET_RAW_DIAG is not set
 CONFIG_INET_TCP_DIAG=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPHI_PHY=y
 CONFIG_INPUT=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_KEYBOARD=y
@@ -573,6 +573,7 @@ CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_BUS_MUX=y
 CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
 CONFIG_MDIO_DEVICE=y
 # CONFIG_MDIO_FSL_BACKPLANE is not set
 # CONFIG_MDIO_GPIO is not set
@@ -580,6 +581,7 @@ CONFIG_MEMORY=y
 CONFIG_MEMORY_BALLOON=y
 CONFIG_MEMORY_ISOLATION=y
 CONFIG_MEMTEST=y
+CONFIG_MFD_CORE=y
 CONFIG_MFD_SYSCON=y
 # CONFIG_MFD_VEXPRESS_SYSREG is not set
 CONFIG_MICREL_PHY=y
@@ -637,7 +639,11 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
 # CONFIG_MTD_UBI_FASTMAP is not set
 # CONFIG_MTD_UBI_GLUEBI is not set
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTIPLEXER=y
 CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_MUX_ADG792A is not set
+# CONFIG_MUX_GPIO is not set
+CONFIG_MUX_MMIO=y
 CONFIG_MV_XOR_V2=y
 CONFIG_NAMESPACES=y
 CONFIG_NEED_DMA_MAP_STATE=y
@@ -694,6 +700,9 @@ CONFIG_PCIEASPM_DEFAULT=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_DW=y
 CONFIG_PCIE_DW_HOST=y
+# CONFIG_PCIE_DW_PLAT_HOST is not set
+CONFIG_PCIE_MOBIVEIL=y
+CONFIG_PCIE_MOBIVEIL_HOST=y
 CONFIG_PCIE_PME=y
 CONFIG_PCI_ATS=y
 CONFIG_PCI_BUS_ADDR_T_64BIT=y
@@ -706,6 +715,7 @@ CONFIG_PCI_HOST_GENERIC=y
 CONFIG_PCI_IOV=y
 CONFIG_PCI_LABEL=y
 CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_LAYERSCAPE_GEN4=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
 CONFIG_PERF_EVENTS=y
@@ -738,8 +748,7 @@ CONFIG_PRINT_QUOTA_WARNING=y
 CONFIG_PROC_CHILDREN=y
 CONFIG_PROFILING=y
 CONFIG_PTP_1588_CLOCK=y
-# CONFIG_PTP_1588_CLOCK_DPAA is not set
-CONFIG_PTP_1588_CLOCK_DPAA2=y
+CONFIG_PTP_1588_CLOCK_QORIQ=y
 CONFIG_QCOM_HIDMA=y
 CONFIG_QCOM_HIDMA_MGMT=y
 CONFIG_QCOM_QDF2400_ERRATUM_0065=y
@@ -828,6 +837,7 @@ CONFIG_SPI=y
 CONFIG_SPI_FSL_DSPI=y
 CONFIG_SPI_FSL_QUADSPI=y
 CONFIG_SPI_MASTER=y
+CONFIG_SPI_NXP_FLEXSPI=y
 CONFIG_SPI_PL022=y
 CONFIG_SPMI=y
 # CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set

target/linux/layerscape/patches-4.14/201-config-support-layerscape.patch

@@ -1,6 +1,6 @@
-From 0bafdb711c1a61fbe5bb5b4d4bb5e32425d95a72 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Fri, 16 Nov 2018 15:36:03 +0800
+From 2a1351617985ef47581de825ae1bbf1d42bf3200 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Mon, 6 May 2019 17:29:32 +0800
 Subject: [PATCH] config: support layerscape
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
@@ -10,45 +10,65 @@ This is an integrated patch of config for layerscape
 
 Signed-off-by: Alison Wang <[email protected]>
 Signed-off-by: Bharat Bhushan <[email protected]>
+Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Bjorn Helgaas <[email protected]>
 Signed-off-by: Bogdan Purcareata <[email protected]>
 Signed-off-by: Calvin Johnson <[email protected]>
 Signed-off-by: Camelia Groza <[email protected]>
 Signed-off-by: Chenhui Zhao <[email protected]>
+Signed-off-by: Florin Chiculita <[email protected]>
 Signed-off-by: Greg Kroah-Hartman <[email protected]>
 Signed-off-by: Horia Geantă <[email protected]>
+Signed-off-by: Hou Zhiqiang <[email protected]>
 Signed-off-by: Ioana Ciornei <[email protected]>
 Signed-off-by: Ioana Radulescu <[email protected]>
 Signed-off-by: Li Yang <[email protected]>
+Signed-off-by: Lorenzo Pieralisi <[email protected]>
 Signed-off-by: Madalin Bucur <[email protected]>
+Signed-off-by: Pankaj Bansal <[email protected]>
 Signed-off-by: Pankit Garg <[email protected]>
 Signed-off-by: Prabhakar Kushwaha <[email protected]>
 Signed-off-by: Ran Wang <[email protected]>
 Signed-off-by: Razvan Stefanescu <[email protected]>
 Signed-off-by: Shengzhou Liu <[email protected]>
+Signed-off-by: Subrahmanya Lingappa <[email protected]>
+Signed-off-by: Xiaowei Bao <[email protected]>
 Signed-off-by: Yangbo Lu <[email protected]>
+Signed-off-by: Yogesh Gaur <[email protected]>
 Signed-off-by: Zhang Ying-22455 <[email protected]>
-Signed-off-by: Zhao Qiang  <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Zhao Qiang <[email protected]>
 ---
+ drivers/Makefile                        |  2 ++
  drivers/irqchip/Makefile                |  1 +
- drivers/net/ethernet/freescale/Kconfig  | 14 ++++----
+ drivers/net/ethernet/freescale/Kconfig  | 14 +++++----
  drivers/net/ethernet/freescale/Makefile |  3 ++
- drivers/ptp/Kconfig                     | 29 +++++++++++++++++
+ drivers/ptp/Kconfig                     | 16 +++++-----
  drivers/soc/Kconfig                     |  1 +
- drivers/soc/fsl/Kconfig                 | 11 +++++++
- drivers/soc/fsl/Kconfig.arm             | 16 +++++++++
- drivers/soc/fsl/Makefile                |  3 ++
+ drivers/soc/fsl/Kconfig                 | 22 +++++++++++++
+ drivers/soc/fsl/Kconfig.arm             | 16 ++++++++++
+ drivers/soc/fsl/Makefile                |  5 +++
  drivers/soc/fsl/layerscape/Kconfig      | 10 ++++++
  drivers/soc/fsl/layerscape/Makefile     |  1 +
  drivers/staging/Kconfig                 |  4 +++
  drivers/staging/Makefile                |  2 ++
- drivers/staging/fsl-dpaa2/Kconfig       | 43 ++++++++++++++++++++++++-
+ drivers/staging/fsl-dpaa2/Kconfig       | 56 ++++++++++++++++++++++++++++++++-
  drivers/staging/fsl-dpaa2/Makefile      |  4 +++
- 14 files changed, 135 insertions(+), 7 deletions(-)
+ 15 files changed, 142 insertions(+), 15 deletions(-)
  create mode 100644 drivers/soc/fsl/Kconfig.arm
  create mode 100644 drivers/soc/fsl/layerscape/Kconfig
  create mode 100644 drivers/soc/fsl/layerscape/Makefile
 
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -20,6 +20,8 @@ obj-$(CONFIG_PCI)		+= pci/
+ obj-$(CONFIG_PCI_ENDPOINT)	+= pci/endpoint/
+ # PCI dwc controller drivers
+ obj-y				+= pci/dwc/
++# PCI mobiveil controller drivers
++obj-y				+= pci/mobiveil/
+ 
+ obj-$(CONFIG_PARISC)		+= parisc/
+ obj-$(CONFIG_RAPIDIO)		+= rapidio/
 --- a/drivers/irqchip/Makefile
 +++ b/drivers/irqchip/Makefile
 @@ -80,3 +80,4 @@ obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed
@@ -106,42 +126,34 @@ Signed-off-by: Biwen Li <[email protected]>
  obj-$(CONFIG_FSL_DPAA_ETH) += dpaa/
 --- a/drivers/ptp/Kconfig
 +++ b/drivers/ptp/Kconfig
-@@ -55,6 +55,35 @@ config PTP_1588_CLOCK_GIANFAR
+@@ -41,19 +41,19 @@ config PTP_1588_CLOCK_DTE
  	  To compile this driver as a module, choose M here: the module
- 	  will be called gianfar_ptp.
+ 	  will be called ptp_dte.
+ 
+-config PTP_1588_CLOCK_GIANFAR
+-	tristate "Freescale eTSEC as PTP clock"
+-	depends on GIANFAR
++config PTP_1588_CLOCK_QORIQ
++	tristate "Freescale QorIQ 1588 timer as PTP clock"
++	depends on GIANFAR || FSL_DPAA_ETH || FSL_SDK_DPAA_ETH
+ 	depends on PTP_1588_CLOCK
+ 	default y
+ 	help
+-	  This driver adds support for using the eTSEC as a PTP
+-	  clock. This clock is only useful if your PTP programs are
+-	  getting hardware time stamps on the PTP Ethernet packets
+-	  using the SO_TIMESTAMPING API.
++	  This driver adds support for using the Freescale QorIQ 1588
++	  timer as a PTP clock. This clock is only useful if your PTP
++	  programs are getting hardware time stamps on the PTP Ethernet
++	  packets using the SO_TIMESTAMPING API.
+ 
+ 	  To compile this driver as a module, choose M here: the module
+-	  will be called gianfar_ptp.
++	  will be called ptp_qoriq.
  
-+config PTP_1588_CLOCK_DPAA
-+	tristate "Freescale DPAA as PTP clock"
-+	depends on FSL_SDK_DPAA_ETH
-+	select PTP_1588_CLOCK
-+        select FSL_DPAA_TS
-+        default n
-+	help
-+	  This driver adds support for using the DPAA 1588 timer module
-+	  as a PTP clock. This clock is only useful if your PTP programs are
-+	  getting hardware time stamps on the PTP Ethernet packets
-+	  using the SO_TIMESTAMPING API.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called dpaa_ptp.
-+
-+config PTP_1588_CLOCK_DPAA2
-+	tristate "Freescale DPAA2 as PTP clock"
-+	depends on FSL_DPAA2_ETH
-+	select PTP_1588_CLOCK
-+	default y
-+	help
-+	  This driver adds support for using the DPAA2 1588 timer module
-+	  as a PTP clock. This clock is only useful if your PTP programs are
-+	  getting hardware time stamps on the PTP Ethernet packets
-+	  using the SO_TIMESTAMPING API.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called dpaa2-rtc.
-+
  config PTP_1588_CLOCK_IXP46X
  	tristate "Intel IXP46x as PTP clock"
- 	depends on IXP4XX_ETH
 --- a/drivers/soc/Kconfig
 +++ b/drivers/soc/Kconfig
 @@ -5,6 +5,7 @@ source "drivers/soc/amlogic/Kconfig"
@@ -154,11 +166,22 @@ Signed-off-by: Biwen Li <[email protected]>
  source "drivers/soc/qcom/Kconfig"
 --- a/drivers/soc/fsl/Kconfig
 +++ b/drivers/soc/fsl/Kconfig
-@@ -16,3 +16,14 @@ config FSL_GUTS
+@@ -16,3 +16,25 @@ config FSL_GUTS
  	  Initially only reading SVR and registering soc device are supported.
  	  Other guts accesses, such as reading RCW, should eventually be moved
  	  into this driver as well.
 +
++config FSL_QIXIS
++	tristate "QIXIS system controller driver"
++	depends on OF
++	select REGMAP_I2C
++	select REGMAP_MMIO
++	select MFD_CORE
++	default n
++	help
++	  Say y here to enable QIXIS system controller api. The qixis driver
++	  provides FPGA functions to control system.
++
 +config FSL_SLEEP_FSM
 +	bool
 +	help
@@ -190,11 +213,14 @@ Signed-off-by: Biwen Li <[email protected]>
 +endif
 --- a/drivers/soc/fsl/Makefile
 +++ b/drivers/soc/fsl/Makefile
-@@ -6,3 +6,6 @@ obj-$(CONFIG_FSL_DPAA)                 +
+@@ -5,4 +5,9 @@
+ obj-$(CONFIG_FSL_DPAA)                 += qbman/
  obj-$(CONFIG_QUICC_ENGINE)		+= qe/
  obj-$(CONFIG_CPM)			+= qe/
++obj-$(CONFIG_FSL_QIXIS) 		+= qixis_ctrl.o
  obj-$(CONFIG_FSL_GUTS)			+= guts.o
 +obj-$(CONFIG_FSL_LS2_CONSOLE)		+= ls2-console/
++obj-$(CONFIG_SUSPEND)			+= rcpm.o
 +obj-$(CONFIG_LS_SOC_DRIVERS)		+= layerscape/
 +obj-$(CONFIG_FSL_SLEEP_FSM)	+= sleep_fsm.o
 --- /dev/null
@@ -244,7 +270,7 @@ Signed-off-by: Biwen Li <[email protected]>
  	---help---
  	  Build drivers for Freescale DataPath Acceleration
  	  Architecture (DPAA2) family of SoCs.
-@@ -16,3 +16,44 @@ config FSL_DPAA2_ETH
+@@ -16,3 +16,57 @@ config FSL_DPAA2_ETH
  	---help---
  	  Ethernet driver for Freescale DPAA2 SoCs, using the
  	  Freescale MC bus driver
@@ -277,6 +303,19 @@ Signed-off-by: Biwen Li <[email protected]>
 +          (PFC) in the driver.
 +
 +          If unsure, say N.
++
++config FSL_DPAA2_PTP_CLOCK
++	tristate "Freescale DPAA2 as PTP clock"
++	select PTP_1588_CLOCK
++	default y
++	help
++	  This driver adds support for using the DPAA2 1588 timer module
++	  as a PTP clock. This clock is only useful if your PTP programs are
++	  getting hardware time stamps on the PTP Ethernet packets
++	  using the SO_TIMESTAMPING API.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called dpaa2-rtc.
 +endif
 +
 +source "drivers/staging/fsl-dpaa2/mac/Kconfig"
@@ -297,5 +336,5 @@ Signed-off-by: Biwen Li <[email protected]>
  obj-$(CONFIG_FSL_DPAA2_ETH)	+= ethernet/
 +obj-$(CONFIG_FSL_DPAA2_MAC)	+= mac/
 +obj-$(CONFIG_FSL_DPAA2_EVB)	+= evb/
-+obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += rtc/
++obj-$(CONFIG_FSL_DPAA2_PTP_CLOCK) += rtc/
 +obj-$(CONFIG_FSL_DPAA2_ETHSW)	+= ethsw/

target/linux/layerscape/patches-4.14/202-core-linux-support-layerscape.patch

@@ -1,54 +1,301 @@
-From 74243154052af635ee9ce9d07aab273ce219c855 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Thu, 13 Dec 2018 13:23:52 +0800
+From d2ef9f2f6d16d34d7eee74cb8efd269341fec5a1 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Mon, 6 May 2019 16:54:17 +0800
 Subject: [PATCH] core-linux: support layerscape
 
-This is an integrated patch of core-linux for layerscape.
+This is an integrated patch of core-linux for layerscape
 
+Signed-off-by: Aaron Lu <[email protected]>
 Signed-off-by: Abhijit Ayarekar <[email protected]>
 Signed-off-by: Amrita Kumari <[email protected]>
+Signed-off-by: Andrew Morton <[email protected]>
 Signed-off-by: Ashish Kumar <[email protected]>
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Camelia Groza <[email protected]>
 Signed-off-by: Christoph Hellwig <[email protected]>
 Signed-off-by: David Ahern <[email protected]>
 Signed-off-by: David S. Miller <[email protected]>
+Signed-off-by: Greg Kroah-Hartman <[email protected]>
 Signed-off-by: Guanhua Gao <[email protected]>
+Signed-off-by: Ioana Ciornei <[email protected]>
 Signed-off-by: Jiri Pirko <[email protected]>
 Signed-off-by: Joel Fernandes <[email protected]>
+Signed-off-by: Laurentiu Tudor <[email protected]>
+Signed-off-by: Linus Torvalds <[email protected]>
 Signed-off-by: Li Yang <[email protected]>
-Signed-off-by: Madalin Bucur <[email protected]>
+Signed-off-by: Lukas Wunner <[email protected]>
 Signed-off-by: Madalin Bucur <[email protected]>
+Signed-off-by: Mark Brown <[email protected]>
 Signed-off-by: Nikhil Badola <[email protected]>
 Signed-off-by: Nipun Gupta <[email protected]>
+Signed-off-by: Pankaj Bansal <[email protected]>
+Signed-off-by: pascal paillet <[email protected]>
+Signed-off-by: Rafael J. Wysocki <[email protected]>
 Signed-off-by: Ramneek Mehresh <[email protected]>
 Signed-off-by: Robin Murphy <[email protected]>
 Signed-off-by: Suresh Gupta <[email protected]>
+Signed-off-by: Vivek Gautam <[email protected]>
 Signed-off-by: Yangbo Lu <[email protected]>
-Signed-off-by: yinbo.zhu <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 ---
- drivers/base/dma-mapping.c                |  7 ++
- drivers/net/bonding/bond_main.c           |  5 +-
- drivers/net/bonding/bond_options.c        |  2 +-
- drivers/net/team/team.c                   |  3 +-
- drivers/net/vrf.c                         |  3 +-
- drivers/of/device.c                       | 13 +++-
- drivers/soc/fsl/guts.c                    |  3 +
- include/linux/fsl_devices.h               |  2 +
- include/linux/netdevice.h                 | 13 +++-
- include/linux/skbuff.h                    |  2 +
- include/net/bonding.h                     |  3 +-
- net/batman-adv/soft-interface.c           |  3 +-
- net/bridge/br_device.c                    |  3 +-
- net/core/dev.c                            | 81 ++++++++++++++---------
- net/core/rtnetlink.c                      | 10 +--
- net/core/skbuff.c                         | 29 +++++++-
- samples/bpf/Makefile                      | 12 +++-
- samples/bpf/map_perf_test_kern.c          |  2 +-
- samples/bpf/map_perf_test_user.c          |  2 +-
- tools/testing/selftests/bpf/bpf_helpers.h | 56 ++++++++++++++--
- 20 files changed, 193 insertions(+), 61 deletions(-)
+ drivers/base/core.c                       | 122 ++++++++++++++++++++++++++----
+ drivers/base/dma-mapping.c                |   7 ++
+ drivers/gpu/ipu-v3/ipu-pre.c              |   3 +-
+ drivers/gpu/ipu-v3/ipu-prg.c              |   3 +-
+ drivers/iommu/dma-iommu.c                 |   3 +
+ drivers/mux/Kconfig                       |  12 +--
+ drivers/mux/mmio.c                        |   6 +-
+ drivers/of/device.c                       |  14 +++-
+ drivers/soc/imx/gpc.c                     |   2 +-
+ include/linux/device.h                    |  20 +++--
+ include/linux/fsl_devices.h               |   2 +
+ include/linux/netdevice.h                 |  10 ++-
+ include/linux/skbuff.h                    |   2 +
+ lib/dma-noop.c                            |  19 +++++
+ mm/page_alloc.c                           |  10 ++-
+ net/core/dev.c                            |  81 ++++++++++++--------
+ net/core/skbuff.c                         |  29 ++++++-
+ samples/bpf/Makefile                      |  12 ++-
+ samples/bpf/map_perf_test_kern.c          |   2 +-
+ samples/bpf/map_perf_test_user.c          |   2 +-
+ tools/testing/selftests/bpf/bpf_helpers.h |  56 ++++++++++++--
+ 21 files changed, 337 insertions(+), 80 deletions(-)
 
+--- a/drivers/base/core.c
++++ b/drivers/base/core.c
+@@ -161,10 +161,10 @@ static int device_reorder_to_tail(struct
+  * of the link.  If DL_FLAG_PM_RUNTIME is not set, DL_FLAG_RPM_ACTIVE will be
+  * ignored.
+  *
+- * If the DL_FLAG_AUTOREMOVE is set, the link will be removed automatically
+- * when the consumer device driver unbinds from it.  The combination of both
+- * DL_FLAG_AUTOREMOVE and DL_FLAG_STATELESS set is invalid and will cause NULL
+- * to be returned.
++ * If the DL_FLAG_AUTOREMOVE_CONSUMER is set, the link will be removed
++ * automatically when the consumer device driver unbinds from it.
++ * The combination of both DL_FLAG_AUTOREMOVE_CONSUMER and DL_FLAG_STATELESS
++ * set is invalid and will cause NULL to be returned.
+  *
+  * A side effect of the link creation is re-ordering of dpm_list and the
+  * devices_kset list by moving the consumer device and all devices depending
+@@ -181,7 +181,8 @@ struct device_link *device_link_add(stru
+ 	struct device_link *link;
+ 
+ 	if (!consumer || !supplier ||
+-	    ((flags & DL_FLAG_STATELESS) && (flags & DL_FLAG_AUTOREMOVE)))
++	    ((flags & DL_FLAG_STATELESS) &&
++	     (flags & DL_FLAG_AUTOREMOVE_CONSUMER)))
+ 		return NULL;
+ 
+ 	device_links_write_lock();
+@@ -199,8 +200,10 @@ struct device_link *device_link_add(stru
+ 	}
+ 
+ 	list_for_each_entry(link, &supplier->links.consumers, s_node)
+-		if (link->consumer == consumer)
++		if (link->consumer == consumer) {
++			kref_get(&link->kref);
+ 			goto out;
++		}
+ 
+ 	link = kzalloc(sizeof(*link), GFP_KERNEL);
+ 	if (!link)
+@@ -232,6 +235,7 @@ struct device_link *device_link_add(stru
+ 	link->consumer = consumer;
+ 	INIT_LIST_HEAD(&link->c_node);
+ 	link->flags = flags;
++	kref_init(&link->kref);
+ 
+ 	/* Determine the initial link state. */
+ 	if (flags & DL_FLAG_STATELESS) {
+@@ -302,8 +306,10 @@ static void __device_link_free_srcu(stru
+ 	device_link_free(container_of(rhead, struct device_link, rcu_head));
+ }
+ 
+-static void __device_link_del(struct device_link *link)
++static void __device_link_del(struct kref *kref)
+ {
++	struct device_link *link = container_of(kref, struct device_link, kref);
++
+ 	dev_info(link->consumer, "Dropping the link to %s\n",
+ 		 dev_name(link->supplier));
+ 
+@@ -315,8 +321,10 @@ static void __device_link_del(struct dev
+ 	call_srcu(&device_links_srcu, &link->rcu_head, __device_link_free_srcu);
+ }
+ #else /* !CONFIG_SRCU */
+-static void __device_link_del(struct device_link *link)
++static void __device_link_del(struct kref *kref)
+ {
++	struct device_link *link = container_of(kref, struct device_link, kref);
++
+ 	dev_info(link->consumer, "Dropping the link to %s\n",
+ 		 dev_name(link->supplier));
+ 
+@@ -334,18 +342,50 @@ static void __device_link_del(struct dev
+  * @link: Device link to delete.
+  *
+  * The caller must ensure proper synchronization of this function with runtime
+- * PM.
++ * PM.  If the link was added multiple times, it needs to be deleted as often.
++ * Care is required for hotplugged devices:  Their links are purged on removal
++ * and calling device_link_del() is then no longer allowed.
+  */
+ void device_link_del(struct device_link *link)
+ {
+ 	device_links_write_lock();
+ 	device_pm_lock();
+-	__device_link_del(link);
++	kref_put(&link->kref, __device_link_del);
+ 	device_pm_unlock();
+ 	device_links_write_unlock();
+ }
+ EXPORT_SYMBOL_GPL(device_link_del);
+ 
++/**
++ * device_link_remove - remove a link between two devices.
++ * @consumer: Consumer end of the link.
++ * @supplier: Supplier end of the link.
++ *
++ * The caller must ensure proper synchronization of this function with runtime
++ * PM.
++ */
++void device_link_remove(void *consumer, struct device *supplier)
++{
++	struct device_link *link;
++
++	if (WARN_ON(consumer == supplier))
++		return;
++
++	device_links_write_lock();
++	device_pm_lock();
++
++	list_for_each_entry(link, &supplier->links.consumers, s_node) {
++		if (link->consumer == consumer) {
++			kref_put(&link->kref, __device_link_del);
++			break;
++		}
++	}
++
++	device_pm_unlock();
++	device_links_write_unlock();
++}
++EXPORT_SYMBOL_GPL(device_link_remove);
++
+ static void device_links_missing_supplier(struct device *dev)
+ {
+ 	struct device_link *link;
+@@ -453,8 +493,8 @@ static void __device_links_no_driver(str
+ 		if (link->flags & DL_FLAG_STATELESS)
+ 			continue;
+ 
+-		if (link->flags & DL_FLAG_AUTOREMOVE)
+-			__device_link_del(link);
++		if (link->flags & DL_FLAG_AUTOREMOVE_CONSUMER)
++			kref_put(&link->kref, __device_link_del);
+ 		else if (link->status != DL_STATE_SUPPLIER_UNBIND)
+ 			WRITE_ONCE(link->status, DL_STATE_AVAILABLE);
+ 	}
+@@ -489,8 +529,18 @@ void device_links_driver_cleanup(struct
+ 		if (link->flags & DL_FLAG_STATELESS)
+ 			continue;
+ 
+-		WARN_ON(link->flags & DL_FLAG_AUTOREMOVE);
++		WARN_ON(link->flags & DL_FLAG_AUTOREMOVE_CONSUMER);
+ 		WARN_ON(link->status != DL_STATE_SUPPLIER_UNBIND);
++
++		/*
++		 * autoremove the links between this @dev and its consumer
++		 * devices that are not active, i.e. where the link state
++		 * has moved to DL_STATE_SUPPLIER_UNBIND.
++		 */
++		if (link->status == DL_STATE_SUPPLIER_UNBIND &&
++		    link->flags & DL_FLAG_AUTOREMOVE_SUPPLIER)
++			kref_put(&link->kref, __device_link_del);
++
+ 		WRITE_ONCE(link->status, DL_STATE_DORMANT);
+ 	}
+ 
+@@ -607,13 +657,13 @@ static void device_links_purge(struct de
+ 
+ 	list_for_each_entry_safe_reverse(link, ln, &dev->links.suppliers, c_node) {
+ 		WARN_ON(link->status == DL_STATE_ACTIVE);
+-		__device_link_del(link);
++		__device_link_del(&link->kref);
+ 	}
+ 
+ 	list_for_each_entry_safe_reverse(link, ln, &dev->links.consumers, s_node) {
+ 		WARN_ON(link->status != DL_STATE_DORMANT &&
+ 			link->status != DL_STATE_NONE);
+-		__device_link_del(link);
++		__device_link_del(&link->kref);
+ 	}
+ 
+ 	device_links_write_unlock();
+@@ -1035,6 +1085,34 @@ static ssize_t online_store(struct devic
+ }
+ static DEVICE_ATTR_RW(online);
+ 
++static ssize_t suppliers_show(struct device *dev, struct device_attribute *attr,
++			      char *buf)
++{
++	struct device_link *link;
++	size_t count = 0;
++
++	list_for_each_entry(link, &dev->links.suppliers, c_node)
++		count += scnprintf(buf + count, PAGE_SIZE - count, "%s\n",
++				   dev_name(link->supplier));
++
++	return count;
++}
++static DEVICE_ATTR_RO(suppliers);
++
++static ssize_t consumers_show(struct device *dev, struct device_attribute *attr,
++			      char *buf)
++{
++	struct device_link *link;
++	size_t count = 0;
++
++	list_for_each_entry(link, &dev->links.consumers, s_node)
++		count += scnprintf(buf + count, PAGE_SIZE - count, "%s\n",
++				   dev_name(link->consumer));
++
++	return count;
++}
++static DEVICE_ATTR_RO(consumers);
++
+ int device_add_groups(struct device *dev, const struct attribute_group **groups)
+ {
+ 	return sysfs_create_groups(&dev->kobj, groups);
+@@ -1206,8 +1284,20 @@ static int device_add_attrs(struct devic
+ 			goto err_remove_dev_groups;
+ 	}
+ 
++	error = device_create_file(dev, &dev_attr_suppliers);
++	if (error)
++		goto err_remove_online;
++
++	error = device_create_file(dev, &dev_attr_consumers);
++	if (error)
++		goto err_remove_suppliers;
++
+ 	return 0;
+ 
++ err_remove_suppliers:
++	device_remove_file(dev, &dev_attr_suppliers);
++ err_remove_online:
++	device_remove_file(dev, &dev_attr_online);
+  err_remove_dev_groups:
+ 	device_remove_groups(dev, dev->groups);
+  err_remove_type_groups:
+@@ -1225,6 +1315,8 @@ static void device_remove_attrs(struct d
+ 	struct class *class = dev->class;
+ 	const struct device_type *type = dev->type;
+ 
++	device_remove_file(dev, &dev_attr_consumers);
++	device_remove_file(dev, &dev_attr_suppliers);
+ 	device_remove_file(dev, &dev_attr_online);
+ 	device_remove_groups(dev, dev->groups);
+ 
 --- a/drivers/base/dma-mapping.c
 +++ b/drivers/base/dma-mapping.c
 @@ -335,6 +335,7 @@ void dma_common_free_remap(void *cpu_add
@@ -72,62 +319,87 @@ Signed-off-by: Biwen Li <[email protected]>
  	if (dma_dev->of_node) {
  		ret = of_dma_configure(dev, dma_dev->of_node);
  	} else if (has_acpi_companion(dma_dev)) {
---- a/drivers/net/bonding/bond_main.c
-+++ b/drivers/net/bonding/bond_main.c
-@@ -1330,7 +1330,8 @@ void bond_lower_state_changed(struct sla
- }
- 
- /* enslave device <slave> to bond device <master> */
--int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev)
-+int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev,
-+		 struct netlink_ext_ack *extack)
- {
- 	struct bonding *bond = netdev_priv(bond_dev);
- 	const struct net_device_ops *slave_ops = slave_dev->netdev_ops;
-@@ -3506,7 +3507,7 @@ static int bond_do_ioctl(struct net_devi
- 	switch (cmd) {
- 	case BOND_ENSLAVE_OLD:
- 	case SIOCBONDENSLAVE:
--		res = bond_enslave(bond_dev, slave_dev);
-+		res = bond_enslave(bond_dev, slave_dev, NULL);
- 		break;
- 	case BOND_RELEASE_OLD:
- 	case SIOCBONDRELEASE:
---- a/drivers/net/bonding/bond_options.c
-+++ b/drivers/net/bonding/bond_options.c
-@@ -1382,7 +1382,7 @@ static int bond_option_slaves_set(struct
- 	switch (command[0]) {
- 	case '+':
- 		netdev_dbg(bond->dev, "Adding slave %s\n", dev->name);
--		ret = bond_enslave(bond->dev, dev);
-+		ret = bond_enslave(bond->dev, dev, NULL);
- 		break;
- 
- 	case '-':
---- a/drivers/net/team/team.c
-+++ b/drivers/net/team/team.c
-@@ -1953,7 +1953,8 @@ static int team_netpoll_setup(struct net
- }
- #endif
- 
--static int team_add_slave(struct net_device *dev, struct net_device *port_dev)
-+static int team_add_slave(struct net_device *dev, struct net_device *port_dev,
-+			  struct netlink_ext_ack *extack)
- {
- 	struct team *team = netdev_priv(dev);
- 	int err;
---- a/drivers/net/vrf.c
-+++ b/drivers/net/vrf.c
-@@ -791,7 +791,8 @@ err:
- 	return ret;
- }
- 
--static int vrf_add_slave(struct net_device *dev, struct net_device *port_dev)
-+static int vrf_add_slave(struct net_device *dev, struct net_device *port_dev,
-+			 struct netlink_ext_ack *extack)
- {
- 	if (netif_is_l3_master(port_dev) || netif_is_l3_slave(port_dev))
- 		return -EINVAL;
+--- a/drivers/gpu/ipu-v3/ipu-pre.c
++++ b/drivers/gpu/ipu-v3/ipu-pre.c
+@@ -124,7 +124,8 @@ ipu_pre_lookup_by_phandle(struct device
+ 	list_for_each_entry(pre, &ipu_pre_list, list) {
+ 		if (pre_node == pre->dev->of_node) {
+ 			mutex_unlock(&ipu_pre_list_mutex);
+-			device_link_add(dev, pre->dev, DL_FLAG_AUTOREMOVE);
++			device_link_add(dev, pre->dev,
++					DL_FLAG_AUTOREMOVE_CONSUMER);
+ 			of_node_put(pre_node);
+ 			return pre;
+ 		}
+--- a/drivers/gpu/ipu-v3/ipu-prg.c
++++ b/drivers/gpu/ipu-v3/ipu-prg.c
+@@ -99,7 +99,8 @@ ipu_prg_lookup_by_phandle(struct device
+ 	list_for_each_entry(prg, &ipu_prg_list, list) {
+ 		if (prg_node == prg->dev->of_node) {
+ 			mutex_unlock(&ipu_prg_list_mutex);
+-			device_link_add(dev, prg->dev, DL_FLAG_AUTOREMOVE);
++			device_link_add(dev, prg->dev,
++					DL_FLAG_AUTOREMOVE_CONSUMER);
+ 			prg->id = ipu_id;
+ 			of_node_put(prg_node);
+ 			return prg;
+--- a/drivers/iommu/dma-iommu.c
++++ b/drivers/iommu/dma-iommu.c
+@@ -381,6 +381,9 @@ static dma_addr_t iommu_dma_alloc_iova(s
+ 	if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1)))
+ 		iova_len = roundup_pow_of_two(iova_len);
+ 
++	if (dev->bus_dma_mask)
++		dma_limit &= dev->bus_dma_mask;
++
+ 	if (domain->geometry.force_aperture)
+ 		dma_limit = min(dma_limit, domain->geometry.aperture_end);
+ 
+--- a/drivers/mux/Kconfig
++++ b/drivers/mux/Kconfig
+@@ -35,14 +35,14 @@ config MUX_GPIO
+ 	  be called mux-gpio.
+ 
+ config MUX_MMIO
+-	tristate "MMIO register bitfield-controlled Multiplexer"
+-	depends on (OF && MFD_SYSCON) || COMPILE_TEST
++	tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
++	depends on OF || COMPILE_TEST
+ 	help
+-	  MMIO register bitfield-controlled Multiplexer controller.
++	  MMIO/Regmap register bitfield-controlled Multiplexer controller.
+ 
+-	  The driver builds multiplexer controllers for bitfields in a syscon
+-	  register. For N bit wide bitfields, there will be 2^N possible
+-	  multiplexer states.
++	  The driver builds multiplexer controllers for bitfields in either
++	  a syscon register or a driver regmap register. For N bit wide
++	  bitfields, there will be 2^N possible multiplexer states.
+ 
+ 	  To compile the driver as a module, choose M here: the module will
+ 	  be called mux-mmio.
+--- a/drivers/mux/mmio.c
++++ b/drivers/mux/mmio.c
+@@ -31,6 +31,7 @@ static const struct mux_control_ops mux_
+ 
+ static const struct of_device_id mux_mmio_dt_ids[] = {
+ 	{ .compatible = "mmio-mux", },
++	{ .compatible = "reg-mux", },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, mux_mmio_dt_ids);
+@@ -46,7 +47,10 @@ static int mux_mmio_probe(struct platfor
+ 	int ret;
+ 	int i;
+ 
+-	regmap = syscon_node_to_regmap(np->parent);
++	if (of_device_is_compatible(np, "mmio-mux"))
++		regmap = syscon_node_to_regmap(np->parent);
++	else
++		regmap = dev_get_regmap(dev->parent, NULL) ?: ERR_PTR(-ENODEV);
+ 	if (IS_ERR(regmap)) {
+ 		ret = PTR_ERR(regmap);
+ 		dev_err(dev, "failed to get regmap: %d\n", ret);
 --- a/drivers/of/device.c
 +++ b/drivers/of/device.c
 @@ -15,6 +15,9 @@
@@ -150,7 +422,11 @@ Signed-off-by: Biwen Li <[email protected]>
  		    dev->bus != &platform_bus_type)
  			return ret == -ENODEV ? 0 : ret;
  
-@@ -155,7 +161,12 @@ int of_dma_configure(struct device *dev,
+@@ -152,10 +158,16 @@ int of_dma_configure(struct device *dev,
+ 	 * set by the driver.
+ 	 */
+ 	mask = DMA_BIT_MASK(ilog2(dma_addr + size - 1) + 1);
++	dev->bus_dma_mask = mask;
  	dev->coherent_dma_mask &= mask;
  	*dev->dma_mask &= mask;
  
@@ -164,18 +440,91 @@ Signed-off-by: Biwen Li <[email protected]>
  	dev_dbg(dev, "device is%sdma coherent\n",
  		coherent ? " " : " not ");
  
---- a/drivers/soc/fsl/guts.c
-+++ b/drivers/soc/fsl/guts.c
-@@ -213,6 +213,9 @@ static const struct of_device_id fsl_gut
- 	{ .compatible = "fsl,ls1021a-dcfg", },
- 	{ .compatible = "fsl,ls1043a-dcfg", },
- 	{ .compatible = "fsl,ls2080a-dcfg", },
-+	{ .compatible = "fsl,ls1088a-dcfg", },
-+	{ .compatible = "fsl,ls1012a-dcfg", },
-+	{ .compatible = "fsl,ls1046a-dcfg", },
- 	{}
- };
- MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
+--- a/drivers/soc/imx/gpc.c
++++ b/drivers/soc/imx/gpc.c
+@@ -209,7 +209,7 @@ static int imx_pgc_power_domain_probe(st
+ 			goto genpd_err;
+ 	}
+ 
+-	device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE);
++	device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE_CONSUMER);
+ 
+ 	return 0;
+ 
+--- a/include/linux/device.h
++++ b/include/linux/device.h
+@@ -55,6 +55,8 @@ struct bus_attribute {
+ 	struct bus_attribute bus_attr_##_name = __ATTR_RW(_name)
+ #define BUS_ATTR_RO(_name) \
+ 	struct bus_attribute bus_attr_##_name = __ATTR_RO(_name)
++#define BUS_ATTR_WO(_name) \
++	struct bus_attribute bus_attr_##_name = __ATTR_WO(_name)
+ 
+ extern int __must_check bus_create_file(struct bus_type *,
+ 					struct bus_attribute *);
+@@ -750,14 +752,16 @@ enum device_link_state {
+  * Device link flags.
+  *
+  * STATELESS: The core won't track the presence of supplier/consumer drivers.
+- * AUTOREMOVE: Remove this link automatically on consumer driver unbind.
++ * AUTOREMOVE_CONSUMER: Remove the link automatically on consumer driver unbind.
+  * PM_RUNTIME: If set, the runtime PM framework will use this link.
+  * RPM_ACTIVE: Run pm_runtime_get_sync() on the supplier during link creation.
++ * AUTOREMOVE_SUPPLIER: Remove the link automatically on supplier driver unbind.
+  */
+-#define DL_FLAG_STATELESS	BIT(0)
+-#define DL_FLAG_AUTOREMOVE	BIT(1)
+-#define DL_FLAG_PM_RUNTIME	BIT(2)
+-#define DL_FLAG_RPM_ACTIVE	BIT(3)
++#define DL_FLAG_STATELESS		BIT(0)
++#define DL_FLAG_AUTOREMOVE_CONSUMER	BIT(1)
++#define DL_FLAG_PM_RUNTIME		BIT(2)
++#define DL_FLAG_RPM_ACTIVE		BIT(3)
++#define DL_FLAG_AUTOREMOVE_SUPPLIER	BIT(4)
+ 
+ /**
+  * struct device_link - Device link representation.
+@@ -768,6 +772,7 @@ enum device_link_state {
+  * @status: The state of the link (with respect to the presence of drivers).
+  * @flags: Link flags.
+  * @rpm_active: Whether or not the consumer device is runtime-PM-active.
++ * @kref: Count repeated addition of the same link.
+  * @rcu_head: An RCU head to use for deferred execution of SRCU callbacks.
+  */
+ struct device_link {
+@@ -778,6 +783,7 @@ struct device_link {
+ 	enum device_link_state status;
+ 	u32 flags;
+ 	bool rpm_active;
++	struct kref kref;
+ #ifdef CONFIG_SRCU
+ 	struct rcu_head rcu_head;
+ #endif
+@@ -850,6 +856,8 @@ struct dev_links_info {
+  * @coherent_dma_mask: Like dma_mask, but for alloc_coherent mapping as not all
+  * 		hardware supports 64-bit addresses for consistent allocations
+  * 		such descriptors.
++ * @bus_dma_mask: Mask of an upstream bridge or bus which imposes a smaller DMA
++ * 		limit than the device itself supports.
+  * @dma_pfn_offset: offset of DMA memory range relatively of RAM
+  * @dma_parms:	A low level driver may set these to teach IOMMU code about
+  * 		segment limitations.
+@@ -929,6 +937,7 @@ struct device {
+ 					     not all hardware supports
+ 					     64 bit addresses for consistent
+ 					     allocations such descriptors. */
++	u64             bus_dma_mask;   /* upstream dma_mask constraint */
+ 	unsigned long	dma_pfn_offset;
+ 
+ 	struct device_dma_parameters *dma_parms;
+@@ -1267,6 +1276,7 @@ extern const char *dev_driver_string(con
+ struct device_link *device_link_add(struct device *consumer,
+ 				    struct device *supplier, u32 flags);
+ void device_link_del(struct device_link *link);
++void device_link_remove(void *consumer, struct device *supplier);
+ 
+ #ifdef CONFIG_PRINTK
+ 
 --- a/include/linux/fsl_devices.h
 +++ b/include/linux/fsl_devices.h
 @@ -99,7 +99,9 @@ struct fsl_usb2_platform_data {
@@ -190,17 +539,7 @@ Signed-off-by: Biwen Li <[email protected]>
  
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -1260,7 +1260,8 @@ struct net_device_ops {
- 						     u32 flow_id);
- #endif
- 	int			(*ndo_add_slave)(struct net_device *dev,
--						 struct net_device *slave_dev);
-+						 struct net_device *slave_dev,
-+						 struct netlink_ext_ack *extack);
- 	int			(*ndo_del_slave)(struct net_device *dev,
- 						 struct net_device *slave_dev);
- 	netdev_features_t	(*ndo_fix_features)(struct net_device *dev,
-@@ -2344,7 +2345,8 @@ int register_netdevice_notifier(struct n
+@@ -2344,7 +2344,8 @@ int register_netdevice_notifier(struct n
  int unregister_netdevice_notifier(struct notifier_block *nb);
  
  struct netdev_notifier_info {
@@ -210,7 +549,7 @@ Signed-off-by: Biwen Li <[email protected]>
  };
  
  struct netdev_notifier_info_ext {
-@@ -2376,6 +2378,7 @@ static inline void netdev_notifier_info_
+@@ -2376,6 +2377,7 @@ static inline void netdev_notifier_info_
  					     struct net_device *dev)
  {
  	info->dev = dev;
@@ -218,7 +557,7 @@ Signed-off-by: Biwen Li <[email protected]>
  }
  
  static inline struct net_device *
-@@ -2384,6 +2387,12 @@ netdev_notifier_info_to_dev(const struct
+@@ -2384,6 +2386,12 @@ netdev_notifier_info_to_dev(const struct
  	return info->dev;
  }
  
@@ -249,42 +588,58 @@ Signed-off-by: Biwen Li <[email protected]>
  int skb_store_bits(struct sk_buff *skb, int offset, const void *from, int len);
  __wsum skb_copy_and_csum_bits(const struct sk_buff *skb, int offset, u8 *to,
  			      int len, __wsum csum);
---- a/include/net/bonding.h
-+++ b/include/net/bonding.h
-@@ -592,7 +592,8 @@ void bond_destroy_sysfs(struct bond_net
- void bond_prepare_sysfs_group(struct bonding *bond);
- int bond_sysfs_slave_add(struct slave *slave);
- void bond_sysfs_slave_del(struct slave *slave);
--int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev);
-+int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev,
-+		 struct netlink_ext_ack *extack);
- int bond_release(struct net_device *bond_dev, struct net_device *slave_dev);
- u32 bond_xmit_hash(struct bonding *bond, struct sk_buff *skb);
- int bond_set_carrier(struct bonding *bond);
---- a/net/batman-adv/soft-interface.c
-+++ b/net/batman-adv/soft-interface.c
-@@ -876,7 +876,8 @@ free_bat_counters:
-  * Return: 0 if successful or error otherwise.
-  */
- static int batadv_softif_slave_add(struct net_device *dev,
--				   struct net_device *slave_dev)
-+				   struct net_device *slave_dev,
-+				   struct netlink_ext_ack *extack)
- {
- 	struct batadv_hard_iface *hard_iface;
- 	struct net *net = dev_net(dev);
---- a/net/bridge/br_device.c
-+++ b/net/bridge/br_device.c
-@@ -324,7 +324,8 @@ void br_netpoll_disable(struct net_bridg
- 
- #endif
+--- a/lib/dma-noop.c
++++ b/lib/dma-noop.c
+@@ -58,11 +58,30 @@ static int dma_noop_map_sg(struct device
+ 	return nents;
+ }
  
--static int br_add_slave(struct net_device *dev, struct net_device *slave_dev)
-+static int br_add_slave(struct net_device *dev, struct net_device *slave_dev,
-+			struct netlink_ext_ack *extack)
++static int dma_noop_supported(struct device *dev, u64 mask)
++{
++#ifdef CONFIG_ZONE_DMA
++	if (mask < DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
++	return 0;
++#else
++	/*
++	 * Because 32-bit DMA masks are so common we expect every architecture
++	 * to be able to satisfy them - either by not supporting more physical
++	 * memory, or by providing a ZONE_DMA32.  If neither is the case, the
++	 * architecture needs to use an IOMMU instead of the direct mapping.
++	 */
++	if (dev->bus_dma_mask && mask > dev->bus_dma_mask)
++		return 0;
++#endif
++	return 1;
++}
++
+ const struct dma_map_ops dma_noop_ops = {
+ 	.alloc			= dma_noop_alloc,
+ 	.free			= dma_noop_free,
+ 	.map_page		= dma_noop_map_page,
+ 	.map_sg			= dma_noop_map_sg,
++	dma_supported		= dma_noop_supported
+ };
  
+ EXPORT_SYMBOL(dma_noop_ops);
+--- a/mm/page_alloc.c
++++ b/mm/page_alloc.c
+@@ -4366,8 +4366,14 @@ void page_frag_free(void *addr)
  {
- 	struct net_bridge *br = netdev_priv(dev);
+ 	struct page *page = virt_to_head_page(addr);
+ 
+-	if (unlikely(put_page_testzero(page)))
+-		__free_pages_ok(page, compound_order(page));
++	if (unlikely(put_page_testzero(page))) {
++		unsigned int order = compound_order(page);
++
++		if (order == 0)		/* Via pcp? */
++			free_hot_cold_page(page, false);
++		else
++			__free_pages_ok(page, order);
++	}
+ }
+ EXPORT_SYMBOL(page_frag_free);
+ 
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
 @@ -162,7 +162,6 @@ static struct list_head offload_base __r
@@ -480,46 +835,6 @@ Signed-off-by: Biwen Li <[email protected]>
  	}
  }
  
---- a/net/core/rtnetlink.c
-+++ b/net/core/rtnetlink.c
-@@ -1912,7 +1912,8 @@ static int do_setvfinfo(struct net_devic
- 	return err;
- }
- 
--static int do_set_master(struct net_device *dev, int ifindex)
-+static int do_set_master(struct net_device *dev, int ifindex,
-+			 struct netlink_ext_ack *extack)
- {
- 	struct net_device *upper_dev = netdev_master_upper_dev_get(dev);
- 	const struct net_device_ops *ops;
-@@ -1937,7 +1938,7 @@ static int do_set_master(struct net_devi
- 			return -EINVAL;
- 		ops = upper_dev->netdev_ops;
- 		if (ops->ndo_add_slave) {
--			err = ops->ndo_add_slave(upper_dev, dev);
-+			err = ops->ndo_add_slave(upper_dev, dev, extack);
- 			if (err)
- 				return err;
- 		} else {
-@@ -2074,7 +2075,7 @@ static int do_setlink(const struct sk_bu
- 	}
- 
- 	if (tb[IFLA_MASTER]) {
--		err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]));
-+		err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]), extack);
- 		if (err)
- 			goto errout;
- 		status |= DO_SETLINK_MODIFIED;
-@@ -2723,7 +2724,8 @@ replay:
- 				goto out_unregister;
- 		}
- 		if (tb[IFLA_MASTER]) {
--			err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]));
-+			err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]),
-+					    extack);
- 			if (err)
- 				goto out_unregister;
- 		}
 --- a/net/core/skbuff.c
 +++ b/net/core/skbuff.c
 @@ -803,6 +803,32 @@ void napi_consume_skb(struct sk_buff *sk

target/linux/layerscape/patches-4.14/301-arch-support-layerscape.patch

@@ -1,12 +1,17 @@
-From 6eeff55fd4756f271ad09a914078c9aa45f8359d Mon Sep 17 00:00:00 2001
-From: Biwen Li <[email protected]>
-Date: Fri, 16 Nov 2018 14:23:40 +0800
-Subject: [PATCH 04/39] arch: support layerscape
+From f29db0048a07384ee4cd962c676b750e13e5d6b0 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <[email protected]>
+Date: Mon, 6 May 2019 17:17:58 +0800
+Subject: [PATCH] arch: support layerscape
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
 This is an integrated patch of arch for layerscape
 
 Signed-off-by: Abhimanyu Saini <[email protected]>
 Signed-off-by: Alison Wang <[email protected]>
 Signed-off-by: Amrita Kumari <[email protected]>
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Chenhui Zhao <[email protected]>
 Signed-off-by: Dave Liu <[email protected]>
 Signed-off-by: Guanhua <[email protected]>
@@ -19,6 +24,7 @@ Signed-off-by: Laurentiu Tudor <[email protected]>
 Signed-off-by: Li Yang <[email protected]>
 Signed-off-by: Madalin Bucur <[email protected]>
 Signed-off-by: Pan Jiafei <[email protected]>
+Signed-off-by: Pankaj Bansal <[email protected]>
 Signed-off-by: Poonam Aggrwal <[email protected]>
 Signed-off-by: Rajesh Bhagat <[email protected]>
 Signed-off-by: Ramneek Mehresh <[email protected]>
@@ -26,28 +32,32 @@ Signed-off-by: Ran Wang <[email protected]>
 Signed-off-by: Roy Pledge <[email protected]>
 Signed-off-by: Shengzhou Liu <[email protected]>
 Signed-off-by: Tang Yuantian <[email protected]>
+Signed-off-by: Vabhav Sharma <[email protected]>
 Signed-off-by: Wang Dongsheng <[email protected]>
 Signed-off-by: Xie Xiaobo <[email protected]>
 Signed-off-by: Yangbo Lu <[email protected]>
+Signed-off-by: Yinbo Zhu <[email protected]>
 Signed-off-by: Zhao Chenhui <[email protected]>
 Signed-off-by: Zhao Qiang <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 ---
- arch/arm/include/asm/delay.h          | 16 ++++++++++++++
- arch/arm/include/asm/io.h             | 31 +++++++++++++++++++++++++++
- arch/arm/include/asm/mach/map.h       |  4 ++--
- arch/arm/include/asm/pgtable.h        |  7 ++++++
- arch/arm/kernel/time.c                |  3 +++
- arch/arm/mm/dma-mapping.c             |  1 +
- arch/arm/mm/ioremap.c                 |  7 ++++++
- arch/arm/mm/mmu.c                     |  9 ++++++++
- arch/arm64/include/asm/cache.h        |  2 +-
- arch/arm64/include/asm/io.h           |  1 +
- arch/arm64/include/asm/pgtable-prot.h |  3 +++
- arch/arm64/include/asm/pgtable.h      |  5 +++++
- arch/arm64/mm/dma-mapping.c           |  1 +
- arch/arm64/mm/init.c                  | 12 +++++++----
- 14 files changed, 95 insertions(+), 7 deletions(-)
+ arch/arm/include/asm/delay.h          |  16 ++++++
+ arch/arm/include/asm/io.h             |  31 ++++++++++
+ arch/arm/include/asm/mach/map.h       |   4 +-
+ arch/arm/include/asm/pgtable.h        |   7 +++
+ arch/arm/kernel/time.c                |   3 +
+ arch/arm/mm/dma-mapping.c             |   1 +
+ arch/arm/mm/ioremap.c                 |   7 +++
+ arch/arm/mm/mmu.c                     |   9 +++
+ arch/arm64/include/asm/cache.h        |   2 +-
+ arch/arm64/include/asm/io.h           |   1 +
+ arch/arm64/include/asm/pgtable-prot.h |   3 +
+ arch/arm64/include/asm/pgtable.h      |   5 ++
+ arch/arm64/mm/dma-mapping.c           |   1 +
+ arch/arm64/mm/init.c                  |  12 ++--
+ drivers/soc/fsl/guts.c                |   9 +++
+ drivers/soc/fsl/qixis_ctrl.c          | 105 ++++++++++++++++++++++++++++++++++
+ 16 files changed, 209 insertions(+), 7 deletions(-)
+ create mode 100644 drivers/soc/fsl/qixis_ctrl.c
 
 --- a/arch/arm/include/asm/delay.h
 +++ b/arch/arm/include/asm/delay.h
@@ -323,3 +333,136 @@ Signed-off-by: Biwen Li <[email protected]>
  	high_memory = __va(memblock_end_of_DRAM() - 1) + 1;
  
  	dma_contiguous_reserve(arm64_dma_phys_limit);
+--- a/drivers/soc/fsl/guts.c
++++ b/drivers/soc/fsl/guts.c
+@@ -100,6 +100,11 @@ static const struct fsl_soc_die_attr fsl
+ 	  .svr		= 0x87000000,
+ 	  .mask		= 0xfff70000,
+ 	},
++	/* Die: LX2160A, SoC: LX2160A/LX2120A/LX2080A */
++	{ .die          = "LX2160A",
++	  .svr          = 0x87360000,
++	  .mask         = 0xff3f0000,
++	},
+ 	{ },
+ };
+ 
+@@ -213,6 +218,10 @@ static const struct of_device_id fsl_gut
+ 	{ .compatible = "fsl,ls1021a-dcfg", },
+ 	{ .compatible = "fsl,ls1043a-dcfg", },
+ 	{ .compatible = "fsl,ls2080a-dcfg", },
++	{ .compatible = "fsl,ls1088a-dcfg", },
++	{ .compatible = "fsl,ls1012a-dcfg", },
++	{ .compatible = "fsl,ls1046a-dcfg", },
++	{ .compatible = "fsl,lx2160a-dcfg", },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
+--- /dev/null
++++ b/drivers/soc/fsl/qixis_ctrl.c
+@@ -0,0 +1,105 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++/* Freescale QIXIS system controller driver.
++ *
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ * Copyright 2018-2019 NXP
++ */
++
++#include <linux/err.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/mfd/core.h>
++#include <linux/of.h>
++#include <linux/regmap.h>
++
++/* QIXIS MAP */
++struct fsl_qixis_regs {
++	u8		id;		/* Identification Registers */
++	u8		version;	/* Version Register */
++	u8		qixis_ver;	/* QIXIS Version Register */
++	u8		reserved1[0x1f];
++};
++
++struct qixis_priv {
++	struct regmap		*regmap;
++};
++
++static struct regmap_config qixis_regmap_config = {
++	.reg_bits = 8,
++	.val_bits = 8,
++};
++
++static const struct mfd_cell fsl_qixis_devs[] = {
++	{
++		.name = "reg-mux",
++		.of_compatible = "reg-mux",
++	},
++};
++
++static int fsl_qixis_i2c_probe(struct i2c_client *client)
++{
++	struct qixis_priv *priv;
++	int ret = 0;
++	u32 qver;
++
++	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
++		return -EOPNOTSUPP;
++
++	priv = devm_kzalloc(&client->dev, sizeof(struct qixis_priv),
++			    GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->regmap = regmap_init_i2c(client, &qixis_regmap_config);
++	regmap_read(priv->regmap, offsetof(struct fsl_qixis_regs, qixis_ver),
++		    &qver);
++	pr_info("Freescale QIXIS Version: 0x%08x\n", qver);
++
++	i2c_set_clientdata(client, priv);
++
++	if (of_device_is_compatible(client->dev.of_node, "simple-mfd"))
++		ret = devm_mfd_add_devices(&client->dev, -1, fsl_qixis_devs,
++					   ARRAY_SIZE(fsl_qixis_devs), NULL, 0,
++					   NULL);
++	if (ret)
++		goto error;
++
++	return ret;
++error:
++	regmap_exit(priv->regmap);
++
++	return ret;
++}
++
++static int fsl_qixis_i2c_remove(struct i2c_client *client)
++{
++	struct qixis_priv *priv;
++
++	priv = i2c_get_clientdata(client);
++	regmap_exit(priv->regmap);
++
++	return 0;
++}
++
++static const struct of_device_id fsl_qixis_i2c_of_match[] = {
++	{ .compatible = "fsl,fpga-qixis-i2c" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, fsl_qixis_i2c_of_match);
++
++static struct i2c_driver fsl_qixis_i2c_driver = {
++	.driver = {
++		.name	= "qixis_ctrl_i2c",
++		.owner	= THIS_MODULE,
++		.of_match_table = of_match_ptr(fsl_qixis_i2c_of_match),
++	},
++	.probe_new	= fsl_qixis_i2c_probe,
++	.remove		= fsl_qixis_i2c_remove,
++};
++module_i2c_driver(fsl_qixis_i2c_driver);
++
++MODULE_AUTHOR("Wang Dongsheng <[email protected]>");
++MODULE_DESCRIPTION("Freescale QIXIS system controller driver");
++MODULE_LICENSE("GPL");
++

target/linux/layerscape/patches-4.14/303-add-DTS-for-Traverse-LS1043-Boards.patch

@@ -1,96 +0,0 @@
-From 263092cd68368ac6f030b847a1d5b0069bc2cef3 Mon Sep 17 00:00:00 2001
-From: Mathew McBride <[email protected]>
-Date: Tue, 17 Apr 2018 10:01:03 +1000
-Subject: [PATCH 05/40] add DTS for Traverse LS1043 Boards
-
-Signed-off-by: Mathew McBride <[email protected]>
----
- arch/arm64/boot/dts/freescale/Makefile        |  5 +++-
- .../boot/dts/freescale/traverse-ls1043s.dts   | 29 +++++++++++++++++++
- .../boot/dts/freescale/traverse-ls1043v.dts   | 29 +++++++++++++++++++
- 3 files changed, 62 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/freescale/Makefile
-+++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -22,7 +22,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
-- 
-+
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043v.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043s.dtb
-+
- always		:= $(dtb-y)
- subdir-y	:= $(dts-dirs)
- clean-files	:= *.dtb
---- a/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts
-+++ b/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts
-@@ -330,3 +330,32 @@
- &sata {
- 	status = "disabled";
- };
-+
-+/* Additions for Layerscape SDK (4.4/4.9) Kernel only
-+ * These kernels need additional setup for FMan/QMan DMA shared memory
-+ */
-+
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+	compatible = "fsl,bman-fbpr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+	compatible = "fsl,qman-fqd";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+	compatible = "fsl,qman-pfdr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+};
-+
-+&fman0 {
-+	compatible = "fsl,fman", "simple-bus";
-+};
---- a/arch/arm64/boot/dts/freescale/traverse-ls1043v.dts
-+++ b/arch/arm64/boot/dts/freescale/traverse-ls1043v.dts
-@@ -251,3 +251,32 @@
- &sata {
- 	status = "disabled";
- };
-+
-+/* Additions for Layerscape SDK (4.4/4.9) Kernel only
-+ * These kernels need additional setup for FMan/QMan DMA shared memory
-+ */
-+
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+	compatible = "fsl,bman-fbpr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+	compatible = "fsl,qman-fqd";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+	compatible = "fsl,qman-pfdr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+};
-+
-+&fman0 {
-+	compatible = "fsl,fman", "simple-bus";
-+};

target/linux/layerscape/patches-4.14/304-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch

@@ -1,289 +0,0 @@
-From bb1a53f1bcb3f4c5983955a1d419c0e4e2531043 Mon Sep 17 00:00:00 2001
-From: Biwen Li <[email protected]>
-Date: Fri, 26 Oct 2018 16:00:37 +0800
-Subject: [PATCH 06/40] arm: dts: ls1021a: Add LS1021A-IOT board support
-
-Signed-off-by: Biwen Li <[email protected]>
----
- arch/arm/boot/dts/Makefile        |   3 +-
- arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++++++++++++++++++++++++++++
- 2 files changed, 264 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -496,7 +496,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
- 	imx7s-warp.dtb
- dtb-$(CONFIG_SOC_LS1021A) += \
- 	ls1021a-qds.dtb \
--	ls1021a-twr.dtb
-+	ls1021a-twr.dtb \
-+	ls1021a-iot.dtb
- dtb-$(CONFIG_SOC_VF610) += \
- 	vf500-colibri-eval-v3.dtb \
- 	vf610-colibri-eval-v3.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/ls1021a-iot.dts
-@@ -0,0 +1,262 @@
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+/dts-v1/;
-+#include "ls1021a.dtsi"
-+
-+/ {
-+	model = "LS1021A IOT Board";
-+
-+	sys_mclk: clock-mclk {
-+		compatible = "fixed-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <24576000>;
-+	};
-+
-+	regulators {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		reg_3p3v: regulator@0 {
-+			compatible = "regulator-fixed";
-+			reg = <0>;
-+			regulator-name = "3P3V";
-+			regulator-min-microvolt = <3300000>;
-+			regulator-max-microvolt = <3300000>;
-+			regulator-always-on;
-+		};
-+
-+		reg_2p5v: regulator@1 {
-+			compatible = "regulator-fixed";
-+			reg = <1>;
-+			regulator-name = "2P5V";
-+			regulator-min-microvolt = <2500000>;
-+			regulator-max-microvolt = <2500000>;
-+			regulator-always-on;
-+		};
-+	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,format = "i2s";
-+		simple-audio-card,widgets =
-+			"Microphone", "Microphone Jack",
-+			"Headphone", "Headphone Jack",
-+			"Speaker", "Speaker Ext",
-+			"Line", "Line In Jack";
-+		simple-audio-card,routing =
-+			"MIC_IN", "Microphone Jack",
-+			"Microphone Jack", "Mic Bias",
-+			"LINE_IN", "Line In Jack",
-+			"Headphone Jack", "HP_OUT",
-+			"Speaker Ext", "LINE_OUT";
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&sai2>;
-+			frame-master;
-+			bitclock-master;
-+		};
-+
-+		simple-audio-card,codec {
-+			sound-dai = <&codec>;
-+			frame-master;
-+			bitclock-master;
-+		};
-+	};
-+
-+	firmware {
-+		optee {
-+			compatible = "linaro,optee-tz";
-+			method = "smc";
-+			};
-+		};
-+};
-+
-+&enet0 {
-+	tbi-handle = <&tbi1>;
-+	phy-handle = <&phy1>;
-+	phy-connection-type = "sgmii";
-+	status = "okay";
-+};
-+
-+&enet1 {
-+	tbi-handle = <&tbi1>;
-+	phy-handle = <&phy3>;
-+	phy-connection-type = "sgmii";
-+	status = "okay";
-+};
-+
-+&enet2 {
-+	fixed-link = <0 1 1000 0 0>;
-+	phy-connection-type = "rgmii-id";
-+	status = "okay";
-+};
-+
-+&can0{
-+	status = "disabled";
-+};
-+
-+&can1{
-+	status = "disabled";
-+};
-+
-+&can2{
-+	status = "disabled";
-+};
-+
-+&can3{
-+	status = "okay";
-+};
-+
-+&esdhc{
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	max1239@35 {
-+		compatible = "maxim,max1239";
-+		reg = <0x35>;
-+		#io-channel-cells = <1>;
-+	};
-+
-+	codec: sgtl5000@2a {
-+               #sound-dai-cells=<0x0>;
-+		compatible = "fsl,sgtl5000";
-+		reg = <0x2a>;
-+		VDDA-supply = <&reg_3p3v>;
-+		VDDIO-supply = <&reg_2p5v>;
-+		clocks = <&sys_mclk 1>;
-+	};
-+
-+	pca9555: pca9555@23 {
-+		compatible = "nxp,pca9555";
-+		/*pinctrl-names = "default";*/
-+		/*interrupt-parent = <&gpio2>;
-+		interrupts = <19 0x2>;*/
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		interrupt-controller;
-+		#interrupt-cells = <2>;
-+		reg = <0x23>;
-+	};
-+
-+	ina220@44 {
-+		compatible = "ti,ina220";
-+		reg = <0x44>;
-+		shunt-resistor = <1000>;
-+	};
-+
-+	ina220@45 {
-+		compatible = "ti,ina220";
-+		reg = <0x45>;
-+		shunt-resistor = <1000>;
-+	};
-+
-+	lm75b@48 {
-+                compatible = "nxp,lm75a";
-+                reg = <0x48>;
-+        };
-+
-+	adt7461a@4c {
-+		compatible = "adt7461a";
-+		reg = <0x4c>;
-+	};
-+
-+	hdmi: sii9022a@39 {
-+		compatible = "fsl,sii902x";
-+		reg = <0x39>;
-+		interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
-+	};
-+};
-+
-+&i2c1 {
-+	status = "disabled";
-+};
-+
-+&ifc {
-+	status = "disabled";
-+};
-+
-+&lpuart0 {
-+	status = "okay";
-+};
-+
-+&mdio0 {
-+	phy0: ethernet-phy@0 {
-+		reg = <0x0>;
-+	};
-+	phy1: ethernet-phy@1 {
-+		reg = <0x1>;
-+	};
-+	phy2: ethernet-phy@2 {
-+		reg = <0x2>;
-+	};
-+	phy3: ethernet-phy@3 {
-+		reg = <0x3>;
-+	};
-+	tbi1: tbi-phy@1f {
-+		reg = <0x1f>;
-+		device_type = "tbi-phy";
-+	};
-+};
-+
-+&qspi {
-+	num-cs = <2>;
-+	status = "okay";
-+
-+	qflash0: s25fl128s@0 {
-+		compatible = "spansion,s25fl129p1";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+	};
-+};
-+
-+&sai2 {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	status = "okay";
-+};
-+
-+&dcu {
-+	display = <&display>;
-+	status = "okay";
-+
-+	display: display@0 {
-+		bits-per-pixel = <24>;
-+
-+		display-timings {
-+			native-mode = <&timing0>;
-+
-+			timing0: mode0 {
-+				clock-frequency = <25000000>;
-+				hactive = <640>;
-+				vactive = <480>;
-+				hback-porch = <80>;
-+				hfront-porch = <80>;
-+				vback-porch = <16>;
-+				vfront-porch = <16>;
-+				hsync-len = <12>;
-+				vsync-len = <2>;
-+				hsync-active = <1>;
-+				vsync-active = <1>;
-+			};
-+		};
-+	};
-+};

target/linux/layerscape/patches-4.14/703-dpaa2-l2switch-support-layerscape.patch

@@ -1,15 +1,15 @@
-From bdb1d42c9398eb14e997e026bd46602543a7ed03 Mon Sep 17 00:00:00 2001
+From 1c96e22d28e1b18c41c71e7d0948378561a6526f Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:26:16 +0800
-Subject: [PATCH 09/40] dpaa2-l2switch: support layerscape
-This is an integrated patch of dpaa2-l2switch for
- layerscape
+Date: Wed, 17 Apr 2019 18:58:29 +0800
+Subject: [PATCH] dpaa2-l2switch: support layerscape
 
+This is an integrated patch of dpaa2-l2switch for layerscape
+
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Greg Kroah-Hartman <[email protected]>
 Signed-off-by: Guanhua Gao <[email protected]>
 Signed-off-by: Ioana Ciornei <[email protected]>
 Signed-off-by: Razvan Stefanescu <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 ---
  drivers/staging/fsl-dpaa2/ethsw/Makefile      |   10 +
  drivers/staging/fsl-dpaa2/ethsw/README        |  106 ++

target/linux/layerscape/patches-4.14/704-dpaa2-mac-phy-support-layerscape.patch

@@ -1,28 +1,33 @@
-From 92cf25fe454dd42136e717ba679a9dba740db0e7 Mon Sep 17 00:00:00 2001
+From dd0cc8d0739a72ee5d85039a9ba7812383e8f555 Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:26:18 +0800
-Subject: [PATCH 10/40] dpaa2-mac-phy: support layerscape
-This is an integrated patch of dpaa2-mac-phy for
- layerscape
+Date: Wed, 17 Apr 2019 18:58:30 +0800
+Subject: [PATCH] dpaa2-mac-phy: support layerscape
+
+This is an integrated patch of dpaa2-mac-phy for layerscape
 
 Signed-off-by: Alex Marginean <[email protected]>
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Bogdan Hamciuc <[email protected]>
 Signed-off-by: Bogdan Purcareata <[email protected]>
+Signed-off-by: Catalin Neacsu <[email protected]>
 Signed-off-by: Constantin Tudor <[email protected]>
+Signed-off-by: Florin Chiculita <[email protected]>
+Signed-off-by: Ioana Ciornei <[email protected]>
 Signed-off-by: Ioana Radulescu <[email protected]>
 Signed-off-by: Itai Katz <[email protected]>
 Signed-off-by: J. German Rivera <[email protected]>
+Signed-off-by: Pankaj Bansal <[email protected]>
 Signed-off-by: Razvan Stefanescu <[email protected]>
 Signed-off-by: Stuart Yoder <[email protected]>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
 ---
  drivers/staging/fsl-dpaa2/mac/Kconfig     |  23 +
  drivers/staging/fsl-dpaa2/mac/Makefile    |  10 +
- drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h | 172 ++++++
- drivers/staging/fsl-dpaa2/mac/dpmac.c     | 619 ++++++++++++++++++++
- drivers/staging/fsl-dpaa2/mac/dpmac.h     | 342 +++++++++++
- drivers/staging/fsl-dpaa2/mac/mac.c       | 672 ++++++++++++++++++++++
- 6 files changed, 1838 insertions(+)
+ drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h | 196 ++++++
+ drivers/staging/fsl-dpaa2/mac/dpmac.c     | 689 ++++++++++++++++++
+ drivers/staging/fsl-dpaa2/mac/dpmac.h     | 374 ++++++++++
+ drivers/staging/fsl-dpaa2/mac/mac.c       | 817 ++++++++++++++++++++++
+ 6 files changed, 2109 insertions(+)
  create mode 100644 drivers/staging/fsl-dpaa2/mac/Kconfig
  create mode 100644 drivers/staging/fsl-dpaa2/mac/Makefile
  create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h
@@ -71,7 +76,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
 --- /dev/null
 +++ b/drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h
-@@ -0,0 +1,172 @@
+@@ -0,0 +1,196 @@
 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -110,9 +115,11 @@ Signed-off-by: Biwen Li <[email protected]>
 +#define DPMAC_VER_MAJOR				4
 +#define DPMAC_VER_MINOR				2
 +#define DPMAC_CMD_BASE_VERSION			1
++#define DPMAC_CMD_2ND_VERSION			2
 +#define DPMAC_CMD_ID_OFFSET			4
 +
 +#define DPMAC_CMD(id)	(((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_BASE_VERSION)
++#define DPMAC_CMD_V2(id) (((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_2ND_VERSION)
 +
 +/* Command IDs */
 +#define DPMAC_CMDID_CLOSE		DPMAC_CMD(0x800)
@@ -132,7 +139,9 @@ Signed-off-by: Biwen Li <[email protected]>
 +#define DPMAC_CMDID_CLEAR_IRQ_STATUS	DPMAC_CMD(0x017)
 +
 +#define DPMAC_CMDID_GET_LINK_CFG	DPMAC_CMD(0x0c2)
++#define DPMAC_CMDID_GET_LINK_CFG_V2	DPMAC_CMD_V2(0x0c2)
 +#define DPMAC_CMDID_SET_LINK_STATE	DPMAC_CMD(0x0c3)
++#define DPMAC_CMDID_SET_LINK_STATE_V2	DPMAC_CMD_V2(0x0c3)
 +#define DPMAC_CMDID_GET_COUNTER		DPMAC_CMD(0x0c4)
 +
 +#define DPMAC_CMDID_SET_PORT_MAC_ADDR	DPMAC_CMD(0x0c5)
@@ -213,8 +222,17 @@ Signed-off-by: Biwen Li <[email protected]>
 +	u32 rate;
 +};
 +
++struct dpmac_rsp_get_link_cfg_v2 {
++	u64 options;
++	u32 rate;
++	u32 pad;
++	u64 advertising;
++};
++
 +#define DPMAC_STATE_SIZE	1
 +#define DPMAC_STATE_SHIFT	0
++#define DPMAC_STATE_VALID_SIZE	1
++#define DPMAC_STATE_VALID_SHIFT	1
 +
 +struct dpmac_cmd_set_link_state {
 +	u64 options;
@@ -224,6 +242,17 @@ Signed-off-by: Biwen Li <[email protected]>
 +	u8 up;
 +};
 +
++struct dpmac_cmd_set_link_state_v2 {
++	u64 options;
++	u32 rate;
++	u32 pad0;
++	/* from lsb: up:1, state_valid:1 */
++	u8 state;
++	u8 pad1[7];
++	u64 supported;
++	u64 advertising;
++};
++
 +struct dpmac_cmd_get_counter {
 +	u8 type;
 +};
@@ -246,7 +275,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +#endif /* _FSL_DPMAC_CMD_H */
 --- /dev/null
 +++ b/drivers/staging/fsl-dpaa2/mac/dpmac.c
-@@ -0,0 +1,619 @@
+@@ -0,0 +1,689 @@
 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -741,6 +770,42 @@ Signed-off-by: Biwen Li <[email protected]>
 +}
 +
 +/**
++ * dpmac_get_link_cfg_v2() - Get Ethernet link configuration
++ * @mc_io:      Pointer to opaque I/O object
++ * @cmd_flags:  Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:      Token of DPMAC object
++ * @cfg:        Returned structure with the link configuration
++ *
++ * Return:      '0' on Success; Error code otherwise.
++ */
++int dpmac_get_link_cfg_v2(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  struct dpmac_link_cfg *cfg)
++{
++	struct dpmac_rsp_get_link_cfg_v2 *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err = 0;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG_V2,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpmac_rsp_get_link_cfg_v2 *)cmd.params;
++	cfg->options = le64_to_cpu(rsp_params->options);
++	cfg->rate = le32_to_cpu(rsp_params->rate);
++	cfg->advertising = le64_to_cpu(rsp_params->advertising);
++
++	return 0;
++}
++
++/**
 + * dpmac_set_link_state() - Set the Ethernet link status
 + * @mc_io:	Pointer to opaque I/O object
 + * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
@@ -764,7 +829,41 @@ Signed-off-by: Biwen Li <[email protected]>
 +	cmd_params = (struct dpmac_cmd_set_link_state *)cmd.params;
 +	cmd_params->options = cpu_to_le64(link_state->options);
 +	cmd_params->rate = cpu_to_le32(link_state->rate);
-+	cmd_params->up = dpmac_get_field(link_state->up, STATE);
++	dpmac_set_field(cmd_params->up, STATE, link_state->up);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpmac_set_link_state_v2() - Set the Ethernet link status
++ * @mc_io:      Pointer to opaque I/O object
++ * @cmd_flags:  Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:      Token of DPMAC object
++ * @link_state: Link state configuration
++ *
++ * Return:      '0' on Success; Error code otherwise.
++ */
++int dpmac_set_link_state_v2(struct fsl_mc_io *mc_io,
++			    u32 cmd_flags,
++			    u16 token,
++			    struct dpmac_link_state *link_state)
++{
++	struct dpmac_cmd_set_link_state_v2 *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE_V2,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpmac_cmd_set_link_state_v2 *)cmd.params;
++	cmd_params->options = cpu_to_le64(link_state->options);
++	cmd_params->rate = cpu_to_le32(link_state->rate);
++	dpmac_set_field(cmd_params->state, STATE, link_state->up);
++	dpmac_set_field(cmd_params->state, STATE_VALID,
++			link_state->state_valid);
++	cmd_params->supported = cpu_to_le64(link_state->supported);
++	cmd_params->advertising = cpu_to_le64(link_state->advertising);
 +
 +	/* send command to mc*/
 +	return mc_send_command(mc_io, &cmd);
@@ -868,7 +967,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +}
 --- /dev/null
 +++ b/drivers/staging/fsl-dpaa2/mac/dpmac.h
-@@ -0,0 +1,342 @@
+@@ -0,0 +1,374 @@
 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -1073,13 +1172,29 @@ Signed-off-by: Biwen Li <[email protected]>
 +#define DPMAC_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
 +
 +/**
++ * Advertised link speeds
++ */
++#define DPMAC_ADVERTISED_10BASET_FULL		0x0000000000000001ULL
++#define DPMAC_ADVERTISED_100BASET_FULL		0x0000000000000002ULL
++#define DPMAC_ADVERTISED_1000BASET_FULL		0x0000000000000004ULL
++#define DPMAC_ADVERTISED_10000BASET_FULL	0x0000000000000010ULL
++#define DPMAC_ADVERTISED_2500BASEX_FULL		0x0000000000000020ULL
++
++/**
++ * Advertise auto-negotiation enable
++ */
++#define DPMAC_ADVERTISED_AUTONEG		0x0000000000000008ULL
++
++/**
 + * struct dpmac_link_cfg - Structure representing DPMAC link configuration
 + * @rate: Link's rate - in Mbps
 + * @options: Enable/Disable DPMAC link cfg features (bitmap)
++ * @advertising: Speeds that are advertised for autoneg (bitmap)
 + */
 +struct dpmac_link_cfg {
 +	u32 rate;
 +	u64 options;
++	u64 advertising;
 +};
 +
 +int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
@@ -1087,16 +1202,27 @@ Signed-off-by: Biwen Li <[email protected]>
 +		       u16 token,
 +		       struct dpmac_link_cfg *cfg);
 +
++int dpmac_get_link_cfg_v2(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  struct dpmac_link_cfg *cfg);
++
 +/**
 + * struct dpmac_link_state - DPMAC link configuration request
 + * @rate: Rate in Mbps
 + * @options: Enable/Disable DPMAC link cfg features (bitmap)
 + * @up: Link state
++ * @state_valid: Ignore/Update the state of the link
++ * @supported: Speeds capability of the phy (bitmap)
++ * @advertising: Speeds that are advertised for autoneg (bitmap)
 + */
 +struct dpmac_link_state {
 +	u32 rate;
 +	u64 options;
 +	int up;
++	int state_valid;
++	u64 supported;
++	u64 advertising;
 +};
 +
 +int dpmac_set_link_state(struct fsl_mc_io *mc_io,
@@ -1104,6 +1230,11 @@ Signed-off-by: Biwen Li <[email protected]>
 +			 u16 token,
 +			 struct dpmac_link_state *link_state);
 +
++int dpmac_set_link_state_v2(struct fsl_mc_io *mc_io,
++			    u32 cmd_flags,
++			    u16 token,
++			    struct dpmac_link_state *link_state);
++
 +/**
 + * enum dpmac_counter - DPMAC counter types
 + * @DPMAC_CNT_ING_FRAME_64: counts 64-bytes frames, good or bad.
@@ -1213,8 +1344,9 @@ Signed-off-by: Biwen Li <[email protected]>
 +#endif /* __FSL_DPMAC_H */
 --- /dev/null
 +++ b/drivers/staging/fsl-dpaa2/mac/mac.c
-@@ -0,0 +1,672 @@
+@@ -0,0 +1,817 @@
 +/* Copyright 2015 Freescale Semiconductor Inc.
++ * Copyright 2018 NXP
 + *
 + * Redistribution and use in source and binary forms, with or without
 + * modification, are permitted provided that the following conditions are met:
@@ -1272,6 +1404,8 @@ Signed-off-by: Biwen Li <[email protected]>
 +	struct fsl_mc_device		*mc_dev;
 +	struct dpmac_attr		attr;
 +	struct dpmac_link_state		old_state;
++	u16				dpmac_ver_major;
++	u16				dpmac_ver_minor;
 +};
 +
 +/* TODO: fix the 10G modes, mapping can't be right:
@@ -1292,8 +1426,62 @@ Signed-off-by: Biwen Li <[email protected]>
 +	PHY_INTERFACE_MODE_QSGMII,	/* DPMAC_ETH_IF_QSGMII */
 +	PHY_INTERFACE_MODE_XGMII,	/* DPMAC_ETH_IF_XAUI */
 +	PHY_INTERFACE_MODE_XGMII,	/* DPMAC_ETH_IF_XFI */
++	PHY_INTERFACE_MODE_XGMII,        /* DPMAC_ETH_IF_CAUI */
++	PHY_INTERFACE_MODE_XGMII,       /* DPMAC_ETH_IF_1000BASEX */
++	PHY_INTERFACE_MODE_XGMII,       /* DPMAC_ETH_IF_USXGMII */
 +};
 +
++static int cmp_dpmac_ver(struct dpaa2_mac_priv *priv,
++			 u16 ver_major, u16 ver_minor)
++{
++	if (priv->dpmac_ver_major == ver_major)
++		return priv->dpmac_ver_minor - ver_minor;
++	return priv->dpmac_ver_major - ver_major;
++}
++
++#define DPMAC_LINK_AUTONEG_VER_MAJOR		4
++#define DPMAC_LINK_AUTONEG_VER_MINOR		3
++
++struct dpaa2_mac_link_mode_map {
++	u64 dpmac_lm;
++	u64 ethtool_lm;
++};
++
++static const struct dpaa2_mac_link_mode_map dpaa2_mac_lm_map[] = {
++	{DPMAC_ADVERTISED_10BASET_FULL, ETHTOOL_LINK_MODE_10baseT_Full_BIT},
++	{DPMAC_ADVERTISED_100BASET_FULL, ETHTOOL_LINK_MODE_100baseT_Full_BIT},
++	{DPMAC_ADVERTISED_1000BASET_FULL, ETHTOOL_LINK_MODE_1000baseT_Full_BIT},
++	{DPMAC_ADVERTISED_10000BASET_FULL, ETHTOOL_LINK_MODE_10000baseT_Full_BIT},
++	{DPMAC_ADVERTISED_2500BASEX_FULL, ETHTOOL_LINK_MODE_2500baseX_Full_BIT},
++	{DPMAC_ADVERTISED_AUTONEG, ETHTOOL_LINK_MODE_Autoneg_BIT},
++};
++
++static void link_mode_dpmac2phydev(u64 dpmac_lm, u32 *phydev_lm)
++{
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dpaa2_mac_lm_map); i++) {
++		if (dpmac_lm & dpaa2_mac_lm_map[i].dpmac_lm)
++			__set_bit(dpaa2_mac_lm_map[i].ethtool_lm, mask);
++	}
++
++	ethtool_convert_link_mode_to_legacy_u32(phydev_lm, mask);
++}
++
++static void link_mode_phydev2dpmac(u32 phydev_lm, u64 *dpni_lm)
++{
++	unsigned long lm;
++	int i;
++
++	ethtool_convert_legacy_u32_to_link_mode(&lm, phydev_lm);
++
++	for (i = 0; i < ARRAY_SIZE(dpaa2_mac_lm_map); i++) {
++		if (test_bit(dpaa2_mac_lm_map[i].ethtool_lm, &lm))
++			*dpni_lm |= dpaa2_mac_lm_map[i].dpmac_lm;
++	}
++}
++
 +static void dpaa2_mac_link_changed(struct net_device *netdev)
 +{
 +	struct phy_device	*phydev;
@@ -1313,6 +1501,12 @@ Signed-off-by: Biwen Li <[email protected]>
 +		if (phydev->autoneg)
 +			state.options |= DPMAC_LINK_OPT_AUTONEG;
 +
++		if (phydev->pause && (phydev->advertising & ADVERTISED_Pause))
++			state.options |= DPMAC_LINK_OPT_PAUSE;
++		if (phydev->pause &&
++		    (phydev->advertising & ADVERTISED_Asym_Pause))
++			state.options |= DPMAC_LINK_OPT_ASYM_PAUSE;
++
 +		netif_carrier_on(netdev);
 +	} else {
 +		netif_carrier_off(netdev);
@@ -1325,11 +1519,18 @@ Signed-off-by: Biwen Li <[email protected]>
 +		phy_print_status(phydev);
 +	}
 +
-+	/* We must interrogate MC at all times, because we don't know
-+	 * when and whether a potential DPNI may have read the link state.
-+	 */
-+	err = dpmac_set_link_state(priv->mc_dev->mc_io, 0,
-+				   priv->mc_dev->mc_handle, &state);
++	if (cmp_dpmac_ver(priv, DPMAC_LINK_AUTONEG_VER_MAJOR,
++			  DPMAC_LINK_AUTONEG_VER_MINOR) < 0) {
++		err = dpmac_set_link_state(priv->mc_dev->mc_io, 0,
++					   priv->mc_dev->mc_handle, &state);
++	} else {
++		link_mode_phydev2dpmac(phydev->supported, &state.supported);
++		link_mode_phydev2dpmac(phydev->advertising, &state.advertising);
++		state.state_valid = 1;
++
++		err = dpmac_set_link_state_v2(priv->mc_dev->mc_io, 0,
++					      priv->mc_dev->mc_handle, &state);
++	}
 +	if (unlikely(err))
 +		dev_err(&priv->mc_dev->dev, "dpmac_set_link_state: %d\n", err);
 +}
@@ -1367,6 +1568,18 @@ Signed-off-by: Biwen Li <[email protected]>
 +	return NETDEV_TX_OK;
 +}
 +
++static void dpaa2_mac_get_drvinfo(struct net_device *net_dev,
++				  struct ethtool_drvinfo *drvinfo)
++{
++	struct dpaa2_mac_priv *priv = netdev_priv(net_dev);
++
++	strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
++	snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
++		 "%u.%u", priv->dpmac_ver_major, priv->dpmac_ver_minor);
++	strlcpy(drvinfo->bus_info, dev_name(net_dev->dev.parent->parent),
++		sizeof(drvinfo->bus_info));
++}
++
 +static int dpaa2_mac_get_link_ksettings(struct net_device *netdev,
 +					struct ethtool_link_ksettings *ks)
 +{
@@ -1536,6 +1749,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +};
 +
 +static const struct ethtool_ops dpaa2_mac_ethtool_ops = {
++	.get_drvinfo		= &dpaa2_mac_get_drvinfo,
 +	.get_link_ksettings	= &dpaa2_mac_get_link_ksettings,
 +	.set_link_ksettings	= &dpaa2_mac_set_link_ksettings,
 +	.get_strings		= &dpaa2_mac_get_strings,
@@ -1555,11 +1769,30 @@ Signed-off-by: Biwen Li <[email protected]>
 +	phydev->speed = cfg->rate;
 +	phydev->duplex  = !!(cfg->options & DPMAC_LINK_OPT_HALF_DUPLEX);
 +
++	if (cfg->advertising != 0) {
++		phydev->advertising = 0;
++		link_mode_dpmac2phydev(cfg->advertising, &phydev->advertising);
++	}
++
++	if (phydev->supported & SUPPORTED_Pause) {
++		if (cfg->options & DPMAC_LINK_OPT_PAUSE)
++			phydev->advertising |= ADVERTISED_Pause;
++		else
++			phydev->advertising &= ~ADVERTISED_Pause;
++	}
++
++	if (phydev->supported & SUPPORTED_Asym_Pause) {
++		if (cfg->options & DPMAC_LINK_OPT_ASYM_PAUSE)
++			phydev->advertising |= ADVERTISED_Asym_Pause;
++		else
++			phydev->advertising &= ~ADVERTISED_Asym_Pause;
++	}
++
 +	if (cfg->options & DPMAC_LINK_OPT_AUTONEG) {
-+		phydev->autoneg = 1;
++		phydev->autoneg = AUTONEG_ENABLE;
 +		phydev->advertising |= ADVERTISED_Autoneg;
 +	} else {
-+		phydev->autoneg = 0;
++		phydev->autoneg = AUTONEG_DISABLE;
 +		phydev->advertising &= ~ADVERTISED_Autoneg;
 +	}
 +
@@ -1571,7 +1804,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	struct device *dev = (struct device *)arg;
 +	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
 +	struct dpaa2_mac_priv *priv = dev_get_drvdata(dev);
-+	struct dpmac_link_cfg link_cfg;
++	struct dpmac_link_cfg link_cfg = { 0 };
 +	u32 status;
 +	int err;
 +
@@ -1582,8 +1815,14 @@ Signed-off-by: Biwen Li <[email protected]>
 +
 +	/* DPNI-initiated link configuration; 'ifconfig up' also calls this */
 +	if (status & DPMAC_IRQ_EVENT_LINK_CFG_REQ) {
-+		err = dpmac_get_link_cfg(mc_dev->mc_io, 0, mc_dev->mc_handle,
-+					 &link_cfg);
++		if (cmp_dpmac_ver(priv, DPMAC_LINK_AUTONEG_VER_MAJOR,
++				  DPMAC_LINK_AUTONEG_VER_MINOR) < 0)
++			err = dpmac_get_link_cfg(mc_dev->mc_io, 0,
++						 mc_dev->mc_handle, &link_cfg);
++		else
++			err = dpmac_get_link_cfg_v2(mc_dev->mc_io, 0,
++						    mc_dev->mc_handle,
++						    &link_cfg);
 +		if (unlikely(err))
 +			goto out;
 +
@@ -1682,7 +1921,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	struct dpaa2_mac_priv	*priv = NULL;
 +	struct device_node	*phy_node, *dpmac_node;
 +	struct net_device	*netdev;
-+	phy_interface_t		if_mode;
++	int			if_mode;
 +	int			err = 0;
 +
 +	dev = &mc_dev->dev;
@@ -1723,6 +1962,21 @@ Signed-off-by: Biwen Li <[email protected]>
 +		goto err_free_mcp;
 +	}
 +
++	err = dpmac_get_api_version(mc_dev->mc_io, 0, &priv->dpmac_ver_major,
++				    &priv->dpmac_ver_minor);
++	if (err) {
++		dev_err(dev, "dpmac_get_api_version failed\n");
++		goto err_version;
++	}
++
++	if (cmp_dpmac_ver(priv, DPMAC_VER_MAJOR, DPMAC_VER_MINOR) < 0) {
++		dev_err(dev, "DPMAC version %u.%u lower than supported %u.%u\n",
++			priv->dpmac_ver_major, priv->dpmac_ver_minor,
++			DPMAC_VER_MAJOR, DPMAC_VER_MINOR);
++		err = -ENOTSUPP;
++		goto err_version;
++	}
++
 +	err = dpmac_get_attributes(mc_dev->mc_io, 0,
 +				   mc_dev->mc_handle, &priv->attr);
 +	if (err) {
@@ -1761,12 +2015,12 @@ Signed-off-by: Biwen Li <[email protected]>
 +	}
 +#endif /* CONFIG_FSL_DPAA2_MAC_NETDEVS */
 +
-+	/* probe the PHY as a fixed-link if there's a phy-handle defined
-+	 * in the device tree
-+	 */
-+	phy_node = of_parse_phandle(dpmac_node, "phy-handle", 0);
-+	if (!phy_node) {
-+		goto probe_fixed_link;
++	/* get the interface mode from the dpmac of node or from the MC attributes */
++	if_mode = of_get_phy_mode(dpmac_node);
++	if (if_mode >= 0) {
++		dev_dbg(dev, "\tusing if mode %s for eth_if %d\n",
++			phy_modes(if_mode), priv->attr.eth_if);
++		goto link_type;
 +	}
 +
 +	if (priv->attr.eth_if < ARRAY_SIZE(dpaa2_mac_iface_mode)) {
@@ -1774,8 +2028,20 @@ Signed-off-by: Biwen Li <[email protected]>
 +		dev_dbg(dev, "\tusing if mode %s for eth_if %d\n",
 +			phy_modes(if_mode), priv->attr.eth_if);
 +	} else {
-+		dev_warn(dev, "Unexpected interface mode %d, will probe as fixed link\n",
-+			 priv->attr.eth_if);
++		dev_err(dev, "Unexpected interface mode %d\n",
++			priv->attr.eth_if);
++		err = -EINVAL;
++		goto err_no_if_mode;
++	}
++
++link_type:
++	/* probe the PHY as fixed-link if the DPMAC attribute indicates so */
++	if (priv->attr.link_type == DPMAC_LINK_TYPE_FIXED)
++		goto probe_fixed_link;
++
++	/* or if there's no phy-handle defined in the device tree */
++	phy_node = of_parse_phandle(dpmac_node, "phy-handle", 0);
++	if (!phy_node) {
 +		goto probe_fixed_link;
 +	}
 +
@@ -1812,6 +2078,14 @@ Signed-off-by: Biwen Li <[email protected]>
 +			err = -EFAULT;
 +			goto err_no_phy;
 +		}
++
++		err = phy_connect_direct(netdev, netdev->phydev,
++					 &dpaa2_mac_link_changed, if_mode);
++		if (err) {
++			dev_err(dev, "error trying to connect to PHY\n");
++			goto err_no_phy;
++		}
++
 +		dev_info(dev, "Registered fixed PHY.\n");
 +	}
 +
@@ -1819,6 +2093,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +
 +	return 0;
 +
++err_no_if_mode:
 +err_defer:
 +err_no_phy:
 +#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
@@ -1826,6 +2101,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +err_free_irq:
 +#endif
 +	teardown_irqs(mc_dev);
++err_version:
 +err_close:
 +	dpmac_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
 +err_free_mcp:

target/linux/layerscape/patches-4.14/705-dpaa2-rtc-support-layerscape.patch

@@ -1,30 +1,34 @@
-From 579f1f6767b1008c6e5ccc2b029acbb56002ed8b Mon Sep 17 00:00:00 2001
+From 802238feea29ddfb765fc0c162e0de34920cd58d Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:26:20 +0800
-Subject: [PATCH 11/40] dpaa2-rtc: support layerscape
+Date: Wed, 17 Apr 2019 18:58:31 +0800
+Subject: [PATCH] dpaa2-rtc: support layerscape
+
 This is an integrated patch of dpaa2-rtc for layerscape
 
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Catalin Horghidan <[email protected]>
+Signed-off-by: Greg Kroah-Hartman <[email protected]>
 Signed-off-by: Yangbo Lu <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 ---
  drivers/staging/fsl-dpaa2/rtc/Makefile    |  10 +
  drivers/staging/fsl-dpaa2/rtc/dprtc-cmd.h | 160 +++++
  drivers/staging/fsl-dpaa2/rtc/dprtc.c     | 746 ++++++++++++++++++++++
  drivers/staging/fsl-dpaa2/rtc/dprtc.h     | 172 +++++
- drivers/staging/fsl-dpaa2/rtc/rtc.c       | 242 +++++++
- 5 files changed, 1330 insertions(+)
+ drivers/staging/fsl-dpaa2/rtc/rtc.c       | 240 +++++++
+ drivers/staging/fsl-dpaa2/rtc/rtc.h       |  14 +
+ 6 files changed, 1342 insertions(+)
  create mode 100644 drivers/staging/fsl-dpaa2/rtc/Makefile
  create mode 100644 drivers/staging/fsl-dpaa2/rtc/dprtc-cmd.h
  create mode 100644 drivers/staging/fsl-dpaa2/rtc/dprtc.c
  create mode 100644 drivers/staging/fsl-dpaa2/rtc/dprtc.h
  create mode 100644 drivers/staging/fsl-dpaa2/rtc/rtc.c
+ create mode 100644 drivers/staging/fsl-dpaa2/rtc/rtc.h
 
 --- /dev/null
 +++ b/drivers/staging/fsl-dpaa2/rtc/Makefile
 @@ -0,0 +1,10 @@
 +
-+obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += dpaa2-rtc.o
++obj-$(CONFIG_FSL_DPAA2_PTP_CLOCK) += dpaa2-rtc.o
 +
 +dpaa2-rtc-objs := rtc.o dprtc.o
 +
@@ -1122,7 +1126,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +#endif /* __FSL_DPRTC_H */
 --- /dev/null
 +++ b/drivers/staging/fsl-dpaa2/rtc/rtc.c
-@@ -0,0 +1,242 @@
+@@ -0,0 +1,240 @@
 +/* Copyright 2013-2015 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -1160,8 +1164,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +
 +#include <linux/fsl/mc.h>
 +
-+#include "dprtc.h"
-+#include "dprtc-cmd.h"
++#include "rtc.h"
 +
 +#define N_EXT_TS	2
 +
@@ -1276,7 +1279,6 @@ Signed-off-by: Biwen Li <[email protected]>
 +{
 +	struct device		*dev;
 +	int			err = 0;
-+	int			dpaa2_phc_index;
 +	u32			tmr_add = 0;
 +
 +	if (!mc_dev)
@@ -1365,3 +1367,20 @@ Signed-off-by: Biwen Li <[email protected]>
 +
 +MODULE_LICENSE("GPL");
 +MODULE_DESCRIPTION("DPAA2 RTC (PTP 1588 clock) driver (prototype)");
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/rtc/rtc.h
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2018 NXP
++ */
++
++#ifndef __RTC_H
++#define __RTC_H
++
++#include "dprtc.h"
++#include "dprtc-cmd.h"
++
++extern int dpaa2_phc_index;
++
++#endif

target/linux/layerscape/patches-4.14/708-mc-bus-support-layerscape.patch

@@ -1,10 +1,15 @@
-From 2aaf8e8caef3ec4c2c155421f62f983892c49387 Mon Sep 17 00:00:00 2001
+From ab58c737bc723f52e787e1767bbbf0fcbe39a27b Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Fri, 16 Nov 2018 12:20:04 +0800
-Subject: [PATCH 13/39] mc-bus: support layerscape
+Date: Wed, 17 Apr 2019 18:58:43 +0800
+Subject: [PATCH] mc-bus: support layerscape
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
 This is an integrated patch of mc-bus for layerscape
 
 Signed-off-by: Bharat Bhushan <[email protected]>
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Bogdan Purcareata <[email protected]>
 Signed-off-by: Cristian Sovaiala <[email protected]>
 Signed-off-by: Greg Kroah-Hartman <[email protected]>
@@ -18,9 +23,8 @@ Signed-off-by: Lijun Pan <[email protected]>
 Signed-off-by: Nipun Gupta <[email protected]>
 Signed-off-by: Radu Alexe <[email protected]>
 Signed-off-by: Razvan Stefanescu <[email protected]>
+Signed-off-by: Roy Pledge <[email protected]>
 Signed-off-by: Stuart Yoder <[email protected]>
-Signed-off-by: Stuart Yoder <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 ---
  drivers/bus/Kconfig                           |    2 +
  drivers/bus/Makefile                          |    4 +
@@ -30,23 +34,21 @@ Signed-off-by: Biwen Li <[email protected]>
  .../fsl-mc/bus => bus/fsl-mc}/dpcon.c         |  103 +-
  drivers/bus/fsl-mc/dpmcp.c                    |   99 ++
  .../fsl-mc/bus => bus/fsl-mc}/dprc-driver.c   |   96 +-
- .../{staging/fsl-mc/bus => bus/fsl-mc}/dprc.c |  288 +----
- .../bus => bus/fsl-mc}/fsl-mc-allocator.c     |  112 +-
- .../fsl-mc/bus => bus/fsl-mc}/fsl-mc-bus.c    |  305 ++++-
+ .../{staging/fsl-mc/bus => bus/fsl-mc}/dprc.c |  289 +----
+ .../bus => bus/fsl-mc}/fsl-mc-allocator.c     |  123 +-
+ .../fsl-mc/bus => bus/fsl-mc}/fsl-mc-bus.c    |  322 +++++-
  .../fsl-mc/bus => bus/fsl-mc}/fsl-mc-msi.c    |   16 +-
  drivers/bus/fsl-mc/fsl-mc-private.h           |  223 ++++
  drivers/bus/fsl-mc/fsl-mc-restool.c           |  219 ++++
- .../fsl-mc/bus => bus/fsl-mc}/mc-io.c         |   36 +-
+ .../fsl-mc/bus => bus/fsl-mc}/mc-io.c         |   51 +-
  .../fsl-mc/bus => bus/fsl-mc}/mc-sys.c        |   33 +-
  drivers/irqchip/Kconfig                       |    6 +
  drivers/irqchip/Makefile                      |    1 +
  drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c   |   98 ++
- drivers/staging/fsl-dpaa2/ethernet/README     |    2 +-
  .../staging/fsl-dpaa2/ethernet/dpaa2-eth.c    |    2 +-
  .../staging/fsl-dpaa2/ethernet/dpaa2-eth.h    |    3 +-
  drivers/staging/fsl-dpaa2/ethernet/dpni.c     |    2 +-
- drivers/staging/fsl-mc/TODO                   |   18 -
- drivers/staging/fsl-mc/bus/Kconfig            |   16 +-
+ drivers/staging/fsl-mc/bus/Kconfig            |   15 +-
  drivers/staging/fsl-mc/bus/Makefile           |   13 -
  drivers/staging/fsl-mc/bus/dpio/dpio-driver.c |    2 +-
  .../staging/fsl-mc/bus/dpio/dpio-service.c    |    2 +-
@@ -57,9 +59,9 @@ Signed-off-by: Biwen Li <[email protected]>
  drivers/staging/fsl-mc/bus/dprc-cmd.h         |  451 --------
  drivers/staging/fsl-mc/bus/dprc.h             |  268 -----
  .../fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c    |    1 +
- include/linux/fsl/mc.h                        | 1020 +++++++++++++++++
+ include/linux/fsl/mc.h                        | 1029 +++++++++++++++++
  include/uapi/linux/fsl_mc.h                   |   31 +
- 37 files changed, 2255 insertions(+), 1546 deletions(-)
+ 35 files changed, 2302 insertions(+), 1531 deletions(-)
  create mode 100644 drivers/bus/fsl-mc/Kconfig
  create mode 100644 drivers/bus/fsl-mc/Makefile
  rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/dpbp.c (67%)
@@ -68,14 +70,13 @@ Signed-off-by: Biwen Li <[email protected]>
  rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/dprc-driver.c (93%)
  rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/dprc.c (68%)
  rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-allocator.c (84%)
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-bus.c (76%)
+ rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-bus.c (75%)
  rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-msi.c (96%)
  create mode 100644 drivers/bus/fsl-mc/fsl-mc-private.h
  create mode 100644 drivers/bus/fsl-mc/fsl-mc-restool.c
  rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/mc-io.c (89%)
  rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/mc-sys.c (90%)
  create mode 100644 drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c
- delete mode 100644 drivers/staging/fsl-mc/TODO
  delete mode 100644 drivers/staging/fsl-mc/bus/dpmcp-cmd.h
  delete mode 100644 drivers/staging/fsl-mc/bus/dpmcp.h
  delete mode 100644 drivers/staging/fsl-mc/bus/dpmng-cmd.h
@@ -3618,7 +3619,7 @@ Signed-off-by: Biwen Li <[email protected]>
 -}
 --- /dev/null
 +++ b/drivers/bus/fsl-mc/dprc.c
-@@ -0,0 +1,575 @@
+@@ -0,0 +1,576 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 +/*
 + * Copyright 2013-2016 Freescale Semiconductor Inc.
@@ -4123,10 +4124,11 @@ Signed-off-by: Biwen Li <[email protected]>
 +
 +	/* retrieve response parameters */
 +	rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params;
-+	region_desc->base_offset = le32_to_cpu(rsp_params->base_addr);
++	region_desc->base_offset = le32_to_cpu(rsp_params->base_offset);
 +	region_desc->size = le32_to_cpu(rsp_params->size);
 +	region_desc->type = rsp_params->type;
 +	region_desc->flags = le32_to_cpu(rsp_params->flags);
++	region_desc->base_address = le64_to_cpu(rsp_params->base_addr);
 +
 +	return 0;
 +}
@@ -4862,7 +4864,7 @@ Signed-off-by: Biwen Li <[email protected]>
 -}
 --- /dev/null
 +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c
-@@ -0,0 +1,655 @@
+@@ -0,0 +1,666 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * fsl-mc object allocator driver
@@ -5160,6 +5162,14 @@ Signed-off-by: Biwen Li <[email protected]>
 +	if (!mc_adev)
 +		goto error;
 +
++	mc_adev->consumer_link = device_link_add(&mc_dev->dev,
++						 &mc_adev->dev,
++						 DL_FLAG_AUTOREMOVE_CONSUMER);
++	if (!mc_adev->consumer_link) {
++		error = -EINVAL;
++		goto error;
++	}
++
 +	*new_mc_adev = mc_adev;
 +	return 0;
 +error:
@@ -5186,6 +5196,9 @@ Signed-off-by: Biwen Li <[email protected]>
 +		return;
 +
 +	fsl_mc_resource_free(resource);
++
++	device_link_del(mc_adev->consumer_link);
++	mc_adev->consumer_link = NULL;
 +}
 +EXPORT_SYMBOL_GPL(fsl_mc_object_free);
 +
@@ -6423,7 +6436,7 @@ Signed-off-by: Biwen Li <[email protected]>
 -postcore_initcall(fsl_mc_bus_driver_init);
 --- /dev/null
 +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c
-@@ -0,0 +1,1139 @@
+@@ -0,0 +1,1148 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Freescale Management Complex (MC) bus driver
@@ -7054,10 +7067,17 @@ Signed-off-by: Biwen Li <[email protected]>
 +				"dprc_get_obj_region() failed: %d\n", error);
 +			goto error_cleanup_regions;
 +		}
-+
-+		error = translate_mc_addr(mc_dev, mc_region_type,
-+					  region_desc.base_offset,
-+					  &regions[i].start);
++		/* Older MC only returned region offset and no base address
++		 * If base address is in the region_desc use it otherwise
++		 * revert to old mechanism
++		 */
++		if (region_desc.base_address)
++			regions[i].start = region_desc.base_address +
++					   region_desc.base_offset;
++		else
++			error = translate_mc_addr(mc_dev, mc_region_type,
++						  region_desc.base_offset,
++						  &regions[i].start);
 +		if (error < 0) {
 +			dev_err(parent_dev,
 +				"Invalid MC offset: %#x (for %s.%d\'s region %d)\n",
@@ -7071,6 +7091,8 @@ Signed-off-by: Biwen Li <[email protected]>
 +		regions[i].flags = IORESOURCE_IO;
 +		if (region_desc.flags & DPRC_REGION_CACHEABLE)
 +			regions[i].flags |= IORESOURCE_CACHEABLE;
++		if (region_desc.flags & DPRC_REGION_SHAREABLE)
++			regions[i].flags |= IORESOURCE_MEM;
 +	}
 +
 +	mc_dev->regions = regions;
@@ -8884,7 +8906,7 @@ Signed-off-by: Biwen Li <[email protected]>
 -EXPORT_SYMBOL_GPL(fsl_mc_portal_reset);
 --- /dev/null
 +++ b/drivers/bus/fsl-mc/mc-io.c
-@@ -0,0 +1,268 @@
+@@ -0,0 +1,281 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 +/*
 + * Copyright 2013-2016 Freescale Semiconductor Inc.
@@ -9057,7 +9079,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	struct fsl_mc_resource *resource = NULL;
 +	struct fsl_mc_io *mc_io = NULL;
 +
-+	if (mc_dev->flags & FSL_MC_IS_DPRC) {
++	if (fsl_mc_is_root_dprc(&mc_dev->dev)) {
 +		mc_bus_dev = mc_dev;
 +	} else {
 +		if (!dev_is_fsl_mc(mc_dev->dev.parent))
@@ -9096,9 +9118,19 @@ Signed-off-by: Biwen Li <[email protected]>
 +	if (error < 0)
 +		goto error_cleanup_resource;
 +
++	dpmcp_dev->consumer_link = device_link_add(&mc_dev->dev,
++						   &dpmcp_dev->dev,
++						   DL_FLAG_AUTOREMOVE_CONSUMER);
++	if (!dpmcp_dev->consumer_link) {
++		error = -EINVAL;
++		goto error_cleanup_mc_io;
++	}
++
 +	*new_mc_io = mc_io;
 +	return 0;
 +
++error_cleanup_mc_io:
++	fsl_destroy_mc_io(mc_io);
 +error_cleanup_resource:
 +	fsl_mc_resource_free(resource);
 +	return error;
@@ -9131,6 +9163,9 @@ Signed-off-by: Biwen Li <[email protected]>
 +
 +	fsl_destroy_mc_io(mc_io);
 +	fsl_mc_resource_free(resource);
++
++	device_link_del(dpmcp_dev->consumer_link);
++	dpmcp_dev->consumer_link = NULL;
 +}
 +EXPORT_SYMBOL_GPL(fsl_mc_portal_free);
 +
@@ -9878,20 +9913,9 @@ Signed-off-by: Biwen Li <[email protected]>
 +}
 +
 +early_initcall(its_fsl_mc_msi_init);
---- a/drivers/staging/fsl-dpaa2/ethernet/README
-+++ b/drivers/staging/fsl-dpaa2/ethernet/README
-@@ -36,7 +36,7 @@ are treated as internal resources of oth
- 
- For a more detailed description of the DPAA2 architecture and its object
- abstractions see:
--	drivers/staging/fsl-mc/README.txt
-+	Documentation/networking/dpaa2/overview.rst
- 
- Each Linux net device is built on top of a Datapath Network Interface (DPNI)
- object and uses Buffer Pools (DPBPs), I/O Portals (DPIOs) and Concentrators
 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
 +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
-@@ -43,7 +43,7 @@
+@@ -16,7 +16,7 @@
  #include <linux/filter.h>
  #include <linux/atomic.h>
  #include <net/sock.h>
@@ -9902,11 +9926,12 @@ Signed-off-by: Biwen Li <[email protected]>
  
 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
 +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
-@@ -36,11 +36,10 @@
+@@ -9,12 +9,11 @@
  #include <linux/dcbnl.h>
  #include <linux/netdevice.h>
  #include <linux/if_vlan.h>
 +#include <linux/fsl/mc.h>
+ #include <linux/filter.h>
  
  #include "../../fsl-mc/include/dpaa2-io.h"
  #include "../../fsl-mc/include/dpaa2-fd.h"
@@ -9917,7 +9942,7 @@ Signed-off-by: Biwen Li <[email protected]>
  
 --- a/drivers/staging/fsl-dpaa2/ethernet/dpni.c
 +++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.c
-@@ -32,7 +32,7 @@
+@@ -4,7 +4,7 @@
   */
  #include <linux/kernel.h>
  #include <linux/errno.h>
@@ -9926,30 +9951,9 @@ Signed-off-by: Biwen Li <[email protected]>
  #include "dpni.h"
  #include "dpni-cmd.h"
  
---- a/drivers/staging/fsl-mc/TODO
-+++ /dev/null
-@@ -1,18 +0,0 @@
--* Add at least one device driver for a DPAA2 object (child device of the
--  fsl-mc bus).  Most likely candidate for this is adding DPAA2 Ethernet
--  driver support, which depends on drivers for several objects: DPNI,
--  DPIO, DPMAC.  Other pre-requisites include:
--
--     * MC firmware uprev.  The MC firmware upon which the fsl-mc
--       bus driver and DPAA2 object drivers are based is continuing
--       to evolve, so minor updates are needed to keep in sync with binary
--       interface changes to the MC.
--
--* Cleanup
--
--Please send any patches to Greg Kroah-Hartman <[email protected]>,
[email protected], [email protected],
[email protected]
--
--[1] https://lkml.org/lkml/2015/7/9/93
--[2] https://lkml.org/lkml/2015/7/7/712
 --- a/drivers/staging/fsl-mc/bus/Kconfig
 +++ b/drivers/staging/fsl-mc/bus/Kconfig
-@@ -5,16 +5,6 @@
+@@ -5,15 +5,6 @@
  # Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  #
  
@@ -9962,11 +9966,10 @@ Signed-off-by: Biwen Li <[email protected]>
 -	  architecture.  The fsl-mc bus driver handles discovery of
 -	  DPAA2 objects (which are represented as Linux devices) and
 -	  binding objects to drivers.
--
+ 
  config FSL_MC_DPIO
          tristate "QorIQ DPAA2 DPIO driver"
-         depends on FSL_MC_BUS
-@@ -24,3 +14,9 @@ config FSL_MC_DPIO
+@@ -24,3 +15,9 @@ config FSL_MC_DPIO
  	  other DPAA2 objects. This driver does not expose the DPIO
  	  objects individually, but groups them under a service layer
  	  API.
@@ -10000,9 +10003,9 @@ Signed-off-by: Biwen Li <[email protected]>
  obj-$(CONFIG_FSL_MC_DPIO) += dpio/
 --- a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
-@@ -14,7 +14,7 @@
- #include <linux/dma-mapping.h>
+@@ -15,7 +15,7 @@
  #include <linux/delay.h>
+ #include <linux/io.h>
  
 -#include "../../include/mc.h"
 +#include <linux/fsl/mc.h>
@@ -11005,7 +11008,7 @@ Signed-off-by: Biwen Li <[email protected]>
  static struct irq_chip its_msi_irq_chip = {
 --- /dev/null
 +++ b/include/linux/fsl/mc.h
-@@ -0,0 +1,1020 @@
+@@ -0,0 +1,1029 @@
 +/* SPDX-License-Identifier: GPL-2.0 */
 +/*
 + * Freescale Management Complex (MC) bus public interface
@@ -11208,6 +11211,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	struct fsl_mc_device_irq **irqs;
 +	struct fsl_mc_resource *resource;
 +	const char *driver_override;
++	struct device_link *consumer_link;
 +};
 +
 +#define to_fsl_mc_device(_dev) \
@@ -11519,9 +11523,11 @@ Signed-off-by: Biwen Li <[email protected]>
 +
 +/* DPRC command versioning */
 +#define DPRC_CMD_BASE_VERSION			1
++#define DPRC_CMD_2ND_VERSION			2
 +#define DPRC_CMD_ID_OFFSET			4
 +
 +#define DPRC_CMD(id)	(((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION)
++#define DPRC_CMD_V2(id)	(((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_2ND_VERSION)
 +
 +/* DPRC command IDs */
 +#define DPRC_CMDID_CLOSE                        DPRC_CMD(0x800)
@@ -11540,7 +11546,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +#define DPRC_CMDID_GET_CONT_ID                  DPRC_CMD(0x830)
 +#define DPRC_CMDID_GET_OBJ_COUNT                DPRC_CMD(0x159)
 +#define DPRC_CMDID_GET_OBJ                      DPRC_CMD(0x15A)
-+#define DPRC_CMDID_GET_OBJ_REG                  DPRC_CMD(0x15E)
++#define DPRC_CMDID_GET_OBJ_REG                  DPRC_CMD_V2(0x15E)
 +#define DPRC_CMDID_SET_OBJ_IRQ                  DPRC_CMD(0x15F)
 +
 +struct dprc_cmd_open {
@@ -11643,7 +11649,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	/* response word 0 */
 +	__le64 pad0;
 +	/* response word 1 */
-+	__le32 base_addr;
++	__le32 base_offset;
 +	__le32 pad1;
 +	/* response word 2 */
 +	__le32 size;
@@ -11651,6 +11657,9 @@ Signed-off-by: Biwen Li <[email protected]>
 +	u8 pad2[3];
 +	/* response word 3 */
 +	__le32 flags;
++	__le32 pad3;
++	/* response word 4 */
++	__le64 base_addr;
 +};
 +
 +struct dprc_cmd_set_obj_irq {
@@ -11783,6 +11792,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +/* Region flags */
 +/* Cacheable - Indicates that region should be mapped as cacheable */
 +#define DPRC_REGION_CACHEABLE	0x00000001
++#define DPRC_REGION_SHAREABLE	0x00000002
 +
 +/**
 + * enum dprc_region_type - Region type
@@ -11791,7 +11801,8 @@ Signed-off-by: Biwen Li <[email protected]>
 + */
 +enum dprc_region_type {
 +	DPRC_REGION_TYPE_MC_PORTAL,
-+	DPRC_REGION_TYPE_QBMAN_PORTAL
++	DPRC_REGION_TYPE_QBMAN_PORTAL,
++	DPRC_REGION_TYPE_QBMAN_MEM_BACKED_PORTAL
 +};
 +
 +/**
@@ -11809,6 +11820,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	u32 size;
 +	u32 flags;
 +	enum dprc_region_type type;
++	u64 base_address;
 +};
 +
 +int dprc_get_obj_region(struct fsl_mc_io *mc_io,

target/linux/layerscape/patches-4.14/711-dpaa-bqman-support-layerscape.patch

@@ -1,28 +1,32 @@
-From 48dbe4b3a31795b8efdfff82f69eccd086052eed Mon Sep 17 00:00:00 2001
+From 371e99a257cb714f9a6027d6571cb1a43855d926 Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Fri, 16 Nov 2018 10:27:30 +0800
-Subject: [PATCH 16/39] dpaa-bqman: support layerscape 
+Date: Wed, 17 Apr 2019 18:58:24 +0800
+Subject: [PATCH] dpaa-bqman: support layerscape
+
 This is an integrated patch of dpaa-bqman for layerscape
 
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Claudiu Manoil <[email protected]>
+Signed-off-by: Laurentiu Tudor <[email protected]>
 Signed-off-by: Madalin Bucur <[email protected]>
 Signed-off-by: Roy Pledge <[email protected]>
 Signed-off-by: Stuart Yoder <[email protected]>
 Signed-off-by: Valentin Rothberg <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 ---
  drivers/soc/fsl/qbman/Kconfig       |   2 +-
- drivers/soc/fsl/qbman/bman.c        |  24 ++++-
- drivers/soc/fsl/qbman/bman_ccsr.c   |  35 ++++++-
- drivers/soc/fsl/qbman/bman_portal.c |  12 ++-
+ drivers/soc/fsl/qbman/bman.c        |  24 +++-
+ drivers/soc/fsl/qbman/bman_ccsr.c   |  57 +++++++++-
+ drivers/soc/fsl/qbman/bman_portal.c |  44 ++++++--
  drivers/soc/fsl/qbman/bman_priv.h   |   3 +
  drivers/soc/fsl/qbman/dpaa_sys.h    |   8 +-
- drivers/soc/fsl/qbman/qman.c        |  46 ++++++++-
- drivers/soc/fsl/qbman/qman_ccsr.c   | 140 ++++++++++++++++++++++------
- drivers/soc/fsl/qbman/qman_portal.c |  12 ++-
+ drivers/soc/fsl/qbman/qman.c        |  46 +++++++-
+ drivers/soc/fsl/qbman/qman_ccsr.c   | 168 +++++++++++++++++++++++-----
+ drivers/soc/fsl/qbman/qman_portal.c |  60 ++++++++--
  drivers/soc/fsl/qbman/qman_priv.h   |   5 +-
  drivers/soc/fsl/qbman/qman_test.h   |   2 -
- 11 files changed, 236 insertions(+), 53 deletions(-)
+ include/soc/fsl/bman.h              |  16 +++
+ include/soc/fsl/qman.h              |  17 +++
+ 13 files changed, 390 insertions(+), 62 deletions(-)
 
 --- a/drivers/soc/fsl/qbman/Kconfig
 +++ b/drivers/soc/fsl/qbman/Kconfig
@@ -83,20 +87,49 @@ Signed-off-by: Biwen Li <[email protected]>
  	return 0;
 --- a/drivers/soc/fsl/qbman/bman_ccsr.c
 +++ b/drivers/soc/fsl/qbman/bman_ccsr.c
-@@ -170,10 +170,11 @@ static int fsl_bman_probe(struct platfor
+@@ -29,6 +29,7 @@
+  */
+ 
+ #include "bman_priv.h"
++#include <linux/iommu.h>
+ 
+ u16 bman_ip_rev;
+ EXPORT_SYMBOL(bman_ip_rev);
+@@ -120,6 +121,7 @@ static void bm_set_memory(u64 ba, u32 si
+  */
+ static dma_addr_t fbpr_a;
+ static size_t fbpr_sz;
++static int __bman_probed;
+ 
+ static int bman_fbpr(struct reserved_mem *rmem)
+ {
+@@ -166,14 +168,24 @@ static irqreturn_t bman_isr(int irq, voi
+ 	return IRQ_HANDLED;
+ }
+ 
++int bman_is_probed(void)
++{
++	return __bman_probed;
++}
++EXPORT_SYMBOL_GPL(bman_is_probed);
++
+ static int fsl_bman_probe(struct platform_device *pdev)
  {
  	int ret, err_irq;
  	struct device *dev = &pdev->dev;
 -	struct device_node *node = dev->of_node;
 +	struct device_node *mem_node, *node = dev->of_node;
++	struct iommu_domain *domain;
  	struct resource *res;
  	u16 id, bm_pool_cnt;
  	u8 major, minor;
 +	u64 size;
++
++	__bman_probed = -1;
  
  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  	if (!res) {
-@@ -201,6 +202,38 @@ static int fsl_bman_probe(struct platfor
+@@ -201,6 +213,47 @@ static int fsl_bman_probe(struct platfor
  		return -ENODEV;
  	}
  
@@ -131,13 +164,98 @@ Signed-off-by: Biwen Li <[email protected]>
 +	}
 +
 +	dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
++
++	/* Create an 1-to-1 iommu mapping for FBPR area */
++	domain = iommu_get_domain_for_dev(dev);
++	if (domain) {
++		ret = iommu_map(domain, fbpr_a, fbpr_a, PAGE_ALIGN(fbpr_sz),
++				IOMMU_READ | IOMMU_WRITE | IOMMU_CACHE);
++		if (ret)
++			dev_warn(dev, "failed to iommu_map() %d\n", ret);
++	}
 +
  	bm_set_memory(fbpr_a, fbpr_sz);
  
  	err_irq = platform_get_irq(pdev, 0);
+@@ -240,6 +293,8 @@ static int fsl_bman_probe(struct platfor
+ 		return ret;
+ 	}
+ 
++	__bman_probed = 1;
++
+ 	return 0;
+ };
+ 
 --- a/drivers/soc/fsl/qbman/bman_portal.c
 +++ b/drivers/soc/fsl/qbman/bman_portal.c
-@@ -123,7 +123,14 @@ static int bman_portal_probe(struct plat
+@@ -32,6 +32,7 @@
+ 
+ static struct bman_portal *affine_bportals[NR_CPUS];
+ static struct cpumask portal_cpus;
++static int __bman_portals_probed;
+ /* protect bman global registers and global data shared among portals */
+ static DEFINE_SPINLOCK(bman_lock);
+ 
+@@ -85,6 +86,12 @@ static int bman_online_cpu(unsigned int
+ 	return 0;
+ }
+ 
++int bman_portals_probed(void)
++{
++	return __bman_portals_probed;
++}
++EXPORT_SYMBOL_GPL(bman_portals_probed);
++
+ static int bman_portal_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -92,11 +99,21 @@ static int bman_portal_probe(struct plat
+ 	struct bm_portal_config *pcfg;
+ 	struct resource *addr_phys[2];
+ 	void __iomem *va;
+-	int irq, cpu;
++	int irq, cpu, err;
++
++	err = bman_is_probed();
++	if (!err)
++		return -EPROBE_DEFER;
++	if (err < 0) {
++		dev_err(&pdev->dev, "failing probe due to bman probe error\n");
++		return -ENODEV;
++	}
+ 
+ 	pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
+-	if (!pcfg)
++	if (!pcfg) {
++		__bman_portals_probed = -1;
+ 		return -ENOMEM;
++	}
+ 
+ 	pcfg->dev = dev;
+ 
+@@ -104,14 +121,14 @@ static int bman_portal_probe(struct plat
+ 					     DPAA_PORTAL_CE);
+ 	if (!addr_phys[0]) {
+ 		dev_err(dev, "Can't get %pOF property 'reg::CE'\n", node);
+-		return -ENXIO;
++		goto err_ioremap1;
+ 	}
+ 
+ 	addr_phys[1] = platform_get_resource(pdev, IORESOURCE_MEM,
+ 					     DPAA_PORTAL_CI);
+ 	if (!addr_phys[1]) {
+ 		dev_err(dev, "Can't get %pOF property 'reg::CI'\n", node);
+-		return -ENXIO;
++		goto err_ioremap1;
+ 	}
+ 
+ 	pcfg->cpu = -1;
+@@ -119,11 +136,18 @@ static int bman_portal_probe(struct plat
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq <= 0) {
+ 		dev_err(dev, "Can't get %pOF IRQ'\n", node);
+-		return -ENXIO;
++		goto err_ioremap1;
  	}
  	pcfg->irq = irq;
  
@@ -153,7 +271,7 @@ Signed-off-by: Biwen Li <[email protected]>
  	if (!va) {
  		dev_err(dev, "ioremap::CE failed\n");
  		goto err_ioremap1;
-@@ -131,8 +138,7 @@ static int bman_portal_probe(struct plat
+@@ -131,8 +155,7 @@ static int bman_portal_probe(struct plat
  
  	pcfg->addr_virt[DPAA_PORTAL_CE] = va;
  
@@ -163,6 +281,25 @@ Signed-off-by: Biwen Li <[email protected]>
  	if (!va) {
  		dev_err(dev, "ioremap::CI failed\n");
  		goto err_ioremap2;
+@@ -149,6 +172,9 @@ static int bman_portal_probe(struct plat
+ 	}
+ 
+ 	cpumask_set_cpu(cpu, &portal_cpus);
++	if (!__bman_portals_probed &&
++	    cpumask_weight(&portal_cpus) == num_online_cpus())
++		__bman_portals_probed = 1;
+ 	spin_unlock(&bman_lock);
+ 	pcfg->cpu = cpu;
+ 
+@@ -168,6 +194,8 @@ err_portal_init:
+ err_ioremap2:
+ 	iounmap(pcfg->addr_virt[DPAA_PORTAL_CE]);
+ err_ioremap1:
++	 __bman_portals_probed = -1;
++
+ 	return -ENXIO;
+ }
+ 
 --- a/drivers/soc/fsl/qbman/bman_priv.h
 +++ b/drivers/soc/fsl/qbman/bman_priv.h
 @@ -33,6 +33,9 @@
@@ -290,7 +427,23 @@ Signed-off-by: Biwen Li <[email protected]>
  	/*
 --- a/drivers/soc/fsl/qbman/qman_ccsr.c
 +++ b/drivers/soc/fsl/qbman/qman_ccsr.c
-@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *d
+@@ -29,6 +29,7 @@
+  */
+ 
+ #include "qman_priv.h"
++#include <linux/iommu.h>
+ 
+ u16 qman_ip_rev;
+ EXPORT_SYMBOL(qman_ip_rev);
+@@ -273,6 +274,7 @@ static const struct qman_error_info_mdat
+ static u32 __iomem *qm_ccsr_start;
+ /* A SDQCR mask comprising all the available/visible pool channels */
+ static u32 qm_pools_sdqcr;
++static int __qman_probed;
+ 
+ static inline u32 qm_ccsr_in(u32 offset)
+ {
+@@ -401,21 +403,42 @@ static int qm_init_pfdr(struct device *d
  }
  
  /*
@@ -338,7 +491,7 @@ Signed-off-by: Biwen Li <[email protected]>
  	return 0;
  }
  RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
-@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem
+@@ -431,32 +454,13 @@ static int qman_pfdr(struct reserved_mem
  }
  RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
  
@@ -373,21 +526,49 @@ Signed-off-by: Biwen Li <[email protected]>
  static void log_edata_bits(struct device *dev, u32 bit_count)
  {
  	u32 i, j, mask = 0xffffffff;
-@@ -687,11 +689,12 @@ static int qman_resource_init(struct dev
+@@ -595,6 +599,7 @@ static int qman_init_ccsr(struct device
+ #define LIO_CFG_LIODN_MASK 0x0fff0000
+ void qman_liodn_fixup(u16 channel)
+ {
++#ifdef CONFIG_PPC
+ 	static int done;
+ 	static u32 liodn_offset;
+ 	u32 before, after;
+@@ -614,6 +619,7 @@ void qman_liodn_fixup(u16 channel)
+ 		qm_ccsr_out(REG_REV3_QCSP_LIO_CFG(idx), after);
+ 	else
+ 		qm_ccsr_out(REG_QCSP_LIO_CFG(idx), after);
++#endif
+ }
+ 
+ #define IO_CFG_SDEST_MASK 0x00ff0000
+@@ -684,14 +690,24 @@ static int qman_resource_init(struct dev
+ 	return 0;
+ }
+ 
++int qman_is_probed(void)
++{
++	return __qman_probed;
++}
++EXPORT_SYMBOL_GPL(qman_is_probed);
++
  static int fsl_qman_probe(struct platform_device *pdev)
  {
  	struct device *dev = &pdev->dev;
 -	struct device_node *node = dev->of_node;
 +	struct device_node *mem_node, *node = dev->of_node;
++	struct iommu_domain *domain;
  	struct resource *res;
  	int ret, err_irq;
  	u16 id;
  	u8 major, minor;
 +	u64 size;
++
++	__qman_probed = -1;
  
  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  	if (!res) {
-@@ -717,6 +720,8 @@ static int fsl_qman_probe(struct platfor
+@@ -717,6 +733,8 @@ static int fsl_qman_probe(struct platfor
  		qman_ip_rev = QMAN_REV30;
  	else if (major == 3 && minor == 1)
  		qman_ip_rev = QMAN_REV31;
@@ -396,7 +577,7 @@ Signed-off-by: Biwen Li <[email protected]>
  	else {
  		dev_err(dev, "Unknown QMan version\n");
  		return -ENODEV;
-@@ -727,10 +732,83 @@ static int fsl_qman_probe(struct platfor
+@@ -727,10 +745,96 @@ static int fsl_qman_probe(struct platfor
  		qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
  	}
  
@@ -481,12 +662,116 @@ Signed-off-by: Biwen Li <[email protected]>
 +		}
 +	}
 +	dev_info(dev, "Allocated PFDR 0x%llx 0x%zx\n", pfdr_a, pfdr_sz);
++
++	/* Create an 1-to-1 iommu mapping for fqd and pfdr areas */
++	domain = iommu_get_domain_for_dev(dev);
++	if (domain) {
++		ret = iommu_map(domain, fqd_a, fqd_a, PAGE_ALIGN(fqd_sz),
++				IOMMU_READ | IOMMU_WRITE | IOMMU_CACHE);
++		if (ret)
++			dev_warn(dev, "iommu_map(fqd) failed %d\n", ret);
++		ret = iommu_map(domain, pfdr_a, pfdr_a, PAGE_ALIGN(pfdr_sz),
++				IOMMU_READ | IOMMU_WRITE | IOMMU_CACHE);
++		if (ret)
++			dev_warn(dev, "iommu_map(pfdr) failed %d\n", ret);
++	}
  
  	ret = qman_init_ccsr(dev);
  	if (ret) {
+@@ -793,6 +897,8 @@ static int fsl_qman_probe(struct platfor
+ 	if (ret)
+ 		return ret;
+ 
++	__qman_probed = 1;
++
+ 	return 0;
+ }
+ 
 --- a/drivers/soc/fsl/qbman/qman_portal.c
 +++ b/drivers/soc/fsl/qbman/qman_portal.c
-@@ -262,7 +262,14 @@ static int qman_portal_probe(struct plat
+@@ -29,6 +29,7 @@
+  */
+ 
+ #include "qman_priv.h"
++#include <linux/iommu.h>
+ 
+ struct qman_portal *qman_dma_portal;
+ EXPORT_SYMBOL(qman_dma_portal);
+@@ -38,6 +39,7 @@ EXPORT_SYMBOL(qman_dma_portal);
+ #define CONFIG_FSL_DPA_PIRQ_FAST  1
+ 
+ static struct cpumask portal_cpus;
++static int __qman_portals_probed;
+ /* protect qman global registers and global data shared among portals */
+ static DEFINE_SPINLOCK(qman_lock);
+ 
+@@ -218,19 +220,36 @@ static int qman_online_cpu(unsigned int
+ 	return 0;
+ }
+ 
++int qman_portals_probed(void)
++{
++	return __qman_portals_probed;
++}
++EXPORT_SYMBOL_GPL(qman_portals_probed);
++
+ static int qman_portal_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *node = dev->of_node;
++	struct iommu_domain *domain;
+ 	struct qm_portal_config *pcfg;
+ 	struct resource *addr_phys[2];
+ 	void __iomem *va;
+ 	int irq, cpu, err;
+ 	u32 val;
+ 
++	err = qman_is_probed();
++	if (!err)
++		return -EPROBE_DEFER;
++	if (err < 0) {
++		dev_err(&pdev->dev, "failing probe due to qman probe error\n");
++		return -ENODEV;
++	}
++
+ 	pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
+-	if (!pcfg)
++	if (!pcfg) {
++		__qman_portals_probed = -1;
+ 		return -ENOMEM;
++	}
+ 
+ 	pcfg->dev = dev;
+ 
+@@ -238,19 +257,20 @@ static int qman_portal_probe(struct plat
+ 					     DPAA_PORTAL_CE);
+ 	if (!addr_phys[0]) {
+ 		dev_err(dev, "Can't get %pOF property 'reg::CE'\n", node);
+-		return -ENXIO;
++		goto err_ioremap1;
+ 	}
+ 
+ 	addr_phys[1] = platform_get_resource(pdev, IORESOURCE_MEM,
+ 					     DPAA_PORTAL_CI);
+ 	if (!addr_phys[1]) {
+ 		dev_err(dev, "Can't get %pOF property 'reg::CI'\n", node);
+-		return -ENXIO;
++		goto err_ioremap1;
+ 	}
+ 
+ 	err = of_property_read_u32(node, "cell-index", &val);
+ 	if (err) {
+ 		dev_err(dev, "Can't get %pOF property 'cell-index'\n", node);
++		__qman_portals_probed = -1;
+ 		return err;
+ 	}
+ 	pcfg->channel = val;
+@@ -258,11 +278,18 @@ static int qman_portal_probe(struct plat
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq <= 0) {
+ 		dev_err(dev, "Can't get %pOF IRQ\n", node);
+-		return -ENXIO;
++		goto err_ioremap1;
  	}
  	pcfg->irq = irq;
  
@@ -502,7 +787,7 @@ Signed-off-by: Biwen Li <[email protected]>
  	if (!va) {
  		dev_err(dev, "ioremap::CE failed\n");
  		goto err_ioremap1;
-@@ -270,8 +277,7 @@ static int qman_portal_probe(struct plat
+@@ -270,8 +297,7 @@ static int qman_portal_probe(struct plat
  
  	pcfg->addr_virt[DPAA_PORTAL_CE] = va;
  
@@ -512,6 +797,47 @@ Signed-off-by: Biwen Li <[email protected]>
  	if (!va) {
  		dev_err(dev, "ioremap::CI failed\n");
  		goto err_ioremap2;
+@@ -279,6 +305,21 @@ static int qman_portal_probe(struct plat
+ 
+ 	pcfg->addr_virt[DPAA_PORTAL_CI] = va;
+ 
++	/* Create an 1-to-1 iommu mapping for cena portal area */
++	domain = iommu_get_domain_for_dev(dev);
++	if (domain) {
++		/*
++		 * Note: not mapping this as cacheable triggers the infamous
++		 * QMan CIDE error.
++		 */
++		err = iommu_map(domain,
++				addr_phys[0]->start, addr_phys[0]->start,
++				PAGE_ALIGN(resource_size(addr_phys[0])),
++				IOMMU_READ | IOMMU_WRITE | IOMMU_CACHE);
++		if (err)
++			dev_warn(dev, "failed to iommu_map() %d\n", err);
++	}
++
+ 	pcfg->pools = qm_get_pools_sdqcr();
+ 
+ 	spin_lock(&qman_lock);
+@@ -290,6 +331,9 @@ static int qman_portal_probe(struct plat
+ 	}
+ 
+ 	cpumask_set_cpu(cpu, &portal_cpus);
++	if (!__qman_portals_probed &&
++	    cpumask_weight(&portal_cpus) == num_online_cpus())
++		__qman_portals_probed = 1;
+ 	spin_unlock(&qman_lock);
+ 	pcfg->cpu = cpu;
+ 
+@@ -314,6 +358,8 @@ err_portal_init:
+ err_ioremap2:
+ 	iounmap(pcfg->addr_virt[DPAA_PORTAL_CE]);
+ err_ioremap1:
++	__qman_portals_probed = -1;
++
+ 	return -ENXIO;
+ }
+ 
 --- a/drivers/soc/fsl/qbman/qman_priv.h
 +++ b/drivers/soc/fsl/qbman/qman_priv.h
 @@ -28,13 +28,13 @@
@@ -548,3 +874,50 @@ Signed-off-by: Biwen Li <[email protected]>
 -
  int qman_test_stash(void);
  int qman_test_api(void);
+--- a/include/soc/fsl/bman.h
++++ b/include/soc/fsl/bman.h
+@@ -126,4 +126,20 @@ int bman_release(struct bman_pool *pool,
+  */
+ int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num);
+ 
++/**
++ * bman_is_probed - Check if bman is probed
++ *
++ * Returns 1 if the bman driver successfully probed, -1 if the bman driver
++ * failed to probe or 0 if the bman driver did not probed yet.
++ */
++int bman_is_probed(void);
++/**
++ * bman_portals_probed - Check if all cpu bound bman portals are probed
++ *
++ * Returns 1 if all the required cpu bound bman portals successfully probed,
++ * -1 if probe errors appeared or 0 if the bman portals did not yet finished
++ * probing.
++ */
++int bman_portals_probed(void);
++
+ #endif	/* __FSL_BMAN_H */
+--- a/include/soc/fsl/qman.h
++++ b/include/soc/fsl/qman.h
+@@ -1186,4 +1186,21 @@ int qman_alloc_cgrid_range(u32 *result,
+  */
+ int qman_release_cgrid(u32 id);
+ 
++/**
++ * qman_is_probed - Check if qman is probed
++ *
++ * Returns 1 if the qman driver successfully probed, -1 if the qman driver
++ * failed to probe or 0 if the qman driver did not probed yet.
++ */
++int qman_is_probed(void);
++
++/**
++ * qman_portals_probed - Check if all cpu bound qman portals are probed
++ *
++ * Returns 1 if all the required cpu bound qman portals successfully probed,
++ * -1 if probe errors appeared or 0 if the qman portals did not yet finished
++ * probing.
++ */
++int qman_portals_probed(void);
++
+ #endif	/* __FSL_QMAN_H */

target/linux/layerscape/patches-4.14/712-etsec-support-layerscape.patch

@@ -0,0 +1,77 @@
+From f0f6e88696957d376d8875f675c1caf75a33fd67 Mon Sep 17 00:00:00 2001
+From: Biwen Li <[email protected]>
+Date: Wed, 17 Apr 2019 18:58:34 +0800
+Subject: [PATCH] etsec: support layerscape
+
+This is an integrated patch of etsec for layerscape
+
+Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+Signed-off-by: Yangbo Lu <[email protected]>
+---
+ drivers/net/ethernet/freescale/gianfar.h      |  3 ---
+ .../net/ethernet/freescale/gianfar_ethtool.c  | 23 +++++++++++++++----
+ 2 files changed, 18 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/gianfar.h
++++ b/drivers/net/ethernet/freescale/gianfar.h
+@@ -1372,7 +1372,4 @@ struct filer_table {
+ 	struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
+ };
+ 
+-/* The gianfar_ptp module will set this variable */
+-extern int gfar_phc_index;
+-
+ #endif /* __GIANFAR_H */
+--- a/drivers/net/ethernet/freescale/gianfar_ethtool.c
++++ b/drivers/net/ethernet/freescale/gianfar_ethtool.c
+@@ -41,6 +41,8 @@
+ #include <linux/phy.h>
+ #include <linux/sort.h>
+ #include <linux/if_vlan.h>
++#include <linux/of_platform.h>
++#include <linux/fsl/ptp_qoriq.h>
+ 
+ #include "gianfar.h"
+ 
+@@ -1509,24 +1511,35 @@ static int gfar_get_nfc(struct net_devic
+ 	return ret;
+ }
+ 
+-int gfar_phc_index = -1;
+-EXPORT_SYMBOL(gfar_phc_index);
+-
+ static int gfar_get_ts_info(struct net_device *dev,
+ 			    struct ethtool_ts_info *info)
+ {
+ 	struct gfar_private *priv = netdev_priv(dev);
++	struct platform_device *ptp_dev;
++	struct device_node *ptp_node;
++	struct qoriq_ptp *ptp = NULL;
++
++	info->phc_index = -1;
+ 
+ 	if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) {
+ 		info->so_timestamping = SOF_TIMESTAMPING_RX_SOFTWARE |
+ 					SOF_TIMESTAMPING_SOFTWARE;
+-		info->phc_index = -1;
+ 		return 0;
+ 	}
++
++	ptp_node = of_find_compatible_node(NULL, NULL, "fsl,etsec-ptp");
++	if (ptp_node) {
++		ptp_dev = of_find_device_by_node(ptp_node);
++		if (ptp_dev)
++			ptp = platform_get_drvdata(ptp_dev);
++	}
++
++	if (ptp)
++		info->phc_index = ptp->phc_index;
++
+ 	info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
+ 				SOF_TIMESTAMPING_RX_HARDWARE |
+ 				SOF_TIMESTAMPING_RAW_HARDWARE;
+-	info->phc_index = gfar_phc_index;
+ 	info->tx_types = (1 << HWTSTAMP_TX_OFF) |
+ 			 (1 << HWTSTAMP_TX_ON);
+ 	info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |

target/linux/layerscape/patches-4.14/712-sdk-dpaa-rgmii-fixed-link.patch

@@ -1,62 +0,0 @@
-From b3544990f8496edda965e1ff9a14727360660676 Mon Sep 17 00:00:00 2001
-From: Mathew McBride <[email protected]>
-Date: Mon, 7 Aug 2017 10:19:48 +1000
-Subject: [PATCH] Recognize when an RGMII Link is set as fixed (in the device
- tree) and set up the MAC accordingly
-
----
- drivers/net/ethernet/freescale/sdk_dpaa/mac.c       |  1 +
- .../freescale/sdk_fman/Peripherals/FM/MAC/memac.c   | 13 +++++++++++++
- 2 files changed, 14 insertions(+)
-
---- a/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
-+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
-@@ -386,6 +386,7 @@ static int __cold mac_probe(struct platf
- 		mac_dev->fixed_link->duplex = phy->duplex;
- 		mac_dev->fixed_link->pause = phy->pause;
- 		mac_dev->fixed_link->asym_pause = phy->asym_pause;
-+		printk(KERN_INFO "Setting up fixed link, speed %d duplex %d\n", mac_dev->fixed_link->speed, mac_dev->fixed_link->duplex);
- 	}
- 
- 	_errno = mac_dev->init(mac_dev);
---- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c
-+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c
-@@ -36,6 +36,8 @@
- 
-  @Description   FM mEMAC driver
- *//***************************************************************************/
-+#include <../../../../sdk_dpaa/mac.h>
-+#include <linux/phy_fixed.h>
- 
- #include "std_ext.h"
- #include "string_ext.h"
-@@ -48,6 +50,8 @@
- #include "memac.h"
- 
- 
-+static t_Error MemacAdjustLink(t_Handle h_Memac, e_EnetSpeed speed, bool fullDuplex);
-+
- /*****************************************************************************/
- /*                      Internal routines                                    */
- /*****************************************************************************/
-@@ -276,11 +280,20 @@ static t_Error MemacEnable(t_Handle h_Me
- {
-     t_Memac     *p_Memac = (t_Memac *)h_Memac;
- 
-+    struct mac_device *mac_dev = (struct mac_device *)p_Memac->h_App;
-+
-     SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
-     SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
- 
-     fman_memac_enable(p_Memac->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX));
- 
-+    if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_RGMII) {
-+	if (mac_dev->fixed_link) {
-+		printk(KERN_INFO "This is a fixed-link, forcing speed %d duplex %d\n",mac_dev->fixed_link->speed,mac_dev->fixed_link->duplex);
-+		MemacAdjustLink(h_Memac,mac_dev->fixed_link->speed,mac_dev->fixed_link->duplex);
-+	}
-+    }
-+
-     return E_OK;
- }
- 

target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch

@@ -1,15 +1,33 @@
-From 918f966af1f0e42ff8ac298e1d7d02e67afcfab4 Mon Sep 17 00:00:00 2001
+From 71fb63c92eae3f9197e2343ed5ed3676440789e1 Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:27:42 +0800
-Subject: [PATCH 18/40] sata: support layerscape
+Date: Wed, 17 Apr 2019 18:59:01 +0800
+Subject: [PATCH] sata: support layerscape
+
 This is an integrated patch of sata for layerscape
 
-Signed-off-by: Tang Yuantian <[email protected]>
 Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Peng Ma <[email protected]>
+Signed-off-by: Tang Yuantian <[email protected]>
 ---
- drivers/ata/ahci_qoriq.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
+ drivers/ata/ahci.h        |   7 ++
+ drivers/ata/ahci_qoriq.c  | 168 ++++++++++++++++++++++++++++++++++++++
+ drivers/ata/libata-core.c |   3 +
+ 3 files changed, 178 insertions(+)
 
+--- a/drivers/ata/ahci.h
++++ b/drivers/ata/ahci.h
+@@ -445,4 +445,11 @@ static inline int ahci_nr_ports(u32 cap)
+ 	return (cap & 0x1f) + 1;
+ }
+ 
++#ifdef CONFIG_AHCI_QORIQ
++extern void fsl_sata_errata_379364(struct ata_link *link);
++#else
++static void fsl_sata_errata_379364(struct ata_link *link)
++{}
++#endif
++
+ #endif /* _AHCI_H */
 --- a/drivers/ata/ahci_qoriq.c
 +++ b/drivers/ata/ahci_qoriq.c
 @@ -35,6 +35,8 @@
@@ -21,7 +39,190 @@ Signed-off-by: Biwen Li <[email protected]>
  #define AHCI_PORT_TRANS_CFG	0x08000029
  #define AHCI_PORT_AXICC_CFG	0x3fffffff
  
-@@ -183,6 +185,8 @@ static int ahci_qoriq_phy_init(struct ah
+@@ -49,6 +51,27 @@
+ #define ECC_DIS_ARMV8_CH2	0x80000000
+ #define ECC_DIS_LS1088A		0x40000000
+ 
++/* errata for lx2160 */
++#define RCWSR29_BASE			0x1E00170
++#define SERDES2_BASE			0x1EB0000
++#define DEVICE_CONFIG_REG_BASE		0x1E00000
++#define SERDES2_LNAX_RX_CR(x)		(0x840 + (0x100 * (x)))
++#define SERDES2_LNAX_RX_CBR(x)		(0x8C0 + (0x100 * (x)))
++#define SYS_VER_REG			0xA4
++#define LN_RX_RST			0x80000010
++#define LN_RX_RST_DONE			0x3
++#define LN_RX_MASK			0xf
++#define LX2160A_VER1			0x1
++
++#define SERDES2_LNAA 0
++#define SERDES2_LNAB 1
++#define SERDES2_LNAC 2
++#define SERDES2_LNAD 3
++#define SERDES2_LNAE 4
++#define SERDES2_LNAF 5
++#define SERDES2_LNAG 6
++#define SERDES2_LNAH 7
++
+ enum ahci_qoriq_type {
+ 	AHCI_LS1021A,
+ 	AHCI_LS1043A,
+@@ -56,6 +79,7 @@ enum ahci_qoriq_type {
+ 	AHCI_LS1046A,
+ 	AHCI_LS1088A,
+ 	AHCI_LS2088A,
++	AHCI_LX2160A,
+ };
+ 
+ struct ahci_qoriq_priv {
+@@ -72,6 +96,7 @@ static const struct of_device_id ahci_qo
+ 	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
+ 	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
+ 	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
++	{ .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
+@@ -156,6 +181,138 @@ static struct scsi_host_template ahci_qo
+ 	AHCI_SHT(DRV_NAME),
+ };
+ 
++void fsl_sata_errata_379364(struct ata_link *link)
++{
++	struct ata_port *ap = link->ap;
++	struct ahci_host_priv *hpriv = ap->host->private_data;
++	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
++	bool lx2160a_workaround = (qoriq_priv->type == AHCI_LX2160A);
++
++	int val = 0;
++	void __iomem *rcw_base = NULL;
++	void __iomem *serdes_base = NULL;
++	void __iomem *dev_con_base = NULL;
++
++	if (!lx2160a_workaround)
++		return;
++	else {
++		dev_con_base = ioremap(DEVICE_CONFIG_REG_BASE, PAGE_SIZE);
++		if (!dev_con_base) {
++			ata_link_err(link, "device config ioremap failed\n");
++			return;
++		}
++
++		val = (readl(dev_con_base + SYS_VER_REG) & GENMASK(7, 4)) >> 4;
++		if (val != LX2160A_VER1)
++			goto dev_unmap;
++
++		/*
++		 * Add few msec delay.
++		 * Check for corresponding serdes lane RST_DONE .
++		 * apply lane reset.
++		 */
++
++		serdes_base = ioremap(SERDES2_BASE, PAGE_SIZE);
++		if (!serdes_base) {
++			ata_link_err(link, "serdes ioremap failed\n");
++			goto dev_unmap;
++		}
++
++		rcw_base = ioremap(RCWSR29_BASE, PAGE_SIZE);
++		if (!rcw_base) {
++			ata_link_err(link, "rcw ioremap failed\n");
++			goto serdes_unmap;
++		}
++
++		ata_msleep(link->ap, 1);
++
++		val = (readl(rcw_base) & GENMASK(25, 21)) >> 21;
++
++		switch (val) {
++		case 1:
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAC)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAC));
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAD)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAD));
++			break;
++
++		case 4:
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAG)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAG));
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAH)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAH));
++			break;
++
++		case 5:
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAE)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAE));
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAF)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAF));
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAG)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAG));
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAH)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAH));
++			break;
++
++		case 8:
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAC)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAC));
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAD)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAD));
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAE)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAE));
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAF)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAF));
++			break;
++
++		case 12:
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAG)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAG));
++			if ((readl(serdes_base + SERDES2_LNAX_RX_CBR(SERDES2_LNAH)) &
++				LN_RX_MASK) != LN_RX_RST_DONE)
++				writel(LN_RX_RST, serdes_base +
++					SERDES2_LNAX_RX_CR(SERDES2_LNAH));
++			break;
++
++		default:
++			break;
++		}
++	}
++
++	iounmap(rcw_base);
++serdes_unmap:
++	iounmap(serdes_base);
++dev_unmap:
++	iounmap(dev_con_base);
++}
++
++
+ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
+ {
+ 	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
+@@ -183,13 +340,18 @@ static int ahci_qoriq_phy_init(struct ah
  		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
  				qpriv->ecc_addr);
  		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
@@ -30,16 +231,17 @@ Signed-off-by: Biwen Li <[email protected]>
  		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  		if (qpriv->is_dmacoherent)
  			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
-@@ -190,6 +194,8 @@ static int ahci_qoriq_phy_init(struct ah
+ 		break;
  
  	case AHCI_LS2080A:
++	case AHCI_LX2160A:
  		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 +		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
 +		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  		if (qpriv->is_dmacoherent)
  			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
-@@ -201,6 +207,8 @@ static int ahci_qoriq_phy_init(struct ah
+@@ -201,6 +363,8 @@ static int ahci_qoriq_phy_init(struct ah
  		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
  				qpriv->ecc_addr);
  		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
@@ -48,7 +250,7 @@ Signed-off-by: Biwen Li <[email protected]>
  		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  		if (qpriv->is_dmacoherent)
  			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
-@@ -212,6 +220,8 @@ static int ahci_qoriq_phy_init(struct ah
+@@ -212,6 +376,8 @@ static int ahci_qoriq_phy_init(struct ah
  		writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
  		       qpriv->ecc_addr);
  		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
@@ -57,7 +259,7 @@ Signed-off-by: Biwen Li <[email protected]>
  		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  		if (qpriv->is_dmacoherent)
  			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
-@@ -219,6 +229,8 @@ static int ahci_qoriq_phy_init(struct ah
+@@ -219,6 +385,8 @@ static int ahci_qoriq_phy_init(struct ah
  
  	case AHCI_LS2088A:
  		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
@@ -66,3 +268,22 @@ Signed-off-by: Biwen Li <[email protected]>
  		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  		if (qpriv->is_dmacoherent)
  			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+--- a/drivers/ata/libata-core.c
++++ b/drivers/ata/libata-core.c
+@@ -76,6 +76,7 @@
+ #define CREATE_TRACE_POINTS
+ #include <trace/events/libata.h>
+ 
++#include "ahci.h"
+ #include "libata.h"
+ #include "libata-transport.h"
+ 
+@@ -4119,6 +4120,8 @@ int sata_link_hardreset(struct ata_link
+ 	 */
+ 	ata_msleep(link->ap, 1);
+ 
++	fsl_sata_errata_379364(link);
++
+ 	/* bring link back */
+ 	rc = sata_link_resume(link, timing, deadline);
+ 	if (rc)

target/linux/layerscape/patches-4.14/802-dma-support-layerscape.patch

@@ -1,35 +1,40 @@
-From 731adfb43892a1d7fe00e2036200f33a9b61a589 Mon Sep 17 00:00:00 2001
+From 5cb4bc977d933323429050033da9c701b24df43e Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:26:02 +0800
-Subject: [PATCH 19/40] dma: support layerscape
+Date: Wed, 17 Apr 2019 18:58:23 +0800
+Subject: [PATCH] dma: support layerscape
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
 This is an integrated patch of dma for layerscape
 
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Catalin Horghidan <[email protected]>
 Signed-off-by: Changming Huang <[email protected]>
 Signed-off-by: Horia Geantă <[email protected]>
+Signed-off-by: Ioana Ciornei <[email protected]>
 Signed-off-by: jiaheng.fan <[email protected]>
+Signed-off-by: Laurentiu Tudor <[email protected]>
 Signed-off-by: Peng Ma <[email protected]>
 Signed-off-by: Radu Alexe <[email protected]>
 Signed-off-by: Rajiv Vishwakarma <[email protected]>
 Signed-off-by: Tudor Ambarus <[email protected]>
 Signed-off-by: Wen He <[email protected]>
 Signed-off-by: Yuan Yao <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 ---
- .../devicetree/bindings/dma/fsl-qdma.txt      |   51 +
- drivers/dma/Kconfig                           |   33 +-
- drivers/dma/Makefile                          |    3 +
- drivers/dma/caam_dma.c                        |  462 ++++++
- drivers/dma/dpaa2-qdma/Kconfig                |    8 +
- drivers/dma/dpaa2-qdma/Makefile               |    8 +
- drivers/dma/dpaa2-qdma/dpaa2-qdma.c           |  940 ++++++++++++
- drivers/dma/dpaa2-qdma/dpaa2-qdma.h           |  227 +++
- drivers/dma/dpaa2-qdma/dpdmai.c               |  515 +++++++
- drivers/dma/dpaa2-qdma/fsl_dpdmai.h           |  521 +++++++
- drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h       |  222 +++
- drivers/dma/fsl-qdma.c                        | 1278 +++++++++++++++++
- 12 files changed, 4267 insertions(+), 1 deletion(-)
- create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
+ drivers/dma/Kconfig                     |   33 +-
+ drivers/dma/Makefile                    |    3 +
+ drivers/dma/caam_dma.c                  |  462 ++++++++
+ drivers/dma/dpaa2-qdma/Kconfig          |    8 +
+ drivers/dma/dpaa2-qdma/Makefile         |    8 +
+ drivers/dma/dpaa2-qdma/dpaa2-qdma.c     |  781 ++++++++++++++
+ drivers/dma/dpaa2-qdma/dpaa2-qdma.h     |  181 ++++
+ drivers/dma/dpaa2-qdma/dpdmai.c         |  515 +++++++++
+ drivers/dma/dpaa2-qdma/fsl_dpdmai.h     |  521 +++++++++
+ drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h |  222 ++++
+ drivers/dma/fsl-edma.c                  |   66 +-
+ drivers/dma/fsl-qdma.c                  | 1278 +++++++++++++++++++++++
+ 12 files changed, 4073 insertions(+), 5 deletions(-)
  create mode 100644 drivers/dma/caam_dma.c
  create mode 100644 drivers/dma/dpaa2-qdma/Kconfig
  create mode 100644 drivers/dma/dpaa2-qdma/Makefile
@@ -40,60 +45,6 @@ Signed-off-by: Biwen Li <[email protected]>
  create mode 100644 drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h
  create mode 100644 drivers/dma/fsl-qdma.c
 
---- /dev/null
-+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
-@@ -0,0 +1,51 @@
-+* Freescale queue Direct Memory Access(qDMA) Controller
-+
-+The qDMA supports channel virtualization by allowing DMA jobs to be enqueued into
-+different command queues. Core can initiate a DMA transaction by preparing a command
-+descriptor for each DMA job and enqueuing this job to a command queue.
-+
-+* qDMA Controller
-+Required properties:
-+- compatible :
-+	should be "fsl,ls1021a-qdma".
-+- reg : Specifies base physical address(s) and size of the qDMA registers.
-+	The 1st region is qDMA control register's address and size.
-+	The 2nd region is status queue control register's address and size.
-+	The 3rd region is virtual block control register's address and size.
-+- interrupts : A list of interrupt-specifiers, one for each entry in
-+	interrupt-names.
-+- interrupt-names : Should contain:
-+	"qdma-queue0" - the block0 interrupt
-+	"qdma-queue1" - the block1 interrupt
-+	"qdma-queue2" - the block2 interrupt
-+	"qdma-queue3" - the block3 interrupt
-+	"qdma-error"  - the error interrupt
-+- channels : Number of DMA channels supported
-+- block-number : the virtual block number
-+- block-offset : the offset of different virtual block
-+- queues : the number of command queue per virtual block
-+- status-sizes : status queue size of per virtual block
-+- queue-sizes : command queue size of per virtual block, the size number based on queues
-+- big-endian: If present registers and hardware scatter/gather descriptors
-+	of the qDMA are implemented in big endian mode, otherwise in little
-+	mode.
-+
-+Examples:
-+	qdma: qdma@8390000 {
-+				compatible = "fsl,ls1021a-qdma";
-+				reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
-+				      <0x0 0x8389000 0x0 0x1000>, /* Status regs */
-+				      <0x0 0x838a000 0x0 0x2000>; /* Block regs */
-+				interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
-+					     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
-+					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-+				interrupt-names = "qdma-error",
-+					"qdma-queue0", "qdma-queue1";
-+				channels = <8>;
-+				block-number = <2>;
-+				block-offset = <0x1000>;
-+				queues = <2>;
-+				status-sizes = <64>;
-+				queue-sizes = <64 64>;
-+				big-endian;
-+			};
 --- a/drivers/dma/Kconfig
 +++ b/drivers/dma/Kconfig
 @@ -129,6 +129,24 @@ config COH901318
@@ -659,7 +610,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +fsl-dpaa2-qdma-objs    := dpaa2-qdma.o dpdmai.o
 --- /dev/null
 +++ b/drivers/dma/dpaa2-qdma/dpaa2-qdma.c
-@@ -0,0 +1,940 @@
+@@ -0,0 +1,781 @@
 +/*
 + * drivers/dma/dpaa2-qdma/dpaa2-qdma.c
 + *
@@ -693,6 +644,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +#include <linux/types.h>
 +#include <linux/delay.h>
 +#include <linux/iommu.h>
++#include <linux/sys_soc.h>
 +
 +#include "../virt-dma.h"
 +
@@ -765,9 +717,6 @@ Signed-off-by: Biwen Li <[email protected]>
 +				sizeof(struct dpaa2_fl_entry) * 3;
 +
 +		comp_temp->qchan = dpaa2_chan;
-+		comp_temp->sg_blk_num = 0;
-+		INIT_LIST_HEAD(&comp_temp->sg_src_head);
-+		INIT_LIST_HEAD(&comp_temp->sg_dst_head);
 +		return comp_temp;
 +	}
 +	comp_temp = list_first_entry(&dpaa2_chan->comp_free,
@@ -802,7 +751,8 @@ Signed-off-by: Biwen Li <[email protected]>
 +/* first frame list for descriptor buffer */
 +static void dpaa2_qdma_populate_first_framel(
 +		struct dpaa2_fl_entry *f_list,
-+		struct dpaa2_qdma_comp *dpaa2_comp)
++		struct dpaa2_qdma_comp *dpaa2_comp,
++		bool wrt_changed)
 +{
 +	struct dpaa2_qdma_sd_d *sdd;
 +
@@ -811,7 +761,12 @@ Signed-off-by: Biwen Li <[email protected]>
 +	/* source and destination descriptor */
 +	sdd->cmd = cpu_to_le32(QDMA_SD_CMD_RDTTYPE_COHERENT); /* source descriptor CMD */
 +	sdd++;
-+	sdd->cmd = cpu_to_le32(QDMA_DD_CMD_WRTTYPE_COHERENT); /* dest descriptor CMD */
++
++	/* dest descriptor CMD */
++	if (wrt_changed)
++		sdd->cmd = cpu_to_le32(LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT);
++	else
++		sdd->cmd = cpu_to_le32(QDMA_DD_CMD_WRTTYPE_COHERENT);
 +
 +	memset(f_list, 0, sizeof(struct dpaa2_fl_entry));
 +	/* first frame list to source descriptor */
@@ -855,11 +810,15 @@ Signed-off-by: Biwen Li <[email protected]>
 +		dma_addr_t src, size_t len, unsigned long flags)
 +{
 +	struct dpaa2_qdma_chan *dpaa2_chan = to_dpaa2_qdma_chan(chan);
++	struct dpaa2_qdma_engine *dpaa2_qdma;
 +	struct dpaa2_qdma_comp *dpaa2_comp;
 +	struct dpaa2_fl_entry *f_list;
++	bool	wrt_changed;
 +	uint32_t format;
 +
++	dpaa2_qdma = dpaa2_chan->qdma;
 +	dpaa2_comp = dpaa2_qdma_request_desc(dpaa2_chan);
++	wrt_changed = dpaa2_qdma->qdma_wrtype_fixup;
 +
 +#ifdef LONG_FORMAT
 +	format = QDMA_FD_LONG_FORMAT;
@@ -873,7 +832,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +
 +#ifdef LONG_FORMAT
 +	/* first frame list for descriptor buffer (logn format) */
-+	dpaa2_qdma_populate_first_framel(f_list, dpaa2_comp);
++	dpaa2_qdma_populate_first_framel(f_list, dpaa2_comp, wrt_changed);
 +
 +	f_list++;
 +#endif
@@ -883,155 +842,6 @@ Signed-off-by: Biwen Li <[email protected]>
 +	return vchan_tx_prep(&dpaa2_chan->vchan, &dpaa2_comp->vdesc, flags);
 +}
 +
-+static struct qdma_sg_blk *dpaa2_qdma_get_sg_blk(
-+	struct dpaa2_qdma_comp *dpaa2_comp,
-+	struct dpaa2_qdma_chan *dpaa2_chan)
-+{
-+	struct qdma_sg_blk *sg_blk = NULL;
-+	dma_addr_t phy_sgb;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&dpaa2_chan->queue_lock, flags);
-+	if (list_empty(&dpaa2_chan->sgb_free)) {
-+		sg_blk = (struct qdma_sg_blk *)dma_pool_alloc(
-+				dpaa2_chan->sg_blk_pool,
-+				GFP_NOWAIT, &phy_sgb);
-+		if (!sg_blk) {
-+			spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags);
-+			return sg_blk;
-+		}
-+		sg_blk->blk_virt_addr = (void *)(sg_blk + 1);
-+		sg_blk->blk_bus_addr = phy_sgb + sizeof(*sg_blk);
-+	} else {
-+		sg_blk = list_first_entry(&dpaa2_chan->sgb_free,
-+			struct qdma_sg_blk, list);
-+		list_del(&sg_blk->list);
-+	}
-+	spin_unlock_irqrestore(&dpaa2_chan->queue_lock, flags);
-+
-+	return sg_blk;
-+}
-+
-+static uint32_t dpaa2_qdma_populate_sg(struct device *dev,
-+		struct dpaa2_qdma_chan *dpaa2_chan,
-+		struct dpaa2_qdma_comp *dpaa2_comp,
-+		struct scatterlist *dst_sg, u32 dst_nents,
-+		struct scatterlist *src_sg, u32 src_nents)
-+{
-+	struct dpaa2_qdma_sg *src_sge;
-+	struct dpaa2_qdma_sg *dst_sge;
-+	struct qdma_sg_blk *sg_blk;
-+	struct qdma_sg_blk *sg_blk_dst;
-+	dma_addr_t src;
-+	dma_addr_t dst;
-+	uint32_t num;
-+	uint32_t blocks;
-+	uint32_t len = 0;
-+	uint32_t total_len = 0;
-+	int i, j = 0;
-+
-+	num = min(dst_nents, src_nents);
-+	blocks = num / (NUM_SG_PER_BLK - 1);
-+	if (num % (NUM_SG_PER_BLK - 1))
-+		blocks += 1;
-+	if (dpaa2_comp->sg_blk_num < blocks) {
-+		len = blocks - dpaa2_comp->sg_blk_num;
-+		for (i = 0; i < len; i++) {
-+			/* source sg blocks */
-+			sg_blk = dpaa2_qdma_get_sg_blk(dpaa2_comp, dpaa2_chan);
-+			if (!sg_blk)
-+				return 0;
-+			list_add_tail(&sg_blk->list, &dpaa2_comp->sg_src_head);
-+			/* destination sg blocks */
-+			sg_blk = dpaa2_qdma_get_sg_blk(dpaa2_comp, dpaa2_chan);
-+			if (!sg_blk)
-+				return 0;
-+			list_add_tail(&sg_blk->list, &dpaa2_comp->sg_dst_head);
-+		}
-+	} else {
-+		len = dpaa2_comp->sg_blk_num - blocks;
-+		for (i = 0; i < len; i++) {
-+			spin_lock(&dpaa2_chan->queue_lock);
-+			/* handle source sg blocks */
-+			sg_blk = list_first_entry(&dpaa2_comp->sg_src_head,
-+					struct qdma_sg_blk, list);
-+			list_del(&sg_blk->list);
-+			list_add_tail(&sg_blk->list, &dpaa2_chan->sgb_free);
-+			/* handle destination sg blocks */
-+			sg_blk = list_first_entry(&dpaa2_comp->sg_dst_head,
-+					struct qdma_sg_blk, list);
-+			list_del(&sg_blk->list);
-+			list_add_tail(&sg_blk->list, &dpaa2_chan->sgb_free);
-+			spin_unlock(&dpaa2_chan->queue_lock);
-+		}
-+	}
-+	dpaa2_comp->sg_blk_num = blocks;
-+
-+	/* get the first source sg phy address */
-+	sg_blk = list_first_entry(&dpaa2_comp->sg_src_head,
-+				struct qdma_sg_blk, list);
-+	dpaa2_comp->sge_src_bus_addr = sg_blk->blk_bus_addr;
-+	/* get the first destinaiton sg phy address */
-+	sg_blk_dst = list_first_entry(&dpaa2_comp->sg_dst_head,
-+				struct qdma_sg_blk, list);
-+	dpaa2_comp->sge_dst_bus_addr = sg_blk_dst->blk_bus_addr;
-+
-+	for (i = 0; i < blocks; i++) {
-+		src_sge = (struct dpaa2_qdma_sg *)sg_blk->blk_virt_addr;
-+		dst_sge = (struct dpaa2_qdma_sg *)sg_blk_dst->blk_virt_addr;
-+
-+		for (j = 0; j < (NUM_SG_PER_BLK - 1); j++) {
-+			len = min(sg_dma_len(dst_sg), sg_dma_len(src_sg));
-+			if (0 == len)
-+				goto fetch;
-+			total_len += len;
-+			src = sg_dma_address(src_sg);
-+			dst = sg_dma_address(dst_sg);
-+
-+			/* source SG */
-+			src_sge->addr_lo = src;
-+			src_sge->addr_hi = (src >> 32);
-+			src_sge->data_len.data_len_sl0 = len;
-+			src_sge->ctrl.sl = QDMA_SG_SL_LONG;
-+			src_sge->ctrl.fmt = QDMA_SG_FMT_SDB;
-+			/* destination SG */
-+			dst_sge->addr_lo = dst;
-+			dst_sge->addr_hi = (dst >> 32);
-+			dst_sge->data_len.data_len_sl0 = len;
-+			dst_sge->ctrl.sl = QDMA_SG_SL_LONG;
-+			dst_sge->ctrl.fmt = QDMA_SG_FMT_SDB;
-+fetch:
-+			num--;
-+			if (0 == num) {
-+				src_sge->ctrl.f = QDMA_SG_F;
-+				dst_sge->ctrl.f = QDMA_SG_F;
-+				goto end;
-+			}
-+			dst_sg = sg_next(dst_sg);
-+			src_sg = sg_next(src_sg);
-+			src_sge++;
-+			dst_sge++;
-+			if (j == (NUM_SG_PER_BLK - 2)) {
-+				/* for next blocks, extension */
-+				sg_blk = list_next_entry(sg_blk, list);
-+				sg_blk_dst = list_next_entry(sg_blk_dst, list);
-+				src_sge->addr_lo = sg_blk->blk_bus_addr;
-+				src_sge->addr_hi = sg_blk->blk_bus_addr >> 32;
-+				src_sge->ctrl.sl = QDMA_SG_SL_LONG;
-+				src_sge->ctrl.fmt = QDMA_SG_FMT_SGTE;
-+				dst_sge->addr_lo = sg_blk_dst->blk_bus_addr;
-+				dst_sge->addr_hi =
-+					sg_blk_dst->blk_bus_addr >> 32;
-+				dst_sge->ctrl.sl = QDMA_SG_SL_LONG;
-+				dst_sge->ctrl.fmt = QDMA_SG_FMT_SGTE;
-+			}
-+		}
-+	}
-+
-+end:
-+	return total_len;
-+}
-+
 +static enum dma_status dpaa2_qdma_tx_status(struct dma_chan *chan,
 +		dma_cookie_t cookie, struct dma_tx_state *txstate)
 +{
@@ -1245,7 +1055,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +		ppriv->nctx.desired_cpu = 1;
 +		ppriv->nctx.id = ppriv->rsp_fqid;
 +		ppriv->nctx.cb = dpaa2_qdma_fqdan_cb;
-+		err = dpaa2_io_service_register(NULL, &ppriv->nctx);
++		err = dpaa2_io_service_register(NULL, &ppriv->nctx, dev);
 +		if (err) {
 +			dev_err(dev, "Notification register failed\n");
 +			goto err_service;
@@ -1263,11 +1073,11 @@ Signed-off-by: Biwen Li <[email protected]>
 +	return 0;
 +
 +err_store:
-+	dpaa2_io_service_deregister(NULL, &ppriv->nctx);
++	dpaa2_io_service_deregister(NULL, &ppriv->nctx, dev);
 +err_service:
 +	ppriv--;
 +	while (ppriv >= priv->ppriv) {
-+		dpaa2_io_service_deregister(NULL, &ppriv->nctx);
++		dpaa2_io_service_deregister(NULL, &ppriv->nctx, dev);
 +		dpaa2_io_store_destroy(ppriv->store);
 +		ppriv--;
 +	}
@@ -1288,10 +1098,11 @@ Signed-off-by: Biwen Li <[email protected]>
 +static void __cold dpaa2_dpdmai_dpio_free(struct dpaa2_qdma_priv *priv)
 +{
 +	struct dpaa2_qdma_priv_per_prio *ppriv = priv->ppriv;
++	struct device *dev = priv->dev;
 +	int i;
 +
 +	for (i = 0; i < priv->num_pairs; i++) {
-+		dpaa2_io_service_deregister(NULL, &ppriv->nctx);
++		dpaa2_io_service_deregister(NULL, &ppriv->nctx, dev);
 +		ppriv++;
 +	}
 +}
@@ -1348,22 +1159,6 @@ Signed-off-by: Biwen Li <[email protected]>
 +	return err;
 +}
 +
-+static void __cold dpaa2_dpdmai_free_pool(struct dpaa2_qdma_chan *qchan,
-+							struct list_head *head)
-+{
-+	struct qdma_sg_blk *sgb_tmp, *_sgb_tmp;
-+	/* free the QDMA SG pool block */
-+	list_for_each_entry_safe(sgb_tmp, _sgb_tmp, head, list) {
-+		sgb_tmp->blk_virt_addr = (void *)((struct qdma_sg_blk *)
-+						sgb_tmp->blk_virt_addr - 1);
-+		sgb_tmp->blk_bus_addr = sgb_tmp->blk_bus_addr
-+							- sizeof(*sgb_tmp);
-+		dma_pool_free(qchan->sg_blk_pool, sgb_tmp->blk_virt_addr,
-+						sgb_tmp->blk_bus_addr);
-+	}
-+
-+}
-+
 +static void __cold dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan,
 +						struct list_head *head)
 +{
@@ -1374,10 +1169,6 @@ Signed-off-by: Biwen Li <[email protected]>
 +		dma_pool_free(qchan->fd_pool,
 +			comp_tmp->fd_virt_addr,
 +			comp_tmp->fd_bus_addr);
-+		/* free the SG source block on comp */
-+		dpaa2_dpdmai_free_pool(qchan, &comp_tmp->sg_src_head);
-+		/* free the SG destination block on comp */
-+		dpaa2_dpdmai_free_pool(qchan, &comp_tmp->sg_dst_head);
 +		list_del(&comp_tmp->list);
 +		kfree(comp_tmp);
 +	}
@@ -1395,9 +1186,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +		qchan = &dpaa2_qdma->chans[i];
 +		dpaa2_dpdmai_free_comp(qchan, &qchan->comp_used);
 +		dpaa2_dpdmai_free_comp(qchan, &qchan->comp_free);
-+		dpaa2_dpdmai_free_pool(qchan, &qchan->sgb_free);
 +		dma_pool_destroy(qchan->fd_pool);
-+		dma_pool_destroy(qchan->sg_blk_pool);
 +	}
 +}
 +
@@ -1418,15 +1207,10 @@ Signed-off-by: Biwen Li <[email protected]>
 +					dev, FD_POOL_SIZE, 32, 0);
 +		if (!dpaa2_chan->fd_pool)
 +			return -1;
-+		dpaa2_chan->sg_blk_pool = dma_pool_create("sg_blk_pool",
-+					dev, SG_POOL_SIZE, 32, 0);
-+		if (!dpaa2_chan->sg_blk_pool)
-+			return -1;
 +
 +		spin_lock_init(&dpaa2_chan->queue_lock);
 +		INIT_LIST_HEAD(&dpaa2_chan->comp_used);
 +		INIT_LIST_HEAD(&dpaa2_chan->comp_free);
-+		INIT_LIST_HEAD(&dpaa2_chan->sgb_free);
 +	}
 +	return 0;
 +}
@@ -1451,7 +1235,10 @@ Signed-off-by: Biwen Li <[email protected]>
 +	/* obtain a MC portal */
 +	err = fsl_mc_portal_allocate(dpdmai_dev, 0, &priv->mc_io);
 +	if (err) {
-+		dev_err(dev, "MC portal allocation failed\n");
++		if (err == -ENXIO)
++			err = -EPROBE_DEFER;
++		else
++			dev_err(dev, "MC portal allocation failed\n");
 +		goto err_mcportal;
 +	}
 +
@@ -1500,6 +1287,11 @@ Signed-off-by: Biwen Li <[email protected]>
 +		goto err_reg;
 +	}
 +
++	if (soc_device_match(soc_fixup_tuning))
++		dpaa2_qdma->qdma_wrtype_fixup = true;
++	else
++		dpaa2_qdma->qdma_wrtype_fixup = false;
++
 +	dma_cap_set(DMA_PRIVATE, dpaa2_qdma->dma_dev.cap_mask);
 +	dma_cap_set(DMA_SLAVE, dpaa2_qdma->dma_dev.cap_mask);
 +	dma_cap_set(DMA_MEMCPY, dpaa2_qdma->dma_dev.cap_mask);
@@ -1602,7 +1394,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +MODULE_LICENSE("Dual BSD/GPL");
 --- /dev/null
 +++ b/drivers/dma/dpaa2-qdma/dpaa2-qdma.h
-@@ -0,0 +1,227 @@
+@@ -0,0 +1,181 @@
 +/* Copyright 2015 NXP Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -1641,7 +1433,6 @@ Signed-off-by: Biwen Li <[email protected]>
 +
 +#define DPAA2_QDMA_STORE_SIZE 16
 +#define NUM_CH 8
-+#define NUM_SG_PER_BLK	16
 +
 +#define QDMA_DMR_OFFSET	0x0
 +#define QDMA_DQ_EN (0 << 30)
@@ -1672,37 +1463,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +/* Destination descriptor command write transaction type for RBP=0:
 + coherent copy of cacheable memory */
 +#define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28)
-+
-+#define QDMA_SG_FMT_SDB		0x0 /* single data buffer */
-+#define QDMA_SG_FMT_FDS		0x1 /* frame data section */
-+#define QDMA_SG_FMT_SGTE	0x2 /* SGT extension */
-+#define QDMA_SG_SL_SHORT	0x1 /* short length */
-+#define QDMA_SG_SL_LONG		0x0 /* short length */
-+#define QDMA_SG_F		0x1 /* last sg entry */
-+struct dpaa2_qdma_sg {
-+	uint32_t addr_lo;		/* address 0:31 */
-+	uint32_t addr_hi:17;	/* address 32:48 */
-+	uint32_t rsv:15;
-+	union {
-+		uint32_t data_len_sl0; /* SL=0, the long format */
-+		struct {
-+			uint32_t len:17; /* SL=1, the short format */
-+			uint32_t reserve:3;
-+			uint32_t sf:1;
-+			uint32_t sr:1;
-+			uint32_t size:10; /* buff size */
-+		} data_len_sl1;
-+	} data_len;	/* AVAIL_LENGTH */
-+	struct {
-+		uint32_t bpid:14;
-+		uint32_t ivp:1;
-+		uint32_t mbt:1;
-+		uint32_t offset:12;
-+		uint32_t fmt:2;
-+		uint32_t sl:1;
-+		uint32_t f:1;
-+	} ctrl;
-+} __attribute__((__packed__));
++#define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28)
 +
 +#define QMAN_FD_FMT_ENABLE (1) /* frame list table enable */
 +#define QMAN_FD_BMT_ENABLE (1 << 15) /* bypass memory translation */
@@ -1710,8 +1471,6 @@ Signed-off-by: Biwen Li <[email protected]>
 +#define QMAN_FD_SL_DISABLE (0 << 14) /* short lengthe disabled */
 +#define QMAN_FD_SL_ENABLE (1 << 14) /* short lengthe enabled */
 +
-+#define QDMA_SB_FRAME (0 << 28) /* single frame */
-+#define QDMA_SG_FRAME (2 << 28) /* scatter gather frames */
 +#define QDMA_FINAL_BIT_DISABLE (0 << 31) /* final bit disable */
 +#define QDMA_FINAL_BIT_ENABLE (1 << 31) /* final bit enable */
 +
@@ -1747,35 +1506,19 @@ Signed-off-by: Biwen Li <[email protected]>
 +	struct mutex            dpaa2_queue_mutex;
 +	spinlock_t		queue_lock;
 +	struct dma_pool		*fd_pool;
-+	struct dma_pool		*sg_blk_pool;
 +
 +	struct list_head	comp_used;
 +	struct list_head	comp_free;
 +
-+	struct list_head	sgb_free;
-+};
-+
-+struct qdma_sg_blk {
-+	dma_addr_t	blk_bus_addr;
-+	void		*blk_virt_addr;
-+	struct list_head	list;
 +};
 +
 +struct dpaa2_qdma_comp {
 +	dma_addr_t		fd_bus_addr;
 +	dma_addr_t		fl_bus_addr;
 +	dma_addr_t		desc_bus_addr;
-+	dma_addr_t		sge_src_bus_addr;
-+	dma_addr_t		sge_dst_bus_addr;
 +	void			*fd_virt_addr;
 +	void			*fl_virt_addr;
 +	void			*desc_virt_addr;
-+	void			*sg_src_virt_addr;
-+	void			*sg_dst_virt_addr;
-+	struct qdma_sg_blk	*sg_blk;
-+	uint32_t		sg_blk_num;
-+	struct list_head	sg_src_head;
-+	struct list_head	sg_dst_head;
 +	struct dpaa2_qdma_chan	*qchan;
 +	struct virt_dma_desc	vdesc;
 +	struct list_head	list;
@@ -1785,6 +1528,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	struct dma_device	dma_dev;
 +	u32			n_chans;
 +	struct dpaa2_qdma_chan	chans[NUM_CH];
++	bool			qdma_wrtype_fixup;
 +
 +	struct dpaa2_qdma_priv *priv;
 +};
@@ -1821,14 +1565,16 @@ Signed-off-by: Biwen Li <[email protected]>
 +	struct dpaa2_qdma_priv *priv;
 +};
 +
++static struct soc_device_attribute soc_fixup_tuning[] = {
++	{ .family = "QorIQ LX2160A"},
++	{ },
++};
++
 +/* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */
 +#define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \
 +		sizeof(struct dpaa2_fl_entry) * 3 + \
 +		sizeof(struct dpaa2_qdma_sd_d) * 2)
 +
-+/* qdma_sg_blk + 16 SGs */
-+#define SG_POOL_SIZE (sizeof(struct qdma_sg_blk) +\
-+		sizeof(struct dpaa2_qdma_sg) * NUM_SG_PER_BLK)
 +#endif /* __DPAA2_QDMA_H */
 --- /dev/null
 +++ b/drivers/dma/dpaa2-qdma/dpdmai.c
@@ -3097,6 +2843,143 @@ Signed-off-by: Biwen Li <[email protected]>
 +	MC_RSP_OP(cmd, 1, 0,  32, uint32_t,  attr->fqid)
 +
 +#endif /* _FSL_DPDMAI_CMD_H */
+--- a/drivers/dma/fsl-edma.c
++++ b/drivers/dma/fsl-edma.c
+@@ -146,6 +146,8 @@ struct fsl_edma_slave_config {
+ 	u32				dev_addr;
+ 	u32				burst;
+ 	u32				attr;
++	dma_addr_t			dma_dev_addr;
++	enum dma_data_direction		dma_dir;
+ };
+ 
+ struct fsl_edma_chan {
+@@ -342,6 +344,53 @@ static int fsl_edma_resume(struct dma_ch
+ 	return 0;
+ }
+ 
++static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan)
++{
++	if (fsl_chan->fsc.dma_dir != DMA_NONE)
++		dma_unmap_resource(fsl_chan->vchan.chan.device->dev,
++				   fsl_chan->fsc.dma_dev_addr,
++				   fsl_chan->fsc.burst, fsl_chan->fsc.dma_dir, 0);
++	fsl_chan->fsc.dma_dir = DMA_NONE;
++}
++
++static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan,
++				    enum dma_transfer_direction dir)
++{
++	struct device *dev = fsl_chan->vchan.chan.device->dev;
++	enum dma_data_direction dma_dir;
++
++	switch (dir) {
++	case DMA_MEM_TO_DEV:
++		dma_dir = DMA_FROM_DEVICE;
++		break;
++	case DMA_DEV_TO_MEM:
++		dma_dir = DMA_TO_DEVICE;
++		break;
++	case DMA_DEV_TO_DEV:
++		dma_dir = DMA_BIDIRECTIONAL;
++		break;
++	default:
++		dma_dir = DMA_NONE;
++		break;
++	}
++
++	/* Already mapped for this config? */
++	if (fsl_chan->fsc.dma_dir == dma_dir)
++		return true;
++
++	fsl_edma_unprep_slave_dma(fsl_chan);
++	fsl_chan->fsc.dma_dev_addr = dma_map_resource(dev,
++						      fsl_chan->fsc.dev_addr,
++						      fsl_chan->fsc.burst,
++						      dma_dir, 0);
++	if (dma_mapping_error(dev, fsl_chan->fsc.dma_dev_addr))
++		return false;
++
++	fsl_chan->fsc.dma_dir = dma_dir;
++
++	return true;
++}
++
+ static int fsl_edma_slave_config(struct dma_chan *chan,
+ 				 struct dma_slave_config *cfg)
+ {
+@@ -361,6 +410,7 @@ static int fsl_edma_slave_config(struct
+ 	} else {
+ 			return -EINVAL;
+ 	}
++	fsl_edma_unprep_slave_dma(fsl_chan);
+ 	return 0;
+ }
+ 
+@@ -553,6 +603,9 @@ static struct dma_async_tx_descriptor *f
+ 	if (!is_slave_direction(fsl_chan->fsc.dir))
+ 		return NULL;
+ 
++	if (!fsl_edma_prep_slave_dma(fsl_chan, fsl_chan->fsc.dir))
++		return NULL;
++
+ 	sg_len = buf_len / period_len;
+ 	fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
+ 	if (!fsl_desc)
+@@ -572,11 +625,11 @@ static struct dma_async_tx_descriptor *f
+ 
+ 		if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
+ 			src_addr = dma_buf_next;
+-			dst_addr = fsl_chan->fsc.dev_addr;
++			dst_addr = fsl_chan->fsc.dma_dev_addr;
+ 			soff = fsl_chan->fsc.addr_width;
+ 			doff = 0;
+ 		} else {
+-			src_addr = fsl_chan->fsc.dev_addr;
++			src_addr = fsl_chan->fsc.dma_dev_addr;
+ 			dst_addr = dma_buf_next;
+ 			soff = 0;
+ 			doff = fsl_chan->fsc.addr_width;
+@@ -606,6 +659,9 @@ static struct dma_async_tx_descriptor *f
+ 	if (!is_slave_direction(fsl_chan->fsc.dir))
+ 		return NULL;
+ 
++	if (!fsl_edma_prep_slave_dma(fsl_chan, fsl_chan->fsc.dir))
++		return NULL;
++
+ 	fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
+ 	if (!fsl_desc)
+ 		return NULL;
+@@ -618,11 +674,11 @@ static struct dma_async_tx_descriptor *f
+ 
+ 		if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
+ 			src_addr = sg_dma_address(sg);
+-			dst_addr = fsl_chan->fsc.dev_addr;
++			dst_addr = fsl_chan->fsc.dma_dev_addr;
+ 			soff = fsl_chan->fsc.addr_width;
+ 			doff = 0;
+ 		} else {
+-			src_addr = fsl_chan->fsc.dev_addr;
++			src_addr = fsl_chan->fsc.dma_dev_addr;
+ 			dst_addr = sg_dma_address(sg);
+ 			soff = 0;
+ 			doff = fsl_chan->fsc.addr_width;
+@@ -802,6 +858,7 @@ static void fsl_edma_free_chan_resources
+ 	fsl_edma_chan_mux(fsl_chan, 0, false);
+ 	fsl_chan->edesc = NULL;
+ 	vchan_get_all_descriptors(&fsl_chan->vchan, &head);
++	fsl_edma_unprep_slave_dma(fsl_chan);
+ 	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+ 
+ 	vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
+@@ -937,6 +994,7 @@ static int fsl_edma_probe(struct platfor
+ 		fsl_chan->slave_id = 0;
+ 		fsl_chan->idle = true;
+ 		fsl_chan->vchan.desc_free = fsl_edma_free_desc;
++		fsl_chan->fsc.dma_dir = DMA_NONE;
+ 		vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
+ 
+ 		edma_writew(fsl_edma, 0x0, fsl_edma->membase + EDMA_TCD_CSR(i));
 --- /dev/null
 +++ b/drivers/dma/fsl-qdma.c
 @@ -0,0 +1,1278 @@

target/linux/layerscape/patches-4.14/803-flextimer-support-layerscape.patch

@@ -1,18 +1,19 @@
-From d586effc9b71ddf240fb294b1ab1205bbe6fec4b Mon Sep 17 00:00:00 2001
+From 0f31298eb0a9b2cd7990b709ff18229fadfa474b Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:26:32 +0800
-Subject: [PATCH 20/40] flextimer: support layerscape
+Date: Wed, 17 Apr 2019 18:58:38 +0800
+Subject: [PATCH] flextimer: support layerscape
+
 This is an integrated patch of flextimer for layerscape
 
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Meng Yi <[email protected]>
 Signed-off-by: Ran Wang <[email protected]>
 Signed-off-by: Zhang Ying-22455 <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 ---
  .../bindings/soc/fsl/layerscape/ftm-alarm.txt |  32 ++
  drivers/clocksource/fsl_ftm_timer.c           |   8 +-
- drivers/soc/fsl/layerscape/ftm_alarm.c        | 375 ++++++++++++++++++
- 3 files changed, 411 insertions(+), 4 deletions(-)
+ drivers/soc/fsl/layerscape/ftm_alarm.c        | 382 ++++++++++++++++++
+ 3 files changed, 418 insertions(+), 4 deletions(-)
  create mode 100644 Documentation/devicetree/bindings/soc/fsl/layerscape/ftm-alarm.txt
  create mode 100644 drivers/soc/fsl/layerscape/ftm_alarm.c
 
@@ -71,7 +72,7 @@ Signed-off-by: Biwen Li <[email protected]>
  static inline void ftm_irq_enable(void __iomem *base)
 --- /dev/null
 +++ b/drivers/soc/fsl/layerscape/ftm_alarm.c
-@@ -0,0 +1,375 @@
+@@ -0,0 +1,382 @@
 +/*
 + * Freescale FlexTimer Module (FTM) Alarm driver.
 + *
@@ -159,6 +160,11 @@ Signed-off-by: Biwen Li <[email protected]>
 +	.flextimer_set_bit = 0x4000,
 +};
 +
++static struct rcpm_cfg lx2160a_rcpm_cfg = {
++	.big_endian = LITTLE_ENDIAN,
++	.flextimer_set_bit = 0x4000,
++};
++
 +static const struct of_device_id ippdexpcr_of_match[] = {
 +	{ .compatible = "fsl,ls1012a-ftm-alarm", .data = &ls1012a_rcpm_cfg},
 +	{ .compatible = "fsl,ls1021a-ftm-alarm", .data = &ls1021a_rcpm_cfg},
@@ -166,6 +172,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	{ .compatible = "fsl,ls1046a-ftm-alarm", .data = &ls1046a_rcpm_cfg},
 +	{ .compatible = "fsl,ls1088a-ftm-alarm", .data = &ls1088a_rcpm_cfg},
 +	{ .compatible = "fsl,ls208xa-ftm-alarm", .data = &ls208xa_rcpm_cfg},
++	{ .compatible = "fsl,lx2160a-ftm-alarm", .data = &lx2160a_rcpm_cfg},
 +	{},
 +};
 +MODULE_DEVICE_TABLE(of, ippdexpcr_of_match);
@@ -429,6 +436,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +	{ .compatible = "fsl,ls1046a-ftm-alarm", },
 +	{ .compatible = "fsl,ls1088a-ftm-alarm", },
 +	{ .compatible = "fsl,ls208xa-ftm-alarm", },
++	{ .compatible = "fsl,lx2160a-ftm-alarm", },
 +	{ .compatible = "fsl,ftm-timer", },
 +	{ },
 +};

target/linux/layerscape/patches-4.14/804-i2c-support-layerscape.patch

@@ -1,15 +1,19 @@
-From 4f22b58a2f809aff55aa9321c9100b0caf3b6694 Mon Sep 17 00:00:00 2001
+From 3f7d59061c38287bdc2fec2e94b4df9e6e62dbc6 Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:26:36 +0800
-Subject: [PATCH 21/40] i2c: support layerscape
+Date: Wed, 17 Apr 2019 18:58:39 +0800
+Subject: [PATCH] i2c: support layerscape
+
 This is an integrated patch of i2c for layerscape
 
-Signed-off-by: Zhang Ying-22455 <[email protected]>
 Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Laurentiu Tudor <[email protected]>
+Signed-off-by: Oleksij Rempel <[email protected]>
+Signed-off-by: Wolfram Sang <[email protected]>
+Signed-off-by: Zhang Ying-22455 <[email protected]>
 ---
- drivers/i2c/busses/i2c-imx.c        | 193 ++++++++++++++++++++++++++++
- drivers/i2c/muxes/i2c-mux-pca954x.c |  44 ++++++-
- 2 files changed, 236 insertions(+), 1 deletion(-)
+ drivers/i2c/busses/i2c-imx.c        | 245 +++++++++++++++++++++++++---
+ drivers/i2c/muxes/i2c-mux-pca954x.c |  44 ++++-
+ 2 files changed, 268 insertions(+), 21 deletions(-)
 
 --- a/drivers/i2c/busses/i2c-imx.c
 +++ b/drivers/i2c/busses/i2c-imx.c
@@ -93,7 +97,84 @@ Signed-off-by: Biwen Li <[email protected]>
  };
  
  static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
-@@ -878,6 +937,78 @@ static int i2c_imx_read(struct imx_i2c_s
+@@ -281,8 +340,8 @@ static inline unsigned char imx_i2c_read
+ }
+ 
+ /* Functions for DMA support */
+-static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
+-						dma_addr_t phy_addr)
++static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
++			       dma_addr_t phy_addr)
+ {
+ 	struct imx_i2c_dma *dma;
+ 	struct dma_slave_config dma_sconfig;
+@@ -291,11 +350,13 @@ static void i2c_imx_dma_request(struct i
+ 
+ 	dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
+ 	if (!dma)
+-		return;
++		return -ENOMEM;
+ 
+-	dma->chan_tx = dma_request_slave_channel(dev, "tx");
+-	if (!dma->chan_tx) {
+-		dev_dbg(dev, "can't request DMA tx channel\n");
++	dma->chan_tx = dma_request_chan(dev, "tx");
++	if (IS_ERR(dma->chan_tx)) {
++		ret = PTR_ERR(dma->chan_tx);
++		if (ret != -ENODEV && ret != -EPROBE_DEFER)
++			dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
+ 		goto fail_al;
+ 	}
+ 
+@@ -306,13 +367,15 @@ static void i2c_imx_dma_request(struct i
+ 	dma_sconfig.direction = DMA_MEM_TO_DEV;
+ 	ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
+ 	if (ret < 0) {
+-		dev_dbg(dev, "can't configure tx channel\n");
++		dev_err(dev, "can't configure tx channel (%d)\n", ret);
+ 		goto fail_tx;
+ 	}
+ 
+-	dma->chan_rx = dma_request_slave_channel(dev, "rx");
+-	if (!dma->chan_rx) {
+-		dev_dbg(dev, "can't request DMA rx channel\n");
++	dma->chan_rx = dma_request_chan(dev, "rx");
++	if (IS_ERR(dma->chan_rx)) {
++		ret = PTR_ERR(dma->chan_rx);
++		if (ret != -ENODEV && ret != -EPROBE_DEFER)
++			dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
+ 		goto fail_tx;
+ 	}
+ 
+@@ -323,7 +386,7 @@ static void i2c_imx_dma_request(struct i
+ 	dma_sconfig.direction = DMA_DEV_TO_MEM;
+ 	ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
+ 	if (ret < 0) {
+-		dev_dbg(dev, "can't configure rx channel\n");
++		dev_err(dev, "can't configure rx channel (%d)\n", ret);
+ 		goto fail_rx;
+ 	}
+ 
+@@ -332,7 +395,7 @@ static void i2c_imx_dma_request(struct i
+ 	dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
+ 		dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
+ 
+-	return;
++	return 0;
+ 
+ fail_rx:
+ 	dma_release_channel(dma->chan_rx);
+@@ -340,7 +403,8 @@ fail_tx:
+ 	dma_release_channel(dma->chan_tx);
+ fail_al:
+ 	devm_kfree(dev, dma);
+-	dev_info(dev, "can't use DMA, using PIO instead.\n");
++	/* return successfully if there is no dma support */
++	return ret == -ENODEV ? 0 : ret;
+ }
+ 
+ static void i2c_imx_dma_callback(void *arg)
+@@ -878,6 +942,78 @@ static int i2c_imx_read(struct imx_i2c_s
  	return 0;
  }
  
@@ -172,7 +253,7 @@ Signed-off-by: Biwen Li <[email protected]>
  static int i2c_imx_xfer(struct i2c_adapter *adapter,
  						struct i2c_msg *msgs, int num)
  {
-@@ -888,6 +1019,19 @@ static int i2c_imx_xfer(struct i2c_adapt
+@@ -888,6 +1024,19 @@ static int i2c_imx_xfer(struct i2c_adapt
  
  	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  
@@ -192,7 +273,7 @@ Signed-off-by: Biwen Li <[email protected]>
  	result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
  	if (result < 0)
  		goto out;
-@@ -1030,6 +1174,50 @@ static int i2c_imx_init_recovery_info(st
+@@ -1030,6 +1179,50 @@ static int i2c_imx_init_recovery_info(st
  	return 0;
  }
  
@@ -243,7 +324,7 @@ Signed-off-by: Biwen Li <[email protected]>
  static u32 i2c_imx_func(struct i2c_adapter *adapter)
  {
  	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
-@@ -1085,6 +1273,11 @@ static int i2c_imx_probe(struct platform
+@@ -1085,6 +1278,11 @@ static int i2c_imx_probe(struct platform
  	i2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
  	i2c_imx->base			= base;
  
@@ -255,6 +336,54 @@ Signed-off-by: Biwen Li <[email protected]>
  	/* Get I2C clock */
  	i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
  	if (IS_ERR(i2c_imx->clk)) {
+@@ -1103,7 +1301,8 @@ static int i2c_imx_probe(struct platform
+ 				pdev->name, i2c_imx);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "can't claim irq %d\n", irq);
+-		goto clk_disable;
++		clk_disable_unprepare(i2c_imx->clk);
++		return ret;
+ 	}
+ 
+ 	/* Init queue */
+@@ -1150,25 +1349,31 @@ static int i2c_imx_probe(struct platform
+ 	pm_runtime_mark_last_busy(&pdev->dev);
+ 	pm_runtime_put_autosuspend(&pdev->dev);
+ 
++	/* Init DMA config if supported */
++	ret = i2c_imx_dma_request(i2c_imx, phy_addr);
++	if (ret) {
++		if (ret != -EPROBE_DEFER)
++			dev_info(&pdev->dev, "can't use DMA, using PIO instead.\n");
++		else
++			goto del_adapter;
++	}
++
+ 	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
+ 	dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
+ 	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
+ 		i2c_imx->adapter.name);
+-	dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
+-
+-	/* Init DMA config if supported */
+-	i2c_imx_dma_request(i2c_imx, phy_addr);
+ 
++	dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
+ 	return 0;   /* Return OK */
+ 
++del_adapter:
++	i2c_del_adapter(&i2c_imx->adapter);
+ rpm_disable:
+ 	pm_runtime_put_noidle(&pdev->dev);
+ 	pm_runtime_disable(&pdev->dev);
+ 	pm_runtime_set_suspended(&pdev->dev);
+ 	pm_runtime_dont_use_autosuspend(&pdev->dev);
+ 
+-clk_disable:
+-	clk_disable_unprepare(i2c_imx->clk);
+ 	return ret;
+ }
+ 
 --- a/drivers/i2c/muxes/i2c-mux-pca954x.c
 +++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
 @@ -85,6 +85,7 @@ struct pca954x {

target/linux/layerscape/patches-4.14/805-qe-support-layerscape.patch

@@ -1,16 +1,17 @@
-From cfa7e6ed5a6ba529097ae8a50ed2c8fa12b4cad0 Mon Sep 17 00:00:00 2001
+From f4e3e2cf6484056225385d717da4e9c4f8613935 Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:27:13 +0800
-Subject: [PATCH 22/40] qe: support layerscape
+Date: Wed, 17 Apr 2019 18:58:58 +0800
+Subject: [PATCH] qe: support layerscape
+
 This is an integrated patch of qe for layerscape
 
-Signed-off-by: Zhao Qiang <[email protected]
 Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Zhao Qiang <[email protected]>
 ---
  .../fsl/qe/qe_ic.c => irqchip/irq-qeic.c}     | 389 +++++++++++-------
  drivers/soc/fsl/qe/Kconfig                    |   2 +-
  drivers/soc/fsl/qe/Makefile                   |   2 +-
- drivers/soc/fsl/qe/qe.c                       |  78 ++--
+ drivers/soc/fsl/qe/qe.c                       |  80 ++--
  drivers/soc/fsl/qe/qe_ic.h                    | 103 -----
  drivers/soc/fsl/qe/qe_io.c                    |  42 +-
  drivers/soc/fsl/qe/qe_tdm.c                   |   8 +-
@@ -19,7 +20,7 @@ Signed-off-by: Biwen Li <[email protected]>
  drivers/tty/serial/ucc_uart.c                 |   1 +
  include/soc/fsl/qe/qe.h                       |   1 -
  include/soc/fsl/qe/qe_ic.h                    | 139 -------
- 12 files changed, 357 insertions(+), 492 deletions(-)
+ 12 files changed, 359 insertions(+), 492 deletions(-)
  rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (54%)
  delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
  delete mode 100644 include/soc/fsl/qe/qe_ic.h
@@ -1266,7 +1267,16 @@ Signed-off-by: Biwen Li <[email protected]>
  
  	of_node_put(qe);
  
-@@ -236,7 +254,7 @@ int qe_setbrg(enum qe_clock brg, unsigne
+@@ -229,14 +247,16 @@ int qe_setbrg(enum qe_clock brg, unsigne
+ 	/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
+ 	   that the BRG divisor must be even if you're not using divide-by-16
+ 	   mode. */
++#ifdef CONFIG_PPC
+ 	if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
+ 		if (!div16 && (divisor & 1) && (divisor > 3))
+ 			divisor++;
++#endif
+ 
  	tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
  		QE_BRGC_ENABLE | div16;
  
@@ -1275,7 +1285,7 @@ Signed-off-by: Biwen Li <[email protected]>
  
  	return 0;
  }
-@@ -370,9 +388,9 @@ static int qe_sdma_init(void)
+@@ -370,9 +390,9 @@ static int qe_sdma_init(void)
  			return -ENOMEM;
  	}
  
@@ -1288,7 +1298,7 @@ Signed-off-by: Biwen Li <[email protected]>
  
  	return 0;
  }
-@@ -410,14 +428,14 @@ static void qe_upload_microcode(const vo
+@@ -410,14 +430,14 @@ static void qe_upload_microcode(const vo
  			"uploading microcode '%s'\n", ucode->id);
  
  	/* Use auto-increment */
@@ -1307,7 +1317,7 @@ Signed-off-by: Biwen Li <[email protected]>
  }
  
  /*
-@@ -502,7 +520,7 @@ int qe_upload_firmware(const struct qe_f
+@@ -502,7 +522,7 @@ int qe_upload_firmware(const struct qe_f
  	 * If the microcode calls for it, split the I-RAM.
  	 */
  	if (!firmware->split)
@@ -1316,7 +1326,7 @@ Signed-off-by: Biwen Li <[email protected]>
  
  	if (firmware->soc.model)
  		printk(KERN_INFO
-@@ -536,11 +554,11 @@ int qe_upload_firmware(const struct qe_f
+@@ -536,11 +556,11 @@ int qe_upload_firmware(const struct qe_f
  			u32 trap = be32_to_cpu(ucode->traps[j]);
  
  			if (trap)
@@ -1330,7 +1340,7 @@ Signed-off-by: Biwen Li <[email protected]>
  	}
  
  	qe_firmware_uploaded = 1;
-@@ -659,9 +677,9 @@ EXPORT_SYMBOL(qe_get_num_of_risc);
+@@ -659,9 +679,9 @@ EXPORT_SYMBOL(qe_get_num_of_risc);
  unsigned int qe_get_num_of_snums(void)
  {
  	struct device_node *qe;
@@ -1342,7 +1352,7 @@ Signed-off-by: Biwen Li <[email protected]>
  
  	num_of_snums = 28; /* The default number of snum for threads is 28 */
  	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
-@@ -675,9 +693,9 @@ unsigned int qe_get_num_of_snums(void)
+@@ -675,9 +695,9 @@ unsigned int qe_get_num_of_snums(void)
  			return num_of_snums;
  	}
  

target/linux/layerscape/patches-4.14/807-usb-support-layerscape.patch

@@ -1,14 +1,18 @@
-From 01b1b2989e907305d8b885468c2743f5e35e1b9a Mon Sep 17 00:00:00 2001
+From ca86ebf3fddbdfa8aecc4b887ef059948ee79621 Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Thu, 13 Dec 2018 11:15:15 +0800
+Date: Wed, 17 Apr 2019 18:59:08 +0800
 Subject: [PATCH] usb: support layerscape
 
 This is an integrated patch of usb for layerscape
 
+Signed-off-by: Anurag Kumar Vulisha <[email protected]>
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Catalin Marinas <[email protected]>
 Signed-off-by: Changming Huang <[email protected]>
 Signed-off-by: Felipe Balbi <[email protected]>
+Signed-off-by: Greg Kroah-Hartman <[email protected]>
 Signed-off-by: Li Yang <[email protected]>
+Signed-off-by: Marc Zyngier <[email protected]>
 Signed-off-by: Nikhil Badola <[email protected]>
 Signed-off-by: Rajesh Bhagat <[email protected]>
 Signed-off-by: Ramneek Mehresh <[email protected]>
@@ -16,50 +20,37 @@ Signed-off-by: Ran Wang <[email protected]>
 Signed-off-by: Roger Quadros <[email protected]>
 Signed-off-by: Shengzhou Liu <[email protected]>
 Signed-off-by: Suresh Gupta <[email protected]>
-Signed-off-by: yinbo.zhu <[email protected]>
-Signed-off-by: Zhao Chenhui <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Yangbo Lu <[email protected]>
+Signed-off-by: Yinbo Zhu <[email protected]>
+Signed-off-by: Zhao Chenhui <[email protected]>
 ---
- .../devicetree/bindings/usb/dwc3.txt          |   2 +
- arch/arm64/include/asm/io.h                   |  28 ++
- drivers/usb/common/common.c                   |  50 ++++
- drivers/usb/core/usb.c                        |   1 +
- drivers/usb/dwc3/core.c                       | 104 +++++++
- drivers/usb/dwc3/core.h                       |  44 +++
- drivers/usb/dwc3/ep0.c                        |   4 +-
- drivers/usb/dwc3/gadget.c                     |   7 +
- drivers/usb/dwc3/host.c                       |   9 +
- drivers/usb/gadget/udc/fsl_udc_core.c         |  46 +--
- drivers/usb/gadget/udc/fsl_usb2_udc.h         |  16 +-
- drivers/usb/host/Kconfig                      |   2 +-
- drivers/usb/host/ehci-fsl.c                   | 276 ++++++++++++++++--
- drivers/usb/host/ehci-fsl.h                   |   3 +
- drivers/usb/host/ehci-hub.c                   |   2 +
- drivers/usb/host/ehci.h                       |   3 +
- drivers/usb/host/fsl-mph-dr-of.c              |  11 +
- drivers/usb/host/xhci-hub.c                   |  22 ++
- drivers/usb/host/xhci-plat.c                  |  16 +-
- drivers/usb/host/xhci-ring.c                  |  28 +-
- drivers/usb/host/xhci.c                       |  39 ++-
- drivers/usb/host/xhci.h                       |   6 +-
- drivers/usb/phy/phy-fsl-usb.c                 |  59 +++-
- drivers/usb/phy/phy-fsl-usb.h                 |   8 +
- include/linux/usb.h                           |   1 +
- include/linux/usb/of.h                        |   2 +
- 26 files changed, 704 insertions(+), 85 deletions(-)
+ arch/arm64/include/asm/io.h           |  28 +++
+ drivers/usb/common/common.c           |  50 +++++
+ drivers/usb/core/usb.c                |   1 +
+ drivers/usb/dwc3/core.c               | 167 ++++++++++++++++
+ drivers/usb/dwc3/core.h               |  58 ++++++
+ drivers/usb/dwc3/ep0.c                |   4 +-
+ drivers/usb/dwc3/gadget.c             |   7 +
+ drivers/usb/dwc3/host.c               |   9 +
+ drivers/usb/gadget/udc/fsl_udc_core.c |  46 +++--
+ drivers/usb/gadget/udc/fsl_usb2_udc.h |  16 +-
+ drivers/usb/host/Kconfig              |   2 +-
+ drivers/usb/host/ehci-fsl.c           | 276 +++++++++++++++++++++++---
+ drivers/usb/host/ehci-fsl.h           |   3 +
+ drivers/usb/host/ehci-hub.c           |   2 +
+ drivers/usb/host/ehci.h               |   3 +
+ drivers/usb/host/fsl-mph-dr-of.c      |  11 +
+ drivers/usb/host/xhci-hub.c           |  22 ++
+ drivers/usb/host/xhci-plat.c          |  16 +-
+ drivers/usb/host/xhci-ring.c          |  28 ++-
+ drivers/usb/host/xhci.c               |  37 +++-
+ drivers/usb/host/xhci.h               |  10 +-
+ drivers/usb/phy/phy-fsl-usb.c         |  59 ++++--
+ drivers/usb/phy/phy-fsl-usb.h         |   8 +
+ include/linux/usb.h                   |   1 +
+ include/linux/usb/of.h                |   2 +
+ 25 files changed, 780 insertions(+), 86 deletions(-)
 
---- a/Documentation/devicetree/bindings/usb/dwc3.txt
-+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
-@@ -47,6 +47,8 @@ Optional properties:
- 			from P0 to P1/P2/P3 without delay.
-  - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
- 			during HS transmit.
-+ - snps,disable_devinit_u1u2: when set, disable device-initiated U1/U2
-+			LPM request in USB device mode.
-  - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
- 			utmi_l1_suspend_n, false when asserts utmi_sleep_n
-  - snps,hird-threshold: HIRD threshold
 --- a/arch/arm64/include/asm/io.h
 +++ b/arch/arm64/include/asm/io.h
 @@ -210,6 +210,34 @@ extern void __iomem *ioremap_cache(phys_
@@ -168,7 +159,65 @@ Signed-off-by: Yangbo Lu <[email protected]>
  	atomic_set(&dev->urbnum, 0);
 --- a/drivers/usb/dwc3/core.c
 +++ b/drivers/usb/dwc3/core.c
-@@ -766,6 +766,96 @@ static void dwc3_core_setup_global_contr
+@@ -103,6 +103,41 @@ static int dwc3_get_dr_mode(struct dwc3
+ static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
+ static int dwc3_event_buffers_setup(struct dwc3 *dwc);
+ 
++/*
++ * dwc3_power_of_all_roothub_ports - Power off all Root hub ports
++ * @dwc3: Pointer to our controller context structure
++ */
++static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc)
++{
++	int i, port_num;
++	u32 reg, op_regs_base, offset;
++	void __iomem		*xhci_regs;
++
++	/* xhci regs is not mapped yet, do it temperary here */
++	if (dwc->xhci_resources[0].start) {
++		xhci_regs = ioremap(dwc->xhci_resources[0].start,
++				DWC3_XHCI_REGS_END);
++		if (IS_ERR(xhci_regs)) {
++			dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
++			return;
++		}
++
++		op_regs_base = HC_LENGTH(readl(xhci_regs));
++		reg = readl(xhci_regs + XHCI_HCSPARAMS1);
++		port_num = HCS_MAX_PORTS(reg);
++
++		for (i = 1; i <= port_num; i++) {
++			offset = op_regs_base + XHCI_PORTSC_BASE + 0x10*(i-1);
++			reg = readl(xhci_regs + offset);
++			reg &= ~PORT_POWER;
++			writel(reg, xhci_regs + offset);
++		}
++
++		iounmap(xhci_regs);
++	} else
++		dev_err(dwc->dev, "xhci base reg invalid\n");
++}
++
+ static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
+ {
+ 	u32 reg;
+@@ -111,6 +146,15 @@ static void dwc3_set_prtcap(struct dwc3
+ 	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
+ 	reg |= DWC3_GCTL_PRTCAPDIR(mode);
+ 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
++
++	/*
++	 * We have to power off all Root hub ports immediately after DWC3 set
++	 * to host mode to avoid VBUS glitch happen when xhci get reset later.
++	 */
++	if (dwc->host_vbus_glitches) {
++		if (mode == DWC3_GCTL_PRTCAP_HOST)
++			dwc3_power_off_all_roothub_ports(dwc);
++	}
+ }
+ 
+ static void __dwc3_set_mode(struct work_struct *work)
+@@ -766,6 +810,96 @@ static void dwc3_core_setup_global_contr
  static int dwc3_core_get_phy(struct dwc3 *dwc);
  static int dwc3_core_ulpi_init(struct dwc3 *dwc);
  
@@ -265,7 +314,7 @@ Signed-off-by: Yangbo Lu <[email protected]>
  /**
   * dwc3_core_init - Low-level initialization of DWC3 Core
   * @dwc: Pointer to our controller context structure
-@@ -828,6 +918,8 @@ static int dwc3_core_init(struct dwc3 *d
+@@ -828,6 +962,8 @@ static int dwc3_core_init(struct dwc3 *d
  	/* Adjust Frame Length */
  	dwc3_frame_length_adjustment(dwc);
  
@@ -274,7 +323,30 @@ Signed-off-by: Yangbo Lu <[email protected]>
  	usb_phy_set_suspend(dwc->usb2_phy, 0);
  	usb_phy_set_suspend(dwc->usb3_phy, 0);
  	ret = phy_power_on(dwc->usb2_generic_phy);
-@@ -1074,6 +1166,8 @@ static void dwc3_get_properties(struct d
+@@ -871,6 +1007,22 @@ static int dwc3_core_init(struct dwc3 *d
+ 		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
+ 	}
+ 
++	if (dwc->dr_mode == USB_DR_MODE_HOST ||
++	    dwc->dr_mode == USB_DR_MODE_OTG) {
++		reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
++
++		/*
++		 * Enable Auto retry Feature to make the controller operating in
++		 * Host mode on seeing transaction errors(CRC errors or internal
++		 * overrun scenerios) on IN transfers to reply to the device
++		 * with a non-terminating retry ACK (i.e, an ACK transcation
++		 * packet with Retry=1 & Nump != 0)
++		 */
++		reg |= DWC3_GUCTL_HSTINAUTORETRY;
++
++		dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
++	}
++
+ 	return 0;
+ 
+ err4:
+@@ -1074,6 +1226,8 @@ static void dwc3_get_properties(struct d
  				&hird_threshold);
  	dwc->usb3_lpm_capable = device_property_read_bool(dev,
  				"snps,usb3_lpm_capable");
@@ -283,7 +355,7 @@ Signed-off-by: Yangbo Lu <[email protected]>
  
  	dwc->disable_scramble_quirk = device_property_read_bool(dev,
  				"snps,disable_scramble_quirk");
-@@ -1106,8 +1200,16 @@ static void dwc3_get_properties(struct d
+@@ -1106,8 +1260,16 @@ static void dwc3_get_properties(struct d
  	dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
  				"snps,dis-tx-ipgap-linecheck-quirk");
  
@@ -300,7 +372,17 @@ Signed-off-by: Yangbo Lu <[email protected]>
  	device_property_read_u8(dev, "snps,tx_de_emphasis",
  				&tx_de_emphasis);
  	device_property_read_string(dev, "snps,hsphy_interface",
-@@ -1365,12 +1467,14 @@ static int dwc3_resume_common(struct dwc
+@@ -1115,6 +1277,9 @@ static void dwc3_get_properties(struct d
+ 	device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
+ 				 &dwc->fladj);
+ 
++	dwc->host_vbus_glitches = device_property_read_bool(dev,
++				"snps,host-vbus-glitches");
++
+ 	dwc->lpm_nyet_threshold = lpm_nyet_threshold;
+ 	dwc->tx_de_emphasis = tx_de_emphasis;
+ 
+@@ -1365,12 +1530,14 @@ static int dwc3_resume_common(struct dwc
  
  	switch (dwc->dr_mode) {
  	case USB_DR_MODE_PERIPHERAL:
@@ -350,7 +432,32 @@ Signed-off-by: Yangbo Lu <[email protected]>
  /* Global Debug Queue/FIFO Space Available Register */
  #define DWC3_GDBGFIFOSPACE_NUM(n)	((n) & 0x1f)
  #define DWC3_GDBGFIFOSPACE_TYPE(n)	(((n) << 5) & 0x1e0)
-@@ -788,6 +814,7 @@ struct dwc3_scratchpad_array {
+@@ -205,6 +231,9 @@
+ #define DWC3_GCTL_GBLHIBERNATIONEN	BIT(1)
+ #define DWC3_GCTL_DSBLCLKGTNG		BIT(0)
+ 
++/* Global User Control Register */
++#define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
++
+ /* Global User Control 1 Register */
+ #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
+ #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
+@@ -477,6 +506,14 @@
+ #define DWC3_DEV_IMOD_INTERVAL_SHIFT	0
+ #define DWC3_DEV_IMOD_INTERVAL_MASK	(0xffff << 0)
+ 
++/* Partial XHCI Register and Bit fields for quirk */
++#define XHCI_HCSPARAMS1		0x4
++#define XHCI_PORTSC_BASE	0x400
++#define PORT_POWER			(1 << 9)
++#define HCS_MAX_PORTS(p)	(((p) >> 24) & 0x7f)
++#define XHCI_HC_LENGTH(p)	(((p)>>00)&0x00ff)
++#define HC_LENGTH(p)		XHCI_HC_LENGTH(p)
++
+ /* Structures */
+ 
+ struct dwc3_trb;
+@@ -788,6 +825,7 @@ struct dwc3_scratchpad_array {
   * @regs: base address for our registers
   * @regs_size: address space size
   * @fladj: frame length adjustment
@@ -358,7 +465,7 @@ Signed-off-by: Yangbo Lu <[email protected]>
   * @irq_gadget: peripheral controller's IRQ number
   * @nr_scratch: number of scratch buffers
   * @u1u2: only used on revisions <1.83a for workaround
-@@ -843,6 +870,7 @@ struct dwc3_scratchpad_array {
+@@ -843,6 +881,7 @@ struct dwc3_scratchpad_array {
   * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
   * @three_stage_setup: set if we perform a three phase setup
   * @usb3_lpm_capable: set if hadrware supports Link Power Management
@@ -366,7 +473,7 @@ Signed-off-by: Yangbo Lu <[email protected]>
   * @disable_scramble_quirk: set if we enable the disable scramble quirk
   * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
   * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
-@@ -869,6 +897,11 @@ struct dwc3_scratchpad_array {
+@@ -869,6 +908,13 @@ struct dwc3_scratchpad_array {
   * 	1	- -3.5dB de-emphasis
   * 	2	- No de-emphasis
   * 	3	- Reserved
@@ -375,10 +482,12 @@ Signed-off-by: Yangbo Lu <[email protected]>
 + * @quirk_stop_transfer_in_block: prevent block transmission from being
 + *				interrupted
 + * @quirk_stop_ep_in_u1: replace stop commad with disable slot command
++ * @host-vbus-glitches: set to avoid vbus glitch during
++ *                      xhci reset.
   * @imod_interval: set the interrupt moderation interval in 250ns
   *                 increments or 0 to disable.
   */
-@@ -921,6 +954,12 @@ struct dwc3 {
+@@ -921,6 +967,12 @@ struct dwc3 {
  	enum usb_phy_interface	hsphy_mode;
  
  	u32			fladj;
@@ -391,7 +500,7 @@ Signed-off-by: Yangbo Lu <[email protected]>
  	u32			irq_gadget;
  	u32			nr_scratch;
  	u32			u1u2;
-@@ -1005,6 +1044,7 @@ struct dwc3 {
+@@ -1005,6 +1057,7 @@ struct dwc3 {
  	unsigned		setup_packet_pending:1;
  	unsigned		three_stage_setup:1;
  	unsigned		usb3_lpm_capable:1;
@@ -399,7 +508,7 @@ Signed-off-by: Yangbo Lu <[email protected]>
  
  	unsigned		disable_scramble_quirk:1;
  	unsigned		u2exit_lfps_quirk:1;
-@@ -1024,6 +1064,10 @@ struct dwc3 {
+@@ -1024,6 +1077,11 @@ struct dwc3 {
  
  	unsigned		tx_de_emphasis_quirk:1;
  	unsigned		tx_de_emphasis:2;
@@ -407,6 +516,7 @@ Signed-off-by: Yangbo Lu <[email protected]>
 +	unsigned                quirk_reverse_in_out:1;
 +	unsigned                quirk_stop_transfer_in_block:1;
 +	unsigned                quirk_stop_ep_in_u1:1;
++	unsigned		host_vbus_glitches:1;
  
  	u16			imod_interval;
  };
@@ -1298,15 +1408,6 @@ Signed-off-by: Yangbo Lu <[email protected]>
  	}
  done:
  	spin_unlock_irqrestore(&xhci->lock, flags);
-@@ -4988,7 +5013,7 @@ int xhci_gen_setup(struct usb_hcd *hcd,
- 		return retval;
- 	xhci_dbg(xhci, "Called HCD init\n");
- 
--	xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
-+	xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%llx\n",
- 		  xhci->hcc_params, xhci->hci_version, xhci->quirks);
- 
- 	return 0;
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
 @@ -1794,7 +1794,7 @@ struct xhci_hcd {
@@ -1314,7 +1415,7 @@ Signed-off-by: Yangbo Lu <[email protected]>
  #define XHCI_STATE_HALTED	(1 << 1)
  #define XHCI_STATE_REMOVING	(1 << 2)
 -	unsigned long long	quirks;
-+	u64		quirks;
++	unsigned long long      quirks;
  #define	XHCI_LINK_TRB_QUIRK	BIT_ULL(0)
  #define XHCI_RESET_EP_QUIRK	BIT_ULL(1)
  #define XHCI_NEC_HOST		BIT_ULL(2)
@@ -1328,11 +1429,15 @@ Signed-off-by: Yangbo Lu <[email protected]>
  /* For controller with a broken Port Disable implementation */
  #define XHCI_BROKEN_PORT_PED	BIT_ULL(25)
  #define XHCI_LIMIT_ENDPOINT_INTERVAL_7	BIT_ULL(26)
-@@ -1840,6 +1843,7 @@ struct xhci_hcd {
+@@ -1838,8 +1841,9 @@ struct xhci_hcd {
+ #define XHCI_HW_LPM_DISABLE	BIT_ULL(29)
+ #define XHCI_SUSPEND_DELAY	BIT_ULL(30)
  #define XHCI_INTEL_USB_ROLE_SW	BIT_ULL(31)
- #define XHCI_RESET_PLL_ON_DISCONNECT	BIT_ULL(34)
- #define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(35)
-+#define XHCI_DIS_U1U2_WHEN_U3 BIT(36)
+-#define XHCI_RESET_PLL_ON_DISCONNECT	BIT_ULL(34)
+-#define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(35)
++#define XHCI_RESET_PLL_ON_DISCONNECT	BIT_ULL(35)
++#define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(36)
++#define XHCI_DIS_U1U2_WHEN_U3 BIT(37)
  
  	unsigned int		num_active_eps;
  	unsigned int		limit_active_eps;

target/linux/layerscape/patches-4.14/808-vfio-support-layerscape.patch

@@ -1,21 +1,24 @@
-From 92f0ef51270b2961f63b2e985831f5e9a6251a2f Mon Sep 17 00:00:00 2001
+From 03ce521cd071706f755e3d2304ab1b8c47fd4910 Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:29:03 +0800
-Subject: [PATCH 25/40] vfio: support layerscape
+Date: Wed, 17 Apr 2019 18:59:09 +0800
+Subject: [PATCH] vfio: support layerscape
+
 This is an integrated patch of vfio for layerscape
 
 Signed-off-by: Bharat Bhushan <[email protected]>
 Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Roy Pledge <[email protected]>
+Signed-off-by: Yangbo Lu <[email protected]>
 ---
  drivers/vfio/Kconfig                      |   1 +
  drivers/vfio/Makefile                     |   1 +
  drivers/vfio/fsl-mc/Kconfig               |   9 +
  drivers/vfio/fsl-mc/Makefile              |   2 +
- drivers/vfio/fsl-mc/vfio_fsl_mc.c         | 751 ++++++++++++++++++++++
+ drivers/vfio/fsl-mc/vfio_fsl_mc.c         | 759 ++++++++++++++++++++++
  drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c    | 199 ++++++
- drivers/vfio/fsl-mc/vfio_fsl_mc_private.h |  55 ++
+ drivers/vfio/fsl-mc/vfio_fsl_mc_private.h |  57 ++
  include/uapi/linux/vfio.h                 |   1 +
- 8 files changed, 1019 insertions(+)
+ 8 files changed, 1029 insertions(+)
  create mode 100644 drivers/vfio/fsl-mc/Kconfig
  create mode 100644 drivers/vfio/fsl-mc/Makefile
  create mode 100644 drivers/vfio/fsl-mc/vfio_fsl_mc.c
@@ -56,7 +59,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +obj-$(CONFIG_VFIO_FSL_MC) += vfio_fsl_mc.o vfio_fsl_mc_intr.o
 --- /dev/null
 +++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
-@@ -0,0 +1,751 @@
+@@ -0,0 +1,759 @@
 +/*
 + * Freescale Management Complex (MC) device passthrough using VFIO
 + *
@@ -118,6 +121,10 @@ Signed-off-by: Biwen Li <[email protected]>
 +		if (mc_dev->regions[i].flags & IORESOURCE_CACHEABLE)
 +			vdev->regions[i].type |=
 +					VFIO_FSL_MC_REGION_TYPE_CACHEABLE;
++		if (mc_dev->regions[i].flags & IORESOURCE_MEM)
++			vdev->regions[i].type |=
++					VFIO_FSL_MC_REGION_TYPE_SHAREABLE;
++
 +		vdev->regions[i].flags = VFIO_REGION_INFO_FLAG_MMAP;
 +		vdev->regions[i].flags |= VFIO_REGION_INFO_FLAG_READ;
 +		if (!(mc_dev->regions[i].flags & IORESOURCE_READONLY))
@@ -390,9 +397,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +		u64 header;
 +		struct mc_cmd_header *resp_hdr;
 +
-+		__iormb();
-+		header = readq(ioaddr);
-+		__iormb();
++		header = cpu_to_le64(readq_relaxed(ioaddr));
 +
 +		resp_hdr = (struct mc_cmd_header *)&header;
 +		status = (enum mc_cmd_status)resp_hdr->status;
@@ -412,9 +417,12 @@ Signed-off-by: Biwen Li <[email protected]>
 +{
 +	int i;
 +
-+	/* Write at command header in the end */
-+	for (i = 7; i >= 0; i--)
-+		writeq(cmd_data[i], ioaddr + i * sizeof(uint64_t));
++	/* Write at command parameter into portal */
++	for (i = 7; i >= 1; i--)
++		writeq_relaxed(cmd_data[i], ioaddr + i * sizeof(uint64_t));
++
++	/* Write command header in the end */
++	writeq(cmd_data[0], ioaddr);
 +
 +	/* Wait for response before returning to user-space
 +	 * This can be optimized in future to even prepare response
@@ -499,9 +507,12 @@ Signed-off-by: Biwen Li <[email protected]>
 +	 * cache inhibited area of the portal to avoid coherency issues
 +	 * if a user migrates to another core.
 +	 */
-+	if (region.type & VFIO_FSL_MC_REGION_TYPE_CACHEABLE)
-+		vma->vm_page_prot = pgprot_cached_ns(vma->vm_page_prot);
-+	else
++	if (region.type & VFIO_FSL_MC_REGION_TYPE_CACHEABLE) {
++		if (region.type & VFIO_FSL_MC_REGION_TYPE_SHAREABLE)
++			vma->vm_page_prot = pgprot_cached(vma->vm_page_prot);
++		else
++			vma->vm_page_prot = pgprot_cached_ns(vma->vm_page_prot);
++	} else
 +		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 +
 +	vma->vm_pgoff = (region.addr >> PAGE_SHIFT) + pgoff;
@@ -1012,7 +1023,7 @@ Signed-off-by: Biwen Li <[email protected]>
 +}
 --- /dev/null
 +++ b/drivers/vfio/fsl-mc/vfio_fsl_mc_private.h
-@@ -0,0 +1,55 @@
+@@ -0,0 +1,57 @@
 +/*
 + * Freescale Management Complex VFIO private declarations
 + *
@@ -1047,6 +1058,8 @@ Signed-off-by: Biwen Li <[email protected]>
 +	u32			flags;
 +#define VFIO_FSL_MC_REGION_TYPE_MMIO  1
 +#define VFIO_FSL_MC_REGION_TYPE_CACHEABLE  2
++#define VFIO_FSL_MC_REGION_TYPE_SHAREABLE  4
++
 +	u32			type;
 +	u64			addr;
 +	resource_size_t		size;

target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch

@@ -1,14 +1,18 @@
-From d94f8863307c0f7fb7aeb2084cc666c47991d78b Mon Sep 17 00:00:00 2001
+From a00c035c7b82f51716a1a30637b1bd276dee3c5a Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Mon, 19 Nov 2018 10:26:57 +0800
+Date: Wed, 17 Apr 2019 18:58:17 +0800
 Subject: [PATCH] clock: support layerscape
+
 This is an integrated patch of clock for layerscape
 
-Signed-off-by: Tang Yuantian <[email protected]>
 Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Tang Yuantian <[email protected]>
+Signed-off-by: Vabhav Sharma <[email protected]>
+Signed-off-by: Yogesh Gaur <[email protected]>
 ---
- drivers/clk/clk-qoriq.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
+ drivers/clk/clk-qoriq.c         | 25 ++++++++++++++++++++++---
+ drivers/cpufreq/qoriq-cpufreq.c |  1 +
+ 2 files changed, 23 insertions(+), 3 deletions(-)
 
 --- a/drivers/clk/clk-qoriq.c
 +++ b/drivers/clk/clk-qoriq.c
@@ -21,7 +25,43 @@ Signed-off-by: Biwen Li <[email protected]>
  };
  
  #define CLKSEL_VALID	1
-@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct
+@@ -79,7 +79,7 @@ struct clockgen_chipinfo {
+ 	const struct clockgen_muxinfo *cmux_groups[2];
+ 	const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
+ 	void (*init_periph)(struct clockgen *cg);
+-	int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
++	int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */
+ 	u32 pll_mask;	/* 1 << n bit set if PLL n is valid */
+ 	u32 flags;	/* CG_xxx */
+ };
+@@ -570,6 +570,17 @@ static const struct clockgen_chipinfo ch
+ 		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
+ 	},
+ 	{
++		.compat = "fsl,lx2160a-clockgen",
++		.cmux_groups = {
++			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
++		},
++		.cmux_to_group = {
++			0, 0, 0, 0, 1, 1, 1, 1, -1
++		},
++		.pll_mask = 0x37,
++		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
++	},
++	{
+ 		.compat = "fsl,p2041-clockgen",
+ 		.guts_compat = "fsl,qoriq-device-config-1.0",
+ 		.init_periph = p2041_init_periph,
+@@ -601,7 +612,7 @@ static const struct clockgen_chipinfo ch
+ 			&p4080_cmux_grp1, &p4080_cmux_grp2
+ 		},
+ 		.cmux_to_group = {
+-			0, 0, 0, 0, 1, 1, 1, 1
++			0, 0, 0, 0, 1, 1, 1, 1, -1
+ 		},
+ 		.pll_mask = 0x1f,
+ 	},
+@@ -1127,6 +1138,13 @@ static void __init create_one_pll(struct
  		struct clk *clk;
  		int ret;
  
@@ -35,3 +75,21 @@ Signed-off-by: Biwen Li <[email protected]>
  		snprintf(pll->div[i].name, sizeof(pll->div[i].name),
  			 "cg-pll%d-div%d", idx, i + 1);
  
+@@ -1417,6 +1435,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "
+ CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
+ 
+ /* Legacy nodes */
+ CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
+--- a/drivers/cpufreq/qoriq-cpufreq.c
++++ b/drivers/cpufreq/qoriq-cpufreq.c
+@@ -320,6 +320,7 @@ static const struct of_device_id node_ma
+ 	{ .compatible = "fsl,ls1046a-clockgen", },
+ 	{ .compatible = "fsl,ls1088a-clockgen", },
+ 	{ .compatible = "fsl,ls2080a-clockgen", },
++	{ .compatible = "fsl,lx2160a-clockgen", },
+ 	{ .compatible = "fsl,p4080-clockgen", },
+ 	{ .compatible = "fsl,qoriq-clockgen-1.0", },
+ 	{ .compatible = "fsl,qoriq-clockgen-2.0", },

target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch

@@ -1,182 +1,1576 @@
-From 31d0f8f19246c9a2fbecb5ca0a03ef6bb70eee2d Mon Sep 17 00:00:00 2001
+From 9875df1e872eb2b0f9d2d72c9a761a5f03400d9f Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Fri, 9 Nov 2018 19:32:53 +0800
+Date: Fri, 19 Apr 2019 13:23:01 +0800
 Subject: [PATCH] flexspi: support layerscape
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
 
 This is an integrated patch of flexspi for layerscape
 
-Signed-off-by: Alistair Strachan <[email protected]>
-Signed-off-by: Ariel Elior <[email protected]>
-Signed-off-by: Brandon Maier <[email protected]>
-Signed-off-by: David S. Miller <[email protected]>
-Signed-off-by: Geert Uytterhoeven <[email protected]>
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
-Signed-off-by: Joe Thornber <[email protected]>
-Signed-off-by: Kirill Kapranov <[email protected]>
-Signed-off-by: Liam Girdwood <[email protected]>
-Signed-off-by: Marcel Ziswiler <[email protected]>
-Signed-off-by: Mark Brown <[email protected]>
-Signed-off-by: Mike Snitzer <[email protected]>
-Signed-off-by: Peng Li <[email protected]>
-Signed-off-by: Reinette Chatre <[email protected]>
-Signed-off-by: Sasha Levin <[email protected]>
-Signed-off-by: Thomas Gleixner <[email protected]>
-Signed-off-by: Tomer Tayar <[email protected]>
-Signed-off-by: Uwe Kleine-König <[email protected]>
+Signed-off-by: Ashish Kumar <[email protected]>
 Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Rajat Srivastava <[email protected]>
+Signed-off-by: Yangbo Lu <[email protected]>
+Signed-off-by: Yogesh Gaur <[email protected]>
 ---
- drivers/md/dm-thin.c                      | 13 +++++++++++++
- drivers/net/ethernet/qlogic/qed/qed_mcp.c |  7 +++++++
- drivers/net/phy/xilinx_gmii2rgmii.c       |  5 +++++
- drivers/spi/spi-tegra20-slink.c           | 18 ++++++++++++++++++
- drivers/staging/android/ashmem.c          |  6 ++++++
- drivers/tty/serial/imx.c                  |  8 ++++++++
- kernel/events/core.c                      |  6 ++++++
- sound/soc/soc-dapm.c                      |  7 +++++++
- 8 files changed, 70 insertions(+)
+ .../devicetree/bindings/mtd/nxp-flexspi.txt   |   41 +
+ drivers/mtd/spi-nor/Kconfig                   |   10 +
+ drivers/mtd/spi-nor/Makefile                  |    1 +
+ drivers/mtd/spi-nor/nxp-flexspi.c             | 1404 +++++++++++++++++
+ drivers/mtd/spi-nor/spi-nor.c                 |   13 +-
+ include/linux/mtd/cfi.h                       |    1 +
+ include/linux/mtd/spi-nor.h                   |    3 +-
+ 7 files changed, 1470 insertions(+), 3 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/mtd/nxp-flexspi.txt
+ create mode 100644 drivers/mtd/spi-nor/nxp-flexspi.c
 
---- a/drivers/md/dm-thin.c
-+++ b/drivers/md/dm-thin.c
-@@ -3697,6 +3697,19 @@ static int process_create_thin_mesg(unsi
- 		return r;
- 	}
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/nxp-flexspi.txt
+@@ -0,0 +1,41 @@
++* NXP Flex Serial Peripheral Interface(FlexSPI)
++
++Required properties:
++  - compatible : Should be "nxp,lx2160a-fspi"
++  - reg : the first contains the register location and length,
++          the second contains the memory mapping address and length
++  - reg-names: Should contain the reg names "FSPI" and "FSPI-memory"
++  - interrupts : Should contain the interrupt for the device
++  - clocks : The clocks needed by the FlexSPI controller
++  - clock-names : Should contain the name of the clocks: "fspi_en" and "fspi"
++
++Optional properties:
++  - nxp,fspi-has-second-chip: The controller has two buses, bus A and bus B.
++			      Each bus can be connected with two NOR flashes.
++			      Most of the time, each bus only has one NOR flash
++			      connected, this is the default case.
++			      But if there are two NOR flashes connected to the
++			      bus, you should enable this property.
++			      (Please check the board's schematic.)
++Example:
++fspi0: flexspi@20c0000 {
++	compatible = "nxp,lx2160a-fspi";
++	reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>;
++	reg-names = "FSPI", "FSPI-memory";
++	interrupts = <0 25 0x4>; /* Level high type */
++	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++	clock-names = "fspi_en", "fspi";
++
++	status = "okay";
++	nxp,fspi-has-second-chip;
++	flash0: mt35xu512aba@0 {
++		reg = <0>;
++		....
++	};
++
++	flash1: mt35xu512aba@1 {
++		reg = <1>;
++		....
++	};
++
++};
+--- a/drivers/mtd/spi-nor/Kconfig
++++ b/drivers/mtd/spi-nor/Kconfig
+@@ -97,6 +97,16 @@ config SPI_NXP_SPIFI
+ 	  Flash. Enable this option if you have a device with a SPIFI
+ 	  controller and want to access the Flash as a mtd device.
  
-+	r = dm_pool_get_free_metadata_block_count(pool->pmd, &free_blocks);
-+	if (r) {
-+		metadata_operation_failed(pool, "dm_pool_get_free_metadata_block_count", r);
-+		return r;
++config	SPI_NXP_FLEXSPI
++	 tristate "NXP Flex SPI controller"
++	 help
++	   This enables support for the Flex SPI controller in master mode.
++	   Up to four slave devices can be connected on two buses with two
++	   chipselects each.
++	   This controller does not support generic SPI messages and only
++	   supports the high-level SPI memory interface using SPI-NOR
++	   framework.
++
+ config SPI_INTEL_SPI
+ 	tristate
+ 
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -7,6 +7,7 @@ obj-$(CONFIG_SPI_FSL_QUADSPI)	+= fsl-qua
+ obj-$(CONFIG_SPI_HISI_SFC)	+= hisi-sfc.o
+ obj-$(CONFIG_MTD_MT81xx_NOR)    += mtk-quadspi.o
+ obj-$(CONFIG_SPI_NXP_SPIFI)	+= nxp-spifi.o
++obj-$(CONFIG_SPI_NXP_FLEXSPI)	+= nxp-flexspi.o
+ obj-$(CONFIG_SPI_INTEL_SPI)	+= intel-spi.o
+ obj-$(CONFIG_SPI_INTEL_SPI_PCI)	+= intel-spi-pci.o
+ obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM)	+= intel-spi-platform.o
+--- /dev/null
++++ b/drivers/mtd/spi-nor/nxp-flexspi.c
+@@ -0,0 +1,1404 @@
++/*
++ * NXP FSPI(FlexSPI controller) driver.
++ *
++ * Copyright 2018 NXP
++ * Author: Yogesh Gaur <[email protected]>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/errno.h>
++#include <linux/platform_device.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/timer.h>
++#include <linux/jiffies.h>
++#include <linux/completion.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/spi-nor.h>
++#include <linux/mutex.h>
++#include <linux/pm_qos.h>
++#include <linux/pci.h>
++
++/* The registers */
++#define FSPI_MCR0			0x00
++#define FSPI_MCR0_AHB_TIMEOUT_SHIFT	24
++#define FSPI_MCR0_AHB_TIMEOUT_MASK	(0xFF << FSPI_MCR0_AHB_TIMEOUT_SHIFT)
++#define FSPI_MCR0_IP_TIMEOUT_SHIFT	16
++#define FSPI_MCR0_IP_TIMEOUT_MASK	(0xFF << FSPI_MCR0_IP_TIMEOUT_SHIFT)
++#define FSPI_MCR0_LEARN_EN_SHIFT	15
++#define FSPI_MCR0_LEARN_EN_MASK		(1 << FSPI_MCR0_LEARN_EN_SHIFT)
++#define FSPI_MCR0_SCRFRUN_EN_SHIFT	14
++#define FSPI_MCR0_SCRFRUN_EN_MASK	(1 << FSPI_MCR0_SCRFRUN_EN_SHIFT)
++#define FSPI_MCR0_OCTCOMB_EN_SHIFT	13
++#define FSPI_MCR0_OCTCOMB_EN_MASK	(1 << FSPI_MCR0_OCTCOMB_EN_SHIFT)
++#define FSPI_MCR0_DOZE_EN_SHIFT		12
++#define FSPI_MCR0_DOZE_EN_MASK		(1 << FSPI_MCR0_DOZE_EN_SHIFT)
++#define FSPI_MCR0_HSEN_SHIFT		11
++#define FSPI_MCR0_HSEN_MASK		(1 << FSPI_MCR0_HSEN_SHIFT)
++#define FSPI_MCR0_SERCLKDIV_SHIFT	8
++#define FSPI_MCR0_SERCLKDIV_MASK	(7 << FSPI_MCR0_SERCLKDIV_SHIFT)
++#define FSPI_MCR0_ATDF_EN_SHIFT		7
++#define FSPI_MCR0_ATDF_EN_MASK		(1 << FSPI_MCR0_ATDF_EN_SHIFT)
++#define FSPI_MCR0_ARDF_EN_SHIFT		6
++#define FSPI_MCR0_ARDF_EN_MASK		(1 << FSPI_MCR0_ARDF_EN_SHIFT)
++#define FSPI_MCR0_RXCLKSRC_SHIFT	4
++#define FSPI_MCR0_RXCLKSRC_MASK		(3 << FSPI_MCR0_RXCLKSRC_SHIFT)
++#define FSPI_MCR0_END_CFG_SHIFT		2
++#define FSPI_MCR0_END_CFG_MASK		(3 << FSPI_MCR0_END_CFG_SHIFT)
++#define FSPI_MCR0_MDIS_SHIFT		1
++#define FSPI_MCR0_MDIS_MASK		(1 << FSPI_MCR0_MDIS_SHIFT)
++#define FSPI_MCR0_SWRST_SHIFT		0
++#define FSPI_MCR0_SWRST_MASK		(1 << FSPI_MCR0_SWRST_SHIFT)
++
++#define FSPI_MCR1			0x04
++#define FSPI_MCR1_SEQ_TIMEOUT_SHIFT	16
++#define FSPI_MCR1_SEQ_TIMEOUT_MASK	\
++	(0xFFFF << FSPI_MCR1_SEQ_TIMEOUT_SHIFT)
++#define FSPI_MCR1_AHB_TIMEOUT_SHIFT	0
++#define FSPI_MCR1_AHB_TIMEOUT_MASK	\
++	(0xFFFF << FSPI_MCR1_AHB_TIMEOUT_SHIFT)
++
++#define FSPI_MCR2			0x08
++#define FSPI_MCR2_IDLE_WAIT_SHIFT	24
++#define FSPI_MCR2_IDLE_WAIT_MASK	(0xFF << FSPI_MCR2_IDLE_WAIT_SHIFT)
++#define FSPI_MCR2_SAMEFLASH_SHIFT	15
++#define FSPI_MCR2_SAMEFLASH_MASK	(1 << FSPI_MCR2_SAMEFLASH_SHIFT)
++#define FSPI_MCR2_CLRLRPHS_SHIFT	14
++#define FSPI_MCR2_CLRLRPHS_MASK		(1 << FSPI_MCR2_CLRLRPHS_SHIFT)
++#define FSPI_MCR2_ABRDATSZ_SHIFT	8
++#define FSPI_MCR2_ABRDATSZ_MASK		(1 << FSPI_MCR2_ABRDATSZ_SHIFT)
++#define FSPI_MCR2_ABRLEARN_SHIFT	7
++#define FSPI_MCR2_ABRLEARN_MASK		(1 << FSPI_MCR2_ABRLEARN_SHIFT)
++#define FSPI_MCR2_ABR_READ_SHIFT	6
++#define FSPI_MCR2_ABR_READ_MASK		(1 << FSPI_MCR2_ABR_READ_SHIFT)
++#define FSPI_MCR2_ABRWRITE_SHIFT	5
++#define FSPI_MCR2_ABRWRITE_MASK		(1 << FSPI_MCR2_ABRWRITE_SHIFT)
++#define FSPI_MCR2_ABRDUMMY_SHIFT	4
++#define FSPI_MCR2_ABRDUMMY_MASK		(1 << FSPI_MCR2_ABRDUMMY_SHIFT)
++#define FSPI_MCR2_ABR_MODE_SHIFT	3
++#define FSPI_MCR2_ABR_MODE_MASK		(1 << FSPI_MCR2_ABR_MODE_SHIFT)
++#define FSPI_MCR2_ABRCADDR_SHIFT	2
++#define FSPI_MCR2_ABRCADDR_MASK		(1 << FSPI_MCR2_ABRCADDR_SHIFT)
++#define FSPI_MCR2_ABRRADDR_SHIFT	1
++#define FSPI_MCR2_ABRRADDR_MASK		(1 << FSPI_MCR2_ABRRADDR_SHIFT)
++#define FSPI_MCR2_ABR_CMD_SHIFT		0
++#define FSPI_MCR2_ABR_CMD_MASK		(1 << FSPI_MCR2_ABR_CMD_SHIFT)
++
++#define FSPI_AHBCR			0x0c
++#define FSPI_AHBCR_RDADDROPT_SHIFT	6
++#define FSPI_AHBCR_RDADDROPT_MASK	(1 << FSPI_AHBCR_RDADDROPT_SHIFT)
++#define FSPI_AHBCR_PREF_EN_SHIFT	5
++#define FSPI_AHBCR_PREF_EN_MASK		(1 << FSPI_AHBCR_PREF_EN_SHIFT)
++#define FSPI_AHBCR_BUFF_EN_SHIFT	4
++#define FSPI_AHBCR_BUFF_EN_MASK		(1 << FSPI_AHBCR_BUFF_EN_SHIFT)
++#define FSPI_AHBCR_CACH_EN_SHIFT	3
++#define FSPI_AHBCR_CACH_EN_MASK		(1 << FSPI_AHBCR_CACH_EN_SHIFT)
++#define FSPI_AHBCR_CLRTXBUF_SHIFT	2
++#define FSPI_AHBCR_CLRTXBUF_MASK	(1 << FSPI_AHBCR_CLRTXBUF_SHIFT)
++#define FSPI_AHBCR_CLRRXBUF_SHIFT	1
++#define FSPI_AHBCR_CLRRXBUF_MASK	(1 << FSPI_AHBCR_CLRRXBUF_SHIFT)
++#define FSPI_AHBCR_PAR_EN_SHIFT		0
++#define FSPI_AHBCR_PAR_EN_MASK		(1 << FSPI_AHBCR_PAR_EN_SHIFT)
++
++#define FSPI_INTEN			0x10
++#define FSPI_INTEN_SCLKSBWR_SHIFT	9
++#define FSPI_INTEN_SCLKSBWR_MASK	(1 << FSPI_INTEN_SCLKSBWR_SHIFT)
++#define FSPI_INTEN_SCLKSBRD_SHIFT	8
++#define FSPI_INTEN_SCLKSBRD_MASK	(1 << FSPI_INTEN_SCLKSBRD_SHIFT)
++#define FSPI_INTEN_DATALRNFL_SHIFT	7
++#define FSPI_INTEN_DATALRNFL_MASK	(1 << FSPI_INTEN_DATALRNFL_SHIFT)
++#define FSPI_INTEN_IPTXWE_SHIFT		6
++#define FSPI_INTEN_IPTXWE_MASK		(1 << FSPI_INTEN_IPTXWE_SHIFT)
++#define FSPI_INTEN_IPRXWA_SHIFT		5
++#define FSPI_INTEN_IPRXWA_MASK		(1 << FSPI_INTEN_IPRXWA_SHIFT)
++#define FSPI_INTEN_AHBCMDERR_SHIFT	4
++#define FSPI_INTEN_AHBCMDERR_MASK	(1 << FSPI_INTEN_AHBCMDERR_SHIFT)
++#define FSPI_INTEN_IPCMDERR_SHIFT	3
++#define FSPI_INTEN_IPCMDERR_MASK	(1 << FSPI_INTEN_IPCMDERR_SHIFT)
++#define FSPI_INTEN_AHBCMDGE_SHIFT	2
++#define FSPI_INTEN_AHBCMDGE_MASK	(1 << FSPI_INTEN_AHBCMDGE_SHIFT)
++#define FSPI_INTEN_IPCMDGE_SHIFT	1
++#define FSPI_INTEN_IPCMDGE_MASK		(1 << FSPI_INTEN_IPCMDGE_SHIFT)
++#define FSPI_INTEN_IPCMDDONE_SHIFT	0
++#define FSPI_INTEN_IPCMDDONE_MASK	(1 << FSPI_INTEN_IPCMDDONE_SHIFT)
++
++#define FSPI_INTR			0x14
++#define FSPI_INTR_SCLKSBWR_SHIFT	9
++#define FSPI_INTR_SCLKSBWR_MASK		(1 << FSPI_INTR_SCLKSBWR_SHIFT)
++#define FSPI_INTR_SCLKSBRD_SHIFT	8
++#define FSPI_INTR_SCLKSBRD_MASK		(1 << FSPI_INTR_SCLKSBRD_SHIFT)
++#define FSPI_INTR_DATALRNFL_SHIFT	7
++#define FSPI_INTR_DATALRNFL_MASK	(1 << FSPI_INTR_DATALRNFL_SHIFT)
++#define FSPI_INTR_IPTXWE_SHIFT		6
++#define FSPI_INTR_IPTXWE_MASK		(1 << FSPI_INTR_IPTXWE_SHIFT)
++#define FSPI_INTR_IPRXWA_SHIFT		5
++#define FSPI_INTR_IPRXWA_MASK		(1 << FSPI_INTR_IPRXWA_SHIFT)
++#define FSPI_INTR_AHBCMDERR_SHIFT	4
++#define FSPI_INTR_AHBCMDERR_MASK	(1 << FSPI_INTR_AHBCMDERR_SHIFT)
++#define FSPI_INTR_IPCMDERR_SHIFT	3
++#define FSPI_INTR_IPCMDERR_MASK		(1 << FSPI_INTR_IPCMDERR_SHIFT)
++#define FSPI_INTR_AHBCMDGE_SHIFT	2
++#define FSPI_INTR_AHBCMDGE_MASK		(1 << FSPI_INTR_AHBCMDGE_SHIFT)
++#define FSPI_INTR_IPCMDGE_SHIFT		1
++#define FSPI_INTR_IPCMDGE_MASK		(1 << FSPI_INTR_IPCMDGE_SHIFT)
++#define FSPI_INTR_IPCMDDONE_SHIFT	0
++#define FSPI_INTR_IPCMDDONE_MASK	(1 << FSPI_INTR_IPCMDDONE_SHIFT)
++
++#define FSPI_LUTKEY			0x18
++#define FSPI_LUTKEY_VALUE		0x5AF05AF0
++
++#define FSPI_LCKCR			0x1C
++#define FSPI_LCKER_LOCK			0x1
++#define FSPI_LCKER_UNLOCK		0x2
++
++#define FSPI_BUFXCR_INVALID_MSTRID	0xe
++#define FSPI_AHBRX_BUF0CR0		0x20
++#define FSPI_AHBRX_BUF1CR0		0x24
++#define FSPI_AHBRX_BUF2CR0		0x28
++#define FSPI_AHBRX_BUF3CR0		0x2C
++#define FSPI_AHBRX_BUF4CR0		0x30
++#define FSPI_AHBRX_BUF5CR0		0x34
++#define FSPI_AHBRX_BUF6CR0		0x38
++#define FSPI_AHBRX_BUF7CR0		0x3C
++#define FSPI_AHBRXBUF0CR7_PREF_SHIFT	31
++#define FSPI_AHBRXBUF0CR7_PREF_MASK	(1 << FSPI_AHBRXBUF0CR7_PREF_SHIFT)
++
++#define FSPI_AHBRX_BUF0CR1		0x40
++#define FSPI_AHBRX_BUF1CR1		0x44
++#define FSPI_AHBRX_BUF2CR1		0x48
++#define FSPI_AHBRX_BUF3CR1		0x4C
++#define FSPI_AHBRX_BUF4CR1		0x50
++#define FSPI_AHBRX_BUF5CR1		0x54
++#define FSPI_AHBRX_BUF6CR1		0x58
++#define FSPI_AHBRX_BUF7CR1		0x5C
++#define FSPI_BUFXCR1_MSID_SHIFT		0
++#define FSPI_BUFXCR1_MSID_MASK		(0xF << FSPI_BUFXCR1_MSID_SHIFT)
++#define FSPI_BUFXCR1_PRIO_SHIFT		8
++#define FSPI_BUFXCR1_PRIO_MASK		(0x7 << FSPI_BUFXCR1_PRIO_SHIFT)
++
++#define FSPI_FLSHA1CR0			0x60
++#define FSPI_FLSHA2CR0			0x64
++#define FSPI_FLSHB1CR0			0x68
++#define FSPI_FLSHB2CR0			0x6C
++#define FSPI_FLSHXCR0_SZ_SHIFT		10
++#define FSPI_FLSHXCR0_SZ_MASK		(0x3FFFFF << FSPI_FLSHXCR0_SZ_SHIFT)
++
++#define FSPI_FLSHA1CR1			0x70
++#define FSPI_FLSHA2CR1			0x74
++#define FSPI_FLSHB1CR1			0x78
++#define FSPI_FLSHB2CR1			0x7C
++#define FSPI_FLSHXCR1_CSINTR_SHIFT	16
++#define FSPI_FLSHXCR1_CSINTR_MASK	\
++		(0xFFFF << FSPI_FLSHXCR1_CSINTR_SHIFT)
++#define FSPI_FLSHXCR1_CAS_SHIFT		11
++#define FSPI_FLSHXCR1_CAS_MASK		(0xF << FSPI_FLSHXCR1_CAS_SHIFT)
++#define FSPI_FLSHXCR1_WA_SHIFT		10
++#define FSPI_FLSHXCR1_WA_MASK		(1 << FSPI_FLSHXCR1_WA_SHIFT)
++#define FSPI_FLSHXCR1_TCSH_SHIFT	5
++#define FSPI_FLSHXCR1_TCSH_MASK		(0x1F << FSPI_FLSHXCR1_TCSH_SHIFT)
++#define FSPI_FLSHXCR1_TCSS_SHIFT	0
++#define FSPI_FLSHXCR1_TCSS_MASK		(0x1F << FSPI_FLSHXCR1_TCSS_SHIFT)
++
++#define FSPI_FLSHA1CR2			0x80
++#define FSPI_FLSHA2CR2			0x84
++#define FSPI_FLSHB1CR2			0x88
++#define FSPI_FLSHB2CR2			0x8C
++#define FSPI_FLSHXCR2_CLRINSP_SHIFT	24
++#define FSPI_FLSHXCR2_CLRINSP_MASK	(1 << FSPI_FLSHXCR2_CLRINSP_SHIFT)
++#define FSPI_FLSHXCR2_AWRWAIT_SHIFT	16
++#define FSPI_FLSHXCR2_AWRWAIT_MASK	(0xFF << FSPI_FLSHXCR2_AWRWAIT_SHIFT)
++#define FSPI_FLSHXCR2_AWRSEQN_SHIFT	13
++#define FSPI_FLSHXCR2_AWRSEQN_MASK	(0x7 << FSPI_FLSHXCR2_AWRSEQN_SHIFT)
++#define FSPI_FLSHXCR2_AWRSEQI_SHIFT	8
++#define FSPI_FLSHXCR2_AWRSEQI_MASK	(0xF << FSPI_FLSHXCR2_AWRSEQI_SHIFT)
++#define FSPI_FLSHXCR2_ARDSEQN_SHIFT	5
++#define FSPI_FLSHXCR2_ARDSEQN_MASK	(0x7 << FSPI_FLSHXCR2_ARDSEQN_SHIFT)
++#define FSPI_FLSHXCR2_ARDSEQI_SHIFT	0
++#define FSPI_FLSHXCR2_ARDSEQI_MASK	(0xF << FSPI_FLSHXCR2_ARDSEQI_SHIFT)
++
++#define FSPI_IPCR0			0xA0
++
++#define FSPI_IPCR1			0xA4
++#define FSPI_IPCR1_IPAREN_SHIFT		31
++#define FSPI_IPCR1_IPAREN_MASK		(1 << FSPI_IPCR1_IPAREN_SHIFT)
++#define FSPI_IPCR1_SEQNUM_SHIFT		24
++#define FSPI_IPCR1_SEQNUM_MASK		(0xF << FSPI_IPCR1_SEQNUM_SHIFT)
++#define FSPI_IPCR1_SEQID_SHIFT		16
++#define FSPI_IPCR1_SEQID_MASK		(0xF << FSPI_IPCR1_SEQID_SHIFT)
++#define FSPI_IPCR1_IDATSZ_SHIFT		0
++#define FSPI_IPCR1_IDATSZ_MASK		(0xFFFF << FSPI_IPCR1_IDATSZ_SHIFT)
++
++#define FSPI_IPCMD			0xB0
++#define FSPI_IPCMD_TRG_SHIFT		0
++#define FSPI_IPCMD_TRG_MASK		(1 << FSPI_IPCMD_TRG_SHIFT)
++
++#define FSPI_DLPR			0xB4
++
++#define FSPI_IPRXFCR			0xB8
++#define FSPI_IPRXFCR_CLR_SHIFT		0
++#define FSPI_IPRXFCR_CLR_MASK		(1 << FSPI_IPRXFCR_CLR_SHIFT)
++#define FSPI_IPRXFCR_DMA_EN_SHIFT	1
++#define FSPI_IPRXFCR_DMA_EN_MASK	(1 << FSPI_IPRXFCR_DMA_EN_SHIFT)
++#define FSPI_IPRXFCR_WMRK_SHIFT		2
++#define FSPI_IPRXFCR_WMRK_MASK		(0x1F << FSPI_IPRXFCR_WMRK_SHIFT)
++
++#define FSPI_IPTXFCR			0xBC
++#define FSPI_IPTXFCR_CLR_SHIFT		0
++#define FSPI_IPTXFCR_CLR_MASK		(1 << FSPI_IPTXFCR_CLR_SHIFT)
++#define FSPI_IPTXFCR_DMA_EN_SHIFT	1
++#define FSPI_IPTXFCR_DMA_EN_MASK	(1 << FSPI_IPTXFCR_DMA_EN_SHIFT)
++#define FSPI_IPTXFCR_WMRK_SHIFT		2
++#define FSPI_IPTXFCR_WMRK_MASK		(0x1F << FSPI_IPTXFCR_WMRK_SHIFT)
++
++#define	FSPI_DLLACR			0xC0
++#define	FSPI_DLLACR_OVRDEN_SHIFT	8
++#define	FSPI_DLLACR_OVRDEN_MASK		(1 << FSPI_DLLACR_OVRDEN_SHIFT)
++
++#define	FSPI_DLLBCR			0xC4
++#define	FSPI_DLLBCR_OVRDEN_SHIFT	8
++#define	FSPI_DLLBCR_OVRDEN_MASK		(1 << FSPI_DLLBCR_OVRDEN_SHIFT)
++
++#define FSPI_STS0			0xE0
++#define FSPI_STS0_DLPHA_SHIFT		9
++#define FSPI_STS0_DLPHA_MASK		(0x1F << FSPI_STS0_DLPHA_SHIFT)
++#define FSPI_STS0_DLPHB_SHIFT		4
++#define FSPI_STS0_DLPHB_MASK		(0x1F << FSPI_STS0_DLPHB_SHIFT)
++#define FSPI_STS0_CMD_SRC_SHIFT		2
++#define FSPI_STS0_CMD_SRC_MASK		(3 << FSPI_STS0_CMD_SRC_SHIFT)
++#define FSPI_STS0_ARB_IDLE_SHIFT	1
++#define FSPI_STS0_ARB_IDLE_MASK		(1 << FSPI_STS0_ARB_IDLE_SHIFT)
++#define FSPI_STS0_SEQ_IDLE_SHIFT	0
++#define FSPI_STS0_SEQ_IDLE_MASK		(1 << FSPI_STS0_SEQ_IDLE_SHIFT)
++
++#define FSPI_STS1			0xE4
++#define FSPI_STS1_IP_ERRCD_SHIFT	24
++#define FSPI_STS1_IP_ERRCD_MASK		(0xF << FSPI_STS1_IP_ERRCD_SHIFT)
++#define FSPI_STS1_IP_ERRID_SHIFT	16
++#define FSPI_STS1_IP_ERRID_MASK		(0xF << FSPI_STS1_IP_ERRID_SHIFT)
++#define FSPI_STS1_AHB_ERRCD_SHIFT	8
++#define FSPI_STS1_AHB_ERRCD_MASK	(0xF << FSPI_STS1_AHB_ERRCD_SHIFT)
++#define FSPI_STS1_AHB_ERRID_SHIFT	0
++#define FSPI_STS1_AHB_ERRID_MASK	(0xF << FSPI_STS1_AHB_ERRID_SHIFT)
++
++#define FSPI_AHBSPNST			0xEC
++#define FSPI_AHBSPNST_DATLFT_SHIFT	16
++#define FSPI_AHBSPNST_DATLFT_MASK	\
++		(0xFFFF << FSPI_AHBSPNST_DATLFT_SHIFT)
++#define FSPI_AHBSPNST_BUFID_SHIFT	1
++#define FSPI_AHBSPNST_BUFID_MASK	(7 << FSPI_AHBSPNST_BUFID_SHIFT)
++#define FSPI_AHBSPNST_ACTIVE_SHIFT	0
++#define FSPI_AHBSPNST_ACTIVE_MASK	(1 << FSPI_AHBSPNST_ACTIVE_SHIFT)
++
++#define FSPI_IPRXFSTS			0xF0
++#define FSPI_IPRXFSTS_RDCNTR_SHIFT	16
++#define FSPI_IPRXFSTS_RDCNTR_MASK	\
++		(0xFFFF << FSPI_IPRXFSTS_RDCNTR_SHIFT)
++#define FSPI_IPRXFSTS_FILL_SHIFT	0
++#define FSPI_IPRXFSTS_FILL_MASK		(0xFF << FSPI_IPRXFSTS_FILL_SHIFT)
++
++#define FSPI_IPTXFSTS			0xF4
++#define FSPI_IPTXFSTS_WRCNTR_SHIFT	16
++#define FSPI_IPTXFSTS_WRCNTR_MASK	\
++		(0xFFFF << FSPI_IPTXFSTS_WRCNTR_SHIFT)
++#define FSPI_IPTXFSTS_FILL_SHIFT	0
++#define FSPI_IPTXFSTS_FILL_MASK		(0xFF << FSPI_IPTXFSTS_FILL_SHIFT)
++
++#define FSPI_RFDR			0x100
++#define FSPI_TFDR			0x180
++
++#define FSPI_LUT_BASE			0x200
++
++/* register map end */
++
++/*
++ * The definition of the LUT register shows below:
++ *
++ *  ---------------------------------------------------
++ *  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
++ *  ---------------------------------------------------
++ */
++#define OPRND0_SHIFT		0
++#define PAD0_SHIFT		8
++#define INSTR0_SHIFT		10
++#define OPRND1_SHIFT		16
++
++/* Instruction set for the LUT register. */
++
++#define LUT_STOP		0x00
++#define LUT_CMD			0x01
++#define LUT_ADDR		0x02
++#define LUT_CADDR_SDR		0x03
++#define LUT_MODE		0x04
++#define LUT_MODE2		0x05
++#define LUT_MODE4		0x06
++#define LUT_MODE8		0x07
++#define LUT_NXP_WRITE		0x08
++#define LUT_NXP_READ		0x09
++#define LUT_LEARN_SDR		0x0A
++#define LUT_DATSZ_SDR		0x0B
++#define LUT_DUMMY		0x0C
++#define LUT_DUMMY_RWDS_SDR	0x0D
++#define LUT_JMP_ON_CS		0x1F
++#define LUT_CMD_DDR		0x21
++#define LUT_ADDR_DDR		0x22
++#define LUT_CADDR_DDR		0x23
++#define LUT_MODE_DDR		0x24
++#define LUT_MODE2_DDR		0x25
++#define LUT_MODE4_DDR		0x26
++#define LUT_MODE8_DDR		0x27
++#define LUT_WRITE_DDR		0x28
++#define LUT_READ_DDR		0x29
++#define LUT_LEARN_DDR		0x2A
++#define LUT_DATSZ_DDR		0x2B
++#define LUT_DUMMY_DDR		0x2C
++#define LUT_DUMMY_RWDS_DDR	0x2D
++
++
++/*
++ * The PAD definitions for LUT register.
++ *
++ * The pad stands for the lines number of IO[0:3].
++ * For example, the Quad read need four IO lines, so you should
++ * set LUT_PAD4 which means we use four IO lines.
++ */
++#define LUT_PAD1		0
++#define LUT_PAD2		1
++#define LUT_PAD4		2
++#define LUT_PAD8		3
++
++/* Oprands for the LUT register. */
++#define ADDR24BIT		0x18
++#define ADDR32BIT		0x20
++
++/* Macros for constructing the LUT register. */
++#define LUT0(ins, pad, opr)						\
++		(((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
++		((LUT_##ins) << INSTR0_SHIFT))
++
++#define LUT1(ins, pad, opr)	(LUT0(ins, pad, opr) << OPRND1_SHIFT)
++
++/* other macros for LUT register. */
++#define FSPI_LUT(x)		(FSPI_LUT_BASE + (x) * 4)
++#define FSPI_LUT_NUM		128
++
++/* SEQID -- we can have 32 seqids at most. */
++#define SEQID_READ		0
++#define SEQID_WREN		1
++#define SEQID_WRDI		2
++#define SEQID_RDSR		3
++#define SEQID_SE		4
++#define SEQID_CHIP_ERASE	5
++#define SEQID_PP		6
++#define SEQID_RDID		7
++#define SEQID_WRSR		8
++#define SEQID_RDCR		9
++#define SEQID_EN4B		10
++#define SEQID_BRWR		11
++#define SEQID_RD_EVCR		12
++#define SEQID_WD_EVCR		13
++#define SEQID_RDFSR		14
++
++#define FSPI_MIN_IOMAP		SZ_4M
++
++#define FSPI_RX_MAX_IPBUF_SIZE		0x200 /* 64 * 64bits  */
++#define FSPI_TX_MAX_IPBUF_SIZE		0x400 /* 128 * 64bits */
++#define FSPI_RX_MAX_AHBBUF_SIZE		0x800 /* 256 * 64bits */
++#define FSPI_TX_MAX_AHBBUF_SIZE		0x40  /* 8 * 64bits   */
++
++#define TX_IPBUF_SIZE		FSPI_TX_MAX_IPBUF_SIZE
++#define RX_IPBUF_SIZE		FSPI_RX_MAX_IPBUF_SIZE
++#define RX_AHBBUF_SIZE		FSPI_RX_MAX_AHBBUF_SIZE
++#define TX_AHBBUF_SIZE		FSPI_TX_MAX_AHBBUF_SIZE
++
++#define FSPI_SINGLE_MODE	1
++#define FSPI_OCTAL_MODE		8
++
++#define FSPINOR_OP_READ_1_1_8_4B	0x7c
++
++enum nxp_fspi_devtype {
++	NXP_FSPI_LX2160A,
++};
++
++struct nxp_fspi_devtype_data {
++	enum nxp_fspi_devtype devtype;
++	int rxfifo;
++	int txfifo;
++	int ahb_buf_size;
++	int driver_data;
++};
++
++static struct nxp_fspi_devtype_data lx2160a_data = {
++	.devtype = NXP_FSPI_LX2160A,
++	.rxfifo = RX_IPBUF_SIZE,
++	.txfifo = TX_IPBUF_SIZE,
++	.ahb_buf_size = RX_AHBBUF_SIZE,
++	.driver_data = 0,
++};
++
++#define NXP_FSPI_MAX_CHIP	4
++struct nxp_fspi {
++	struct mtd_info mtd[NXP_FSPI_MAX_CHIP];
++	struct spi_nor nor[NXP_FSPI_MAX_CHIP];
++	void __iomem *iobase;
++	void __iomem *ahb_addr;
++	u32 memmap_phy;
++	u32 memmap_offs;
++	u32 memmap_len;
++	struct clk *clk, *clk_en;
++	struct device *dev;
++	struct completion c;
++	struct nxp_fspi_devtype_data *devtype_data;
++	u32 nor_size;
++	u32 nor_num;
++	u32 clk_rate;
++	u32 spi_rx_bus_width;
++	u32 spi_tx_bus_width;
++	unsigned int chip_base_addr; /* We may support two chips. */
++	bool has_second_chip;
++	struct mutex lock;
++	struct pm_qos_request pm_qos_req;
++};
++
++static inline void nxp_fspi_unlock_lut(struct nxp_fspi *fspi)
++{
++	writel(FSPI_LUTKEY_VALUE, fspi->iobase + FSPI_LUTKEY);
++	writel(FSPI_LCKER_UNLOCK, fspi->iobase + FSPI_LCKCR);
++}
++
++static inline void nxp_fspi_lock_lut(struct nxp_fspi *fspi)
++{
++	writel(FSPI_LUTKEY_VALUE, fspi->iobase + FSPI_LUTKEY);
++	writel(FSPI_LCKER_LOCK, fspi->iobase + FSPI_LCKCR);
++}
++
++static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id)
++{
++	struct nxp_fspi *fspi = dev_id;
++	u32 reg;
++
++	reg = readl(fspi->iobase + FSPI_INTR);
++	writel(FSPI_INTR_IPCMDDONE_MASK, fspi->iobase + FSPI_INTR);
++	if (reg & FSPI_INTR_IPCMDDONE_MASK)
++		complete(&fspi->c);
++
++	return IRQ_HANDLED;
++}
++
++static void nxp_fspi_init_lut(struct nxp_fspi *fspi)
++{
++	void __iomem *base = fspi->iobase;
++	struct spi_nor *nor = &fspi->nor[0];
++	u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
++	u32 lut_base;
++	u8 op, dm;
++	int i;
++
++	nxp_fspi_unlock_lut(fspi);
++
++	/* Clear all the LUT table */
++	for (i = 0; i < FSPI_LUT_NUM; i++)
++		writel(0, base + FSPI_LUT_BASE + i * 4);
++
++	/* Read */
++	lut_base = SEQID_READ * 4;
++	op = nor->read_opcode;
++	dm = nor->read_dummy;
++
++	if (fspi->spi_rx_bus_width == FSPI_OCTAL_MODE) {
++		dm = 8;
++		op = FSPINOR_OP_READ_1_1_8_4B;
++		writel(LUT0(CMD, PAD1, op) | LUT1(ADDR, PAD1, addrlen),
++				base + FSPI_LUT(lut_base));
++		writel(LUT0(DUMMY, PAD8, dm) | LUT1(NXP_READ, PAD8, 0),
++				base + FSPI_LUT(lut_base + 1));
++	} else {
++		if ((op == SPINOR_OP_READ_FAST_4B) ||
++		     (op == SPINOR_OP_READ_FAST) ||
++		     (op == SPINOR_OP_READ) ||
++		     (op == SPINOR_OP_READ_4B)) {
++			dm = 8;
++			writel(LUT0(CMD, PAD1, op) | LUT1(ADDR, PAD1, addrlen),
++					base + FSPI_LUT(lut_base));
++			writel(LUT0(DUMMY, PAD1, dm) | LUT1(NXP_READ, PAD1, 0),
++					base + FSPI_LUT(lut_base + 1));
++		} else if (nor->read_proto == SNOR_PROTO_1_4_4) {
++			dev_dbg(nor->dev, "Unsupported opcode : 0x%.2x\n", op);
++			/* TODO Add support for other Read ops. */
++		} else {
++			dev_dbg(nor->dev, "Unsupported opcode : 0x%.2x\n", op);
++		}
++	}
++
++	/* Write enable */
++	lut_base = SEQID_WREN * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + FSPI_LUT(lut_base));
++
++	/* Page Program */
++	lut_base = SEQID_PP * 4;
++	writel(LUT0(CMD, PAD1, nor->program_opcode) | LUT1(ADDR, PAD1, addrlen),
++			base + FSPI_LUT(lut_base));
++	writel(LUT0(NXP_WRITE, PAD1, 0), base + FSPI_LUT(lut_base + 1));
++
++	/* Read Status */
++	lut_base = SEQID_RDSR * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(NXP_READ, PAD1, 0x1),
++			base + FSPI_LUT(lut_base));
++
++	/* Erase a sector */
++	lut_base = SEQID_SE * 4;
++	writel(LUT0(CMD, PAD1, nor->erase_opcode) | LUT1(ADDR, PAD1, addrlen),
++			base + FSPI_LUT(lut_base));
++
++	/* Erase the whole chip */
++	lut_base = SEQID_CHIP_ERASE * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
++			base + FSPI_LUT(lut_base));
++
++	/* READ ID */
++	lut_base = SEQID_RDID * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(NXP_READ, PAD1, 0x8),
++			base + FSPI_LUT(lut_base));
++
++	/* Write Register */
++	lut_base = SEQID_WRSR * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(NXP_WRITE, PAD1, 0x2),
++			base + FSPI_LUT(lut_base));
++
++	/* Read Configuration Register */
++	lut_base = SEQID_RDCR * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(NXP_READ, PAD1, 0x1),
++			base + FSPI_LUT(lut_base));
++
++	/* Write disable */
++	lut_base = SEQID_WRDI * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + FSPI_LUT(lut_base));
++
++	/* Enter 4 Byte Mode (Micron) */
++	lut_base = SEQID_EN4B * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + FSPI_LUT(lut_base));
++
++	/* Enter 4 Byte Mode (Spansion) */
++	lut_base = SEQID_BRWR * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + FSPI_LUT(lut_base));
++
++	/* Read EVCR register */
++	lut_base = SEQID_RD_EVCR * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
++	       base + FSPI_LUT(lut_base));
++
++	/* Write EVCR register */
++	lut_base = SEQID_WD_EVCR * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
++	       base + FSPI_LUT(lut_base));
++
++	/* Read Flag Status */
++	lut_base = SEQID_RDFSR * 4;
++	writel(LUT0(CMD, PAD1, SPINOR_OP_RDFSR) | LUT1(NXP_READ, PAD1, 0x1),
++			base + FSPI_LUT(lut_base));
++
++	nxp_fspi_lock_lut(fspi);
++}
++
++/* Get the SEQID for the command */
++static int nxp_fspi_get_seqid(struct nxp_fspi *fspi, u8 cmd)
++{
++
++	switch (cmd) {
++	case SPINOR_OP_READ_1_1_4_4B:
++	case SPINOR_OP_READ_1_1_4:
++	case SPINOR_OP_READ:
++	case SPINOR_OP_READ_4B:
++	case SPINOR_OP_READ_FAST:
++	case SPINOR_OP_READ_FAST_4B:
++		return SEQID_READ;
++	case SPINOR_OP_WREN:
++		return SEQID_WREN;
++	case SPINOR_OP_WRDI:
++		return SEQID_WRDI;
++	case SPINOR_OP_RDSR:
++		return SEQID_RDSR;
++	case SPINOR_OP_RDFSR:
++		return SEQID_RDFSR;
++	case SPINOR_OP_BE_4K:
++	case SPINOR_OP_SE:
++	case SPINOR_OP_SE_4B:
++	case SPINOR_OP_BE_4K_4B:
++		return SEQID_SE;
++	case SPINOR_OP_CHIP_ERASE:
++		return SEQID_CHIP_ERASE;
++	case SPINOR_OP_PP:
++	case SPINOR_OP_PP_4B:
++		return SEQID_PP;
++	case SPINOR_OP_RDID:
++		return SEQID_RDID;
++	case SPINOR_OP_WRSR:
++		return SEQID_WRSR;
++	case SPINOR_OP_RDCR:
++		return SEQID_RDCR;
++	case SPINOR_OP_EN4B:
++		return SEQID_EN4B;
++	case SPINOR_OP_BRWR:
++		return SEQID_BRWR;
++	case SPINOR_OP_RD_EVCR:
++		return SEQID_RD_EVCR;
++	case SPINOR_OP_WD_EVCR:
++		return SEQID_WD_EVCR;
++	default:
++		dev_err(fspi->dev, "Unsupported cmd 0x%.2x\n", cmd);
++		break;
 +	}
++	return -EINVAL;
++}
++
++static int
++nxp_fspi_runcmd(struct nxp_fspi *fspi, u8 cmd, unsigned int addr, int len)
++{
++	void __iomem *base = fspi->iobase;
++	int seqid;
++	int seqnum = 0;
++	u32 reg;
++	int err;
++	int iprxfcr = 0;
++
++	iprxfcr = readl(fspi->iobase + FSPI_IPRXFCR);
++	/* invalid RXFIFO first */
++	iprxfcr &= ~FSPI_IPRXFCR_DMA_EN_MASK;
++	iprxfcr = iprxfcr | FSPI_IPRXFCR_CLR_MASK;
++	writel(iprxfcr, fspi->iobase + FSPI_IPRXFCR);
++
++	init_completion(&fspi->c);
++	dev_dbg(fspi->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
++			fspi->chip_base_addr, addr, len, cmd);
++
++	/* write address */
++	writel(fspi->chip_base_addr + addr, base + FSPI_IPCR0);
++
++	seqid = nxp_fspi_get_seqid(fspi, cmd);
 +
-+	if (!free_blocks) {
-+		/* Let's commit before we use up the metadata reserve. */
-+		r = commit(pool);
-+		if (r)
-+			return r;
++	writel((seqnum << FSPI_IPCR1_SEQNUM_SHIFT) |
++			(seqid << FSPI_IPCR1_SEQID_SHIFT) | len,
++			base + FSPI_IPCR1);
++
++	/* wait till controller is idle */
++	do {
++		reg = readl(base + FSPI_STS0);
++		if ((reg & FSPI_STS0_ARB_IDLE_MASK) &&
++		    (reg & FSPI_STS0_SEQ_IDLE_MASK))
++			break;
++		udelay(1);
++		dev_dbg(fspi->dev, "The controller is busy, 0x%x\n", reg);
++	} while (1);
++
++	/* trigger the LUT now */
++	writel(1, base + FSPI_IPCMD);
++
++	/* Wait for the interrupt. */
++	if (!wait_for_completion_timeout(&fspi->c, msecs_to_jiffies(1000))) {
++		dev_err(fspi->dev,
++			"cmd 0x%.2x timeout, addr@%.8x, Status0:0x%.8x, Status1:0x%.8x\n",
++			cmd, addr, readl(base + FSPI_STS0),
++			readl(base + FSPI_STS1));
++		err = -ETIMEDOUT;
++	} else {
++		err = 0;
++		dev_dbg(fspi->dev, "FSPI Intr done,INTR:<0x%.8x>\n",
++			 readl(base + FSPI_INTR));
 +	}
 +
- 	return 0;
- }
- 
---- a/drivers/net/ethernet/qlogic/qed/qed_mcp.c
-+++ b/drivers/net/ethernet/qlogic/qed/qed_mcp.c
-@@ -616,6 +616,13 @@ static int qed_mcp_cmd_and_union(struct
- 		return -EBUSY;
- 	}
- 
-+	if (p_hwfn->mcp_info->b_block_cmd) {
-+		DP_NOTICE(p_hwfn,
-+			  "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
-+			  p_mb_params->cmd, p_mb_params->param);
++	return err;
++}
++
++/* Read out the data from the FSPI_RBDR buffer registers. */
++static void nxp_fspi_read_data(struct nxp_fspi *fspi, int len, u8 *rxbuf)
++{
++	int i = 0, j = 0, tmp_size = 0;
++	int size;
++	u32 tmp = 0;
++
++	while (len > 0) {
++
++		size = len / 8;
++
++		for (i = 0; i < size; ++i) {
++			/* Wait for RXFIFO available*/
++			while (!(readl(fspi->iobase + FSPI_INTR)
++				 & FSPI_INTR_IPRXWA_MASK))
++				;
++
++			j = 0;
++			tmp_size = 8;
++			while (tmp_size > 0) {
++				tmp = 0;
++				tmp = readl(fspi->iobase + FSPI_RFDR + j * 4);
++				memcpy(rxbuf, &tmp, 4);
++				tmp_size -= 4;
++				j++;
++				rxbuf += 4;
++			}
++
++			/* move the FIFO pointer */
++			writel(FSPI_INTR_IPRXWA_MASK,
++			       fspi->iobase + FSPI_INTR);
++			len -= 8;
++		}
++
++		size = len % 8;
++
++		j = 0;
++		if (size) {
++			/* Wait for RXFIFO available*/
++			while (!(readl(fspi->iobase + FSPI_INTR)
++				 & FSPI_INTR_IPRXWA_MASK))
++				;
++
++			while (len > 0) {
++				tmp = 0;
++				size = (len < 4) ? len : 4;
++				tmp = readl(fspi->iobase + FSPI_RFDR + j * 4);
++				memcpy(rxbuf, &tmp, size);
++				len -= size;
++				j++;
++				rxbuf += size;
++			}
++		}
++
++		/* invalid the RXFIFO */
++		writel(FSPI_IPRXFCR_CLR_MASK,
++		       fspi->iobase + FSPI_IPRXFCR);
++
++		writel(FSPI_INTR_IPRXWA_MASK,
++		       fspi->iobase + FSPI_INTR);
++	}
++}
++
++static inline void nxp_fspi_invalid(struct nxp_fspi *fspi)
++{
++	u32 reg;
++
++	reg = readl(fspi->iobase + FSPI_MCR0);
++	writel(reg | FSPI_MCR0_SWRST_MASK, fspi->iobase + FSPI_MCR0);
++
++	/*
++	 * The minimum delay : 1 AHB + 2 SFCK clocks.
++	 * Delay 1 us is enough.
++	 */
++	while (readl(fspi->iobase + FSPI_MCR0) & FSPI_MCR0_SWRST_MASK)
++		;
++}
++
++static ssize_t nxp_fspi_nor_write(struct nxp_fspi *fspi,
++				     struct spi_nor *nor, u8 opcode,
++				     unsigned int to, u32 *txbuf,
++				     unsigned int count)
++{
++	int ret, i, j;
++	int size, tmp_size;
++	u32 data = 0;
++
++	dev_dbg(fspi->dev, "nor write to 0x%.8x:0x%.8x, len : %d\n",
++		fspi->chip_base_addr, to, count);
++
++	/* clear the TX FIFO. */
++	writel(FSPI_IPTXFCR_CLR_MASK, fspi->iobase + FSPI_IPTXFCR);
++
++	size = count / 8;
++	for (i = 0; i < size; i++) {
++		/* Wait for TXFIFO empty*/
++		while (!(readl(fspi->iobase + FSPI_INTR)
++			 & FSPI_INTR_IPTXWE_MASK))
++			;
++		j = 0;
++		tmp_size = 8;
++		while (tmp_size > 0) {
++			data = 0;
++			memcpy(&data, txbuf, 4);
++			writel(data, fspi->iobase + FSPI_TFDR + j * 4);
++			tmp_size -= 4;
++			j++;
++			txbuf += 1;
++		}
++
++		writel(FSPI_INTR_IPTXWE_MASK, fspi->iobase + FSPI_INTR);
++	}
++
++	size = count % 8;
++	if (size) {
++		/* Wait for TXFIFO empty*/
++		while (!(readl(fspi->iobase + FSPI_INTR)
++			 & FSPI_INTR_IPTXWE_MASK))
++			;
++
++		j = 0;
++		tmp_size = 0;
++		while (size > 0) {
++			data = 0;
++			tmp_size = (size < 4) ? size : 4;
++			memcpy(&data, txbuf, tmp_size);
++			writel(data, fspi->iobase + FSPI_TFDR + j * 4);
++			size -= tmp_size;
++			j++;
++			txbuf += 1;
++		}
++
++		writel(FSPI_INTR_IPTXWE_MASK, fspi->iobase + FSPI_INTR);
++	}
++
++	/* Trigger it */
++	ret = nxp_fspi_runcmd(fspi, opcode, to, count);
++
++	if (ret == 0)
++		return count;
++
++	return ret;
++}
++
++static void nxp_fspi_set_map_addr(struct nxp_fspi *fspi)
++{
++	int nor_size = fspi->nor_size >> 10;
++	void __iomem *base = fspi->iobase;
++
++	/*
++	 * Supporting same flash device as slaves on different chip-select.
++	 * As SAMEDEVICEEN bit set, by default, in mcr2 reg then need not to
++	 * configure FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register as setting for
++	 * these would be ignored.
++	 * Need to Reset SAMEDEVICEEN bit in mcr2 reg, when require to add
++	 * support for different flashes.
++	 */
++	writel(nor_size, base + FSPI_FLSHA1CR0);
++	writel(0, base + FSPI_FLSHA2CR0);
++	writel(0, base + FSPI_FLSHB1CR0);
++	writel(0, base + FSPI_FLSHB2CR0);
++}
++
++static void nxp_fspi_init_ahb_read(struct nxp_fspi *fspi)
++{
++	void __iomem *base = fspi->iobase;
++	struct spi_nor *nor = &fspi->nor[0];
++	int i = 0;
++	int seqid;
++
++	/* AHB configuration for access buffer 0~7. */
++	for (i = 0; i < 7; i++)
++		writel(0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
++
++	/*
++	 * Set ADATSZ with the maximum AHB buffer size to improve the read
++	 * performance.
++	 */
++	writel((fspi->devtype_data->ahb_buf_size / 8 |
++		FSPI_AHBRXBUF0CR7_PREF_MASK), base + FSPI_AHBRX_BUF7CR0);
++
++	/* prefetch and no start address alignment limitation */
++	writel(FSPI_AHBCR_PREF_EN_MASK | FSPI_AHBCR_RDADDROPT_MASK,
++		    base + FSPI_AHBCR);
++
++
++	/* Set the default lut sequence for AHB Read. */
++	seqid = nxp_fspi_get_seqid(fspi, nor->read_opcode);
++	writel(seqid, base + FSPI_FLSHA1CR2);
++}
++
++/* This function was used to prepare and enable FSPI clock */
++static int nxp_fspi_clk_prep_enable(struct nxp_fspi *fspi)
++{
++	int ret;
++
++	ret = clk_prepare_enable(fspi->clk_en);
++	if (ret)
++		return ret;
++
++	ret = clk_prepare_enable(fspi->clk);
++	if (ret) {
++		clk_disable_unprepare(fspi->clk_en);
++		return ret;
++	}
++
++	return 0;
++}
++
++/* This function was used to disable and unprepare FSPI clock */
++static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *fspi)
++{
++	clk_disable_unprepare(fspi->clk);
++	clk_disable_unprepare(fspi->clk_en);
++}
++
++/* We use this function to do some basic init for spi_nor_scan(). */
++static int nxp_fspi_nor_setup(struct nxp_fspi *fspi)
++{
++	void __iomem *base = fspi->iobase;
++	u32 reg;
++
++	/* Reset the module */
++	writel(FSPI_MCR0_SWRST_MASK, base + FSPI_MCR0);
++	do {
++		udelay(1);
++	} while (0x1 & readl(base + FSPI_MCR0));
++
++	/* Disable the module */
++	writel(FSPI_MCR0_MDIS_MASK, base + FSPI_MCR0);
++
++	/* Reset the DLL register to default value */
++	writel(FSPI_DLLACR_OVRDEN_MASK, base + FSPI_DLLACR);
++	writel(FSPI_DLLBCR_OVRDEN_MASK, base + FSPI_DLLBCR);
++
++	/* enable module */
++	writel(FSPI_MCR0_AHB_TIMEOUT_MASK | FSPI_MCR0_IP_TIMEOUT_MASK,
++	       base + FSPI_MCR0);
++
++	/* Read the register value */
++	reg = readl(base + FSPI_MCR0);
++
++	/* Init the LUT table. */
++	nxp_fspi_init_lut(fspi);
++
++	/* enable the interrupt */
++	writel(FSPI_INTEN_IPCMDDONE_MASK, fspi->iobase + FSPI_INTEN);
++	return 0;
++}
++
++static int nxp_fspi_nor_setup_last(struct nxp_fspi *fspi)
++{
++	unsigned long rate = fspi->clk_rate;
++	int ret;
++
++	/* disable and unprepare clock to avoid glitch pass to controller */
++	nxp_fspi_clk_disable_unprep(fspi);
++
++	ret = clk_set_rate(fspi->clk, rate);
++	if (ret)
++		return ret;
++
++	ret = nxp_fspi_clk_prep_enable(fspi);
++	if (ret)
++		return ret;
++
++	/* Init the LUT table again. */
++	nxp_fspi_init_lut(fspi);
++
++	/* Init for AHB read */
++	nxp_fspi_init_ahb_read(fspi);
++
++	return 0;
++}
++
++static void nxp_fspi_set_base_addr(struct nxp_fspi *fspi,
++				      struct spi_nor *nor)
++{
++	fspi->chip_base_addr = fspi->nor_size * (nor - fspi->nor);
++}
++
++static int nxp_fspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
++				int len)
++{
++	int ret;
++	struct nxp_fspi *fspi = nor->priv;
++
++	ret = nxp_fspi_runcmd(fspi, opcode, 0, len);
++	if (ret)
++		return ret;
++
++	nxp_fspi_read_data(fspi, len, buf);
++	return 0;
++}
++
++static int nxp_fspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
++				 int len)
++{
++	struct nxp_fspi *fspi = nor->priv;
++	int ret;
++
++	if (!buf) {
++		ret = nxp_fspi_runcmd(fspi, opcode, 0, 1);
++		if (ret)
++			return ret;
++
++		if (opcode == SPINOR_OP_CHIP_ERASE)
++			nxp_fspi_invalid(fspi);
++
++	} else if (len > 0) {
++		ret = nxp_fspi_nor_write(fspi, nor, opcode, 0,
++					(u32 *)buf, len);
++	} else {
++		dev_err(fspi->dev, "invalid cmd %d\n", opcode);
++		ret = -EINVAL;
++	}
++
++	return ret;
++}
++
++static ssize_t nxp_fspi_write(struct spi_nor *nor, loff_t to,
++		size_t len, const u_char *buf)
++{
++	struct nxp_fspi *fspi = nor->priv;
++	ssize_t tx_size = 0, act_wrt = 0, ret = 0;
++
++	while (len > 0) {
++		tx_size = (len > TX_IPBUF_SIZE) ? TX_IPBUF_SIZE : len;
++
++		act_wrt = nxp_fspi_nor_write(fspi, nor, nor->program_opcode, to,
++					(u32 *)buf, tx_size);
++		len -= tx_size;
++		to  += tx_size;
++		ret += act_wrt;
++	}
++
++	/* invalid the data in the AHB buffer. */
++	nxp_fspi_invalid(fspi);
++	return ret;
++}
++
++static ssize_t nxp_fspi_read(struct spi_nor *nor, loff_t from,
++		size_t len, u_char *buf)
++{
++	struct nxp_fspi *fspi = nor->priv;
++
++	/* if necessary, ioremap buffer before AHB read, */
++	if (!fspi->ahb_addr) {
++		fspi->memmap_offs = fspi->chip_base_addr + from;
++		fspi->memmap_len = len > FSPI_MIN_IOMAP ?
++				   len : FSPI_MIN_IOMAP;
++
++		fspi->ahb_addr = ioremap_nocache(
++					fspi->memmap_phy + fspi->memmap_offs,
++					fspi->memmap_len);
++		if (!fspi->ahb_addr) {
++			dev_err(fspi->dev, "ioremap failed\n");
++			return -ENOMEM;
++		}
++	/* ioremap if the data requested is out of range */
++	} else if (fspi->chip_base_addr + from < fspi->memmap_offs
++			|| fspi->chip_base_addr + from + len >
++			fspi->memmap_offs + fspi->memmap_len) {
++		iounmap(fspi->ahb_addr);
++
++		fspi->memmap_offs = fspi->chip_base_addr + from;
++		fspi->memmap_len = len > FSPI_MIN_IOMAP ?
++				   len : FSPI_MIN_IOMAP;
++		fspi->ahb_addr = ioremap_nocache(
++					fspi->memmap_phy + fspi->memmap_offs,
++					fspi->memmap_len);
++		if (!fspi->ahb_addr) {
++			dev_err(fspi->dev, "ioremap failed\n");
++			return -ENOMEM;
++		}
++	}
++
++	dev_dbg(fspi->dev, "cmd [%x],read from %p, len:%zd\n",
++		nor->read_opcode, fspi->ahb_addr + fspi->chip_base_addr
++		+ from - fspi->memmap_offs, len);
++
++	/* Read out the data directly from the AHB buffer.*/
++	memcpy_toio(buf, fspi->ahb_addr + fspi->chip_base_addr
++		+ from - fspi->memmap_offs, len);
++
++	return len;
++}
++
++static int nxp_fspi_erase(struct spi_nor *nor, loff_t offs)
++{
++	struct nxp_fspi *fspi = nor->priv;
++	int ret;
++
++	dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
++		nor->mtd.erasesize / 1024, fspi->chip_base_addr, (u32)offs);
++
++	ret = nxp_fspi_runcmd(fspi, nor->erase_opcode, offs, 0);
++	if (ret)
++		return ret;
++
++	nxp_fspi_invalid(fspi);
++	return 0;
++}
++
++static int nxp_fspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
++{
++	struct nxp_fspi *fspi = nor->priv;
++	int ret;
++
++	mutex_lock(&fspi->lock);
++
++	ret = nxp_fspi_clk_prep_enable(fspi);
++	if (ret)
++		goto err_mutex;
++
++	nxp_fspi_set_base_addr(fspi, nor);
++	return 0;
++
++err_mutex:
++	mutex_unlock(&fspi->lock);
++	return ret;
++}
++
++static void nxp_fspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
++{
++	struct nxp_fspi *fspi = nor->priv;
++
++	nxp_fspi_clk_disable_unprep(fspi);
++	mutex_unlock(&fspi->lock);
++}
++
++static const struct of_device_id nxp_fspi_dt_ids[] = {
++	{ .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);
++
++static int nxp_fspi_probe(struct platform_device *pdev)
++{
++	struct spi_nor_hwcaps hwcaps = {
++		.mask = SPINOR_OP_READ_FAST_4B |
++			SPINOR_OP_READ_4B |
++			SNOR_HWCAPS_PP
++	};
++	struct device_node *np = pdev->dev.of_node;
++	struct device *dev = &pdev->dev;
++	struct nxp_fspi *fspi;
++	struct resource *res;
++	struct spi_nor *nor;
++	struct mtd_info *mtd;
++	int ret, i = 0;
++	int find_node = 0;
++
++	const struct of_device_id *of_id =
++			of_match_device(nxp_fspi_dt_ids, &pdev->dev);
++
++	fspi = devm_kzalloc(dev, sizeof(*fspi), GFP_KERNEL);
++	if (!fspi)
++		return -ENOMEM;
++
++	fspi->nor_num = of_get_child_count(dev->of_node);
++	if (!fspi->nor_num || fspi->nor_num > 4)
++		return -ENODEV;
++
++	fspi->dev = dev;
++	fspi->devtype_data = (struct nxp_fspi_devtype_data *)of_id->data;
++	platform_set_drvdata(pdev, fspi);
++
++	/* find the resources */
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "FSPI");
++	if (!res) {
++		dev_err(dev, "FSPI get resource IORESOURCE_MEM failed\n");
++		return -ENODEV;
++	}
++
++	fspi->iobase = devm_ioremap_resource(dev, res);
++	if (IS_ERR(fspi->iobase))
++		return PTR_ERR(fspi->iobase);
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
++					   "FSPI-memory");
++	if (!res) {
++		dev_err(dev,
++			"FSPI-memory get resource IORESOURCE_MEM failed\n");
++		return -ENODEV;
++	}
++
++	if (!devm_request_mem_region(dev, res->start, resource_size(res),
++				     res->name)) {
++		dev_err(dev, "can't request region for resource %pR\n", res);
 +		return -EBUSY;
 +	}
 +
- 	if (p_mb_params->data_src_size > union_data_size ||
- 	    p_mb_params->data_dst_size > union_data_size) {
- 		DP_ERR(p_hwfn,
---- a/drivers/net/phy/xilinx_gmii2rgmii.c
-+++ b/drivers/net/phy/xilinx_gmii2rgmii.c
-@@ -92,6 +92,11 @@ static int xgmiitorgmii_probe(struct mdi
- 		return -EPROBE_DEFER;
- 	}
- 
-+	if (!priv->phy_dev->drv) {
-+		dev_info(dev, "Attached phy not ready\n");
-+		return -EPROBE_DEFER;
-+	}
-+
- 	priv->addr = mdiodev->addr;
- 	priv->phy_drv = priv->phy_dev->drv;
- 	memcpy(&priv->conv_phy_drv, priv->phy_dev->drv,
---- a/drivers/spi/spi-tegra20-slink.c
-+++ b/drivers/spi/spi-tegra20-slink.c
-@@ -1081,6 +1081,24 @@ static int tegra_slink_probe(struct plat
- 		goto exit_free_master;
- 	}
- 
-+	/* disabled clock may cause interrupt storm upon request */
-+	tspi->clk = devm_clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(tspi->clk)) {
-+		ret = PTR_ERR(tspi->clk);
-+		dev_err(&pdev->dev, "Can not get clock %d\n", ret);
-+		goto exit_free_master;
-+	}
-+	ret = clk_prepare(tspi->clk);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
-+		goto exit_free_master;
++	fspi->memmap_phy = res->start;
++
++	/* find the clocks */
++	fspi->clk_en = devm_clk_get(dev, "fspi_en");
++	if (IS_ERR(fspi->clk_en))
++		return PTR_ERR(fspi->clk_en);
++
++	fspi->clk = devm_clk_get(dev, "fspi");
++	if (IS_ERR(fspi->clk))
++		return PTR_ERR(fspi->clk);
++
++	ret = nxp_fspi_clk_prep_enable(fspi);
++	if (ret) {
++		dev_err(dev, "can not enable the clock\n");
++		goto clk_failed;
 +	}
-+	ret = clk_enable(tspi->clk);
++
++	/* find the irq */
++	ret = platform_get_irq(pdev, 0);
 +	if (ret < 0) {
-+		dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
-+		goto exit_free_master;
-+	}
-+
- 	spi_irq = platform_get_irq(pdev, 0);
- 	tspi->irq = spi_irq;
- 	ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
---- a/drivers/staging/android/ashmem.c
-+++ b/drivers/staging/android/ashmem.c
-@@ -380,6 +380,12 @@ static int ashmem_mmap(struct file *file
- 		goto out;
- 	}
- 
-+	/* requested mapping size larger than object size */
-+	if (vma->vm_end - vma->vm_start > PAGE_ALIGN(asma->size)) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
- 	/* requested protection bits must match our allowed protection mask */
- 	if (unlikely((vma->vm_flags & ~calc_vm_prot_bits(asma->prot_mask, 0)) &
- 		     calc_vm_prot_bits(PROT_MASK, 0))) {
---- a/drivers/tty/serial/imx.c
-+++ b/drivers/tty/serial/imx.c
-@@ -2221,6 +2221,14 @@ static int serial_imx_probe(struct platf
- 				ret);
- 			return ret;
- 		}
-+
-+		ret = devm_request_irq(&pdev->dev, rtsirq, imx_rtsint, 0,
-+				       dev_name(&pdev->dev), sport);
-+		if (ret) {
-+			dev_err(&pdev->dev, "failed to request rts irq: %d\n",
-+				ret);
-+			return ret;
++		dev_err(dev, "failed to get the irq: %d\n", ret);
++		goto irq_failed;
++	}
++
++	ret = devm_request_irq(dev, ret,
++			nxp_fspi_irq_handler, 0, pdev->name, fspi);
++	if (ret) {
++		dev_err(dev, "failed to request irq: %d\n", ret);
++		goto irq_failed;
++	}
++
++	ret = nxp_fspi_nor_setup(fspi);
++	if (ret)
++		goto irq_failed;
++
++	if (of_get_property(np, "nxp,fspi-has-second-chip", NULL))
++		fspi->has_second_chip = true;
++
++	mutex_init(&fspi->lock);
++
++	find_node = 0;
++	/* iterate the subnodes. */
++	for_each_available_child_of_node(dev->of_node, np) {
++		/* skip the holes */
++		if (!fspi->has_second_chip)
++			i *= 2;
++
++		nor = &fspi->nor[i];
++		mtd = &nor->mtd;
++
++		nor->dev = dev;
++		spi_nor_set_flash_node(nor, np);
++		nor->priv = fspi;
++
++		/* fill the hooks */
++		nor->read_reg = nxp_fspi_read_reg;
++		nor->write_reg = nxp_fspi_write_reg;
++		nor->read = nxp_fspi_read;
++		nor->write = nxp_fspi_write;
++		nor->erase = nxp_fspi_erase;
++
++		nor->prepare = nxp_fspi_prep;
++		nor->unprepare = nxp_fspi_unprep;
++
++		ret = of_property_read_u32(np, "spi-max-frequency",
++				&fspi->clk_rate);
++		if (ret < 0)
++			goto next_node;
++
++		/* set the chip address for READID */
++		nxp_fspi_set_base_addr(fspi, nor);
++
++		ret = of_property_read_u32(np, "spi-rx-bus-width",
++				&fspi->spi_rx_bus_width);
++		if (ret < 0)
++			fspi->spi_rx_bus_width = FSPI_SINGLE_MODE;
++
++		ret = of_property_read_u32(np, "spi-tx-bus-width",
++				&fspi->spi_tx_bus_width);
++		if (ret < 0)
++			fspi->spi_tx_bus_width = FSPI_SINGLE_MODE;
++
++		ret = spi_nor_scan(nor, NULL, &hwcaps);
++		if (ret)
++			goto next_node;
++
++		ret = mtd_device_register(mtd, NULL, 0);
++		if (ret)
++			goto next_node;
++
++		/* Set the correct NOR size now. */
++		if (fspi->nor_size == 0) {
++			fspi->nor_size = mtd->size;
++
++			/* Map the SPI NOR to accessiable address */
++			nxp_fspi_set_map_addr(fspi);
 +		}
- 	} else {
- 		ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
- 				       dev_name(&pdev->dev), sport);
---- a/kernel/events/core.c
-+++ b/kernel/events/core.c
-@@ -3763,6 +3763,12 @@ int perf_event_read_local(struct perf_ev
- 		goto out;
- 	}
++
++		/*
++		 * The write is working in the  unit of the TX FIFO,
++		 * not in the unit of the SPI NOR's page size.
++		 *
++		 * So shrink the spi_nor->page_size if it is larger then the
++		 * TX FIFO.
++		 */
++		if (nor->page_size > fspi->devtype_data->txfifo)
++			nor->page_size = fspi->devtype_data->txfifo;
++
++		find_node++;
++next_node:
++		i++;
++	}
++
++	if (find_node == 0)
++		goto mutex_failed;
++
++	/* finish the rest init. */
++	ret = nxp_fspi_nor_setup_last(fspi);
++	if (ret)
++		goto last_init_failed;
++
++	nxp_fspi_clk_disable_unprep(fspi);
++	return 0;
++
++last_init_failed:
++	for (i = 0; i < fspi->nor_num; i++) {
++		/* skip the holes */
++		if (!fspi->has_second_chip)
++			i *= 2;
++		mtd_device_unregister(&fspi->mtd[i]);
++	}
++mutex_failed:
++	mutex_destroy(&fspi->lock);
++irq_failed:
++	nxp_fspi_clk_disable_unprep(fspi);
++clk_failed:
++	dev_err(dev, "NXP FSPI probe failed\n");
++	return ret;
++}
++
++static int nxp_fspi_remove(struct platform_device *pdev)
++{
++	struct nxp_fspi *fspi = platform_get_drvdata(pdev);
++	int i;
++
++	for (i = 0; i < fspi->nor_num; i++) {
++		/* skip the holes */
++		if (!fspi->has_second_chip)
++			i *= 2;
++		mtd_device_unregister(&fspi->nor[i].mtd);
++	}
++
++	/* disable the hardware */
++	writel(FSPI_MCR0_MDIS_MASK, fspi->iobase + FSPI_MCR0);
++
++	mutex_destroy(&fspi->lock);
++
++	if (fspi->ahb_addr)
++		iounmap(fspi->ahb_addr);
++
++	return 0;
++}
++
++static int nxp_fspi_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	return 0;
++}
++
++static int nxp_fspi_resume(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static struct platform_driver nxp_fspi_driver = {
++	.driver = {
++		.name	= "nxp-fspi",
++		.bus	= &platform_bus_type,
++		.of_match_table = nxp_fspi_dt_ids,
++	},
++	.probe          = nxp_fspi_probe,
++	.remove		= nxp_fspi_remove,
++	.suspend	= nxp_fspi_suspend,
++	.resume		= nxp_fspi_resume,
++};
++module_platform_driver(nxp_fspi_driver);
++
++MODULE_DESCRIPTION("NXP FSPI Controller Driver");
++MODULE_AUTHOR("NXP Semiconductor");
++MODULE_LICENSE("GPL v2");
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -269,6 +269,7 @@ static inline int set_4byte(struct spi_n
+ 	u8 cmd;
  
-+	/* If this is a pinned event it must be running on this CPU */
-+	if (event->attr.pinned && event->oncpu != smp_processor_id()) {
-+		ret = -EBUSY;
-+		goto out;
-+	}
-+
- 	/*
- 	 * If the event is currently on this CPU, its either a per-task event,
- 	 * or local to this CPU. Furthermore it means its ACTIVE (otherwise
---- a/sound/soc/soc-dapm.c
-+++ b/sound/soc/soc-dapm.c
-@@ -4036,6 +4036,13 @@ int snd_soc_dapm_link_dai_widgets(struct
- 			continue;
- 		}
+ 	switch (JEDEC_MFR(info)) {
++	case SNOR_MFR_ST:
+ 	case SNOR_MFR_MICRON:
+ 		/* Some Micron need WREN command; all will accept it */
+ 		need_wren = true;
+@@ -1039,7 +1040,7 @@ static const struct flash_info spi_nor_i
+ 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
  
-+		/* let users know there is no DAI to link */
-+		if (!dai_w->priv) {
-+			dev_dbg(card->dev, "dai widget %s has no DAI\n",
-+				dai_w->name);
-+			continue;
-+		}
+-	/* Micron */
++	/* Micron <--> ST Micro */
+ 	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | SPI_NOR_QUAD_READ) },
+ 	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
+ 	{ "n25q032a",	 INFO(0x20bb16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
+@@ -1054,6 +1055,12 @@ static const struct flash_info spi_nor_i
+ 	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+ 	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+ 
++	/* Micron */
++	{
++		"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
++			SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
++	},
 +
- 		dai = dai_w->priv;
+ 	/* PMC */
+ 	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
+ 	{ "pm25lv010",   INFO(0,        0, 32 * 1024,    4, SECT_4K_PMC) },
+@@ -2431,6 +2438,7 @@ static int spi_nor_init_params(struct sp
+ 			params->quad_enable = macronix_quad_enable;
+ 			break;
+ 
++		case SNOR_MFR_ST:
+ 		case SNOR_MFR_MICRON:
+ 			break;
+ 
+@@ -2749,7 +2757,8 @@ int spi_nor_scan(struct spi_nor *nor, co
+ 	mtd->_read = spi_nor_read;
+ 
+ 	/* NOR protection support for STmicro/Micron chips and similar */
+-	if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
++	if (JEDEC_MFR(info) == SNOR_MFR_ST ||
++	    JEDEC_MFR(info) == SNOR_MFR_MICRON ||
+ 	    JEDEC_MFR(info) == SNOR_MFR_WINBOND ||
+ 	    info->flags & SPI_NOR_HAS_LOCK) {
+ 		nor->flash_lock = stm_lock;
+--- a/include/linux/mtd/cfi.h
++++ b/include/linux/mtd/cfi.h
+@@ -377,6 +377,7 @@ struct cfi_fixup {
+ #define CFI_MFR_SHARP		0x00B0
+ #define CFI_MFR_SST		0x00BF
+ #define CFI_MFR_ST		0x0020 /* STMicroelectronics */
++#define CFI_MFR_MICRON		0x002C /* Micron */
+ #define CFI_MFR_TOSHIBA		0x0098
+ #define CFI_MFR_WINBOND		0x00DA
  
- 		/* ...find all widgets with the same stream and link them */
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -23,7 +23,8 @@
+ #define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
+ #define SNOR_MFR_GIGADEVICE	0xc8
+ #define SNOR_MFR_INTEL		CFI_MFR_INTEL
+-#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <--> Micron */
++#define SNOR_MFR_ST		CFI_MFR_ST	/* ST Micro */
++#define SNOR_MFR_MICRON		CFI_MFR_MICRON	/* Micron */
+ #define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
+ #define SNOR_MFR_SPANSION	CFI_MFR_AMD
+ #define SNOR_MFR_SST		CFI_MFR_SST

target/linux/layerscape/patches-4.14/818-qspi-support-layerscape.patch

@@ -1,68 +1,26 @@
-From 60eee49f37b77bc2d5f46c5db5a5c24d0c31bd02 Mon Sep 17 00:00:00 2001
+From fe21ef44284a3aa6fd80448e4ab2e1e8a55fb926 Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 20 Nov 2018 15:36:57 +0800
+Date: Wed, 17 Apr 2019 18:58:59 +0800
 Subject: [PATCH] qspi: support layerscape
 
 This is an integrated patch of qspi for layerscape
 
 Signed-off-by: Abhimanyu Saini <[email protected]>
+Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Chuanhua Han <[email protected]>
 Signed-off-by: Cyrille Pitchen <[email protected]>
+Signed-off-by: Mark Brown <[email protected]>
 Signed-off-by: Neil Armstrong <[email protected]>
 Signed-off-by: Prabhakar Kushwaha <[email protected]>
 Signed-off-by: Suresh Gupta <[email protected]>
-Signed-off-by: Yogesh Gaur <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Yangbo Lu <[email protected]>
+Signed-off-by: Yogesh Gaur <[email protected]>
 ---
- .../devicetree/bindings/mtd/fsl-quadspi.txt   |  31 ++
- drivers/mtd/spi-nor/fsl-quadspi.c             | 444 +++++++++++-------
- drivers/mtd/spi-nor/spi-nor.c                 |   5 +
- 3 files changed, 320 insertions(+), 160 deletions(-)
+ drivers/mtd/spi-nor/fsl-quadspi.c | 444 +++++++++++++++++++-----------
+ drivers/mtd/spi-nor/spi-nor.c     |   5 +
+ drivers/spi/spi-fsl-dspi.c        |   4 +-
+ 3 files changed, 291 insertions(+), 162 deletions(-)
 
---- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
-+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
-@@ -7,6 +7,7 @@ Required properties:
- 		 or
- 		 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
- 		 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
-+		 "fsl,ls2080a-qspi" followed by "fsl,ls1088a-qspi",
-   - reg : the first contains the register location and length,
-           the second contains the memory mapping address and length
-   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-@@ -39,3 +40,33 @@ qspi0: quadspi@40044000 {
- 		....
- 	};
- };
-+
-+qspi1: quadspi@20c0000 {
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	reg = <0x0 0x20c0000 0x0 0x10000>,
-+		<0x0 0x20000000 0x0 0x10000000>;
-+	reg-names = "QuadSPI", "QuadSPI-memory";
-+	interrupts = <0 25 0x4>; /* Level high type */
-+	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+	clock-names = "qspi_en", "qspi";
-+	status = "okay";
-+
-+	qflash0: s25fs512s@0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+
-+	qflash1: s25fs512s@1 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <1>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+};
 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
 @@ -41,6 +41,7 @@
@@ -760,7 +718,7 @@ Signed-off-by: Yangbo Lu <[email protected]>
  
 --- a/drivers/mtd/spi-nor/spi-nor.c
 +++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -1147,6 +1147,11 @@ static const struct flash_info spi_nor_i
+@@ -1154,6 +1154,11 @@ static const struct flash_info spi_nor_i
  	{ "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
  	{ "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
  	{ "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
@@ -772,3 +730,16 @@ Signed-off-by: Yangbo Lu <[email protected]>
  	{ "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
  	{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
  	{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
+--- a/drivers/spi/spi-fsl-dspi.c
++++ b/drivers/spi/spi-fsl-dspi.c
+@@ -1024,8 +1024,8 @@ static int dspi_probe(struct platform_de
+ 		goto out_clk_put;
+ 	}
+ 
+-	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
+-			pdev->name, dspi);
++	ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt,
++				   IRQF_SHARED, pdev->name, dspi);
+ 	if (ret < 0) {
+ 		dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
+ 		goto out_clk_put;

target/linux/layerscape/patches-4.14/819-sdhc-support-layerscape.patch

@@ -1,18 +1,75 @@
-From f901f791d07deaeba6310ac070769575a0bb790a Mon Sep 17 00:00:00 2001
+From 6ca94d2e7dc72b21703e6d9be4e8ec3ad4a26f41 Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:27:54 +0800
-Subject: [PATCH 36/40] sdhc: support layerscape
+Date: Wed, 17 Apr 2019 18:59:02 +0800
+Subject: [PATCH] sdhc: support layerscape
+
 This is an integrated patch of sdhc for layerscape
 
-Signed-off-by: Yinbo Zhu <[email protected]>
 Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Mathew McBride <[email protected]>
+Signed-off-by: Ulf Hansson <[email protected]>
+Signed-off-by: Yangbo Lu <[email protected]>
+Signed-off-by: Yinbo Zhu <[email protected]>
 ---
- drivers/mmc/host/sdhci-of-esdhc.c | 85 +++++++++++++++++++++----------
- 1 file changed, 57 insertions(+), 28 deletions(-)
+ drivers/mmc/core/mmc.c            |   3 +
+ drivers/mmc/host/sdhci-esdhc.h    |  25 +++
+ drivers/mmc/host/sdhci-of-esdhc.c | 270 ++++++++++++++++++++++++++----
+ drivers/mmc/host/sdhci.c          |   9 +-
+ drivers/mmc/host/sdhci.h          |   1 +
+ include/linux/mmc/card.h          |   1 +
+ include/linux/mmc/host.h          |   2 +
+ 7 files changed, 272 insertions(+), 39 deletions(-)
 
+--- a/drivers/mmc/core/mmc.c
++++ b/drivers/mmc/core/mmc.c
+@@ -1174,6 +1174,9 @@ static int mmc_select_hs400(struct mmc_c
+ 		goto out_err;
+ 
+ 	/* Switch card to DDR */
++	if (host->ops->prepare_ddr_to_hs400)
++		host->ops->prepare_ddr_to_hs400(host);
++
+ 	err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ 			 EXT_CSD_BUS_WIDTH,
+ 			 EXT_CSD_DDR_BUS_WIDTH_8,
+--- a/drivers/mmc/host/sdhci-esdhc.h
++++ b/drivers/mmc/host/sdhci-esdhc.h
+@@ -59,7 +59,32 @@
+ 
+ /* Tuning Block Control Register */
+ #define ESDHC_TBCTL			0x120
++#define ESDHC_HS400_WNDW_ADJUST		0x00000040
++#define ESDHC_HS400_MODE		0x00000010
+ #define ESDHC_TB_EN			0x00000004
++#define ESDHC_TBPTR			0x128
++
++/* SD Clock Control Register */
++#define ESDHC_SDCLKCTL			0x144
++#define ESDHC_LPBK_CLK_SEL		0x80000000
++#define ESDHC_CMD_CLK_CTL		0x00008000
++
++/* SD Timing Control Register */
++#define ESDHC_SDTIMNGCTL		0x148
++#define ESDHC_FLW_CTL_BG		0x00008000
++
++/* DLL Config 0 Register */
++#define ESDHC_DLLCFG0			0x160
++#define ESDHC_DLL_ENABLE		0x80000000
++#define ESDHC_DLL_FREQ_SEL		0x08000000
++
++/* DLL Config 1 Register */
++#define ESDHC_DLLCFG1			0x164
++#define ESDHC_DLL_PD_PULSE_STRETCH_SEL	0x80000000
++
++/* DLL Status 0 Register */
++#define ESDHC_DLLSTAT0			0x170
++#define ESDHC_DLL_STS_SLV_LOCK		0x08000000
+ 
+ /* Control Register for DMA transfer */
+ #define ESDHC_DMA_SYSCTL		0x40c
 --- a/drivers/mmc/host/sdhci-of-esdhc.c
 +++ b/drivers/mmc/host/sdhci-of-esdhc.c
-@@ -30,11 +30,56 @@
+@@ -30,11 +30,61 @@
  #define VENDOR_V_22	0x12
  #define VENDOR_V_23	0x13
  
@@ -64,20 +121,38 @@ Signed-off-by: Biwen Li <[email protected]>
  	u8 vendor_ver;
  	u8 spec_ver;
  	bool quirk_incorrect_hostver;
++	bool quirk_limited_clk_division;
++	bool quirk_unreliable_pulse_detection;
++	bool quirk_fixup_tuning;
++	bool quirk_incorrect_delay_chain;
  	unsigned int peripheral_clock;
 +	const struct esdhc_clk_fixup *clk_fixup;
++	u32 div_ratio;
  };
  
  /**
-@@ -502,6 +547,7 @@ static void esdhc_of_set_clock(struct sd
+@@ -495,13 +545,20 @@ static void esdhc_clock_enable(struct sd
+ 	}
+ }
+ 
++static struct soc_device_attribute soc_incorrect_delay_chain[] = {
++	{ .family = "QorIQ LX2160A", .revision = "1.0", },
++	{ },
++};
++
+ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
+ {
+ 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
  	int pre_div = 1;
  	int div = 1;
++	int division;
  	ktime_t timeout;
 +	long fixup = 0;
  	u32 temp;
  
  	host->mmc->actual_clock = 0;
-@@ -515,27 +561,14 @@ static void esdhc_of_set_clock(struct sd
+@@ -515,27 +572,14 @@ static void esdhc_of_set_clock(struct sd
  	if (esdhc->vendor_ver < VENDOR_V_23)
  		pre_div = 2;
  
@@ -112,25 +187,300 @@ Signed-off-by: Biwen Li <[email protected]>
  
  	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
  	temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
-@@ -800,6 +833,7 @@ static struct soc_device_attribute soc_i
+@@ -548,9 +592,30 @@ static void esdhc_of_set_clock(struct sd
+ 	while (host->max_clk / pre_div / div > clock && div < 16)
+ 		div++;
+ 
++	if (esdhc->quirk_limited_clk_division &&
++	    clock == MMC_HS200_MAX_DTR &&
++	    (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
++	     host->flags & SDHCI_HS400_TUNING)) {
++		division = pre_div * div;
++		if (division <= 4) {
++			pre_div = 4;
++			div = 1;
++		} else if (division <= 8) {
++			pre_div = 4;
++			div = 2;
++		} else if (division <= 12) {
++			pre_div = 4;
++			div = 3;
++		} else {
++			pr_warn("%s: using upsupported clock division.\n",
++				mmc_hostname(host->mmc));
++		}
++	}
++
+ 	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
+ 		clock, host->max_clk / pre_div / div);
+ 	host->mmc->actual_clock = host->max_clk / pre_div / div;
++	esdhc->div_ratio = pre_div * div;
+ 	pre_div >>= 1;
+ 	div--;
+ 
+@@ -560,6 +625,29 @@ static void esdhc_of_set_clock(struct sd
+ 		| (pre_div << ESDHC_PREDIV_SHIFT));
+ 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
+ 
++	if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
++	    clock == MMC_HS200_MAX_DTR) {
++		temp = sdhci_readl(host, ESDHC_TBCTL);
++		sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
++		temp = sdhci_readl(host, ESDHC_SDCLKCTL);
++		sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
++		esdhc_clock_enable(host, true);
++
++		temp = sdhci_readl(host, ESDHC_DLLCFG0);
++		temp |= ESDHC_DLL_ENABLE;
++		if (host->mmc->actual_clock == MMC_HS200_MAX_DTR ||
++		    esdhc->quirk_incorrect_delay_chain == false)
++			temp |= ESDHC_DLL_FREQ_SEL;
++		sdhci_writel(host, temp, ESDHC_DLLCFG0);
++		temp = sdhci_readl(host, ESDHC_TBCTL);
++		sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
++
++		esdhc_clock_enable(host, false);
++		temp = sdhci_readl(host, ESDHC_DMA_SYSCTL);
++		temp |= ESDHC_FLUSH_ASYNC_FIFO;
++		sdhci_writel(host, temp, ESDHC_DMA_SYSCTL);
++	}
++
+ 	/* Wait max 20 ms */
+ 	timeout = ktime_add_ms(ktime_get(), 20);
+ 	while (1) {
+@@ -575,6 +663,7 @@ static void esdhc_of_set_clock(struct sd
+ 		udelay(10);
+ 	}
+ 
++	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
+ 	temp |= ESDHC_CLOCK_SDCLKEN;
+ 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
+ }
+@@ -603,6 +692,8 @@ static void esdhc_pltfm_set_bus_width(st
+ 
+ static void esdhc_reset(struct sdhci_host *host, u8 mask)
+ {
++	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
+ 	u32 val;
+ 
+ 	sdhci_reset(host, mask);
+@@ -617,6 +708,12 @@ static void esdhc_reset(struct sdhci_hos
+ 		val = sdhci_readl(host, ESDHC_TBCTL);
+ 		val &= ~ESDHC_TB_EN;
+ 		sdhci_writel(host, val, ESDHC_TBCTL);
++
++		if (esdhc->quirk_unreliable_pulse_detection) {
++			val = sdhci_readl(host, ESDHC_DLLCFG1);
++			val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
++			sdhci_writel(host, val, ESDHC_DLLCFG1);
++		}
+ 	}
+ }
+ 
+@@ -628,6 +725,7 @@ static void esdhc_reset(struct sdhci_hos
+ static const struct of_device_id scfg_device_ids[] = {
+ 	{ .compatible = "fsl,t1040-scfg", },
+ 	{ .compatible = "fsl,ls1012a-scfg", },
++	{ .compatible = "fsl,ls1043a-scfg", },
+ 	{ .compatible = "fsl,ls1046a-scfg", },
+ 	{}
+ };
+@@ -690,23 +788,91 @@ static int esdhc_signal_voltage_switch(s
+ 	}
+ }
+ 
+-static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
++static struct soc_device_attribute soc_fixup_tuning[] = {
++	{ .family = "QorIQ T1040", .revision = "1.0", },
++	{ .family = "QorIQ T2080", .revision = "1.0", },
++	{ .family = "QorIQ T1023", .revision = "1.0", },
++	{ .family = "QorIQ LS1021A", .revision = "1.0", },
++	{ .family = "QorIQ LS1080A", .revision = "1.0", },
++	{ .family = "QorIQ LS2080A", .revision = "1.0", },
++	{ .family = "QorIQ LS1012A", .revision = "1.0", },
++	{ .family = "QorIQ LS1043A", .revision = "1.*", },
++	{ .family = "QorIQ LS1046A", .revision = "1.0", },
++	{ },
++};
++
++static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
+ {
+-	struct sdhci_host *host = mmc_priv(mmc);
+ 	u32 val;
+ 
+-	/* Use tuning block for tuning procedure */
+ 	esdhc_clock_enable(host, false);
++
+ 	val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
+ 	val |= ESDHC_FLUSH_ASYNC_FIFO;
+ 	sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
+ 
+ 	val = sdhci_readl(host, ESDHC_TBCTL);
+-	val |= ESDHC_TB_EN;
++	if (enable)
++		val |= ESDHC_TB_EN;
++	else
++		val &= ~ESDHC_TB_EN;
+ 	sdhci_writel(host, val, ESDHC_TBCTL);
++
+ 	esdhc_clock_enable(host, true);
++}
++
++static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
++{
++	struct sdhci_host *host = mmc_priv(mmc);
++	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
++	bool hs400_tuning;
++	u32 val;
++	int ret;
++
++	if (esdhc->quirk_limited_clk_division &&
++	    host->flags & SDHCI_HS400_TUNING)
++		esdhc_of_set_clock(host, host->clock);
++
++	esdhc_tuning_block_enable(host, true);
++
++	hs400_tuning = host->flags & SDHCI_HS400_TUNING;
++	ret = sdhci_execute_tuning(mmc, opcode);
++
++	if (hs400_tuning) {
++		val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
++		val |= ESDHC_FLW_CTL_BG;
++		sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
++	}
+ 
+-	return sdhci_execute_tuning(mmc, opcode);
++	if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) {
++
++		/* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and
++		 * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO
++		 */
++		val = sdhci_readl(host, ESDHC_TBPTR);
++		val = (val & ~((0x7f << 8) | 0x7f)) |
++		(3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8);
++		sdhci_writel(host, val, ESDHC_TBPTR);
++
++		/* program the software tuning mode by setting
++		 * TBCTL[TB_MODE]=2'h3
++		 */
++		val = sdhci_readl(host, ESDHC_TBCTL);
++		val |= 0x3;
++		sdhci_writel(host, val, ESDHC_TBCTL);
++		sdhci_execute_tuning(mmc, opcode);
++	}
++	return ret;
++}
++
++static void esdhc_set_uhs_signaling(struct sdhci_host *host,
++				   unsigned int timing)
++{
++	if (timing == MMC_TIMING_MMC_HS400)
++		esdhc_tuning_block_enable(host, true);
++	else
++		sdhci_set_uhs_signaling(host, timing);
+ }
+ 
+ #ifdef CONFIG_PM_SLEEP
+@@ -755,7 +921,7 @@ static const struct sdhci_ops sdhci_esdh
+ 	.adma_workaround = esdhc_of_adma_workaround,
+ 	.set_bus_width = esdhc_pltfm_set_bus_width,
+ 	.reset = esdhc_reset,
+-	.set_uhs_signaling = sdhci_set_uhs_signaling,
++	.set_uhs_signaling = esdhc_set_uhs_signaling,
+ };
+ 
+ static const struct sdhci_ops sdhci_esdhc_le_ops = {
+@@ -772,7 +938,7 @@ static const struct sdhci_ops sdhci_esdh
+ 	.adma_workaround = esdhc_of_adma_workaround,
+ 	.set_bus_width = esdhc_pltfm_set_bus_width,
+ 	.reset = esdhc_reset,
+-	.set_uhs_signaling = sdhci_set_uhs_signaling,
++	.set_uhs_signaling = esdhc_set_uhs_signaling,
+ };
+ 
+ static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
+@@ -798,8 +964,20 @@ static struct soc_device_attribute soc_i
+ 	{ },
+ };
  
++static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
++	{ .family = "QorIQ LX2160A", .revision = "1.0", },
++	{ .family = "QorIQ LX2160A", .revision = "2.0", },
++	{ },
++};
++
++static struct soc_device_attribute soc_unreliable_pulse_detection[] = {
++	{ .family = "QorIQ LX2160A", .revision = "1.0", },
++	{ },
++};
++
  static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
  {
 +	const struct of_device_id *match;
  	struct sdhci_pltfm_host *pltfm_host;
  	struct sdhci_esdhc *esdhc;
  	struct device_node *np;
-@@ -819,6 +853,9 @@ static void esdhc_init(struct platform_d
+@@ -819,6 +997,24 @@ static void esdhc_init(struct platform_d
  	else
  		esdhc->quirk_incorrect_hostver = false;
  
++	if (soc_device_match(soc_fixup_sdhc_clkdivs))
++		esdhc->quirk_limited_clk_division = true;
++	else
++		esdhc->quirk_limited_clk_division = false;
++
++	if (soc_device_match(soc_unreliable_pulse_detection))
++		esdhc->quirk_unreliable_pulse_detection = true;
++	else
++		esdhc->quirk_unreliable_pulse_detection = false;
++
++	if (soc_device_match(soc_incorrect_delay_chain))
++		esdhc->quirk_incorrect_delay_chain = true;
++	else
++		esdhc->quirk_incorrect_delay_chain = false;
++
 +	match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
 +	if (match)
 +		esdhc->clk_fixup = match->data;
  	np = pdev->dev.of_node;
  	clk = of_clk_get(np, 0);
  	if (!IS_ERR(clk)) {
-@@ -923,14 +960,6 @@ static int sdhci_esdhc_probe(struct plat
+@@ -846,6 +1042,12 @@ static void esdhc_init(struct platform_d
+ 	}
+ }
+ 
++static int esdhc_prepare_ddr_to_hs400(struct mmc_host *mmc)
++{
++	esdhc_tuning_block_enable(mmc_priv(mmc), false);
++	return 0;
++}
++
+ static int sdhci_esdhc_probe(struct platform_device *pdev)
+ {
+ 	struct sdhci_host *host;
+@@ -869,6 +1071,7 @@ static int sdhci_esdhc_probe(struct plat
+ 	host->mmc_host_ops.start_signal_voltage_switch =
+ 		esdhc_signal_voltage_switch;
+ 	host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
++	host->mmc_host_ops.prepare_ddr_to_hs400 = esdhc_prepare_ddr_to_hs400;
+ 	host->tuning_delay = 1;
+ 
+ 	esdhc_init(pdev, host);
+@@ -877,6 +1080,11 @@ static int sdhci_esdhc_probe(struct plat
+ 
+ 	pltfm_host = sdhci_priv(host);
+ 	esdhc = sdhci_pltfm_priv(pltfm_host);
++	if (soc_device_match(soc_fixup_tuning))
++		esdhc->quirk_fixup_tuning = true;
++	else
++		esdhc->quirk_fixup_tuning = false;
++
+ 	if (esdhc->vendor_ver == VENDOR_V_22)
+ 		host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+ 
+@@ -923,14 +1131,6 @@ static int sdhci_esdhc_probe(struct plat
  	return ret;
  }
  
@@ -145,3 +495,78 @@ Signed-off-by: Biwen Li <[email protected]>
  static struct platform_driver sdhci_esdhc_driver = {
  	.driver = {
  		.name = "sdhci-esdhc",
+--- a/drivers/mmc/host/sdhci.c
++++ b/drivers/mmc/host/sdhci.c
+@@ -2148,7 +2148,7 @@ static void sdhci_send_tuning(struct sdh
+ 
+ }
+ 
+-static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
++static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
+ {
+ 	int i;
+ 
+@@ -2165,13 +2165,13 @@ static void __sdhci_execute_tuning(struc
+ 			pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
+ 				mmc_hostname(host->mmc));
+ 			sdhci_abort_tuning(host, opcode);
+-			return;
++			return -ETIMEDOUT;
+ 		}
+ 
+ 		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ 		if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
+ 			if (ctrl & SDHCI_CTRL_TUNED_CLK)
+-				return; /* Success! */
++				return 0; /* Success! */
+ 			break;
+ 		}
+ 
+@@ -2183,6 +2183,7 @@ static void __sdhci_execute_tuning(struc
+ 	pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
+ 		mmc_hostname(host->mmc));
+ 	sdhci_reset_tuning(host);
++	return -EAGAIN;
+ }
+ 
+ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+@@ -2244,7 +2245,7 @@ int sdhci_execute_tuning(struct mmc_host
+ 
+ 	sdhci_start_tuning(host);
+ 
+-	__sdhci_execute_tuning(host, opcode);
++	host->tuning_err = __sdhci_execute_tuning(host, opcode);
+ 
+ 	sdhci_end_tuning(host);
+ out:
+--- a/drivers/mmc/host/sdhci.h
++++ b/drivers/mmc/host/sdhci.h
+@@ -545,6 +545,7 @@ struct sdhci_host {
+ 
+ 	unsigned int		tuning_count;	/* Timer count for re-tuning */
+ 	unsigned int		tuning_mode;	/* Re-tuning mode supported by host */
++	unsigned int		tuning_err;	/* Error code for re-tuning */
+ #define SDHCI_TUNING_MODE_1	0
+ #define SDHCI_TUNING_MODE_2	1
+ #define SDHCI_TUNING_MODE_3	2
+--- a/include/linux/mmc/card.h
++++ b/include/linux/mmc/card.h
+@@ -156,6 +156,7 @@ struct sd_switch_caps {
+ #define UHS_DDR50_MAX_DTR	50000000
+ #define UHS_SDR25_MAX_DTR	UHS_DDR50_MAX_DTR
+ #define UHS_SDR12_MAX_DTR	25000000
++#define DEFAULT_SPEED_MAX_DTR	UHS_SDR12_MAX_DTR
+ 	unsigned int		sd3_bus_mode;
+ #define UHS_SDR12_BUS_SPEED	0
+ #define HIGH_SPEED_BUS_SPEED	1
+--- a/include/linux/mmc/host.h
++++ b/include/linux/mmc/host.h
+@@ -145,6 +145,8 @@ struct mmc_host_ops {
+ 
+ 	/* Prepare HS400 target operating frequency depending host driver */
+ 	int	(*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios);
++	int     (*prepare_ddr_to_hs400)(struct mmc_host *host);
++
+ 	/* Prepare enhanced strobe depending host driver */
+ 	void	(*hs400_enhanced_strobe)(struct mmc_host *host,
+ 					 struct mmc_ios *ios);

target/linux/layerscape/patches-4.14/823-pm-support-layerscape.patch

@@ -1,113 +1,28 @@
-From aded309f403c4202b9c6f61ea6a635e0c736eb77 Mon Sep 17 00:00:00 2001
+From 62ac0c4fda3b40a8994f2abfdc52784ced80c83b Mon Sep 17 00:00:00 2001
 From: Biwen Li <[email protected]>
-Date: Tue, 30 Oct 2018 18:27:07 +0800
-Subject: [PATCH 40/40] pm: support layerscape
+Date: Wed, 17 Apr 2019 18:58:51 +0800
+Subject: [PATCH] pm: support layerscape
+
 This is an integrated patch of pm for layerscape
 
+Signed-off-by: Biwen Li <[email protected]>
 Signed-off-by: Chenhui Zhao <[email protected]>
 Signed-off-by: Hongbo Zhang <[email protected]>
 Signed-off-by: Li Yang <[email protected]>
 Signed-off-by: Ran Wang <[email protected]>
 Signed-off-by: Tang Yuantian <[email protected]>
+Signed-off-by: Yinbo Zhu <[email protected]>
 Signed-off-by: Zhao Chenhui <[email protected]>
-Signed-off-by: Biwen Li <[email protected]>
 ---
- .../devicetree/bindings/powerpc/fsl/pmc.txt   |  59 ++--
- drivers/firmware/psci.c                       |  16 +-
- drivers/soc/fsl/rcpm.c                        | 158 ++++++++++
- drivers/soc/fsl/sleep_fsm.c                   | 279 ++++++++++++++++++
- drivers/soc/fsl/sleep_fsm.h                   | 130 ++++++++
- 5 files changed, 615 insertions(+), 27 deletions(-)
+ drivers/firmware/psci.c     |  16 ++-
+ drivers/soc/fsl/rcpm.c      | 156 ++++++++++++++++++++
+ drivers/soc/fsl/sleep_fsm.c | 279 ++++++++++++++++++++++++++++++++++++
+ drivers/soc/fsl/sleep_fsm.h | 130 +++++++++++++++++
+ 4 files changed, 579 insertions(+), 2 deletions(-)
  create mode 100644 drivers/soc/fsl/rcpm.c
  create mode 100644 drivers/soc/fsl/sleep_fsm.c
  create mode 100644 drivers/soc/fsl/sleep_fsm.h
 
---- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
-+++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
-@@ -9,15 +9,20 @@ Properties:
- 
-   "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
-   compatible.  "fsl,mpc8536-pmc" should also be listed for any chip
--  whose PMC is compatible, and implies deep-sleep capability.
-+  whose PMC is compatible, and implies deep-sleep capability and
-+  wake on user defined packet(wakeup on ARP).
-+
-+  "fsl,p1022-pmc" should be listed for any chip whose PMC is
-+  compatible, and implies lossless Ethernet capability during sleep.
- 
-   "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
-   compatible; all statements below that apply to "fsl,mpc8548-pmc" also
-   apply to "fsl,mpc8641d-pmc".
- 
-   Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
--  bit assignments are indicated via the sleep specifier in each device's
--  sleep property.
-+  bit assignments are indicated via the clock nodes.  Device which has a
-+  controllable clock source should have a "fsl,pmc-handle" property pointing
-+  to the clock node.
- 
- - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
-   is the PMC block, and the second resource is the Clock Configuration
-@@ -33,31 +38,35 @@ Properties:
-   this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
-   a wakeup source from deep sleep.
- 
--Sleep specifiers:
--
--  fsl,mpc8349-pmc: Sleep specifiers consist of one cell.  For each bit
--  that is set in the cell, the corresponding bit in SCCR will be saved
--  and cleared on suspend, and restored on resume.  This sleep controller
--  supports disabling and resuming devices at any time.
--
--  fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
--  which will be ORed into PMCDR upon suspend, and cleared from PMCDR
--  upon resume.  The first two cells are as described for fsl,mpc8578-pmc.
--  This sleep controller only supports disabling devices during system
--  sleep, or permanently.
--
--  fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
--  first of which will be ORed into DEVDISR (and the second into
--  DEVDISR2, if present -- this cell should be zero or absent if the
--  hardware does not have DEVDISR2) upon a request for permanent device
--  disabling.  This sleep controller does not support configuring devices
--  to disable during system sleep (unless supported by another compatible
--  match), or dynamically.
-+Clock nodes:
-+The clock nodes are to describe the masks in PM controller registers for each
-+soc clock.
-+- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
-+  ORed into PMCDR before suspend if the device using this clock is the wake-up
-+  source and need to be running during low power mode; clear the mask if
-+  otherwise.
-+
-+- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
-+  bit specified by the mask in SCCR will be saved and cleared on suspend, and
-+  restored on resume.
-+
-+- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
-+  DEVDISR2 register.  For compatible devices, the mask will be ORed into DEVDISR
-+  or DEVDISR2 when the clock should be permenently disabled.
- 
- Example:
- 
--	power@b00 {
--		compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
--		reg = <0xb00 0x100 0xa00 0x100>;
--		interrupts = <80 8>;
-+	power@e0070 {
-+		compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
-+		reg = <0xe0070 0x20>;
-+
-+		etsec1_clk: soc-clk@24 {
-+			fsl,pmcdr-mask = <0x00000080>;
-+		};
-+		etsec2_clk: soc-clk@25 {
-+			fsl,pmcdr-mask = <0x00000040>;
-+		};
-+		etsec3_clk: soc-clk@26 {
-+			fsl,pmcdr-mask = <0x00000020>;
-+		};
- 	};
 --- a/drivers/firmware/psci.c
 +++ b/drivers/firmware/psci.c
 @@ -437,8 +437,18 @@ CPUIDLE_METHOD_OF_DECLARE(psci, "psci",
@@ -142,7 +57,7 @@ Signed-off-by: Biwen Li <[email protected]>
  /*
 --- /dev/null
 +++ b/drivers/soc/fsl/rcpm.c
-@@ -0,0 +1,158 @@
+@@ -0,0 +1,156 @@
 +/*
 + * Run Control and Power Management (RCPM) driver
 + *
@@ -278,10 +193,8 @@ Signed-off-by: Biwen Li <[email protected]>
 +	struct device_node *np;
 +
 +	np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
-+	if (!np) {
-+		pr_err("Can't find the RCPM node.\n");
++	if (!np)
 +		return -EINVAL;
-+	}
 +
 +	if (match->data)
 +		rcpm = (struct rcpm_config *)match->data;

target/linux/layerscape/patches-4.14/824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch

@@ -1,23 +0,0 @@
-From bb7412794db9b48dc4cc041c75d380e512dfff2a Mon Sep 17 00:00:00 2001
-From: Mathew McBride <[email protected]>
-Date: Tue, 20 Nov 2018 14:36:54 +0800
-Subject: [PATCH] mmc: sdhci-of-esdhc: add voltage switch support for ls1043a
-
-Added voltage switch support for ls1043a.
-
-Signed-off-by: Mathew McBride <[email protected]>
-Signed-off-by: Yangbo Lu <[email protected]>
----
- drivers/mmc/host/sdhci-of-esdhc.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mmc/host/sdhci-of-esdhc.c
-+++ b/drivers/mmc/host/sdhci-of-esdhc.c
-@@ -661,6 +661,7 @@ static void esdhc_reset(struct sdhci_hos
- static const struct of_device_id scfg_device_ids[] = {
- 	{ .compatible = "fsl,t1040-scfg", },
- 	{ .compatible = "fsl,ls1012a-scfg", },
-+	{ .compatible = "fsl,ls1043a-scfg", },
- 	{ .compatible = "fsl,ls1046a-scfg", },
- 	{}
- };

target/linux/layerscape/patches-4.14/824-ptp-support-layerscape.patch

@@ -0,0 +1,1399 @@
+From bba7af6efb0aad1d52ee5e7d80f9e2ab59d85e20 Mon Sep 17 00:00:00 2001
+From: Biwen Li <[email protected]>
+Date: Wed, 17 Apr 2019 18:58:52 +0800
+Subject: [PATCH] ptp: support layerscape
+
+This is an integrated patch of ptp for layerscape
+
+Signed-off-by: Arnd Bergmann <[email protected]>
+Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+Signed-off-by: Yangbo Lu <[email protected]>
+---
+ drivers/net/ethernet/freescale/Makefile      |   1 -
+ drivers/net/ethernet/freescale/gianfar_ptp.c | 572 ------------------
+ drivers/ptp/Makefile                         |   1 +
+ drivers/ptp/ptp_chardev.c                    |   4 +-
+ drivers/ptp/ptp_qoriq.c                      | 589 +++++++++++++++++++
+ include/linux/fsl/ptp_qoriq.h                | 169 ++++++
+ 6 files changed, 761 insertions(+), 575 deletions(-)
+ delete mode 100644 drivers/net/ethernet/freescale/gianfar_ptp.c
+ create mode 100644 drivers/ptp/ptp_qoriq.c
+ create mode 100644 include/linux/fsl/ptp_qoriq.h
+
+--- a/drivers/net/ethernet/freescale/Makefile
++++ b/drivers/net/ethernet/freescale/Makefile
+@@ -14,7 +14,6 @@ obj-$(CONFIG_FS_ENET) += fs_enet/
+ obj-$(CONFIG_FSL_PQ_MDIO) += fsl_pq_mdio.o
+ obj-$(CONFIG_FSL_XGMAC_MDIO) += xgmac_mdio.o
+ obj-$(CONFIG_GIANFAR) += gianfar_driver.o
+-obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
+ gianfar_driver-objs := gianfar.o \
+ 		gianfar_ethtool.o
+ obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
+--- a/drivers/net/ethernet/freescale/gianfar_ptp.c
++++ /dev/null
+@@ -1,572 +0,0 @@
+-/*
+- * PTP 1588 clock using the eTSEC
+- *
+- * Copyright (C) 2010 OMICRON electronics GmbH
+- *
+- *  This program is free software; you can redistribute it and/or modify
+- *  it under the terms of the GNU General Public License as published by
+- *  the Free Software Foundation; either version 2 of the License, or
+- *  (at your option) any later version.
+- *
+- *  This program is distributed in the hope that it will be useful,
+- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *  GNU General Public License for more details.
+- *
+- *  You should have received a copy of the GNU General Public License
+- *  along with this program; if not, write to the Free Software
+- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+- */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-#include <linux/device.h>
+-#include <linux/hrtimer.h>
+-#include <linux/interrupt.h>
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/of.h>
+-#include <linux/of_platform.h>
+-#include <linux/timex.h>
+-#include <linux/io.h>
+-
+-#include <linux/ptp_clock_kernel.h>
+-
+-#include "gianfar.h"
+-
+-/*
+- * gianfar ptp registers
+- * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
+- */
+-struct gianfar_ptp_registers {
+-	u32 tmr_ctrl;     /* Timer control register */
+-	u32 tmr_tevent;   /* Timestamp event register */
+-	u32 tmr_temask;   /* Timer event mask register */
+-	u32 tmr_pevent;   /* Timestamp event register */
+-	u32 tmr_pemask;   /* Timer event mask register */
+-	u32 tmr_stat;     /* Timestamp status register */
+-	u32 tmr_cnt_h;    /* Timer counter high register */
+-	u32 tmr_cnt_l;    /* Timer counter low register */
+-	u32 tmr_add;      /* Timer drift compensation addend register */
+-	u32 tmr_acc;      /* Timer accumulator register */
+-	u32 tmr_prsc;     /* Timer prescale */
+-	u8  res1[4];
+-	u32 tmroff_h;     /* Timer offset high */
+-	u32 tmroff_l;     /* Timer offset low */
+-	u8  res2[8];
+-	u32 tmr_alarm1_h; /* Timer alarm 1 high register */
+-	u32 tmr_alarm1_l; /* Timer alarm 1 high register */
+-	u32 tmr_alarm2_h; /* Timer alarm 2 high register */
+-	u32 tmr_alarm2_l; /* Timer alarm 2 high register */
+-	u8  res3[48];
+-	u32 tmr_fiper1;   /* Timer fixed period interval */
+-	u32 tmr_fiper2;   /* Timer fixed period interval */
+-	u32 tmr_fiper3;   /* Timer fixed period interval */
+-	u8  res4[20];
+-	u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */
+-	u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */
+-	u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */
+-	u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */
+-};
+-
+-/* Bit definitions for the TMR_CTRL register */
+-#define ALM1P                 (1<<31) /* Alarm1 output polarity */
+-#define ALM2P                 (1<<30) /* Alarm2 output polarity */
+-#define FIPERST               (1<<28) /* FIPER start indication */
+-#define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */
+-#define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */
+-#define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */
+-#define TCLK_PERIOD_MASK      (0x3ff)
+-#define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */
+-#define FRD                   (1<<14) /* FIPER Realignment Disable */
+-#define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */
+-#define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */
+-#define ETEP2                 (1<<9) /* External trigger 2 edge polarity */
+-#define ETEP1                 (1<<8) /* External trigger 1 edge polarity */
+-#define COPH                  (1<<7) /* Generated clock output phase. */
+-#define CIPH                  (1<<6) /* External oscillator input clock phase */
+-#define TMSR                  (1<<5) /* Timer soft reset. */
+-#define BYP                   (1<<3) /* Bypass drift compensated clock */
+-#define TE                    (1<<2) /* 1588 timer enable. */
+-#define CKSEL_SHIFT           (0)    /* 1588 Timer reference clock source */
+-#define CKSEL_MASK            (0x3)
+-
+-/* Bit definitions for the TMR_TEVENT register */
+-#define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */
+-#define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */
+-#define ALM2                  (1<<17) /* Current time = alarm time register 2 */
+-#define ALM1                  (1<<16) /* Current time = alarm time register 1 */
+-#define PP1                   (1<<7)  /* periodic pulse generated on FIPER1 */
+-#define PP2                   (1<<6)  /* periodic pulse generated on FIPER2 */
+-#define PP3                   (1<<5)  /* periodic pulse generated on FIPER3 */
+-
+-/* Bit definitions for the TMR_TEMASK register */
+-#define ETS2EN                (1<<25) /* External trigger 2 timestamp enable */
+-#define ETS1EN                (1<<24) /* External trigger 1 timestamp enable */
+-#define ALM2EN                (1<<17) /* Timer ALM2 event enable */
+-#define ALM1EN                (1<<16) /* Timer ALM1 event enable */
+-#define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */
+-#define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */
+-
+-/* Bit definitions for the TMR_PEVENT register */
+-#define TXP2                  (1<<9) /* PTP transmitted timestamp im TXTS2 */
+-#define TXP1                  (1<<8) /* PTP transmitted timestamp in TXTS1 */
+-#define RXP                   (1<<0) /* PTP frame has been received */
+-
+-/* Bit definitions for the TMR_PEMASK register */
+-#define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */
+-#define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */
+-#define RXPEN                 (1<<0) /* Receive PTP packet event enable */
+-
+-/* Bit definitions for the TMR_STAT register */
+-#define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */
+-#define STAT_VEC_MASK         (0x3f)
+-
+-/* Bit definitions for the TMR_PRSC register */
+-#define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */
+-#define PRSC_OCK_MASK         (0xffff)
+-
+-
+-#define DRIVER		"gianfar_ptp"
+-#define DEFAULT_CKSEL	1
+-#define N_EXT_TS	2
+-#define REG_SIZE	sizeof(struct gianfar_ptp_registers)
+-
+-struct etsects {
+-	struct gianfar_ptp_registers __iomem *regs;
+-	spinlock_t lock; /* protects regs */
+-	struct ptp_clock *clock;
+-	struct ptp_clock_info caps;
+-	struct resource *rsrc;
+-	int irq;
+-	u64 alarm_interval; /* for periodic alarm */
+-	u64 alarm_value;
+-	u32 tclk_period;  /* nanoseconds */
+-	u32 tmr_prsc;
+-	u32 tmr_add;
+-	u32 cksel;
+-	u32 tmr_fiper1;
+-	u32 tmr_fiper2;
+-};
+-
+-/*
+- * Register access functions
+- */
+-
+-/* Caller must hold etsects->lock. */
+-static u64 tmr_cnt_read(struct etsects *etsects)
+-{
+-	u64 ns;
+-	u32 lo, hi;
+-
+-	lo = gfar_read(&etsects->regs->tmr_cnt_l);
+-	hi = gfar_read(&etsects->regs->tmr_cnt_h);
+-	ns = ((u64) hi) << 32;
+-	ns |= lo;
+-	return ns;
+-}
+-
+-/* Caller must hold etsects->lock. */
+-static void tmr_cnt_write(struct etsects *etsects, u64 ns)
+-{
+-	u32 hi = ns >> 32;
+-	u32 lo = ns & 0xffffffff;
+-
+-	gfar_write(&etsects->regs->tmr_cnt_l, lo);
+-	gfar_write(&etsects->regs->tmr_cnt_h, hi);
+-}
+-
+-/* Caller must hold etsects->lock. */
+-static void set_alarm(struct etsects *etsects)
+-{
+-	u64 ns;
+-	u32 lo, hi;
+-
+-	ns = tmr_cnt_read(etsects) + 1500000000ULL;
+-	ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
+-	ns -= etsects->tclk_period;
+-	hi = ns >> 32;
+-	lo = ns & 0xffffffff;
+-	gfar_write(&etsects->regs->tmr_alarm1_l, lo);
+-	gfar_write(&etsects->regs->tmr_alarm1_h, hi);
+-}
+-
+-/* Caller must hold etsects->lock. */
+-static void set_fipers(struct etsects *etsects)
+-{
+-	set_alarm(etsects);
+-	gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
+-	gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
+-}
+-
+-/*
+- * Interrupt service routine
+- */
+-
+-static irqreturn_t isr(int irq, void *priv)
+-{
+-	struct etsects *etsects = priv;
+-	struct ptp_clock_event event;
+-	u64 ns;
+-	u32 ack = 0, lo, hi, mask, val;
+-
+-	val = gfar_read(&etsects->regs->tmr_tevent);
+-
+-	if (val & ETS1) {
+-		ack |= ETS1;
+-		hi = gfar_read(&etsects->regs->tmr_etts1_h);
+-		lo = gfar_read(&etsects->regs->tmr_etts1_l);
+-		event.type = PTP_CLOCK_EXTTS;
+-		event.index = 0;
+-		event.timestamp = ((u64) hi) << 32;
+-		event.timestamp |= lo;
+-		ptp_clock_event(etsects->clock, &event);
+-	}
+-
+-	if (val & ETS2) {
+-		ack |= ETS2;
+-		hi = gfar_read(&etsects->regs->tmr_etts2_h);
+-		lo = gfar_read(&etsects->regs->tmr_etts2_l);
+-		event.type = PTP_CLOCK_EXTTS;
+-		event.index = 1;
+-		event.timestamp = ((u64) hi) << 32;
+-		event.timestamp |= lo;
+-		ptp_clock_event(etsects->clock, &event);
+-	}
+-
+-	if (val & ALM2) {
+-		ack |= ALM2;
+-		if (etsects->alarm_value) {
+-			event.type = PTP_CLOCK_ALARM;
+-			event.index = 0;
+-			event.timestamp = etsects->alarm_value;
+-			ptp_clock_event(etsects->clock, &event);
+-		}
+-		if (etsects->alarm_interval) {
+-			ns = etsects->alarm_value + etsects->alarm_interval;
+-			hi = ns >> 32;
+-			lo = ns & 0xffffffff;
+-			spin_lock(&etsects->lock);
+-			gfar_write(&etsects->regs->tmr_alarm2_l, lo);
+-			gfar_write(&etsects->regs->tmr_alarm2_h, hi);
+-			spin_unlock(&etsects->lock);
+-			etsects->alarm_value = ns;
+-		} else {
+-			gfar_write(&etsects->regs->tmr_tevent, ALM2);
+-			spin_lock(&etsects->lock);
+-			mask = gfar_read(&etsects->regs->tmr_temask);
+-			mask &= ~ALM2EN;
+-			gfar_write(&etsects->regs->tmr_temask, mask);
+-			spin_unlock(&etsects->lock);
+-			etsects->alarm_value = 0;
+-			etsects->alarm_interval = 0;
+-		}
+-	}
+-
+-	if (val & PP1) {
+-		ack |= PP1;
+-		event.type = PTP_CLOCK_PPS;
+-		ptp_clock_event(etsects->clock, &event);
+-	}
+-
+-	if (ack) {
+-		gfar_write(&etsects->regs->tmr_tevent, ack);
+-		return IRQ_HANDLED;
+-	} else
+-		return IRQ_NONE;
+-}
+-
+-/*
+- * PTP clock operations
+- */
+-
+-static int ptp_gianfar_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
+-{
+-	u64 adj, diff;
+-	u32 tmr_add;
+-	int neg_adj = 0;
+-	struct etsects *etsects = container_of(ptp, struct etsects, caps);
+-
+-	if (scaled_ppm < 0) {
+-		neg_adj = 1;
+-		scaled_ppm = -scaled_ppm;
+-	}
+-	tmr_add = etsects->tmr_add;
+-	adj = tmr_add;
+-
+-	/* calculate diff as adj*(scaled_ppm/65536)/1000000
+-	 * and round() to the nearest integer
+-	 */
+-	adj *= scaled_ppm;
+-	diff = div_u64(adj, 8000000);
+-	diff = (diff >> 13) + ((diff >> 12) & 1);
+-
+-	tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
+-
+-	gfar_write(&etsects->regs->tmr_add, tmr_add);
+-
+-	return 0;
+-}
+-
+-static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
+-{
+-	s64 now;
+-	unsigned long flags;
+-	struct etsects *etsects = container_of(ptp, struct etsects, caps);
+-
+-	spin_lock_irqsave(&etsects->lock, flags);
+-
+-	now = tmr_cnt_read(etsects);
+-	now += delta;
+-	tmr_cnt_write(etsects, now);
+-	set_fipers(etsects);
+-
+-	spin_unlock_irqrestore(&etsects->lock, flags);
+-
+-	return 0;
+-}
+-
+-static int ptp_gianfar_gettime(struct ptp_clock_info *ptp,
+-			       struct timespec64 *ts)
+-{
+-	u64 ns;
+-	unsigned long flags;
+-	struct etsects *etsects = container_of(ptp, struct etsects, caps);
+-
+-	spin_lock_irqsave(&etsects->lock, flags);
+-
+-	ns = tmr_cnt_read(etsects);
+-
+-	spin_unlock_irqrestore(&etsects->lock, flags);
+-
+-	*ts = ns_to_timespec64(ns);
+-
+-	return 0;
+-}
+-
+-static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
+-			       const struct timespec64 *ts)
+-{
+-	u64 ns;
+-	unsigned long flags;
+-	struct etsects *etsects = container_of(ptp, struct etsects, caps);
+-
+-	ns = timespec64_to_ns(ts);
+-
+-	spin_lock_irqsave(&etsects->lock, flags);
+-
+-	tmr_cnt_write(etsects, ns);
+-	set_fipers(etsects);
+-
+-	spin_unlock_irqrestore(&etsects->lock, flags);
+-
+-	return 0;
+-}
+-
+-static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
+-			      struct ptp_clock_request *rq, int on)
+-{
+-	struct etsects *etsects = container_of(ptp, struct etsects, caps);
+-	unsigned long flags;
+-	u32 bit, mask;
+-
+-	switch (rq->type) {
+-	case PTP_CLK_REQ_EXTTS:
+-		switch (rq->extts.index) {
+-		case 0:
+-			bit = ETS1EN;
+-			break;
+-		case 1:
+-			bit = ETS2EN;
+-			break;
+-		default:
+-			return -EINVAL;
+-		}
+-		spin_lock_irqsave(&etsects->lock, flags);
+-		mask = gfar_read(&etsects->regs->tmr_temask);
+-		if (on)
+-			mask |= bit;
+-		else
+-			mask &= ~bit;
+-		gfar_write(&etsects->regs->tmr_temask, mask);
+-		spin_unlock_irqrestore(&etsects->lock, flags);
+-		return 0;
+-
+-	case PTP_CLK_REQ_PPS:
+-		spin_lock_irqsave(&etsects->lock, flags);
+-		mask = gfar_read(&etsects->regs->tmr_temask);
+-		if (on)
+-			mask |= PP1EN;
+-		else
+-			mask &= ~PP1EN;
+-		gfar_write(&etsects->regs->tmr_temask, mask);
+-		spin_unlock_irqrestore(&etsects->lock, flags);
+-		return 0;
+-
+-	default:
+-		break;
+-	}
+-
+-	return -EOPNOTSUPP;
+-}
+-
+-static const struct ptp_clock_info ptp_gianfar_caps = {
+-	.owner		= THIS_MODULE,
+-	.name		= "gianfar clock",
+-	.max_adj	= 512000,
+-	.n_alarm	= 0,
+-	.n_ext_ts	= N_EXT_TS,
+-	.n_per_out	= 0,
+-	.n_pins		= 0,
+-	.pps		= 1,
+-	.adjfine	= ptp_gianfar_adjfine,
+-	.adjtime	= ptp_gianfar_adjtime,
+-	.gettime64	= ptp_gianfar_gettime,
+-	.settime64	= ptp_gianfar_settime,
+-	.enable		= ptp_gianfar_enable,
+-};
+-
+-static int gianfar_ptp_probe(struct platform_device *dev)
+-{
+-	struct device_node *node = dev->dev.of_node;
+-	struct etsects *etsects;
+-	struct timespec64 now;
+-	int err = -ENOMEM;
+-	u32 tmr_ctrl;
+-	unsigned long flags;
+-
+-	etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
+-	if (!etsects)
+-		goto no_memory;
+-
+-	err = -ENODEV;
+-
+-	etsects->caps = ptp_gianfar_caps;
+-
+-	if (of_property_read_u32(node, "fsl,cksel", &etsects->cksel))
+-		etsects->cksel = DEFAULT_CKSEL;
+-
+-	if (of_property_read_u32(node,
+-				 "fsl,tclk-period", &etsects->tclk_period) ||
+-	    of_property_read_u32(node,
+-				 "fsl,tmr-prsc", &etsects->tmr_prsc) ||
+-	    of_property_read_u32(node,
+-				 "fsl,tmr-add", &etsects->tmr_add) ||
+-	    of_property_read_u32(node,
+-				 "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
+-	    of_property_read_u32(node,
+-				 "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
+-	    of_property_read_u32(node,
+-				 "fsl,max-adj", &etsects->caps.max_adj)) {
+-		pr_err("device tree node missing required elements\n");
+-		goto no_node;
+-	}
+-
+-	etsects->irq = platform_get_irq(dev, 0);
+-
+-	if (etsects->irq < 0) {
+-		pr_err("irq not in device tree\n");
+-		goto no_node;
+-	}
+-	if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
+-		pr_err("request_irq failed\n");
+-		goto no_node;
+-	}
+-
+-	etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
+-	if (!etsects->rsrc) {
+-		pr_err("no resource\n");
+-		goto no_resource;
+-	}
+-	if (request_resource(&iomem_resource, etsects->rsrc)) {
+-		pr_err("resource busy\n");
+-		goto no_resource;
+-	}
+-
+-	spin_lock_init(&etsects->lock);
+-
+-	etsects->regs = ioremap(etsects->rsrc->start,
+-				resource_size(etsects->rsrc));
+-	if (!etsects->regs) {
+-		pr_err("ioremap ptp registers failed\n");
+-		goto no_ioremap;
+-	}
+-	getnstimeofday64(&now);
+-	ptp_gianfar_settime(&etsects->caps, &now);
+-
+-	tmr_ctrl =
+-	  (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
+-	  (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
+-
+-	spin_lock_irqsave(&etsects->lock, flags);
+-
+-	gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl);
+-	gfar_write(&etsects->regs->tmr_add,    etsects->tmr_add);
+-	gfar_write(&etsects->regs->tmr_prsc,   etsects->tmr_prsc);
+-	gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
+-	gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
+-	set_alarm(etsects);
+-	gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl|FIPERST|RTPE|TE|FRD);
+-
+-	spin_unlock_irqrestore(&etsects->lock, flags);
+-
+-	etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev);
+-	if (IS_ERR(etsects->clock)) {
+-		err = PTR_ERR(etsects->clock);
+-		goto no_clock;
+-	}
+-	gfar_phc_index = ptp_clock_index(etsects->clock);
+-
+-	platform_set_drvdata(dev, etsects);
+-
+-	return 0;
+-
+-no_clock:
+-	iounmap(etsects->regs);
+-no_ioremap:
+-	release_resource(etsects->rsrc);
+-no_resource:
+-	free_irq(etsects->irq, etsects);
+-no_node:
+-	kfree(etsects);
+-no_memory:
+-	return err;
+-}
+-
+-static int gianfar_ptp_remove(struct platform_device *dev)
+-{
+-	struct etsects *etsects = platform_get_drvdata(dev);
+-
+-	gfar_write(&etsects->regs->tmr_temask, 0);
+-	gfar_write(&etsects->regs->tmr_ctrl,   0);
+-
+-	gfar_phc_index = -1;
+-	ptp_clock_unregister(etsects->clock);
+-	iounmap(etsects->regs);
+-	release_resource(etsects->rsrc);
+-	free_irq(etsects->irq, etsects);
+-	kfree(etsects);
+-
+-	return 0;
+-}
+-
+-static const struct of_device_id match_table[] = {
+-	{ .compatible = "fsl,etsec-ptp" },
+-	{},
+-};
+-MODULE_DEVICE_TABLE(of, match_table);
+-
+-static struct platform_driver gianfar_ptp_driver = {
+-	.driver = {
+-		.name		= "gianfar_ptp",
+-		.of_match_table	= match_table,
+-	},
+-	.probe       = gianfar_ptp_probe,
+-	.remove      = gianfar_ptp_remove,
+-};
+-
+-module_platform_driver(gianfar_ptp_driver);
+-
+-MODULE_AUTHOR("Richard Cochran <[email protected]>");
+-MODULE_DESCRIPTION("PTP clock using the eTSEC");
+-MODULE_LICENSE("GPL");
+--- a/drivers/ptp/Makefile
++++ b/drivers/ptp/Makefile
+@@ -9,3 +9,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_DTE)	+= ptp_
+ obj-$(CONFIG_PTP_1588_CLOCK_IXP46X)	+= ptp_ixp46x.o
+ obj-$(CONFIG_PTP_1588_CLOCK_PCH)	+= ptp_pch.o
+ obj-$(CONFIG_PTP_1588_CLOCK_KVM)	+= ptp_kvm.o
++obj-$(CONFIG_PTP_1588_CLOCK_QORIQ)	+= ptp_qoriq.o
+--- a/drivers/ptp/ptp_chardev.c
++++ b/drivers/ptp/ptp_chardev.c
+@@ -224,7 +224,7 @@ long ptp_ioctl(struct posix_clock *pc, u
+ 		}
+ 		pct = &sysoff->ts[0];
+ 		for (i = 0; i < sysoff->n_samples; i++) {
+-			getnstimeofday64(&ts);
++			ktime_get_real_ts64(&ts);
+ 			pct->sec = ts.tv_sec;
+ 			pct->nsec = ts.tv_nsec;
+ 			pct++;
+@@ -235,7 +235,7 @@ long ptp_ioctl(struct posix_clock *pc, u
+ 			pct->nsec = ts.tv_nsec;
+ 			pct++;
+ 		}
+-		getnstimeofday64(&ts);
++		ktime_get_real_ts64(&ts);
+ 		pct->sec = ts.tv_sec;
+ 		pct->nsec = ts.tv_nsec;
+ 		if (copy_to_user((void __user *)arg, sysoff, sizeof(*sysoff)))
+--- /dev/null
++++ b/drivers/ptp/ptp_qoriq.c
+@@ -0,0 +1,589 @@
++/*
++ * PTP 1588 clock for Freescale QorIQ 1588 timer
++ *
++ * Copyright (C) 2010 OMICRON electronics GmbH
++ *
++ *  This program is free software; you can redistribute it and/or modify
++ *  it under the terms of the GNU General Public License as published by
++ *  the Free Software Foundation; either version 2 of the License, or
++ *  (at your option) any later version.
++ *
++ *  This program is distributed in the hope that it will be useful,
++ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *  GNU General Public License for more details.
++ *
++ *  You should have received a copy of the GNU General Public License
++ *  along with this program; if not, write to the Free Software
++ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/device.h>
++#include <linux/hrtimer.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/timex.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++
++#include <linux/fsl/ptp_qoriq.h>
++
++/*
++ * Register access functions
++ */
++
++/* Caller must hold qoriq_ptp->lock. */
++static u64 tmr_cnt_read(struct qoriq_ptp *qoriq_ptp)
++{
++	struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
++	u64 ns;
++	u32 lo, hi;
++
++	lo = qoriq_read(&regs->ctrl_regs->tmr_cnt_l);
++	hi = qoriq_read(&regs->ctrl_regs->tmr_cnt_h);
++	ns = ((u64) hi) << 32;
++	ns |= lo;
++	return ns;
++}
++
++/* Caller must hold qoriq_ptp->lock. */
++static void tmr_cnt_write(struct qoriq_ptp *qoriq_ptp, u64 ns)
++{
++	struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
++	u32 hi = ns >> 32;
++	u32 lo = ns & 0xffffffff;
++
++	qoriq_write(&regs->ctrl_regs->tmr_cnt_l, lo);
++	qoriq_write(&regs->ctrl_regs->tmr_cnt_h, hi);
++}
++
++/* Caller must hold qoriq_ptp->lock. */
++static void set_alarm(struct qoriq_ptp *qoriq_ptp)
++{
++	struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
++	u64 ns;
++	u32 lo, hi;
++
++	ns = tmr_cnt_read(qoriq_ptp) + 1500000000ULL;
++	ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
++	ns -= qoriq_ptp->tclk_period;
++	hi = ns >> 32;
++	lo = ns & 0xffffffff;
++	qoriq_write(&regs->alarm_regs->tmr_alarm1_l, lo);
++	qoriq_write(&regs->alarm_regs->tmr_alarm1_h, hi);
++}
++
++/* Caller must hold qoriq_ptp->lock. */
++static void set_fipers(struct qoriq_ptp *qoriq_ptp)
++{
++	struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
++
++	set_alarm(qoriq_ptp);
++	qoriq_write(&regs->fiper_regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
++	qoriq_write(&regs->fiper_regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
++}
++
++/*
++ * Interrupt service routine
++ */
++
++static irqreturn_t isr(int irq, void *priv)
++{
++	struct qoriq_ptp *qoriq_ptp = priv;
++	struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
++	struct ptp_clock_event event;
++	u64 ns;
++	u32 ack = 0, lo, hi, mask, val;
++
++	val = qoriq_read(&regs->ctrl_regs->tmr_tevent);
++
++	if (val & ETS1) {
++		ack |= ETS1;
++		hi = qoriq_read(&regs->etts_regs->tmr_etts1_h);
++		lo = qoriq_read(&regs->etts_regs->tmr_etts1_l);
++		event.type = PTP_CLOCK_EXTTS;
++		event.index = 0;
++		event.timestamp = ((u64) hi) << 32;
++		event.timestamp |= lo;
++		ptp_clock_event(qoriq_ptp->clock, &event);
++	}
++
++	if (val & ETS2) {
++		ack |= ETS2;
++		hi = qoriq_read(&regs->etts_regs->tmr_etts2_h);
++		lo = qoriq_read(&regs->etts_regs->tmr_etts2_l);
++		event.type = PTP_CLOCK_EXTTS;
++		event.index = 1;
++		event.timestamp = ((u64) hi) << 32;
++		event.timestamp |= lo;
++		ptp_clock_event(qoriq_ptp->clock, &event);
++	}
++
++	if (val & ALM2) {
++		ack |= ALM2;
++		if (qoriq_ptp->alarm_value) {
++			event.type = PTP_CLOCK_ALARM;
++			event.index = 0;
++			event.timestamp = qoriq_ptp->alarm_value;
++			ptp_clock_event(qoriq_ptp->clock, &event);
++		}
++		if (qoriq_ptp->alarm_interval) {
++			ns = qoriq_ptp->alarm_value + qoriq_ptp->alarm_interval;
++			hi = ns >> 32;
++			lo = ns & 0xffffffff;
++			spin_lock(&qoriq_ptp->lock);
++			qoriq_write(&regs->alarm_regs->tmr_alarm2_l, lo);
++			qoriq_write(&regs->alarm_regs->tmr_alarm2_h, hi);
++			spin_unlock(&qoriq_ptp->lock);
++			qoriq_ptp->alarm_value = ns;
++		} else {
++			qoriq_write(&regs->ctrl_regs->tmr_tevent, ALM2);
++			spin_lock(&qoriq_ptp->lock);
++			mask = qoriq_read(&regs->ctrl_regs->tmr_temask);
++			mask &= ~ALM2EN;
++			qoriq_write(&regs->ctrl_regs->tmr_temask, mask);
++			spin_unlock(&qoriq_ptp->lock);
++			qoriq_ptp->alarm_value = 0;
++			qoriq_ptp->alarm_interval = 0;
++		}
++	}
++
++	if (val & PP1) {
++		ack |= PP1;
++		event.type = PTP_CLOCK_PPS;
++		ptp_clock_event(qoriq_ptp->clock, &event);
++	}
++
++	if (ack) {
++		qoriq_write(&regs->ctrl_regs->tmr_tevent, ack);
++		return IRQ_HANDLED;
++	} else
++		return IRQ_NONE;
++}
++
++/*
++ * PTP clock operations
++ */
++
++static int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
++{
++	u64 adj, diff;
++	u32 tmr_add;
++	int neg_adj = 0;
++	struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
++	struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
++
++	if (scaled_ppm < 0) {
++		neg_adj = 1;
++		scaled_ppm = -scaled_ppm;
++	}
++	tmr_add = qoriq_ptp->tmr_add;
++	adj = tmr_add;
++
++	/* calculate diff as adj*(scaled_ppm/65536)/1000000
++	 * and round() to the nearest integer
++	 */
++	adj *= scaled_ppm;
++	diff = div_u64(adj, 8000000);
++	diff = (diff >> 13) + ((diff >> 12) & 1);
++
++	tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
++
++	qoriq_write(&regs->ctrl_regs->tmr_add, tmr_add);
++
++	return 0;
++}
++
++static int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta)
++{
++	s64 now;
++	unsigned long flags;
++	struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
++
++	spin_lock_irqsave(&qoriq_ptp->lock, flags);
++
++	now = tmr_cnt_read(qoriq_ptp);
++	now += delta;
++	tmr_cnt_write(qoriq_ptp, now);
++	set_fipers(qoriq_ptp);
++
++	spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
++
++	return 0;
++}
++
++static int ptp_qoriq_gettime(struct ptp_clock_info *ptp,
++			       struct timespec64 *ts)
++{
++	u64 ns;
++	unsigned long flags;
++	struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
++
++	spin_lock_irqsave(&qoriq_ptp->lock, flags);
++
++	ns = tmr_cnt_read(qoriq_ptp);
++
++	spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
++
++	*ts = ns_to_timespec64(ns);
++
++	return 0;
++}
++
++static int ptp_qoriq_settime(struct ptp_clock_info *ptp,
++			       const struct timespec64 *ts)
++{
++	u64 ns;
++	unsigned long flags;
++	struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
++
++	ns = timespec64_to_ns(ts);
++
++	spin_lock_irqsave(&qoriq_ptp->lock, flags);
++
++	tmr_cnt_write(qoriq_ptp, ns);
++	set_fipers(qoriq_ptp);
++
++	spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
++
++	return 0;
++}
++
++static int ptp_qoriq_enable(struct ptp_clock_info *ptp,
++			      struct ptp_clock_request *rq, int on)
++{
++	struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
++	struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
++	unsigned long flags;
++	u32 bit, mask;
++
++	switch (rq->type) {
++	case PTP_CLK_REQ_EXTTS:
++		switch (rq->extts.index) {
++		case 0:
++			bit = ETS1EN;
++			break;
++		case 1:
++			bit = ETS2EN;
++			break;
++		default:
++			return -EINVAL;
++		}
++		spin_lock_irqsave(&qoriq_ptp->lock, flags);
++		mask = qoriq_read(&regs->ctrl_regs->tmr_temask);
++		if (on)
++			mask |= bit;
++		else
++			mask &= ~bit;
++		qoriq_write(&regs->ctrl_regs->tmr_temask, mask);
++		spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
++		return 0;
++
++	case PTP_CLK_REQ_PPS:
++		spin_lock_irqsave(&qoriq_ptp->lock, flags);
++		mask = qoriq_read(&regs->ctrl_regs->tmr_temask);
++		if (on)
++			mask |= PP1EN;
++		else
++			mask &= ~PP1EN;
++		qoriq_write(&regs->ctrl_regs->tmr_temask, mask);
++		spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
++		return 0;
++
++	default:
++		break;
++	}
++
++	return -EOPNOTSUPP;
++}
++
++static const struct ptp_clock_info ptp_qoriq_caps = {
++	.owner		= THIS_MODULE,
++	.name		= "qoriq ptp clock",
++	.max_adj	= 512000,
++	.n_alarm	= 0,
++	.n_ext_ts	= N_EXT_TS,
++	.n_per_out	= 0,
++	.n_pins		= 0,
++	.pps		= 1,
++	.adjfine	= ptp_qoriq_adjfine,
++	.adjtime	= ptp_qoriq_adjtime,
++	.gettime64	= ptp_qoriq_gettime,
++	.settime64	= ptp_qoriq_settime,
++	.enable		= ptp_qoriq_enable,
++};
++
++/**
++ * qoriq_ptp_nominal_freq - calculate nominal frequency according to
++ *			    reference clock frequency
++ *
++ * @clk_src: reference clock frequency
++ *
++ * The nominal frequency is the desired clock frequency.
++ * It should be less than the reference clock frequency.
++ * It should be a factor of 1000MHz.
++ *
++ * Return the nominal frequency
++ */
++static u32 qoriq_ptp_nominal_freq(u32 clk_src)
++{
++	u32 remainder = 0;
++
++	clk_src /= 1000000;
++	remainder = clk_src % 100;
++	if (remainder) {
++		clk_src -= remainder;
++		clk_src += 100;
++	}
++
++	do {
++		clk_src -= 100;
++
++	} while (1000 % clk_src);
++
++	return clk_src * 1000000;
++}
++
++/**
++ * qoriq_ptp_auto_config - calculate a set of default configurations
++ *
++ * @qoriq_ptp: pointer to qoriq_ptp
++ * @node: pointer to device_node
++ *
++ * If below dts properties are not provided, this function will be
++ * called to calculate a set of default configurations for them.
++ *   "fsl,tclk-period"
++ *   "fsl,tmr-prsc"
++ *   "fsl,tmr-add"
++ *   "fsl,tmr-fiper1"
++ *   "fsl,tmr-fiper2"
++ *   "fsl,max-adj"
++ *
++ * Return 0 if success
++ */
++static int qoriq_ptp_auto_config(struct qoriq_ptp *qoriq_ptp,
++				 struct device_node *node)
++{
++	struct clk *clk;
++	u64 freq_comp;
++	u64 max_adj;
++	u32 nominal_freq;
++	u32 remainder = 0;
++	u32 clk_src = 0;
++
++	qoriq_ptp->cksel = DEFAULT_CKSEL;
++
++	clk = of_clk_get(node, 0);
++	if (!IS_ERR(clk)) {
++		clk_src = clk_get_rate(clk);
++		clk_put(clk);
++	}
++
++	if (clk_src <= 100000000UL) {
++		pr_err("error reference clock value, or lower than 100MHz\n");
++		return -EINVAL;
++	}
++
++	nominal_freq = qoriq_ptp_nominal_freq(clk_src);
++	if (!nominal_freq)
++		return -EINVAL;
++
++	qoriq_ptp->tclk_period = 1000000000UL / nominal_freq;
++	qoriq_ptp->tmr_prsc = DEFAULT_TMR_PRSC;
++
++	/* Calculate initial frequency compensation value for TMR_ADD register.
++	 * freq_comp = ceil(2^32 / freq_ratio)
++	 * freq_ratio = reference_clock_freq / nominal_freq
++	 */
++	freq_comp = ((u64)1 << 32) * nominal_freq;
++	freq_comp = div_u64_rem(freq_comp, clk_src, &remainder);
++	if (remainder)
++		freq_comp++;
++
++	qoriq_ptp->tmr_add = freq_comp;
++	qoriq_ptp->tmr_fiper1 = DEFAULT_FIPER1_PERIOD - qoriq_ptp->tclk_period;
++	qoriq_ptp->tmr_fiper2 = DEFAULT_FIPER2_PERIOD - qoriq_ptp->tclk_period;
++
++	/* max_adj = 1000000000 * (freq_ratio - 1.0) - 1
++	 * freq_ratio = reference_clock_freq / nominal_freq
++	 */
++	max_adj = 1000000000ULL * (clk_src - nominal_freq);
++	max_adj = div_u64(max_adj, nominal_freq) - 1;
++	qoriq_ptp->caps.max_adj = max_adj;
++
++	return 0;
++}
++
++static int qoriq_ptp_probe(struct platform_device *dev)
++{
++	struct device_node *node = dev->dev.of_node;
++	struct qoriq_ptp *qoriq_ptp;
++	struct qoriq_ptp_registers *regs;
++	struct timespec64 now;
++	int err = -ENOMEM;
++	u32 tmr_ctrl;
++	unsigned long flags;
++	void __iomem *base;
++
++	qoriq_ptp = kzalloc(sizeof(*qoriq_ptp), GFP_KERNEL);
++	if (!qoriq_ptp)
++		goto no_memory;
++
++	err = -EINVAL;
++
++	qoriq_ptp->caps = ptp_qoriq_caps;
++
++	if (of_property_read_u32(node, "fsl,cksel", &qoriq_ptp->cksel))
++		qoriq_ptp->cksel = DEFAULT_CKSEL;
++
++	if (of_property_read_u32(node,
++				 "fsl,tclk-period", &qoriq_ptp->tclk_period) ||
++	    of_property_read_u32(node,
++				 "fsl,tmr-prsc", &qoriq_ptp->tmr_prsc) ||
++	    of_property_read_u32(node,
++				 "fsl,tmr-add", &qoriq_ptp->tmr_add) ||
++	    of_property_read_u32(node,
++				 "fsl,tmr-fiper1", &qoriq_ptp->tmr_fiper1) ||
++	    of_property_read_u32(node,
++				 "fsl,tmr-fiper2", &qoriq_ptp->tmr_fiper2) ||
++	    of_property_read_u32(node,
++				 "fsl,max-adj", &qoriq_ptp->caps.max_adj)) {
++		pr_warn("device tree node missing required elements, try automatic configuration\n");
++
++		if (qoriq_ptp_auto_config(qoriq_ptp, node))
++			goto no_config;
++	}
++
++	err = -ENODEV;
++
++	qoriq_ptp->irq = platform_get_irq(dev, 0);
++
++	if (qoriq_ptp->irq < 0) {
++		pr_err("irq not in device tree\n");
++		goto no_node;
++	}
++	if (request_irq(qoriq_ptp->irq, isr, IRQF_SHARED, DRIVER, qoriq_ptp)) {
++		pr_err("request_irq failed\n");
++		goto no_node;
++	}
++
++	qoriq_ptp->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
++	if (!qoriq_ptp->rsrc) {
++		pr_err("no resource\n");
++		goto no_resource;
++	}
++	if (request_resource(&iomem_resource, qoriq_ptp->rsrc)) {
++		pr_err("resource busy\n");
++		goto no_resource;
++	}
++
++	spin_lock_init(&qoriq_ptp->lock);
++
++	base = ioremap(qoriq_ptp->rsrc->start,
++		       resource_size(qoriq_ptp->rsrc));
++	if (!base) {
++		pr_err("ioremap ptp registers failed\n");
++		goto no_ioremap;
++	}
++
++	qoriq_ptp->base = base;
++
++	if (of_device_is_compatible(node, "fsl,fman-ptp-timer")) {
++		qoriq_ptp->regs.ctrl_regs = base + FMAN_CTRL_REGS_OFFSET;
++		qoriq_ptp->regs.alarm_regs = base + FMAN_ALARM_REGS_OFFSET;
++		qoriq_ptp->regs.fiper_regs = base + FMAN_FIPER_REGS_OFFSET;
++		qoriq_ptp->regs.etts_regs = base + FMAN_ETTS_REGS_OFFSET;
++	} else {
++		qoriq_ptp->regs.ctrl_regs = base + CTRL_REGS_OFFSET;
++		qoriq_ptp->regs.alarm_regs = base + ALARM_REGS_OFFSET;
++		qoriq_ptp->regs.fiper_regs = base + FIPER_REGS_OFFSET;
++		qoriq_ptp->regs.etts_regs = base + ETTS_REGS_OFFSET;
++	}
++
++	ktime_get_real_ts64(&now);
++	ptp_qoriq_settime(&qoriq_ptp->caps, &now);
++
++	tmr_ctrl =
++	  (qoriq_ptp->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
++	  (qoriq_ptp->cksel & CKSEL_MASK) << CKSEL_SHIFT;
++
++	spin_lock_irqsave(&qoriq_ptp->lock, flags);
++
++	regs = &qoriq_ptp->regs;
++	qoriq_write(&regs->ctrl_regs->tmr_ctrl,   tmr_ctrl);
++	qoriq_write(&regs->ctrl_regs->tmr_add,    qoriq_ptp->tmr_add);
++	qoriq_write(&regs->ctrl_regs->tmr_prsc,   qoriq_ptp->tmr_prsc);
++	qoriq_write(&regs->fiper_regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
++	qoriq_write(&regs->fiper_regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
++	set_alarm(qoriq_ptp);
++	qoriq_write(&regs->ctrl_regs->tmr_ctrl,   tmr_ctrl|FIPERST|RTPE|TE|FRD);
++
++	spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
++
++	qoriq_ptp->clock = ptp_clock_register(&qoriq_ptp->caps, &dev->dev);
++	if (IS_ERR(qoriq_ptp->clock)) {
++		err = PTR_ERR(qoriq_ptp->clock);
++		goto no_clock;
++	}
++	qoriq_ptp->phc_index = ptp_clock_index(qoriq_ptp->clock);
++
++	platform_set_drvdata(dev, qoriq_ptp);
++
++	return 0;
++
++no_clock:
++	iounmap(qoriq_ptp->base);
++no_ioremap:
++	release_resource(qoriq_ptp->rsrc);
++no_resource:
++	free_irq(qoriq_ptp->irq, qoriq_ptp);
++no_config:
++no_node:
++	kfree(qoriq_ptp);
++no_memory:
++	return err;
++}
++
++static int qoriq_ptp_remove(struct platform_device *dev)
++{
++	struct qoriq_ptp *qoriq_ptp = platform_get_drvdata(dev);
++	struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
++
++	qoriq_write(&regs->ctrl_regs->tmr_temask, 0);
++	qoriq_write(&regs->ctrl_regs->tmr_ctrl,   0);
++
++	ptp_clock_unregister(qoriq_ptp->clock);
++	iounmap(qoriq_ptp->base);
++	release_resource(qoriq_ptp->rsrc);
++	free_irq(qoriq_ptp->irq, qoriq_ptp);
++	kfree(qoriq_ptp);
++
++	return 0;
++}
++
++static const struct of_device_id match_table[] = {
++	{ .compatible = "fsl,etsec-ptp" },
++	{ .compatible = "fsl,fman-ptp-timer" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, match_table);
++
++static struct platform_driver qoriq_ptp_driver = {
++	.driver = {
++		.name		= "ptp_qoriq",
++		.of_match_table	= match_table,
++	},
++	.probe       = qoriq_ptp_probe,
++	.remove      = qoriq_ptp_remove,
++};
++
++module_platform_driver(qoriq_ptp_driver);
++
++MODULE_AUTHOR("Richard Cochran <[email protected]>");
++MODULE_DESCRIPTION("PTP clock for Freescale QorIQ 1588 timer");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/include/linux/fsl/ptp_qoriq.h
+@@ -0,0 +1,169 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2010 OMICRON electronics GmbH
++ * Copyright 2018 NXP
++ */
++#ifndef __PTP_QORIQ_H__
++#define __PTP_QORIQ_H__
++
++#include <linux/io.h>
++#include <linux/ptp_clock_kernel.h>
++
++/*
++ * qoriq ptp registers
++ */
++struct ctrl_regs {
++	u32 tmr_ctrl;     /* Timer control register */
++	u32 tmr_tevent;   /* Timestamp event register */
++	u32 tmr_temask;   /* Timer event mask register */
++	u32 tmr_pevent;   /* Timestamp event register */
++	u32 tmr_pemask;   /* Timer event mask register */
++	u32 tmr_stat;     /* Timestamp status register */
++	u32 tmr_cnt_h;    /* Timer counter high register */
++	u32 tmr_cnt_l;    /* Timer counter low register */
++	u32 tmr_add;      /* Timer drift compensation addend register */
++	u32 tmr_acc;      /* Timer accumulator register */
++	u32 tmr_prsc;     /* Timer prescale */
++	u8  res1[4];
++	u32 tmroff_h;     /* Timer offset high */
++	u32 tmroff_l;     /* Timer offset low */
++};
++
++struct alarm_regs {
++	u32 tmr_alarm1_h; /* Timer alarm 1 high register */
++	u32 tmr_alarm1_l; /* Timer alarm 1 high register */
++	u32 tmr_alarm2_h; /* Timer alarm 2 high register */
++	u32 tmr_alarm2_l; /* Timer alarm 2 high register */
++};
++
++struct fiper_regs {
++	u32 tmr_fiper1;   /* Timer fixed period interval */
++	u32 tmr_fiper2;   /* Timer fixed period interval */
++	u32 tmr_fiper3;   /* Timer fixed period interval */
++};
++
++struct etts_regs {
++	u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */
++	u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */
++	u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */
++	u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */
++};
++
++struct qoriq_ptp_registers {
++	struct ctrl_regs __iomem *ctrl_regs;
++	struct alarm_regs __iomem *alarm_regs;
++	struct fiper_regs __iomem *fiper_regs;
++	struct etts_regs __iomem *etts_regs;
++};
++
++/* Offset definitions for the four register groups */
++#define CTRL_REGS_OFFSET	0x0
++#define ALARM_REGS_OFFSET	0x40
++#define FIPER_REGS_OFFSET	0x80
++#define ETTS_REGS_OFFSET	0xa0
++
++#define FMAN_CTRL_REGS_OFFSET	0x80
++#define FMAN_ALARM_REGS_OFFSET	0xb8
++#define FMAN_FIPER_REGS_OFFSET	0xd0
++#define FMAN_ETTS_REGS_OFFSET	0xe0
++
++
++/* Bit definitions for the TMR_CTRL register */
++#define ALM1P                 (1<<31) /* Alarm1 output polarity */
++#define ALM2P                 (1<<30) /* Alarm2 output polarity */
++#define FIPERST               (1<<28) /* FIPER start indication */
++#define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */
++#define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */
++#define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */
++#define TCLK_PERIOD_MASK      (0x3ff)
++#define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */
++#define FRD                   (1<<14) /* FIPER Realignment Disable */
++#define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */
++#define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */
++#define ETEP2                 (1<<9) /* External trigger 2 edge polarity */
++#define ETEP1                 (1<<8) /* External trigger 1 edge polarity */
++#define COPH                  (1<<7) /* Generated clock output phase. */
++#define CIPH                  (1<<6) /* External oscillator input clock phase */
++#define TMSR                  (1<<5) /* Timer soft reset. */
++#define BYP                   (1<<3) /* Bypass drift compensated clock */
++#define TE                    (1<<2) /* 1588 timer enable. */
++#define CKSEL_SHIFT           (0)    /* 1588 Timer reference clock source */
++#define CKSEL_MASK            (0x3)
++
++/* Bit definitions for the TMR_TEVENT register */
++#define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */
++#define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */
++#define ALM2                  (1<<17) /* Current time = alarm time register 2 */
++#define ALM1                  (1<<16) /* Current time = alarm time register 1 */
++#define PP1                   (1<<7)  /* periodic pulse generated on FIPER1 */
++#define PP2                   (1<<6)  /* periodic pulse generated on FIPER2 */
++#define PP3                   (1<<5)  /* periodic pulse generated on FIPER3 */
++
++/* Bit definitions for the TMR_TEMASK register */
++#define ETS2EN                (1<<25) /* External trigger 2 timestamp enable */
++#define ETS1EN                (1<<24) /* External trigger 1 timestamp enable */
++#define ALM2EN                (1<<17) /* Timer ALM2 event enable */
++#define ALM1EN                (1<<16) /* Timer ALM1 event enable */
++#define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */
++#define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */
++
++/* Bit definitions for the TMR_PEVENT register */
++#define TXP2                  (1<<9) /* PTP transmitted timestamp im TXTS2 */
++#define TXP1                  (1<<8) /* PTP transmitted timestamp in TXTS1 */
++#define RXP                   (1<<0) /* PTP frame has been received */
++
++/* Bit definitions for the TMR_PEMASK register */
++#define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */
++#define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */
++#define RXPEN                 (1<<0) /* Receive PTP packet event enable */
++
++/* Bit definitions for the TMR_STAT register */
++#define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */
++#define STAT_VEC_MASK         (0x3f)
++
++/* Bit definitions for the TMR_PRSC register */
++#define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */
++#define PRSC_OCK_MASK         (0xffff)
++
++
++#define DRIVER		"ptp_qoriq"
++#define N_EXT_TS	2
++
++#define DEFAULT_CKSEL		1
++#define DEFAULT_TMR_PRSC	2
++#define DEFAULT_FIPER1_PERIOD	1000000000
++#define DEFAULT_FIPER2_PERIOD	100000
++
++struct qoriq_ptp {
++	void __iomem *base;
++	struct qoriq_ptp_registers regs;
++	spinlock_t lock; /* protects regs */
++	struct ptp_clock *clock;
++	struct ptp_clock_info caps;
++	struct resource *rsrc;
++	int irq;
++	int phc_index;
++	u64 alarm_interval; /* for periodic alarm */
++	u64 alarm_value;
++	u32 tclk_period;  /* nanoseconds */
++	u32 tmr_prsc;
++	u32 tmr_add;
++	u32 cksel;
++	u32 tmr_fiper1;
++	u32 tmr_fiper2;
++};
++
++static inline u32 qoriq_read(unsigned __iomem *addr)
++{
++	u32 val;
++
++	val = ioread32be(addr);
++	return val;
++}
++
++static inline void qoriq_write(unsigned __iomem *addr, u32 val)
++{
++	iowrite32be(val, addr);
++}
++
++#endif

target/linux/layerscape/patches-4.14/825-tmu-support-layerscape.patch

@@ -0,0 +1,188 @@
+From 2ddaec76dbe9b6e911e2a1442248ab103909cce3 Mon Sep 17 00:00:00 2001
+From: Biwen Li <[email protected]>
+Date: Wed, 17 Apr 2019 18:59:06 +0800
+Subject: [PATCH] tmu: support layerscape
+
+This is an integrated patch of tmu for layerscape
+
+Signed-off-by: Biwen Li <[email protected]>
+Signed-off-by: Eduardo Valentin <[email protected]>
+Signed-off-by: Fabio Estevam <[email protected]>
+Signed-off-by: Yuantian Tang <[email protected]>
+---
+ drivers/thermal/qoriq_thermal.c | 102 ++++++++++++++------------------
+ 1 file changed, 46 insertions(+), 56 deletions(-)
+
+--- a/drivers/thermal/qoriq_thermal.c
++++ b/drivers/thermal/qoriq_thermal.c
+@@ -69,14 +69,21 @@ struct qoriq_tmu_regs {
+ 	u32 ttr3cr;		/* Temperature Range 3 Control Register */
+ };
+ 
++struct qoriq_tmu_data;
++
+ /*
+  * Thermal zone data
+  */
++struct qoriq_sensor {
++	struct thermal_zone_device	*tzd;
++	struct qoriq_tmu_data		*qdata;
++	int				id;
++};
++
+ struct qoriq_tmu_data {
+-	struct thermal_zone_device *tz;
+ 	struct qoriq_tmu_regs __iomem *regs;
+-	int sensor_id;
+ 	bool little_endian;
++	struct qoriq_sensor	*sensor[SITES_MAX];
+ };
+ 
+ static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
+@@ -97,48 +104,51 @@ static u32 tmu_read(struct qoriq_tmu_dat
+ 
+ static int tmu_get_temp(void *p, int *temp)
+ {
++	struct qoriq_sensor *qsensor = p;
++	struct qoriq_tmu_data *qdata = qsensor->qdata;
+ 	u32 val;
+-	struct qoriq_tmu_data *data = p;
+ 
+-	val = tmu_read(data, &data->regs->site[data->sensor_id].tritsr);
++	val = tmu_read(qdata, &qdata->regs->site[qsensor->id].tritsr);
+ 	*temp = (val & 0xff) * 1000;
+ 
+ 	return 0;
+ }
+ 
+-static int qoriq_tmu_get_sensor_id(void)
++static const struct thermal_zone_of_device_ops tmu_tz_ops = {
++	.get_temp = tmu_get_temp,
++};
++
++static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
+ {
+-	int ret, id;
+-	struct of_phandle_args sensor_specs;
+-	struct device_node *np, *sensor_np;
++	struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
++	int id, sites = 0;
+ 
+-	np = of_find_node_by_name(NULL, "thermal-zones");
+-	if (!np)
+-		return -ENODEV;
++	for (id = 0; id < SITES_MAX; id++) {
++		qdata->sensor[id] = devm_kzalloc(&pdev->dev,
++				sizeof(struct qoriq_sensor), GFP_KERNEL);
++		if (!qdata->sensor[id])
++			return -ENOMEM;
++
++		qdata->sensor[id]->id = id;
++		qdata->sensor[id]->qdata = qdata;
++
++		qdata->sensor[id]->tzd = devm_thermal_zone_of_sensor_register(
++				&pdev->dev, id, qdata->sensor[id], &tmu_tz_ops);
++		if (IS_ERR(qdata->sensor[id]->tzd)) {
++			if (PTR_ERR(qdata->sensor[id]->tzd) == -ENODEV)
++				continue;
++			else
++				return PTR_ERR(qdata->sensor[id]->tzd);
+ 
+-	sensor_np = of_get_next_child(np, NULL);
+-	ret = of_parse_phandle_with_args(sensor_np, "thermal-sensors",
+-			"#thermal-sensor-cells",
+-			0, &sensor_specs);
+-	if (ret) {
+-		of_node_put(np);
+-		of_node_put(sensor_np);
+-		return ret;
+-	}
+-
+-	if (sensor_specs.args_count >= 1) {
+-		id = sensor_specs.args[0];
+-		WARN(sensor_specs.args_count > 1,
+-				"%s: too many cells in sensor specifier %d\n",
+-				sensor_specs.np->name, sensor_specs.args_count);
+-	} else {
+-		id = 0;
+-	}
++		}
+ 
+-	of_node_put(np);
+-	of_node_put(sensor_np);
++		sites |= 0x1 << (15 - id);
++	}
++	/* Enable monitoring */
++	if (sites != 0)
++		tmu_write(qdata, sites | TMR_ME | TMR_ALPF, &qdata->regs->tmr);
+ 
+-	return id;
++	return 0;
+ }
+ 
+ static int qoriq_tmu_calibration(struct platform_device *pdev)
+@@ -188,16 +198,11 @@ static void qoriq_tmu_init_device(struct
+ 	tmu_write(data, TMR_DISABLE, &data->regs->tmr);
+ }
+ 
+-static const struct thermal_zone_of_device_ops tmu_tz_ops = {
+-	.get_temp = tmu_get_temp,
+-};
+-
+ static int qoriq_tmu_probe(struct platform_device *pdev)
+ {
+ 	int ret;
+ 	struct qoriq_tmu_data *data;
+ 	struct device_node *np = pdev->dev.of_node;
+-	u32 site = 0;
+ 
+ 	if (!np) {
+ 		dev_err(&pdev->dev, "Device OF-Node is NULL");
+@@ -213,13 +218,6 @@ static int qoriq_tmu_probe(struct platfo
+ 
+ 	data->little_endian = of_property_read_bool(np, "little-endian");
+ 
+-	data->sensor_id = qoriq_tmu_get_sensor_id();
+-	if (data->sensor_id < 0) {
+-		dev_err(&pdev->dev, "Failed to get sensor id\n");
+-		ret = -ENODEV;
+-		goto err_iomap;
+-	}
+-
+ 	data->regs = of_iomap(np, 0);
+ 	if (!data->regs) {
+ 		dev_err(&pdev->dev, "Failed to get memory region\n");
+@@ -233,19 +231,13 @@ static int qoriq_tmu_probe(struct platfo
+ 	if (ret < 0)
+ 		goto err_tmu;
+ 
+-	data->tz = thermal_zone_of_sensor_register(&pdev->dev, data->sensor_id,
+-				data, &tmu_tz_ops);
+-	if (IS_ERR(data->tz)) {
+-		ret = PTR_ERR(data->tz);
+-		dev_err(&pdev->dev,
+-			"Failed to register thermal zone device %d\n", ret);
+-		goto err_tmu;
++	ret = qoriq_tmu_register_tmu_zone(pdev);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Failed to register sensors\n");
++		ret = -ENODEV;
++		goto err_iomap;
+ 	}
+ 
+-	/* Enable monitoring */
+-	site |= 0x1 << (15 - data->sensor_id);
+-	tmu_write(data, site | TMR_ME | TMR_ALPF, &data->regs->tmr);
+-
+ 	return 0;
+ 
+ err_tmu:
+@@ -261,8 +253,6 @@ static int qoriq_tmu_remove(struct platf
+ {
+ 	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
+ 
+-	thermal_zone_of_sensor_unregister(&pdev->dev, data->tz);
+-
+ 	/* Disable monitoring */
+ 	tmu_write(data, TMR_DISABLE, &data->regs->tmr);
+ 

target/linux/layerscape/patches-4.14/825-vfio-fsl-mc-Improve-send-mc-command-and-read-respons.patch

@@ -1,48 +0,0 @@
-From 703b2ca94467a029942fa478a38f0a14c8109766 Mon Sep 17 00:00:00 2001
-From: Bharat Bhushan <[email protected]>
-Date: Fri, 1 Mar 2019 13:33:58 +0800
-Subject: [PATCH] vfio/fsl-mc: Improve send mc-command and read response
-
-Actually there is no ordering need when reading response
-from mc-portal. Similarly when writing the mc-command,
-ordering needed before command is submitted.
-
-This patch removes un-necessary barriers, response is read
-relaxed and maintain ordering when submit command. This also
-fixes compilation issue with newer kernel.
-
-Signed-off-by: Bharat Bhushan <[email protected]>
-Signed-off-by: Yangbo Lu <[email protected]>
----
- drivers/vfio/fsl-mc/vfio_fsl_mc.c | 13 +++++++------
- 1 file changed, 7 insertions(+), 6 deletions(-)
-
---- a/drivers/vfio/fsl-mc/vfio_fsl_mc.c
-+++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
-@@ -331,9 +331,7 @@ static int vfio_fsl_mc_dprc_wait_for_res
- 		u64 header;
- 		struct mc_cmd_header *resp_hdr;
- 
--		__iormb();
--		header = readq(ioaddr);
--		__iormb();
-+		header = cpu_to_le64(readq_relaxed(ioaddr));
- 
- 		resp_hdr = (struct mc_cmd_header *)&header;
- 		status = (enum mc_cmd_status)resp_hdr->status;
-@@ -353,9 +351,12 @@ static int vfio_fsl_mc_send_command(void
- {
- 	int i;
- 
--	/* Write at command header in the end */
--	for (i = 7; i >= 0; i--)
--		writeq(cmd_data[i], ioaddr + i * sizeof(uint64_t));
-+	/* Write at command parameter into portal */
-+	for (i = 7; i >= 1; i--)
-+		writeq_relaxed(cmd_data[i], ioaddr + i * sizeof(uint64_t));
-+
-+	/* Write command header in the end */
-+	writeq(cmd_data[0], ioaddr);
- 
- 	/* Wait for response before returning to user-space
- 	 * This can be optimized in future to even prepare response