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@@ -1,271 +0,0 @@
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-From 8fe9821b478e5c61fef4786b7ec96b6766af196d Mon Sep 17 00:00:00 2001
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-From: Mathias Kresin <[email protected]>
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-Date: Mon, 8 Jan 2018 23:04:57 +0100
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-Subject: [PATCH] Revert "MIPS: smp-mt: Use CPU interrupt controller IPI IRQ
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- domain support"
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-
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-The problem is that the Lantiq IRQ controller gets registered first and
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-it directly handles the MIPS native SW1/2 and HW0 - HW5 IRQs. It looks
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-like this controller already registers IRQ 0 - 7 and the generic driver
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-only gets the following IRQs starting later.
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-
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-The upstream discussion can be found at https://www.linux-mips.org/archives/linux-mips/2017-05/msg00059.html
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-
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-This reverts kernel commit 1eed40043579 ("MIPS: smp-mt: Use CPU interrupt
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-controller IPI IRQ domain support").
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-
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-Signed-off-by: Mathias Kresin <[email protected]>
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-
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----
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- arch/mips/kernel/smp-mt.c | 49 ++++++++++++++++++++++--
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- arch/mips/lantiq/irq.c | 52 ++++++++++++++++++++++++++
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- arch/mips/mti-malta/malta-int.c | 83 +++++++++++++++++++++++++++++++++++++++--
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- 3 files changed, 176 insertions(+), 8 deletions(-)
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-
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---- a/arch/mips/kernel/smp-mt.c
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-+++ b/arch/mips/kernel/smp-mt.c
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-@@ -83,8 +83,6 @@ static unsigned int __init smvp_vpe_init
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- if (tc != 0)
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- smvp_copy_vpe_config();
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-
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-- cpu_set_vpe_id(&cpu_data[ncpu], tc);
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--
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- return ncpu;
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- }
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-
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-@@ -116,6 +114,49 @@ static void __init smvp_tc_init(unsigned
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- write_tc_c0_tchalt(TCHALT_H);
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- }
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-
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-+static void vsmp_send_ipi_single(int cpu, unsigned int action)
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-+{
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-+ int i;
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-+ unsigned long flags;
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-+ int vpflags;
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-+
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-+#ifdef CONFIG_MIPS_GIC
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-+ if (gic_present) {
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-+ mips_smp_send_ipi_single(cpu, action);
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-+ return;
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-+ }
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-+#endif
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-+ local_irq_save(flags);
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-+
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-+ vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */
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-+
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-+ switch (action) {
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-+ case SMP_CALL_FUNCTION:
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-+ i = C_SW1;
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-+ break;
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-+
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-+ case SMP_RESCHEDULE_YOURSELF:
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-+ default:
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-+ i = C_SW0;
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-+ break;
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-+ }
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-+
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-+ /* 1:1 mapping of vpe and tc... */
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-+ settc(cpu);
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-+ write_vpe_c0_cause(read_vpe_c0_cause() | i);
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-+ evpe(vpflags);
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-+
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-+ local_irq_restore(flags);
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-+}
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-+
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-+static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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-+{
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-+ unsigned int i;
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-+
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-+ for_each_cpu(i, mask)
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-+ vsmp_send_ipi_single(i, action);
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-+}
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-+
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- static void vsmp_init_secondary(void)
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- {
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- /* This is Malta specific: IPI,performance and timer interrupts */
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-@@ -240,8 +281,8 @@ static void __init vsmp_prepare_cpus(uns
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- }
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-
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- const struct plat_smp_ops vsmp_smp_ops = {
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-- .send_ipi_single = mips_smp_send_ipi_single,
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-- .send_ipi_mask = mips_smp_send_ipi_mask,
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-+ .send_ipi_single = vsmp_send_ipi_single,
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-+ .send_ipi_mask = vsmp_send_ipi_mask,
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- .init_secondary = vsmp_init_secondary,
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- .smp_finish = vsmp_smp_finish,
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- .boot_secondary = vsmp_boot_secondary,
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---- a/arch/mips/lantiq/irq.c
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-+++ b/arch/mips/lantiq/irq.c
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-@@ -272,6 +272,47 @@ static void ltq_hw_irq_handler(struct ir
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- ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
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- }
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-
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-+#ifdef CONFIG_MIPS_MT_SMP
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-+void __init arch_init_ipiirq(int irq, struct irqaction *action)
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-+{
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-+ setup_irq(irq, action);
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-+ irq_set_handler(irq, handle_percpu_irq);
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-+}
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-+
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-+static void ltq_sw0_irqdispatch(void)
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-+{
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-+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
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-+}
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-+
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-+static void ltq_sw1_irqdispatch(void)
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-+{
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-+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
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-+}
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-+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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-+{
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-+ scheduler_ipi();
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-+ return IRQ_HANDLED;
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-+}
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-+
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-+static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
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-+{
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-+ generic_smp_call_function_interrupt();
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-+ return IRQ_HANDLED;
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-+}
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-+
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-+static struct irqaction irq_resched = {
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-+ .handler = ipi_resched_interrupt,
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-+ .flags = IRQF_PERCPU,
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-+ .name = "IPI_resched"
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-+};
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-+
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-+static struct irqaction irq_call = {
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-+ .handler = ipi_call_interrupt,
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-+ .flags = IRQF_PERCPU,
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-+ .name = "IPI_call"
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-+};
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-+#endif
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-+
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- asmlinkage void plat_irq_dispatch(void)
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- {
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- unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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-@@ -359,6 +400,17 @@ int __init icu_of_init(struct device_nod
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- (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
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- &irq_domain_ops, 0);
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-
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-+#if defined(CONFIG_MIPS_MT_SMP)
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-+ if (cpu_has_vint) {
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-+ pr_info("Setting up IPI vectored interrupts\n");
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-+ set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
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-+ set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
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-+ }
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-+ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
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-+ &irq_resched);
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-+ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
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-+#endif
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-+
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- #ifndef CONFIG_MIPS_MT_SMP
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- set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
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- IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
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---- a/arch/mips/mti-malta/malta-int.c
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-+++ b/arch/mips/mti-malta/malta-int.c
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-@@ -144,6 +144,56 @@ static irqreturn_t corehi_handler(int ir
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- return IRQ_HANDLED;
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- }
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-
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-+#ifdef CONFIG_MIPS_MT_SMP
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-+
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-+#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
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-+#define C_RESCHED C_SW0
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-+#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
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-+#define C_CALL C_SW1
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-+static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
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-+
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-+static void ipi_resched_dispatch(void)
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-+{
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-+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
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-+}
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-+
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-+static void ipi_call_dispatch(void)
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-+{
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-+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
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-+}
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-+
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-+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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-+{
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-+#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
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-+ if (aprp_hook)
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-+ aprp_hook();
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-+#endif
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-+
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-+ scheduler_ipi();
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-+
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-+ return IRQ_HANDLED;
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-+}
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-+
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-+static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
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-+{
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-+ generic_smp_call_function_interrupt();
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-+
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-+ return IRQ_HANDLED;
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-+}
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-+
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-+static struct irqaction irq_resched = {
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-+ .handler = ipi_resched_interrupt,
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-+ .flags = IRQF_PERCPU,
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-+ .name = "IPI_resched"
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-+};
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-+
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-+static struct irqaction irq_call = {
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-+ .handler = ipi_call_interrupt,
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-+ .flags = IRQF_PERCPU,
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-+ .name = "IPI_call"
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-+};
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-+#endif /* CONFIG_MIPS_MT_SMP */
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-+
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- static struct irqaction corehi_irqaction = {
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- .handler = corehi_handler,
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- .name = "CoreHi",
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-@@ -171,6 +221,12 @@ static msc_irqmap_t msc_eicirqmap[] __in
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-
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- static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
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-
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-+void __init arch_init_ipiirq(int irq, struct irqaction *action)
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-+{
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-+ setup_irq(irq, action);
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-+ irq_set_handler(irq, handle_percpu_irq);
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-+}
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-+
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- void __init arch_init_irq(void)
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- {
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- int corehi_irq;
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-@@ -216,11 +272,30 @@ void __init arch_init_irq(void)
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-
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- if (mips_gic_present()) {
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- corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
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-- } else if (cpu_has_veic) {
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-- set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
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-- corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
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- } else {
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-- corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
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-+#if defined(CONFIG_MIPS_MT_SMP)
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-+ /* set up ipi interrupts */
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-+ if (cpu_has_veic) {
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-+ set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
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-+ set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
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-+ cpu_ipi_resched_irq = MSC01E_INT_SW0;
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-+ cpu_ipi_call_irq = MSC01E_INT_SW1;
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-+ } else {
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-+ cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
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-+ MIPS_CPU_IPI_RESCHED_IRQ;
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-+ cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
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-+ MIPS_CPU_IPI_CALL_IRQ;
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-+ }
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-+ arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
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-+ arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
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-+#endif
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-+ if (cpu_has_veic) {
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-+ set_vi_handler(MSC01E_INT_COREHI,
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-+ corehi_irqdispatch);
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-+ corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
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-+ } else {
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-+ corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
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-+ }
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- }
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-
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- setup_irq(corehi_irq, &corehi_irqaction);
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Koen Vandeputte