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@@ -0,0 +1,384 @@
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+From db791eb2970bad193b1dc95a4461b222dd22cb64 Mon Sep 17 00:00:00 2001
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+From: Jon Mason <[email protected]>
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+Date: Thu, 7 Jul 2016 19:08:56 -0400
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+Subject: [PATCH 4/5] net: ethernet: bgmac: convert to feature flags
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+
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+The bgmac driver is using the bcma provides device ID and revision, as
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+well as the SoC ID and package, to determine which features are
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+necessary to enable, reset, etc in the driver. In anticipation of
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+removing the bcma requirement for this driver, these must be changed to
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+not reference that struct. In place of that, each "feature" has been
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+given a flag, and the flags are enabled for their respective device and
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+SoC.
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+
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+Signed-off-by: Jon Mason <[email protected]>
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+Acked-by: Arnd Bergmann <[email protected]>
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+Reviewed-by: Florian Fainelli <[email protected]>
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+Tested-by: Florian Fainelli <[email protected]>
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+Signed-off-by: David S. Miller <[email protected]>
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+---
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+ drivers/net/ethernet/broadcom/bgmac.c | 167 ++++++++++++++++++++++++----------
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+ drivers/net/ethernet/broadcom/bgmac.h | 21 ++++-
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+ 2 files changed, 140 insertions(+), 48 deletions(-)
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+
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+--- a/drivers/net/ethernet/broadcom/bgmac.c
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++++ b/drivers/net/ethernet/broadcom/bgmac.c
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+@@ -109,7 +109,7 @@ static void bgmac_dma_tx_enable(struct b
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+ u32 ctl;
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+
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+ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
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+- if (bgmac->core->id.rev >= 4) {
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++ if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
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+ ctl &= ~BGMAC_DMA_TX_BL_MASK;
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+ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
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+
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+@@ -331,7 +331,7 @@ static void bgmac_dma_rx_enable(struct b
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+ u32 ctl;
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+
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+ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
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+- if (bgmac->core->id.rev >= 4) {
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++ if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
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+ ctl &= ~BGMAC_DMA_RX_BL_MASK;
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+ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
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+
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+@@ -769,14 +769,20 @@ static void bgmac_cmdcfg_maskset(struct
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+ {
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+ u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
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+ u32 new_val = (cmdcfg & mask) | set;
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++ u32 cmdcfg_sr;
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+
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+- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
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++ if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
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++ cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
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++ else
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++ cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
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++
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++ bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
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+ udelay(2);
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+
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+ if (new_val != cmdcfg || force)
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+ bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
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+
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+- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
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++ bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
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+ udelay(2);
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+ }
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+
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+@@ -805,7 +811,7 @@ static void bgmac_chip_stats_update(stru
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+ {
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+ int i;
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+
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+- if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
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++ if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
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+ for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
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+ bgmac->mib_tx_regs[i] =
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+ bgmac_read(bgmac,
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+@@ -824,7 +830,7 @@ static void bgmac_clear_mib(struct bgmac
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+ {
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+ int i;
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+
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+- if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
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++ if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
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+ return;
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+
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+ bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
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+@@ -867,9 +873,8 @@ static void bgmac_mac_speed(struct bgmac
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+ static void bgmac_miiconfig(struct bgmac *bgmac)
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+ {
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+ struct bcma_device *core = bgmac->core;
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+- u8 imode;
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+
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+- if (bgmac_is_bcm4707_family(bgmac)) {
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++ if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
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+ bcma_awrite32(core, BCMA_IOCTL,
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+ bcma_aread32(core, BCMA_IOCTL) | 0x40 |
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+ BGMAC_BCMA_IOCTL_SW_CLKEN);
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+@@ -877,6 +882,8 @@ static void bgmac_miiconfig(struct bgmac
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+ bgmac->mac_duplex = DUPLEX_FULL;
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+ bgmac_mac_speed(bgmac);
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+ } else {
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++ u8 imode;
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++
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+ imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
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+ BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
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+ if (imode == 0 || imode == 1) {
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+@@ -891,9 +898,7 @@ static void bgmac_miiconfig(struct bgmac
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+ static void bgmac_chip_reset(struct bgmac *bgmac)
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+ {
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+ struct bcma_device *core = bgmac->core;
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+- struct bcma_bus *bus = core->bus;
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+- struct bcma_chipinfo *ci = &bus->chipinfo;
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+- u32 flags;
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++ u32 cmdcfg_sr;
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+ u32 iost;
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+ int i;
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+
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+@@ -916,15 +921,12 @@ static void bgmac_chip_reset(struct bgma
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+ }
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+
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+ iost = bcma_aread32(core, BCMA_IOST);
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+- if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
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+- (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
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+- (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
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++ if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
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+ iost &= ~BGMAC_BCMA_IOST_ATTACHED;
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+
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+ /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
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+- if (ci->id != BCMA_CHIP_ID_BCM4707 &&
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+- ci->id != BCMA_CHIP_ID_BCM47094) {
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+- flags = 0;
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++ if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
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++ u32 flags = 0;
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+ if (iost & BGMAC_BCMA_IOST_ATTACHED) {
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+ flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
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+ if (!bgmac->has_robosw)
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+@@ -934,7 +936,7 @@ static void bgmac_chip_reset(struct bgma
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+ }
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+
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+ /* Request Misc PLL for corerev > 2 */
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+- if (core->id.rev > 2 && !bgmac_is_bcm4707_family(bgmac)) {
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++ if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
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+ bgmac_set(bgmac, BCMA_CLKCTLST,
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+ BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
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+ bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
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+@@ -943,9 +945,7 @@ static void bgmac_chip_reset(struct bgma
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+ 1000);
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+ }
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+
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+- if (ci->id == BCMA_CHIP_ID_BCM5357 ||
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+- ci->id == BCMA_CHIP_ID_BCM4749 ||
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+- ci->id == BCMA_CHIP_ID_BCM53572) {
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++ if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
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+ struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
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+ u8 et_swtype = 0;
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+ u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
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+@@ -959,11 +959,9 @@ static void bgmac_chip_reset(struct bgma
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+ et_swtype &= 0x0f;
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+ et_swtype <<= 4;
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+ sw_type = et_swtype;
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+- } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
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++ } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
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+ sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
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+- } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
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+- (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
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+- (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
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++ } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
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+ sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
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+ BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
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+ }
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+@@ -983,6 +981,11 @@ static void bgmac_chip_reset(struct bgma
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+ * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
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+ * be keps until taking MAC out of the reset.
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+ */
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++ if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
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++ cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
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++ else
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++ cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
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++
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+ bgmac_cmdcfg_maskset(bgmac,
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+ ~(BGMAC_CMDCFG_TE |
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+ BGMAC_CMDCFG_RE |
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+@@ -1000,13 +1003,13 @@ static void bgmac_chip_reset(struct bgma
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+ BGMAC_CMDCFG_PROM |
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+ BGMAC_CMDCFG_NLC |
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+ BGMAC_CMDCFG_CFE |
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+- BGMAC_CMDCFG_SR(core->id.rev),
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++ cmdcfg_sr,
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+ false);
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+ bgmac->mac_speed = SPEED_UNKNOWN;
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+ bgmac->mac_duplex = DUPLEX_UNKNOWN;
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+
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+ bgmac_clear_mib(bgmac);
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+- if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
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++ if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
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+ bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
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+ BCMA_GMAC_CMN_PC_MTE);
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+ else
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+@@ -1032,46 +1035,48 @@ static void bgmac_chip_intrs_off(struct
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+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
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+ static void bgmac_enable(struct bgmac *bgmac)
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+ {
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+- struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
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++ u32 cmdcfg_sr;
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+ u32 cmdcfg;
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+ u32 mode;
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+- u32 rxq_ctl;
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+- u32 fl_ctl;
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+- u16 bp_clk;
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+- u8 mdp;
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++
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++ if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
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++ cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
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++ else
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++ cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
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+
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+ cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
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+ bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
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+- BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
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++ cmdcfg_sr, true);
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+ udelay(2);
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+ cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
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+ bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
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+
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+ mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
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+ BGMAC_DS_MM_SHIFT;
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+- if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
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++ if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
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+ bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
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+- if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
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++ if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST && mode == 2)
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+ bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
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+ BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
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+
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+- switch (ci->id) {
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+- case BCMA_CHIP_ID_BCM5357:
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+- case BCMA_CHIP_ID_BCM4749:
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+- case BCMA_CHIP_ID_BCM53572:
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+- case BCMA_CHIP_ID_BCM4716:
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+- case BCMA_CHIP_ID_BCM47162:
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+- fl_ctl = 0x03cb04cb;
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+- if (ci->id == BCMA_CHIP_ID_BCM5357 ||
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+- ci->id == BCMA_CHIP_ID_BCM4749 ||
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+- ci->id == BCMA_CHIP_ID_BCM53572)
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++ if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
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++ BGMAC_FEAT_FLW_CTRL2)) {
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++ u32 fl_ctl;
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++
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++ if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
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+ fl_ctl = 0x2300e1;
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++ else
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++ fl_ctl = 0x03cb04cb;
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++
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+ bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
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+ bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
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+- break;
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+ }
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+
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+- if (!bgmac_is_bcm4707_family(bgmac)) {
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++ if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
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++ u32 rxq_ctl;
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++ u16 bp_clk;
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++ u8 mdp;
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++
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+ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
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+ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
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+ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
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+@@ -1603,6 +1608,74 @@ static int bgmac_probe(struct bcma_devic
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+ if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
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+ dev_warn(bgmac->dev, "Support for ADMtek ethernet switch not implemented\n");
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+
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++ /* Feature Flags */
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++ switch (core->bus->chipinfo.id) {
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++ case BCMA_CHIP_ID_BCM5357:
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++ bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
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++ bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
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++ bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL1;
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++ bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_PHY;
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++ if (core->bus->chipinfo.pkg == BCMA_PKG_ID_BCM47186) {
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++ bgmac->feature_flags |= BGMAC_FEAT_IOST_ATTACHED;
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++ bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_RGMII;
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++ }
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++ if (core->bus->chipinfo.pkg == BCMA_PKG_ID_BCM5358)
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++ bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_EPHYRMII;
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++ break;
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++ case BCMA_CHIP_ID_BCM53572:
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++ bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
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++ bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
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++ bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL1;
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++ bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_PHY;
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++ if (core->bus->chipinfo.pkg == BCMA_PKG_ID_BCM47188) {
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++ bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_RGMII;
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++ bgmac->feature_flags |= BGMAC_FEAT_IOST_ATTACHED;
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++ }
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++ break;
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++ case BCMA_CHIP_ID_BCM4749:
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++ bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
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++ bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
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++ bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL1;
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++ bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_PHY;
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++ if (core->bus->chipinfo.pkg == 10) {
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++ bgmac->feature_flags |= BGMAC_FEAT_SW_TYPE_RGMII;
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++ bgmac->feature_flags |= BGMAC_FEAT_IOST_ATTACHED;
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++ }
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++ break;
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++ case BCMA_CHIP_ID_BCM4716:
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++ bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
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++ /* fallthrough */
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++ case BCMA_CHIP_ID_BCM47162:
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++ bgmac->feature_flags |= BGMAC_FEAT_FLW_CTRL2;
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++ bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
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++ break;
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++ /* bcm4707_family */
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++ case BCMA_CHIP_ID_BCM4707:
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|
++ case BCMA_CHIP_ID_BCM47094:
|
|
|
++ case BCMA_CHIP_ID_BCM53018:
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_NO_RESET;
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;
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|
|
++ break;
|
|
|
++ default:
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_SET_RXQ_CLK;
|
|
|
++ }
|
|
|
++
|
|
|
++ if (!bgmac_is_bcm4707_family(bgmac) && core->id.rev > 2)
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_MISC_PLL_REQ;
|
|
|
++
|
|
|
++ if (core->id.id == BCMA_CORE_4706_MAC_GBIT) {
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_CMN_PHY_CTL;
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_NO_CLR_MIB;
|
|
|
++ }
|
|
|
++
|
|
|
++ if (core->id.rev >= 4) {
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_CMDCFG_SR_REV4;
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_TX_MASK_SETUP;
|
|
|
++ bgmac->feature_flags |= BGMAC_FEAT_RX_MASK_SETUP;
|
|
|
++ }
|
|
|
++
|
|
|
+ netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
|
|
|
+
|
|
|
+ if (!bgmac_is_bcm4707_family(bgmac)) {
|
|
|
+--- a/drivers/net/ethernet/broadcom/bgmac.h
|
|
|
++++ b/drivers/net/ethernet/broadcom/bgmac.h
|
|
|
+@@ -190,7 +190,6 @@
|
|
|
+ #define BGMAC_CMDCFG_HD_SHIFT 10
|
|
|
+ #define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */
|
|
|
+ #define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */
|
|
|
+-#define BGMAC_CMDCFG_SR(rev) ((rev >= 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
|
|
|
+ #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
|
|
|
+ #define BGMAC_CMDCFG_AE 0x00400000
|
|
|
+ #define BGMAC_CMDCFG_CFE 0x00800000
|
|
|
+@@ -376,6 +375,24 @@
|
|
|
+
|
|
|
+ #define ETHER_MAX_LEN 1518
|
|
|
+
|
|
|
++/* Feature Flags */
|
|
|
++#define BGMAC_FEAT_TX_MASK_SETUP BIT(0)
|
|
|
++#define BGMAC_FEAT_RX_MASK_SETUP BIT(1)
|
|
|
++#define BGMAC_FEAT_IOST_ATTACHED BIT(2)
|
|
|
++#define BGMAC_FEAT_NO_RESET BIT(3)
|
|
|
++#define BGMAC_FEAT_MISC_PLL_REQ BIT(4)
|
|
|
++#define BGMAC_FEAT_SW_TYPE_PHY BIT(5)
|
|
|
++#define BGMAC_FEAT_SW_TYPE_EPHYRMII BIT(6)
|
|
|
++#define BGMAC_FEAT_SW_TYPE_RGMII BIT(7)
|
|
|
++#define BGMAC_FEAT_CMN_PHY_CTL BIT(8)
|
|
|
++#define BGMAC_FEAT_FLW_CTRL1 BIT(9)
|
|
|
++#define BGMAC_FEAT_FLW_CTRL2 BIT(10)
|
|
|
++#define BGMAC_FEAT_SET_RXQ_CLK BIT(11)
|
|
|
++#define BGMAC_FEAT_CLKCTLST BIT(12)
|
|
|
++#define BGMAC_FEAT_NO_CLR_MIB BIT(13)
|
|
|
++#define BGMAC_FEAT_FORCE_SPEED_2500 BIT(14)
|
|
|
++#define BGMAC_FEAT_CMDCFG_SR_REV4 BIT(15)
|
|
|
++
|
|
|
+ struct bgmac_slot_info {
|
|
|
+ union {
|
|
|
+ struct sk_buff *skb;
|
|
|
+@@ -430,6 +447,8 @@ struct bgmac {
|
|
|
+
|
|
|
+ struct device *dev;
|
|
|
+ struct device *dma_dev;
|
|
|
++ u32 feature_flags;
|
|
|
++
|
|
|
+ struct net_device *net_dev;
|
|
|
+ struct napi_struct napi;
|
|
|
+ struct mii_bus *mii_bus;
|