uboot-rockchip: Update to 2023.07.02

* Removed swig hacks and prebuilt of-platdata
* Removed upstreamed patches
  - 101-rock64pro-disable-CONFIG_USE_PREBOOT.patch
  - 102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch
* Reordered patches

* Introduced new dependencies check
* Overrided default PATH to avoid race condition
    (host python3 vs hostpkg python3)
* Switched to use UBOOT_CUSTOMIZE_CONFIG for config update

Signed-off-by: Tianling Shen <[email protected]>

package/boot/uboot-rockchip/Makefile

@@ -5,13 +5,15 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
-PKG_VERSION:=2021.07
-PKG_RELEASE:=5
-
-PKG_HASH:=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e
+PKG_VERSION:=2023.07.02
+PKG_RELEASE:=1
+PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
 
 PKG_MAINTAINER:=Tobias Maedel <[email protected]>
 
+UBOOT_USE_BINMAN:=1
+UBOOT_USE_INTREE_DTC:=1
+
 include $(INCLUDE_DIR)/u-boot.mk
 include $(INCLUDE_DIR)/package.mk
 
@@ -28,7 +30,6 @@ define U-Boot/rk3328/Default
   BUILD_SUBTARGET:=armv8
   DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3328
   ATF:=rk3328_bl31.elf
-  OF_PLATDATA:=$(1)
 endef
 
 define U-Boot/nanopi-r2c-rk3328
@@ -131,24 +132,15 @@ UBOOT_TARGETS := \
 
 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
 
+UBOOT_CUSTOMIZE_CONFIG := \
+	--disable SPL_FIT_SIGNATURE \
+	--disable TOOLS_MKEFICAPSULE \
+	--set-str MKIMAGE_DTC_PATH $(PKG_BUILD_DIR)/scripts/dtc/dtc
+
 UBOOT_MAKE_FLAGS += \
+  PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \
   BL31=$(STAGING_DIR_IMAGE)/$(ATF)
 
-define Build/Configure
-	$(call Build/Configure/U-Boot)
-
-ifneq ($(OF_PLATDATA),)
-	mkdir -p $(PKG_BUILD_DIR)/tpl/dts
-	mkdir -p $(PKG_BUILD_DIR)/include/generated
-
-	$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c
-	$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h
-	$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h
-endif
-
-	$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
-endef
-
 define Build/InstallDev
 	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
 	$(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img

package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch

@@ -1,24 +0,0 @@
-From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001
-From: David Bauer <[email protected]>
-Date: Mon, 13 Jul 2020 23:37:37 +0200
-Subject: [PATCH] scripts: remove dependency on swig
-
-Don't build the libfdt tool, as it has a dependency on swig (which
-OpenWrt does not ship).
-
-This requires more hacks, as of-platdata generation does not work
-without it.
-
-Signed-off-by: David Bauer <[email protected]>
----
- scripts/dtc/Makefile | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/scripts/dtc/Makefile
-+++ b/scripts/dtc/Makefile
-@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src)
- # dependencies on generated files need to be listed explicitly
- $(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h
- 
--# Added for U-Boot
--subdir-$(CONFIG_PYLIBFDT) += pylibfdt

package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch

@@ -1,28 +0,0 @@
-From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001
-From: David Bauer <[email protected]>
-Date: Tue, 14 Jul 2020 22:44:22 +0200
-Subject: [PATCH] spl: remove dtoc of-pdata generation
-
-Remove the dtoc of-pdata generation. This generation is dependant on
-libpython-dev. As OpenWrt does not ship with this dependency, use
-pre-generated pdata files and remove the generation from the
-build-process.
-
-This only affects RK3328 boards.
-
-Signed-off-by: David Bauer <[email protected]>
----
- scripts/Makefile.spl | 6 ------
- 1 file changed, 6 deletions(-)
-
---- a/scripts/Makefile.spl
-+++ b/scripts/Makefile.spl
-@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c)
- 	@# of OF_PLATDATA_INST and this might change between builds. Leaving old
- 	@# ones around is confusing and it is possible that switching the
- 	@# setting again will use the old one instead of regenerating it.
--	@rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata)
--	$(call if_changed,dtoc)
- 
- ifdef CONFIG_SAMSUNG
- ifdef CONFIG_VAR_SIZE_SPL

package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch → package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch

@@ -1,4 +1,4 @@
-From ff312af37d5f263f181468639aab83f645d331f1 Mon Sep 17 00:00:00 2001
+From 89afb631d965292aaf433806d8224b53d9e74036 Mon Sep 17 00:00:00 2001
 From: Tianling Shen <[email protected]>
 Date: Sat, 20 May 2023 18:50:38 +0800
 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus
@@ -27,7 +27,7 @@ Signed-off-by: Tianling Shen <[email protected]>
 
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+@@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
  	rk3328-evb.dtb \
  	rk3328-nanopi-r2c.dtb \
  	rk3328-nanopi-r2s.dtb \
@@ -53,24 +53,24 @@ Signed-off-by: Tianling Shen <[email protected]>
 +};
 +
 +&gpio0 {
-+	u-boot,dm-spl;
++	bootph-pre-ram;
 +};
 +
 +&pinctrl {
-+	u-boot,dm-spl;
++	bootph-pre-ram;
 +};
 +
-+&sdmmc0m1_gpio {
-+	u-boot,dm-spl;
++&sdmmc0m1_pin {
++	bootph-pre-ram;
 +};
 +
 +&pcfg_pull_up_4ma {
-+	u-boot,dm-spl;
++	bootph-pre-ram;
 +};
 +
 +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
 +&vcc_sd {
-+	u-boot,dm-spl;
++	bootph-pre-ram;
 +};
 +
 +&gmac2io {
@@ -81,12 +81,12 @@ Signed-off-by: Tianling Shen <[email protected]>
 +
 +&spi0 {
 +	spi_flash: spiflash@0 {
-+		u-boot,dm-pre-reloc;
++		bootph-all;
 +	};
 +};
 --- /dev/null
 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
-@@ -0,0 +1,359 @@
+@@ -0,0 +1,373 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
 + * Based on rk3328-nanopi-r2s.dts, which is:
@@ -104,6 +104,7 @@ Signed-off-by: Tianling Shen <[email protected]>
 +	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
 +
 +	aliases {
++		ethernet1 = &rtl8153;
 +		mmc0 = &sdmmc;
 +	};
 +
@@ -146,7 +147,7 @@ Signed-off-by: Tianling Shen <[email protected]>
 +	vcc_sd: sdmmc-regulator {
 +		compatible = "regulator-fixed";
 +		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
-+		pinctrl-0 = <&sdmmc0m1_gpio>;
++		pinctrl-0 = <&sdmmc0m1_pin>;
 +		pinctrl-names = "default";
 +		regulator-name = "vcc_sd";
 +		regulator-boot-on;
@@ -439,6 +440,19 @@ Signed-off-by: Tianling Shen <[email protected]>
 +	status = "okay";
 +};
 +
++&usbdrd3 {
++	dr_mode = "host";
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	/* Second port is for USB 3.0 */
++	rtl8153: device@2 {
++		compatible = "usbbda,8153";
++		reg = <2>;
++	};
++};
++
 +&usb_host0_ehci {
 +	status = "okay";
 +};
@@ -463,39 +477,52 @@ Signed-off-by: Tianling Shen <[email protected]>
  M:      Chen-Yu Tsai <[email protected]>
 --- /dev/null
 +++ b/configs/orangepi-r1-plus-rk3328_defconfig
-@@ -0,0 +1,98 @@
+@@ -0,0 +1,114 @@
 +CONFIG_ARM=y
++CONFIG_SKIP_LOWLEVEL_INIT=y
++CONFIG_COUNTER_FREQUENCY=24000000
 +CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SYS_TEXT_BASE=0x00200000
-+CONFIG_SPL_GPIO_SUPPORT=y
++CONFIG_TEXT_BASE=0x00200000
++CONFIG_SPL_GPIO=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
 +CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
++CONFIG_DM_RESET=y
 +CONFIG_ROCKCHIP_RK3328=y
 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
-+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
++CONFIG_SPL_DRIVERS_MISC=y
 +CONFIG_SPL_STACK_R_ADDR=0x600000
-+CONFIG_NR_DRAM_BANKS=1
++CONFIG_SPL_STACK=0x400000
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 +CONFIG_DEBUG_UART_BASE=0xFF130000
 +CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_SYSINFO=y
++CONFIG_SYS_LOAD_ADDR=0x800800
 +CONFIG_DEBUG_UART=y
-+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 +CONFIG_FIT=y
 +CONFIG_FIT_VERBOSE=y
 +CONFIG_SPL_LOAD_FIT=y
 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
-+CONFIG_MISC_INIT_R=y
 +# CONFIG_DISPLAY_CPUINFO is not set
 +CONFIG_DISPLAY_BOARDINFO_LATE=y
++CONFIG_MISC_INIT_R=y
++CONFIG_SPL_MAX_SIZE=0x40000
++CONFIG_SPL_PAD_TO=0x7f8000
++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
++CONFIG_SPL_BSS_START_ADDR=0x2000000
++CONFIG_SPL_BSS_MAX_SIZE=0x2000
 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 +CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_I2C_SUPPORT=y
-+CONFIG_SPL_POWER_SUPPORT=y
++CONFIG_SPL_I2C=y
++CONFIG_SPL_POWER=y
 +CONFIG_SPL_ATF=y
 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 +CONFIG_CMD_BOOTZ=y
 +CONFIG_CMD_GPT=y
 +CONFIG_CMD_MMC=y
@@ -504,11 +531,11 @@ Signed-off-by: Tianling Shen <[email protected]>
 +CONFIG_CMD_TIME=y
 +CONFIG_SPL_OF_CONTROL=y
 +CONFIG_TPL_OF_CONTROL=y
-+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 +CONFIG_TPL_OF_PLATDATA=y
 +CONFIG_ENV_IS_IN_MMC=y
 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_SYS_MMC_ENV_DEV=1
 +CONFIG_NET_RANDOM_ETHADDR=y
 +CONFIG_TPL_DM=y
 +CONFIG_REGMAP=y
@@ -526,13 +553,14 @@ Signed-off-by: Tianling Shen <[email protected]>
 +CONFIG_MMC_DW=y
 +CONFIG_MMC_DW_ROCKCHIP=y
 +CONFIG_SF_DEFAULT_SPEED=20000000
-+CONFIG_DM_ETH=y
++CONFIG_SPI_FLASH_GIGADEVICE=y
 +CONFIG_ETH_DESIGNWARE=y
 +CONFIG_GMAC_ROCKCHIP=y
 +CONFIG_PINCTRL=y
 +CONFIG_SPL_PINCTRL=y
 +CONFIG_DM_PMIC=y
 +CONFIG_PMIC_RK8XX=y
++CONFIG_SPL_PMIC_RK8XX=y
 +CONFIG_SPL_DM_REGULATOR=y
 +CONFIG_REGULATOR_PWM=y
 +CONFIG_DM_REGULATOR_FIXED=y
@@ -542,9 +570,11 @@ Signed-off-by: Tianling Shen <[email protected]>
 +CONFIG_RAM=y
 +CONFIG_SPL_RAM=y
 +CONFIG_TPL_RAM=y
-+CONFIG_DM_RESET=y
 +CONFIG_BAUDRATE=1500000
 +CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYS_NS16550_MEM32=y
++CONFIG_ROCKCHIP_SPI=y
++CONFIG_SYSINFO=y
 +CONFIG_SYSRESET=y
 +# CONFIG_TPL_SYSRESET is not set
 +CONFIG_USB=y

package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch

@@ -1,27 +0,0 @@
-From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001
-From: Marty Jones <[email protected]>
-Date: Sun, 17 Jan 2021 15:26:09 -0500
-Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT
-
-On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3
-CONFIG_USE_PREBOOT was enabled on the RockPro64.
-
-When the board is booting, U-Boot hangs as soon as it disables the USB
-controller. This is a workaround until a final solution is deployed
-upstream.
-
-Signed-off-by: Marty Jones <[email protected]>
----
- configs/rockpro64-rk3399_defconfig | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/configs/rockpro64-rk3399_defconfig
-+++ b/configs/rockpro64-rk3399_defconfig
-@@ -12,7 +12,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
- CONFIG_SPL_SPI_FLASH_SUPPORT=y
- CONFIG_SPL_SPI_SUPPORT=y
- CONFIG_DEBUG_UART=y
--CONFIG_USE_PREBOOT=y
- CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
- CONFIG_DISPLAY_BOARDINFO_LATE=y
- CONFIG_MISC_INIT_R=y

package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch → package/boot/uboot-rockchip/patches/101-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch

@@ -1,4 +1,4 @@
-From 7a9326a96098bc63d2b60538f657c3a533415276 Mon Sep 17 00:00:00 2001
+From 408fd4570c0f1e6b1fe3722998394651144f2a29 Mon Sep 17 00:00:00 2001
 From: Tianling Shen <[email protected]>
 Date: Sat, 20 May 2023 18:52:14 +0800
 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS
@@ -10,7 +10,6 @@ changed from DDR4 to LPDDR3.
 The device tree is taken from kernel v6.4-rc1.
 
 Signed-off-by: Tianling Shen <[email protected]>
-
 ---
  arch/arm/dts/Makefile                         |   1 +
  .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi   |  46 +++++++
@@ -24,7 +23,7 @@ Signed-off-by: Tianling Shen <[email protected]>
 
 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+@@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
  	rk3328-nanopi-r2c.dtb \
  	rk3328-nanopi-r2s.dtb \
  	rk3328-orangepi-r1-plus.dtb \
@@ -50,24 +49,24 @@ Signed-off-by: Tianling Shen <[email protected]>
 +};
 +
 +&gpio0 {
-+	u-boot,dm-spl;
++	bootph-pre-ram;
 +};
 +
 +&pinctrl {
-+	u-boot,dm-spl;
++	bootph-pre-ram;
 +};
 +
-+&sdmmc0m1_gpio {
-+	u-boot,dm-spl;
++&sdmmc0m1_pin {
++	bootph-pre-ram;
 +};
 +
 +&pcfg_pull_up_4ma {
-+	u-boot,dm-spl;
++	bootph-pre-ram;
 +};
 +
 +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
 +&vcc_sd {
-+	u-boot,dm-spl;
++	bootph-pre-ram;
 +};
 +
 +&gmac2io {
@@ -78,7 +77,7 @@ Signed-off-by: Tianling Shen <[email protected]>
 +
 +&spi0 {
 +	spi_flash: spiflash@0 {
-+		u-boot,dm-pre-reloc;
++		bootph-all;
 +	};
 +};
 --- /dev/null
@@ -141,39 +140,52 @@ Signed-off-by: Tianling Shen <[email protected]>
  M:      Chen-Yu Tsai <[email protected]>
 --- /dev/null
 +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
-@@ -0,0 +1,98 @@
+@@ -0,0 +1,114 @@
 +CONFIG_ARM=y
++CONFIG_SKIP_LOWLEVEL_INIT=y
++CONFIG_COUNTER_FREQUENCY=24000000
 +CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SYS_TEXT_BASE=0x00200000
-+CONFIG_SPL_GPIO_SUPPORT=y
++CONFIG_TEXT_BASE=0x00200000
++CONFIG_SPL_GPIO=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
 +CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
++CONFIG_DM_RESET=y
 +CONFIG_ROCKCHIP_RK3328=y
 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
-+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
++CONFIG_SPL_DRIVERS_MISC=y
 +CONFIG_SPL_STACK_R_ADDR=0x600000
-+CONFIG_NR_DRAM_BANKS=1
++CONFIG_SPL_STACK=0x400000
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 +CONFIG_DEBUG_UART_BASE=0xFF130000
 +CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_SYSINFO=y
++CONFIG_SYS_LOAD_ADDR=0x800800
 +CONFIG_DEBUG_UART=y
-+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 +CONFIG_FIT=y
 +CONFIG_FIT_VERBOSE=y
 +CONFIG_SPL_LOAD_FIT=y
 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
-+CONFIG_MISC_INIT_R=y
 +# CONFIG_DISPLAY_CPUINFO is not set
 +CONFIG_DISPLAY_BOARDINFO_LATE=y
++CONFIG_MISC_INIT_R=y
++CONFIG_SPL_MAX_SIZE=0x40000
++CONFIG_SPL_PAD_TO=0x7f8000
++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
++CONFIG_SPL_BSS_START_ADDR=0x2000000
++CONFIG_SPL_BSS_MAX_SIZE=0x2000
 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 +CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_I2C_SUPPORT=y
-+CONFIG_SPL_POWER_SUPPORT=y
++CONFIG_SPL_I2C=y
++CONFIG_SPL_POWER=y
 +CONFIG_SPL_ATF=y
 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 +CONFIG_CMD_BOOTZ=y
 +CONFIG_CMD_GPT=y
 +CONFIG_CMD_MMC=y
@@ -182,11 +194,11 @@ Signed-off-by: Tianling Shen <[email protected]>
 +CONFIG_CMD_TIME=y
 +CONFIG_SPL_OF_CONTROL=y
 +CONFIG_TPL_OF_CONTROL=y
-+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 +CONFIG_TPL_OF_PLATDATA=y
 +CONFIG_ENV_IS_IN_MMC=y
 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_SYS_MMC_ENV_DEV=1
 +CONFIG_NET_RANDOM_ETHADDR=y
 +CONFIG_TPL_DM=y
 +CONFIG_REGMAP=y
@@ -204,13 +216,14 @@ Signed-off-by: Tianling Shen <[email protected]>
 +CONFIG_MMC_DW=y
 +CONFIG_MMC_DW_ROCKCHIP=y
 +CONFIG_SF_DEFAULT_SPEED=20000000
-+CONFIG_DM_ETH=y
++CONFIG_SPI_FLASH_GIGADEVICE=y
 +CONFIG_ETH_DESIGNWARE=y
 +CONFIG_GMAC_ROCKCHIP=y
 +CONFIG_PINCTRL=y
 +CONFIG_SPL_PINCTRL=y
 +CONFIG_DM_PMIC=y
 +CONFIG_PMIC_RK8XX=y
++CONFIG_SPL_PMIC_RK8XX=y
 +CONFIG_SPL_DM_REGULATOR=y
 +CONFIG_REGULATOR_PWM=y
 +CONFIG_DM_REGULATOR_FIXED=y
@@ -220,9 +233,11 @@ Signed-off-by: Tianling Shen <[email protected]>
 +CONFIG_RAM=y
 +CONFIG_SPL_RAM=y
 +CONFIG_TPL_RAM=y
-+CONFIG_DM_RESET=y
 +CONFIG_BAUDRATE=1500000
 +CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYS_NS16550_MEM32=y
++CONFIG_ROCKCHIP_SPI=y
++CONFIG_SYSINFO=y
 +CONFIG_SYSRESET=y
 +# CONFIG_TPL_SYSRESET is not set
 +CONFIG_USB=y

package/boot/uboot-rockchip/patches/102-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R2C.patch

@@ -1,199 +0,0 @@
-From 7000a609473ffe14d32c656cdd0ff3ca0d3ecbd7 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <[email protected]>
-Date: Tue, 11 Apr 2023 18:14:49 +0800
-Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2C
-
-The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
-chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
-
-The device tree is taken from the kernel linux-next branch:
-https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9
-
-Signed-off-by: Tianling Shen <[email protected]>
-Reviewed-by: Kever Yang <[email protected]>
----
- arch/arm/dts/Makefile                      |   1 +
- arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi |   3 +
- arch/arm/dts/rk3328-nanopi-r2c.dts         |  40 ++++++++
- board/rockchip/evb_rk3328/MAINTAINERS      |   6 ++
- configs/nanopi-r2c-rk3328_defconfig        | 112 +++++++++++++++++++++
- 5 files changed, 162 insertions(+)
- create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
- create mode 100644 arch/arm/dts/rk3328-nanopi-r2c.dts
- create mode 100644 configs/nanopi-r2c-rk3328_defconfig
-
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
- 
- dtb-$(CONFIG_ROCKCHIP_RK3328) += \
- 	rk3328-evb.dtb \
-+	rk3328-nanopi-r2c.dtb \
- 	rk3328-nanopi-r2s.dtb \
- 	rk3328-roc-cc.dtb \
- 	rk3328-rock64.dtb \
---- /dev/null
-+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
-@@ -0,0 +1,3 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later
-+
-+#include "rk3328-nanopi-r2s-u-boot.dtsi"
---- /dev/null
-+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts
-@@ -0,0 +1,40 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2021-2023 Tianling Shen <[email protected]>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+	model = "FriendlyElec NanoPi R2C";
-+	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+	phy-handle = <&yt8521s>;
-+	tx_delay = <0x22>;
-+	rx_delay = <0x12>;
-+
-+	mdio {
-+		/delete-node/ ethernet-phy@1;
-+
-+		yt8521s: ethernet-phy@3 {
-+			compatible = "ethernet-phy-ieee802.3-c22";
-+			reg = <3>;
-+
-+			motorcomm,clk-out-frequency-hz = <125000000>;
-+			motorcomm,keep-pll-enabled;
-+			motorcomm,auto-sleep-disabled;
-+
-+			pinctrl-0 = <&eth_phy_reset_pin>;
-+			pinctrl-names = "default";
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <50000>;
-+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+};
---- a/board/rockchip/evb_rk3328/MAINTAINERS
-+++ b/board/rockchip/evb_rk3328/MAINTAINERS
-@@ -5,6 +5,12 @@ F:      board/rockchip/evb_rk3328
- F:      include/configs/evb_rk3328.h
- F:      configs/evb-rk3328_defconfig
- 
-+NANOPI-R2C-RK3328
-+M:      Tianling Shen <[email protected]>
-+S:      Maintained
-+F:      configs/nanopi-r2c-rk3328_defconfig
-+F:      arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
-+
- NANOPI-R2S-RK3328
- M:      David Bauer <[email protected]>
- S:      Maintained
---- /dev/null
-+++ b/configs/nanopi-r2c-rk3328_defconfig
-@@ -0,0 +1,98 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SYS_TEXT_BASE=0x00200000
-+CONFIG_SPL_GPIO_SUPPORT=y
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_ENV_OFFSET=0x3F8000
-+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
-+CONFIG_ROCKCHIP_RK3328=y
-+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-+CONFIG_TPL_LIBCOMMON_SUPPORT=y
-+CONFIG_TPL_LIBGENERIC_SUPPORT=y
-+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-+CONFIG_SPL_STACK_R_ADDR=0x600000
-+CONFIG_DEBUG_UART_BASE=0xFF130000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_DEBUG_UART=y
-+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-+# CONFIG_ANDROID_BOOT_IMAGE is not set
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_SPL_LOAD_FIT=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_DISPLAY_BOARDINFO_LATE=y
-+CONFIG_MISC_INIT_R=y
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
-+CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_I2C_SUPPORT=y
-+CONFIG_SPL_POWER_SUPPORT=y
-+CONFIG_SPL_ATF=y
-+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-+CONFIG_CMD_BOOTZ=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_USB=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_TIME=y
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_TPL_OF_CONTROL=y
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_TPL_OF_PLATDATA=y
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_TPL_DM=y
-+CONFIG_REGMAP=y
-+CONFIG_SPL_REGMAP=y
-+CONFIG_TPL_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_SPL_SYSCON=y
-+CONFIG_TPL_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_SPL_CLK=y
-+CONFIG_FASTBOOT_BUF_ADDR=0x800800
-+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_SPEED=20000000
-+CONFIG_DM_ETH=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_GMAC_ROCKCHIP=y
-+CONFIG_PINCTRL=y
-+CONFIG_SPL_PINCTRL=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_SPL_DM_REGULATOR=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_DM_REGULATOR_FIXED=y
-+CONFIG_SPL_DM_REGULATOR_FIXED=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_RAM=y
-+CONFIG_SPL_RAM=y
-+CONFIG_TPL_RAM=y
-+CONFIG_DM_RESET=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYSINFO=y
-+CONFIG_SYSRESET=y
-+# CONFIG_TPL_SYSRESET is not set
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_DWC3=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_GENERIC=y
-+CONFIG_USB_DWC2=y
-+CONFIG_USB_DWC3=y
-+# CONFIG_USB_DWC3_GADGET is not set
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DWC2_OTG=y
-+CONFIG_SPL_TINY_MEMSET=y
-+CONFIG_TPL_TINY_MEMSET=y
-+CONFIG_ERRNO_STR=y

package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-decl.h

@@ -1,23 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares externs for all device/uclass instances.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <dm/device-internal.h>
-#include <dm/uclass-internal.h>
-
-/* driver declarations - these allow DM_DRIVER_GET() to be used */
-extern U_BOOT_DRIVER(rockchip_rk3328_cru);
-extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(ns16550_serial);
-extern U_BOOT_DRIVER(rockchip_rk3328_grf);
-
-/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
-extern UCLASS_DRIVER(clk);
-extern UCLASS_DRIVER(mmc);
-extern UCLASS_DRIVER(ram);
-extern UCLASS_DRIVER(serial);
-extern UCLASS_DRIVER(syscon);

package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-plat.c

@@ -1,155 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares the U_BOOT_DRIVER() records and platform data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-/* Allow use of U_BOOT_DRVINFO() in this file */
-#define DT_PLAT_C
-
-#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
-/*
- * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
- *
- * idx  driver_info          driver
- * ---  -------------------- --------------------
- *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
- *   1: dmc                  rockchip_rk3328_dmc
- *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
- *   3: serial_at_ff130000   ns16550_serial
- *   4: syscon_at_ff100000   rockchip_rk3328_grf
- * ---  -------------------- --------------------
- */
-
-/*
- * Node /clock-controller@ff440000 index 0
- * driver rockchip_rk3328_cru parent None
- */
-static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
-	.reg			= {0xff440000, 0x1000},
-	.rockchip_grf		= 0x3a,
-};
-U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
-	.name		= "rockchip_rk3328_cru",
-	.plat		= &dtv_clock_controller_at_ff440000,
-	.plat_size	= sizeof(dtv_clock_controller_at_ff440000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /dmc index 1
- * driver rockchip_rk3328_dmc parent None
- */
-static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
-	.reg			= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
-		0xff720000, 0x1000, 0xff798000, 0x1000},
-	.rockchip_sdram_params	= {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
-		0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
-		0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
-		0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
-		0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
-		0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
-		0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
-		0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
-		0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
-		0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
-		0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
-		0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
-		0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
-		0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
-		0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
-		0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
-		0x77, 0x77, 0x79, 0x9},
-};
-U_BOOT_DRVINFO(dmc) = {
-	.name		= "rockchip_rk3328_dmc",
-	.plat		= &dtv_dmc,
-	.plat_size	= sizeof(dtv_dmc),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff500000 index 2
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
-	.bus_width		= 0x4,
-	.cap_sd_highspeed	= true,
-	.clocks			= {
-			{0, {317}},
-			{0, {33}},
-			{0, {74}},
-			{0, {78}},},
-	.disable_wp		= true,
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xc, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.pinctrl_0		= {0x47, 0x48, 0x49, 0x4a},
-	.pinctrl_names		= "default",
-	.reg			= {0xff500000, 0x4000},
-	.sd_uhs_sdr104		= true,
-	.sd_uhs_sdr12		= true,
-	.sd_uhs_sdr25		= true,
-	.sd_uhs_sdr50		= true,
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x4b,
-	.vqmmc_supply		= 0x1e,
-};
-U_BOOT_DRVINFO(mmc_at_ff500000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff500000,
-	.plat_size	= sizeof(dtv_mmc_at_ff500000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /serial@ff130000 index 3
- * driver ns16550_serial parent None
- */
-static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
-	.clock_frequency	= 0x16e3600,
-	.clocks			= {
-			{0, {40}},
-			{0, {212}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x6, 0x10, 0x7},
-	.interrupts		= {0x0, 0x39, 0x4},
-	.pinctrl_0		= 0x26,
-	.pinctrl_names		= "default",
-	.reg			= {0xff130000, 0x100},
-	.reg_io_width		= 0x4,
-	.reg_shift		= 0x2,
-};
-U_BOOT_DRVINFO(serial_at_ff130000) = {
-	.name		= "ns16550_serial",
-	.plat		= &dtv_serial_at_ff130000,
-	.plat_size	= sizeof(dtv_serial_at_ff130000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /syscon@ff100000 index 4
- * driver rockchip_rk3328_grf parent None
- */
-static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
-	.reg			= {0xff100000, 0x1000},
-};
-U_BOOT_DRVINFO(syscon_at_ff100000) = {
-	.name		= "rockchip_rk3328_grf",
-	.plat		= &dtv_syscon_at_ff100000,
-	.plat_size	= sizeof(dtv_syscon_at_ff100000),
-	.parent_idx	= -1,
-};
-

package/boot/uboot-rockchip/src/of-platdata/nanopi-r2c-rk3328/dt-structs-gen.h

@@ -1,51 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Defines the structs used to hold devicetree data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <stdbool.h>
-#include <linux/libfdt.h>
-struct dtd_ns16550_serial {
-	fdt32_t		clock_frequency;
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0;
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	fdt32_t		reg_io_width;
-	fdt32_t		reg_shift;
-};
-struct dtd_rockchip_rk3288_dw_mshc {
-	fdt32_t		bus_width;
-	bool		cap_sd_highspeed;
-	struct phandle_1_arg clocks[4];
-	bool		disable_wp;
-	fdt32_t		fifo_depth;
-	fdt32_t		interrupts[3];
-	fdt32_t		max_frequency;
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	bool		sd_uhs_sdr104;
-	bool		sd_uhs_sdr12;
-	bool		sd_uhs_sdr25;
-	bool		sd_uhs_sdr50;
-	bool		u_boot_spl_fifo_mode;
-	fdt32_t		vmmc_supply;
-	fdt32_t		vqmmc_supply;
-};
-struct dtd_rockchip_rk3328_cru {
-	fdt64_t		reg[2];
-	fdt32_t		rockchip_grf;
-};
-struct dtd_rockchip_rk3328_dmc {
-	fdt64_t		reg[12];
-	fdt32_t		rockchip_sdram_params[196];
-};
-struct dtd_rockchip_rk3328_grf {
-	fdt64_t		reg[2];
-};

package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h

@@ -1,23 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares externs for all device/uclass instances.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <dm/device-internal.h>
-#include <dm/uclass-internal.h>
-
-/* driver declarations - these allow DM_DRIVER_GET() to be used */
-extern U_BOOT_DRIVER(rockchip_rk3328_cru);
-extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(ns16550_serial);
-extern U_BOOT_DRIVER(rockchip_rk3328_grf);
-
-/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
-extern UCLASS_DRIVER(clk);
-extern UCLASS_DRIVER(mmc);
-extern UCLASS_DRIVER(ram);
-extern UCLASS_DRIVER(serial);
-extern UCLASS_DRIVER(syscon);

package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c

@@ -1,155 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares the U_BOOT_DRIVER() records and platform data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-/* Allow use of U_BOOT_DRVINFO() in this file */
-#define DT_PLAT_C
-
-#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
-/*
- * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
- *
- * idx  driver_info          driver
- * ---  -------------------- --------------------
- *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
- *   1: dmc                  rockchip_rk3328_dmc
- *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
- *   3: serial_at_ff130000   ns16550_serial
- *   4: syscon_at_ff100000   rockchip_rk3328_grf
- * ---  -------------------- --------------------
- */
-
-/*
- * Node /clock-controller@ff440000 index 0
- * driver rockchip_rk3328_cru parent None
- */
-static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
-	.reg			= {0xff440000, 0x1000},
-	.rockchip_grf		= 0x3a,
-};
-U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
-	.name		= "rockchip_rk3328_cru",
-	.plat		= &dtv_clock_controller_at_ff440000,
-	.plat_size	= sizeof(dtv_clock_controller_at_ff440000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /dmc index 1
- * driver rockchip_rk3328_dmc parent None
- */
-static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
-	.reg			= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
-		0xff720000, 0x1000, 0xff798000, 0x1000},
-	.rockchip_sdram_params	= {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
-		0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
-		0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
-		0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
-		0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
-		0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
-		0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
-		0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
-		0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
-		0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
-		0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
-		0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
-		0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
-		0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
-		0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
-		0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
-		0x77, 0x77, 0x79, 0x9},
-};
-U_BOOT_DRVINFO(dmc) = {
-	.name		= "rockchip_rk3328_dmc",
-	.plat		= &dtv_dmc,
-	.plat_size	= sizeof(dtv_dmc),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff500000 index 2
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
-	.bus_width		= 0x4,
-	.cap_sd_highspeed	= true,
-	.clocks			= {
-			{0, {317}},
-			{0, {33}},
-			{0, {74}},
-			{0, {78}},},
-	.disable_wp		= true,
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xc, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.pinctrl_0		= {0x47, 0x48, 0x49, 0x4a},
-	.pinctrl_names		= "default",
-	.reg			= {0xff500000, 0x4000},
-	.sd_uhs_sdr104		= true,
-	.sd_uhs_sdr12		= true,
-	.sd_uhs_sdr25		= true,
-	.sd_uhs_sdr50		= true,
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x4b,
-	.vqmmc_supply		= 0x1e,
-};
-U_BOOT_DRVINFO(mmc_at_ff500000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff500000,
-	.plat_size	= sizeof(dtv_mmc_at_ff500000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /serial@ff130000 index 3
- * driver ns16550_serial parent None
- */
-static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
-	.clock_frequency	= 0x16e3600,
-	.clocks			= {
-			{0, {40}},
-			{0, {212}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x6, 0x10, 0x7},
-	.interrupts		= {0x0, 0x39, 0x4},
-	.pinctrl_0		= 0x26,
-	.pinctrl_names		= "default",
-	.reg			= {0xff130000, 0x100},
-	.reg_io_width		= 0x4,
-	.reg_shift		= 0x2,
-};
-U_BOOT_DRVINFO(serial_at_ff130000) = {
-	.name		= "ns16550_serial",
-	.plat		= &dtv_serial_at_ff130000,
-	.plat_size	= sizeof(dtv_serial_at_ff130000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /syscon@ff100000 index 4
- * driver rockchip_rk3328_grf parent None
- */
-static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
-	.reg			= {0xff100000, 0x1000},
-};
-U_BOOT_DRVINFO(syscon_at_ff100000) = {
-	.name		= "rockchip_rk3328_grf",
-	.plat		= &dtv_syscon_at_ff100000,
-	.plat_size	= sizeof(dtv_syscon_at_ff100000),
-	.parent_idx	= -1,
-};
-

package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h

@@ -1,51 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Defines the structs used to hold devicetree data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <stdbool.h>
-#include <linux/libfdt.h>
-struct dtd_ns16550_serial {
-	fdt32_t		clock_frequency;
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0;
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	fdt32_t		reg_io_width;
-	fdt32_t		reg_shift;
-};
-struct dtd_rockchip_rk3288_dw_mshc {
-	fdt32_t		bus_width;
-	bool		cap_sd_highspeed;
-	struct phandle_1_arg clocks[4];
-	bool		disable_wp;
-	fdt32_t		fifo_depth;
-	fdt32_t		interrupts[3];
-	fdt32_t		max_frequency;
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	bool		sd_uhs_sdr104;
-	bool		sd_uhs_sdr12;
-	bool		sd_uhs_sdr25;
-	bool		sd_uhs_sdr50;
-	bool		u_boot_spl_fifo_mode;
-	fdt32_t		vmmc_supply;
-	fdt32_t		vqmmc_supply;
-};
-struct dtd_rockchip_rk3328_cru {
-	fdt64_t		reg[2];
-	fdt32_t		rockchip_grf;
-};
-struct dtd_rockchip_rk3328_dmc {
-	fdt64_t		reg[12];
-	fdt32_t		rockchip_sdram_params[196];
-};
-struct dtd_rockchip_rk3328_grf {
-	fdt64_t		reg[2];
-};

package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h

@@ -1,24 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares externs for all device/uclass instances.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <dm/device-internal.h>
-#include <dm/uclass-internal.h>
-
-/* driver declarations - these allow DM_DRIVER_GET() to be used */
-extern U_BOOT_DRIVER(rockchip_rk3328_cru);
-extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(ns16550_serial);
-extern U_BOOT_DRIVER(rockchip_rk3328_spi);
-extern U_BOOT_DRIVER(rockchip_rk3328_grf);
-
-/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
-extern UCLASS_DRIVER(clk);
-extern UCLASS_DRIVER(mmc);
-extern UCLASS_DRIVER(ram);
-extern UCLASS_DRIVER(serial);
-extern UCLASS_DRIVER(syscon);

package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c

@@ -1,170 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares the U_BOOT_DRIVER() records and platform data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-/* Allow use of U_BOOT_DRVINFO() in this file */
-#define DT_PLAT_C
-
-#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
-/*
- * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
- *
- * idx  driver_info          driver
- * ---  -------------------- --------------------
- *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
- *   1: dmc                  rockchip_rk3328_dmc
- *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
- *   3: serial_at_ff130000   ns16550_serial
- *   4: spi_at_ff190000      rockchip_rk3328_spi
- *   5: syscon_at_ff100000   rockchip_rk3328_grf
- * ---  -------------------- --------------------
- */
-
-/*
- * Node /clock-controller@ff440000 index 0
- * driver rockchip_rk3328_cru parent None
- */
-static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
-	.reg			= {0xff440000, 0x1000},
-	.rockchip_grf		= 0x38,
-};
-U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
-	.name		= "rockchip_rk3328_cru",
-	.plat		= &dtv_clock_controller_at_ff440000,
-	.plat_size	= sizeof(dtv_clock_controller_at_ff440000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /dmc index 1
- * driver rockchip_rk3328_dmc parent None
- */
-static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
-	.reg			= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
-		0xff720000, 0x1000, 0xff798000, 0x1000},
-	.rockchip_sdram_params	= {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
-		0x10, 0x10, 0x0, 0x8c48a18a, 0x0, 0x21, 0x482, 0x15,
-		0x21a, 0xff, 0x14d, 0x6, 0x1, 0x0, 0x0, 0x0,
-		0x43041008, 0x64, 0x140023, 0xd0, 0x220002, 0xd4, 0x10000, 0xd8,
-		0x703, 0xdc, 0x830004, 0xe0, 0x10000, 0xe4, 0x70003, 0xf4,
-		0xf011f, 0x100, 0x6090b07, 0x104, 0x2020b, 0x108, 0x2030506, 0x10c,
-		0x505000, 0x110, 0x3020204, 0x114, 0x1010303, 0x118, 0x2020003, 0x120,
-		0x303, 0x138, 0x25, 0x180, 0x3c000f, 0x184, 0x900000, 0x190,
-		0x7020000, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0x900090c, 0x244,
-		0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
-		0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0x6, 0x2c,
-		0x0, 0x30, 0x3, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
-		0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
-		0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
-		0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
-		0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
-		0x77, 0x77, 0x79, 0x9},
-};
-U_BOOT_DRVINFO(dmc) = {
-	.name		= "rockchip_rk3328_dmc",
-	.plat		= &dtv_dmc,
-	.plat_size	= sizeof(dtv_dmc),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff500000 index 2
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
-	.bus_width		= 0x4,
-	.cap_sd_highspeed	= true,
-	.clocks			= {
-			{0, {317}},
-			{0, {33}},
-			{0, {74}},
-			{0, {78}},},
-	.disable_wp		= true,
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xc, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.pinctrl_0		= {0x45, 0x46, 0x47, 0x48},
-	.pinctrl_names		= "default",
-	.reg			= {0xff500000, 0x4000},
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x49,
-};
-U_BOOT_DRVINFO(mmc_at_ff500000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff500000,
-	.plat_size	= sizeof(dtv_mmc_at_ff500000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /serial@ff130000 index 3
- * driver ns16550_serial parent None
- */
-static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
-	.clock_frequency	= 0x16e3600,
-	.clocks			= {
-			{0, {40}},
-			{0, {212}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x6, 0x10, 0x7},
-	.interrupts		= {0x0, 0x39, 0x4},
-	.pinctrl_0		= 0x24,
-	.pinctrl_names		= "default",
-	.reg			= {0xff130000, 0x100},
-	.reg_io_width		= 0x4,
-	.reg_shift		= 0x2,
-};
-U_BOOT_DRVINFO(serial_at_ff130000) = {
-	.name		= "ns16550_serial",
-	.plat		= &dtv_serial_at_ff130000,
-	.plat_size	= sizeof(dtv_serial_at_ff130000),
-	.parent_idx	= -1,
-};
-
-/* Node /spi@ff190000 index 4 */
-static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
-	.clocks			= {
-			{0, {32}},
-			{0, {209}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x8, 0x10, 0x9},
-	.interrupts		= {0x0, 0x31, 0x4},
-	.pinctrl_0		= {0x2c, 0x2d, 0x2e, 0x2f},
-	.pinctrl_names		= "default",
-	.reg			= {0xff190000, 0x1000},
-};
-U_BOOT_DRVINFO(spi_at_ff190000) = {
-	.name		= "rockchip_rk3328_spi",
-	.plat		= &dtv_spi_at_ff190000,
-	.plat_size	= sizeof(dtv_spi_at_ff190000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /syscon@ff100000 index 5
- * driver rockchip_rk3328_grf parent None
- */
-static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
-	.reg			= {0xff100000, 0x1000},
-};
-U_BOOT_DRVINFO(syscon_at_ff100000) = {
-	.name		= "rockchip_rk3328_grf",
-	.plat		= &dtv_syscon_at_ff100000,
-	.plat_size	= sizeof(dtv_syscon_at_ff100000),
-	.parent_idx	= -1,
-};
-

package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h

@@ -1,55 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Defines the structs used to hold devicetree data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <stdbool.h>
-#include <linux/libfdt.h>
-struct dtd_ns16550_serial {
-	fdt32_t		clock_frequency;
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0;
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	fdt32_t		reg_io_width;
-	fdt32_t		reg_shift;
-};
-struct dtd_rockchip_rk3288_dw_mshc {
-	fdt32_t		bus_width;
-	bool		cap_sd_highspeed;
-	struct phandle_1_arg clocks[4];
-	bool		disable_wp;
-	fdt32_t		fifo_depth;
-	fdt32_t		interrupts[3];
-	fdt32_t		max_frequency;
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	bool		u_boot_spl_fifo_mode;
-	fdt32_t		vmmc_supply;
-};
-struct dtd_rockchip_rk3328_cru {
-	fdt64_t		reg[2];
-	fdt32_t		rockchip_grf;
-};
-struct dtd_rockchip_rk3328_dmc {
-	fdt64_t		reg[12];
-	fdt32_t		rockchip_sdram_params[196];
-};
-struct dtd_rockchip_rk3328_grf {
-	fdt64_t		reg[2];
-};
-struct dtd_rockchip_rk3328_spi {
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-};

package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h

@@ -1,24 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares externs for all device/uclass instances.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <dm/device-internal.h>
-#include <dm/uclass-internal.h>
-
-/* driver declarations - these allow DM_DRIVER_GET() to be used */
-extern U_BOOT_DRIVER(rockchip_rk3328_cru);
-extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(ns16550_serial);
-extern U_BOOT_DRIVER(rockchip_rk3328_spi);
-extern U_BOOT_DRIVER(rockchip_rk3328_grf);
-
-/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
-extern UCLASS_DRIVER(clk);
-extern UCLASS_DRIVER(mmc);
-extern UCLASS_DRIVER(ram);
-extern UCLASS_DRIVER(serial);
-extern UCLASS_DRIVER(syscon);

package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c

@@ -1,170 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares the U_BOOT_DRIVER() records and platform data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-/* Allow use of U_BOOT_DRVINFO() in this file */
-#define DT_PLAT_C
-
-#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
-/*
- * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
- *
- * idx  driver_info          driver
- * ---  -------------------- --------------------
- *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
- *   1: dmc                  rockchip_rk3328_dmc
- *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
- *   3: serial_at_ff130000   ns16550_serial
- *   4: spi_at_ff190000      rockchip_rk3328_spi
- *   5: syscon_at_ff100000   rockchip_rk3328_grf
- * ---  -------------------- --------------------
- */
-
-/*
- * Node /clock-controller@ff440000 index 0
- * driver rockchip_rk3328_cru parent None
- */
-static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
-	.reg			= {0xff440000, 0x1000},
-	.rockchip_grf		= 0x38,
-};
-U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
-	.name		= "rockchip_rk3328_cru",
-	.plat		= &dtv_clock_controller_at_ff440000,
-	.plat_size	= sizeof(dtv_clock_controller_at_ff440000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /dmc index 1
- * driver rockchip_rk3328_dmc parent None
- */
-static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
-	.reg			= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
-		0xff720000, 0x1000, 0xff798000, 0x1000},
-	.rockchip_sdram_params	= {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
-		0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
-		0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
-		0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
-		0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
-		0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
-		0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
-		0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
-		0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
-		0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
-		0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
-		0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
-		0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
-		0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
-		0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
-		0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
-		0x77, 0x77, 0x79, 0x9},
-};
-U_BOOT_DRVINFO(dmc) = {
-	.name		= "rockchip_rk3328_dmc",
-	.plat		= &dtv_dmc,
-	.plat_size	= sizeof(dtv_dmc),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff500000 index 2
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
-	.bus_width		= 0x4,
-	.cap_sd_highspeed	= true,
-	.clocks			= {
-			{0, {317}},
-			{0, {33}},
-			{0, {74}},
-			{0, {78}},},
-	.disable_wp		= true,
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xc, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.pinctrl_0		= {0x45, 0x46, 0x47, 0x48},
-	.pinctrl_names		= "default",
-	.reg			= {0xff500000, 0x4000},
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x49,
-};
-U_BOOT_DRVINFO(mmc_at_ff500000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff500000,
-	.plat_size	= sizeof(dtv_mmc_at_ff500000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /serial@ff130000 index 3
- * driver ns16550_serial parent None
- */
-static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
-	.clock_frequency	= 0x16e3600,
-	.clocks			= {
-			{0, {40}},
-			{0, {212}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x6, 0x10, 0x7},
-	.interrupts		= {0x0, 0x39, 0x4},
-	.pinctrl_0		= 0x24,
-	.pinctrl_names		= "default",
-	.reg			= {0xff130000, 0x100},
-	.reg_io_width		= 0x4,
-	.reg_shift		= 0x2,
-};
-U_BOOT_DRVINFO(serial_at_ff130000) = {
-	.name		= "ns16550_serial",
-	.plat		= &dtv_serial_at_ff130000,
-	.plat_size	= sizeof(dtv_serial_at_ff130000),
-	.parent_idx	= -1,
-};
-
-/* Node /spi@ff190000 index 4 */
-static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
-	.clocks			= {
-			{0, {32}},
-			{0, {209}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x8, 0x10, 0x9},
-	.interrupts		= {0x0, 0x31, 0x4},
-	.pinctrl_0		= {0x2c, 0x2d, 0x2e, 0x2f},
-	.pinctrl_names		= "default",
-	.reg			= {0xff190000, 0x1000},
-};
-U_BOOT_DRVINFO(spi_at_ff190000) = {
-	.name		= "rockchip_rk3328_spi",
-	.plat		= &dtv_spi_at_ff190000,
-	.plat_size	= sizeof(dtv_spi_at_ff190000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /syscon@ff100000 index 5
- * driver rockchip_rk3328_grf parent None
- */
-static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
-	.reg			= {0xff100000, 0x1000},
-};
-U_BOOT_DRVINFO(syscon_at_ff100000) = {
-	.name		= "rockchip_rk3328_grf",
-	.plat		= &dtv_syscon_at_ff100000,
-	.plat_size	= sizeof(dtv_syscon_at_ff100000),
-	.parent_idx	= -1,
-};
-

package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h

@@ -1,55 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Defines the structs used to hold devicetree data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <stdbool.h>
-#include <linux/libfdt.h>
-struct dtd_ns16550_serial {
-	fdt32_t		clock_frequency;
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0;
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	fdt32_t		reg_io_width;
-	fdt32_t		reg_shift;
-};
-struct dtd_rockchip_rk3288_dw_mshc {
-	fdt32_t		bus_width;
-	bool		cap_sd_highspeed;
-	struct phandle_1_arg clocks[4];
-	bool		disable_wp;
-	fdt32_t		fifo_depth;
-	fdt32_t		interrupts[3];
-	fdt32_t		max_frequency;
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	bool		u_boot_spl_fifo_mode;
-	fdt32_t		vmmc_supply;
-};
-struct dtd_rockchip_rk3328_cru {
-	fdt64_t		reg[2];
-	fdt32_t		rockchip_grf;
-};
-struct dtd_rockchip_rk3328_dmc {
-	fdt64_t		reg[12];
-	fdt32_t		rockchip_sdram_params[196];
-};
-struct dtd_rockchip_rk3328_grf {
-	fdt64_t		reg[2];
-};
-struct dtd_rockchip_rk3328_spi {
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-};

package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-decl.h

@@ -1,24 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares externs for all device/uclass instances.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <dm/device-internal.h>
-#include <dm/uclass-internal.h>
-
-/* driver declarations - these allow DM_DRIVER_GET() to be used */
-extern U_BOOT_DRIVER(rockchip_rk3328_cru);
-extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(ns16550_serial);
-extern U_BOOT_DRIVER(rockchip_rk3328_grf);
-
-/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
-extern UCLASS_DRIVER(clk);
-extern UCLASS_DRIVER(mmc);
-extern UCLASS_DRIVER(ram);
-extern UCLASS_DRIVER(serial);
-extern UCLASS_DRIVER(syscon);

package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-plat.c

@@ -1,189 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares the U_BOOT_DRIVER() records and platform data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-/* Allow use of U_BOOT_DRVINFO() in this file */
-#define DT_PLAT_C
-
-#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
-/*
- * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
- *
- * idx  driver_info          driver
- * ---  -------------------- --------------------
- *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
- *   1: dmc                  rockchip_rk3328_dmc
- *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
- *   3: mmc_at_ff520000      rockchip_rk3288_dw_mshc
- *   4: serial_at_ff130000   ns16550_serial
- *   5: syscon_at_ff100000   rockchip_rk3328_grf
- * ---  -------------------- --------------------
- */
-
-/*
- * Node /clock-controller@ff440000 index 0
- * driver rockchip_rk3328_cru parent None
- */
-static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
-	.reg			= {0xff440000, 0x1000},
-	.rockchip_grf		= 0x3a,
-};
-U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
-	.name		= "rockchip_rk3328_cru",
-	.plat		= &dtv_clock_controller_at_ff440000,
-	.plat_size	= sizeof(dtv_clock_controller_at_ff440000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /dmc index 1
- * driver rockchip_rk3328_dmc parent None
- */
-static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
-	.reg			= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
-		0xff720000, 0x1000, 0xff798000, 0x1000},
-	.rockchip_sdram_params	= {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
-		0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
-		0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
-		0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
-		0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
-		0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
-		0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
-		0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
-		0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
-		0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
-		0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
-		0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
-		0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
-		0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
-		0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
-		0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
-		0x77, 0x77, 0x79, 0x9},
-};
-U_BOOT_DRVINFO(dmc) = {
-	.name		= "rockchip_rk3328_dmc",
-	.plat		= &dtv_dmc,
-	.plat_size	= sizeof(dtv_dmc),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff500000 index 2
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
-	.bus_width		= 0x4,
-	.cap_mmc_highspeed	= true,
-	.cap_sd_highspeed	= true,
-	.clocks			= {
-			{0, {317}},
-			{0, {33}},
-			{0, {74}},
-			{0, {78}},},
-	.disable_wp		= true,
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xc, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.pinctrl_0		= {0x47, 0x48, 0x49, 0x4a},
-	.pinctrl_names		= "default",
-	.reg			= {0xff500000, 0x4000},
-	.sd_uhs_sdr104		= true,
-	.sd_uhs_sdr12		= true,
-	.sd_uhs_sdr25		= true,
-	.sd_uhs_sdr50		= true,
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x4b,
-	.vqmmc_supply		= 0x1e,
-};
-U_BOOT_DRVINFO(mmc_at_ff500000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff500000,
-	.plat_size	= sizeof(dtv_mmc_at_ff500000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff520000 index 3
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
-	.bus_width		= 0x8,
-	.cap_mmc_highspeed	= true,
-	.clocks			= {
-			{0, {319}},
-			{0, {35}},
-			{0, {76}},
-			{0, {80}},},
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xe, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.mmc_ddr_1_8v		= true,
-	.mmc_hs200_1_8v		= true,
-	.non_removable		= true,
-	.pinctrl_0		= {0x4c, 0x4d, 0x4e, 0x0},
-	.pinctrl_names		= "default",
-	.reg			= {0xff520000, 0x4000},
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x1c,
-	.vqmmc_supply		= 0x1d,
-};
-U_BOOT_DRVINFO(mmc_at_ff520000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff520000,
-	.plat_size	= sizeof(dtv_mmc_at_ff520000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /serial@ff130000 index 4
- * driver ns16550_serial parent None
- */
-static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
-	.clock_frequency	= 0x16e3600,
-	.clocks			= {
-			{0, {40}},
-			{0, {212}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x6, 0x10, 0x7},
-	.interrupts		= {0x0, 0x39, 0x4},
-	.pinctrl_0		= 0x26,
-	.pinctrl_names		= "default",
-	.reg			= {0xff130000, 0x100},
-	.reg_io_width		= 0x4,
-	.reg_shift		= 0x2,
-};
-U_BOOT_DRVINFO(serial_at_ff130000) = {
-	.name		= "ns16550_serial",
-	.plat		= &dtv_serial_at_ff130000,
-	.plat_size	= sizeof(dtv_serial_at_ff130000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /syscon@ff100000 index 5
- * driver rockchip_rk3328_grf parent None
- */
-static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
-	.reg			= {0xff100000, 0x1000},
-};
-U_BOOT_DRVINFO(syscon_at_ff100000) = {
-	.name		= "rockchip_rk3328_grf",
-	.plat		= &dtv_syscon_at_ff100000,
-	.plat_size	= sizeof(dtv_syscon_at_ff100000),
-	.parent_idx	= -1,
-};
-

package/boot/uboot-rockchip/src/of-platdata/roc-cc-rk3328/dt-structs-gen.h

@@ -1,55 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Defines the structs used to hold devicetree data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <stdbool.h>
-#include <linux/libfdt.h>
-struct dtd_ns16550_serial {
-	fdt32_t		clock_frequency;
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0;
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	fdt32_t		reg_io_width;
-	fdt32_t		reg_shift;
-};
-struct dtd_rockchip_rk3288_dw_mshc {
-	fdt32_t		bus_width;
-	bool		cap_mmc_highspeed;
-	bool		cap_sd_highspeed;
-	struct phandle_1_arg clocks[4];
-	bool		disable_wp;
-	fdt32_t		fifo_depth;
-	fdt32_t		interrupts[3];
-	fdt32_t		max_frequency;
-	bool		mmc_ddr_1_8v;
-	bool		mmc_hs200_1_8v;
-	bool		non_removable;
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	bool		sd_uhs_sdr104;
-	bool		sd_uhs_sdr12;
-	bool		sd_uhs_sdr25;
-	bool		sd_uhs_sdr50;
-	bool		u_boot_spl_fifo_mode;
-	fdt32_t		vmmc_supply;
-	fdt32_t		vqmmc_supply;
-};
-struct dtd_rockchip_rk3328_cru {
-	fdt64_t		reg[2];
-	fdt32_t		rockchip_grf;
-};
-struct dtd_rockchip_rk3328_dmc {
-	fdt64_t		reg[12];
-	fdt32_t		rockchip_sdram_params[196];
-};
-struct dtd_rockchip_rk3328_grf {
-	fdt64_t		reg[2];
-};

package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h

@@ -1,24 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares externs for all device/uclass instances.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <dm/device-internal.h>
-#include <dm/uclass-internal.h>
-
-/* driver declarations - these allow DM_DRIVER_GET() to be used */
-extern U_BOOT_DRIVER(rockchip_rk3328_cru);
-extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(ns16550_serial);
-extern U_BOOT_DRIVER(rockchip_rk3328_grf);
-
-/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
-extern UCLASS_DRIVER(clk);
-extern UCLASS_DRIVER(mmc);
-extern UCLASS_DRIVER(ram);
-extern UCLASS_DRIVER(serial);
-extern UCLASS_DRIVER(syscon);

package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c

@@ -1,189 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares the U_BOOT_DRIVER() records and platform data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-/* Allow use of U_BOOT_DRVINFO() in this file */
-#define DT_PLAT_C
-
-#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
-/*
- * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
- *
- * idx  driver_info          driver
- * ---  -------------------- --------------------
- *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
- *   1: dmc                  rockchip_rk3328_dmc
- *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
- *   3: mmc_at_ff520000      rockchip_rk3288_dw_mshc
- *   4: serial_at_ff130000   ns16550_serial
- *   5: syscon_at_ff100000   rockchip_rk3328_grf
- * ---  -------------------- --------------------
- */
-
-/*
- * Node /clock-controller@ff440000 index 0
- * driver rockchip_rk3328_cru parent None
- */
-static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
-	.reg			= {0xff440000, 0x1000},
-	.rockchip_grf		= 0x38,
-};
-U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
-	.name		= "rockchip_rk3328_cru",
-	.plat		= &dtv_clock_controller_at_ff440000,
-	.plat_size	= sizeof(dtv_clock_controller_at_ff440000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /dmc index 1
- * driver rockchip_rk3328_dmc parent None
- */
-static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
-	.reg			= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
-		0xff720000, 0x1000, 0xff798000, 0x1000},
-	.rockchip_sdram_params	= {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
-		0x10, 0x10, 0x0, 0x9028b189, 0x0, 0x21, 0x482, 0x15,
-		0x222, 0xff, 0x14d, 0x3, 0x1, 0x0, 0x0, 0x0,
-		0x43041001, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x20000, 0xd8,
-		0x100, 0xdc, 0x3200000, 0xe0, 0x0, 0xe4, 0x90000, 0xf4,
-		0xf011f, 0x100, 0x7090b06, 0x104, 0x50209, 0x108, 0x3030407, 0x10c,
-		0x202006, 0x110, 0x3020204, 0x114, 0x3030202, 0x120, 0x903, 0x180,
-		0x800020, 0x184, 0x0, 0x190, 0x7010001, 0x198, 0x5001100, 0x1a0,
-		0xc0400003, 0x240, 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490,
-		0x1, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-		0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xa, 0x28, 0x6, 0x2c,
-		0x0, 0x30, 0x5, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
-		0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
-		0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
-		0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
-		0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
-		0x77, 0x77, 0x79, 0x9},
-};
-U_BOOT_DRVINFO(dmc) = {
-	.name		= "rockchip_rk3328_dmc",
-	.plat		= &dtv_dmc,
-	.plat_size	= sizeof(dtv_dmc),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff500000 index 2
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
-	.bus_width		= 0x4,
-	.cap_mmc_highspeed	= true,
-	.cap_sd_highspeed	= true,
-	.card_detect_delay	= 0xc8,
-	.clocks			= {
-			{0, {317}},
-			{0, {33}},
-			{0, {74}},
-			{0, {78}},},
-	.disable_wp		= true,
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xc, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.num_slots		= 0x1,
-	.pinctrl_0		= {0x45, 0x46, 0x47, 0x48},
-	.pinctrl_names		= "default",
-	.reg			= {0xff500000, 0x4000},
-	.supports_sd		= true,
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x49,
-};
-U_BOOT_DRVINFO(mmc_at_ff500000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff500000,
-	.plat_size	= sizeof(dtv_mmc_at_ff500000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff520000 index 3
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
-	.bus_width		= 0x8,
-	.cap_mmc_highspeed	= true,
-	.clocks			= {
-			{0, {319}},
-			{0, {35}},
-			{0, {76}},
-			{0, {80}},},
-	.disable_wp		= true,
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xe, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.mmc_hs200_1_8v		= true,
-	.non_removable		= true,
-	.num_slots		= 0x1,
-	.pinctrl_0		= {0x4a, 0x4b, 0x4c, 0x0},
-	.pinctrl_names		= "default",
-	.reg			= {0xff520000, 0x4000},
-	.supports_emmc		= true,
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x1c,
-	.vqmmc_supply		= 0x1d,
-};
-U_BOOT_DRVINFO(mmc_at_ff520000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff520000,
-	.plat_size	= sizeof(dtv_mmc_at_ff520000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /serial@ff130000 index 4
- * driver ns16550_serial parent None
- */
-static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
-	.clock_frequency	= 0x16e3600,
-	.clocks			= {
-			{0, {40}},
-			{0, {212}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x6, 0x10, 0x7},
-	.interrupts		= {0x0, 0x39, 0x4},
-	.pinctrl_0		= 0x24,
-	.pinctrl_names		= "default",
-	.reg			= {0xff130000, 0x100},
-	.reg_io_width		= 0x4,
-	.reg_shift		= 0x2,
-};
-U_BOOT_DRVINFO(serial_at_ff130000) = {
-	.name		= "ns16550_serial",
-	.plat		= &dtv_serial_at_ff130000,
-	.plat_size	= sizeof(dtv_serial_at_ff130000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /syscon@ff100000 index 5
- * driver rockchip_rk3328_grf parent None
- */
-static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
-	.reg			= {0xff100000, 0x1000},
-};
-U_BOOT_DRVINFO(syscon_at_ff100000) = {
-	.name		= "rockchip_rk3328_grf",
-	.plat		= &dtv_syscon_at_ff100000,
-	.plat_size	= sizeof(dtv_syscon_at_ff100000),
-	.parent_idx	= -1,
-};
-

package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h

@@ -1,54 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Defines the structs used to hold devicetree data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <stdbool.h>
-#include <linux/libfdt.h>
-struct dtd_ns16550_serial {
-	fdt32_t		clock_frequency;
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0;
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	fdt32_t		reg_io_width;
-	fdt32_t		reg_shift;
-};
-struct dtd_rockchip_rk3288_dw_mshc {
-	fdt32_t		bus_width;
-	bool		cap_mmc_highspeed;
-	bool		cap_sd_highspeed;
-	fdt32_t		card_detect_delay;
-	struct phandle_1_arg clocks[4];
-	bool		disable_wp;
-	fdt32_t		fifo_depth;
-	fdt32_t		interrupts[3];
-	fdt32_t		max_frequency;
-	bool		mmc_hs200_1_8v;
-	bool		non_removable;
-	fdt32_t		num_slots;
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	bool		supports_emmc;
-	bool		supports_sd;
-	bool		u_boot_spl_fifo_mode;
-	fdt32_t		vmmc_supply;
-	fdt32_t		vqmmc_supply;
-};
-struct dtd_rockchip_rk3328_cru {
-	fdt64_t		reg[2];
-	fdt32_t		rockchip_grf;
-};
-struct dtd_rockchip_rk3328_dmc {
-	fdt64_t		reg[12];
-	fdt32_t		rockchip_sdram_params[196];
-};
-struct dtd_rockchip_rk3328_grf {
-	fdt64_t		reg[2];
-};

package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h

@@ -1,27 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares externs for all device/uclass instances.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <dm/device-internal.h>
-#include <dm/uclass-internal.h>
-
-/* driver declarations - these allow DM_DRIVER_GET() to be used */
-extern U_BOOT_DRIVER(rockchip_rk3328_cru);
-extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
-extern U_BOOT_DRIVER(ns16550_serial);
-extern U_BOOT_DRIVER(rockchip_rk3328_spi);
-extern U_BOOT_DRIVER(jedec_spi_nor);
-extern U_BOOT_DRIVER(rockchip_rk3328_grf);
-
-/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
-extern UCLASS_DRIVER(clk);
-extern UCLASS_DRIVER(mmc);
-extern UCLASS_DRIVER(ram);
-extern UCLASS_DRIVER(serial);
-extern UCLASS_DRIVER(spi_flash);
-extern UCLASS_DRIVER(syscon);

package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c

@@ -1,219 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Declares the U_BOOT_DRIVER() records and platform data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-/* Allow use of U_BOOT_DRVINFO() in this file */
-#define DT_PLAT_C
-
-#include <common.h>
-#include <dm.h>
-#include <dt-structs.h>
-
-/*
- * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
- *
- * idx  driver_info          driver
- * ---  -------------------- --------------------
- *   0: clock_controller_at_ff440000 rockchip_rk3328_cru
- *   1: dmc                  rockchip_rk3328_dmc
- *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc
- *   3: mmc_at_ff520000      rockchip_rk3288_dw_mshc
- *   4: serial_at_ff130000   ns16550_serial
- *   5: spi_at_ff190000      rockchip_rk3328_spi
- *   6: spiflash_at_0        jedec_spi_nor
- *   7: syscon_at_ff100000   rockchip_rk3328_grf
- * ---  -------------------- --------------------
- */
-
-/*
- * Node /clock-controller@ff440000 index 0
- * driver rockchip_rk3328_cru parent None
- */
-static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
-	.reg			= {0xff440000, 0x1000},
-	.rockchip_grf		= 0x3b,
-};
-U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
-	.name		= "rockchip_rk3328_cru",
-	.plat		= &dtv_clock_controller_at_ff440000,
-	.plat_size	= sizeof(dtv_clock_controller_at_ff440000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /dmc index 1
- * driver rockchip_rk3328_dmc parent None
- */
-static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
-	.reg			= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
-		0xff720000, 0x1000, 0xff798000, 0x1000},
-	.rockchip_sdram_params	= {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
-		0x10, 0x10, 0x0, 0x98899459, 0x0, 0x2e, 0x544, 0x15,
-		0x432, 0xff, 0x320, 0x6, 0x1, 0x0, 0x1, 0x0,
-		0x43041008, 0x64, 0x300054, 0xd0, 0x500002, 0xd4, 0x10000, 0xd8,
-		0xe03, 0xdc, 0x43001a, 0xe0, 0x10000, 0xe4, 0xe0005, 0xf4,
-		0xf011f, 0x100, 0xb141b11, 0x104, 0x3031a, 0x108, 0x3060809, 0x10c,
-		0x606000, 0x110, 0x8020409, 0x114, 0x1010606, 0x118, 0x2020004, 0x120,
-		0x404, 0x138, 0x58, 0x180, 0x900024, 0x184, 0x1400000, 0x190,
-		0x7050002, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0xa020b28, 0x244,
-		0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
-		0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0xc, 0x2c,
-		0x0, 0x30, 0x6, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
-		0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
-		0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
-		0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
-		0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
-		0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
-		0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
-		0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
-		0x77, 0x77, 0x79, 0x9},
-};
-U_BOOT_DRVINFO(dmc) = {
-	.name		= "rockchip_rk3328_dmc",
-	.plat		= &dtv_dmc,
-	.plat_size	= sizeof(dtv_dmc),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff500000 index 2
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
-	.bus_width		= 0x4,
-	.cap_mmc_highspeed	= true,
-	.cap_sd_highspeed	= true,
-	.clocks			= {
-			{0, {317}},
-			{0, {33}},
-			{0, {74}},
-			{0, {78}},},
-	.disable_wp		= true,
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xc, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.pinctrl_0		= {0x4a, 0x4b, 0x4c, 0x4d},
-	.pinctrl_names		= "default",
-	.reg			= {0xff500000, 0x4000},
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x4e,
-};
-U_BOOT_DRVINFO(mmc_at_ff500000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff500000,
-	.plat_size	= sizeof(dtv_mmc_at_ff500000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /mmc@ff520000 index 3
- * driver rockchip_rk3288_dw_mshc parent None
- */
-static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
-	.bus_width		= 0x8,
-	.cap_mmc_highspeed	= true,
-	.clocks			= {
-			{0, {319}},
-			{0, {35}},
-			{0, {76}},
-			{0, {80}},},
-	.fifo_depth		= 0x100,
-	.interrupts		= {0x0, 0xe, 0x4},
-	.max_frequency		= 0x8f0d180,
-	.mmc_hs200_1_8v		= true,
-	.non_removable		= true,
-	.pinctrl_0		= {0x4f, 0x50, 0x51, 0x0},
-	.pinctrl_names		= "default",
-	.reg			= {0xff520000, 0x4000},
-	.u_boot_spl_fifo_mode	= true,
-	.vmmc_supply		= 0x1e,
-	.vqmmc_supply		= 0x1f,
-};
-U_BOOT_DRVINFO(mmc_at_ff520000) = {
-	.name		= "rockchip_rk3288_dw_mshc",
-	.plat		= &dtv_mmc_at_ff520000,
-	.plat_size	= sizeof(dtv_mmc_at_ff520000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /serial@ff130000 index 4
- * driver ns16550_serial parent None
- */
-static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
-	.clock_frequency	= 0x16e3600,
-	.clocks			= {
-			{0, {40}},
-			{0, {212}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x6, 0x10, 0x7},
-	.interrupts		= {0x0, 0x39, 0x4},
-	.pinctrl_0		= 0x27,
-	.pinctrl_names		= "default",
-	.reg			= {0xff130000, 0x100},
-	.reg_io_width		= 0x4,
-	.reg_shift		= 0x2,
-};
-U_BOOT_DRVINFO(serial_at_ff130000) = {
-	.name		= "ns16550_serial",
-	.plat		= &dtv_serial_at_ff130000,
-	.plat_size	= sizeof(dtv_serial_at_ff130000),
-	.parent_idx	= -1,
-};
-
-/* Node /spi@ff190000 index 5 */
-static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
-	.clocks			= {
-			{0, {32}},
-			{0, {209}},},
-	.dma_names		= {"tx", "rx"},
-	.dmas			= {0x10, 0x8, 0x10, 0x9},
-	.interrupts		= {0x0, 0x31, 0x4},
-	.pinctrl_0		= {0x2f, 0x30, 0x31, 0x32},
-	.pinctrl_names		= "default",
-	.reg			= {0xff190000, 0x1000},
-};
-U_BOOT_DRVINFO(spi_at_ff190000) = {
-	.name		= "rockchip_rk3328_spi",
-	.plat		= &dtv_spi_at_ff190000,
-	.plat_size	= sizeof(dtv_spi_at_ff190000),
-	.parent_idx	= -1,
-};
-
-/*
- * Node /spi@ff190000/spiflash@0 index 6
- * driver jedec_spi_nor parent None
- */
-static struct dtd_jedec_spi_nor dtv_spiflash_at_0 = {
-	.reg			= {0x0},
-	.spi_max_frequency	= 0x2faf080,
-};
-U_BOOT_DRVINFO(spiflash_at_0) = {
-	.name		= "jedec_spi_nor",
-	.plat		= &dtv_spiflash_at_0,
-	.plat_size	= sizeof(dtv_spiflash_at_0),
-	.parent_idx	= 5,
-};
-
-/*
- * Node /syscon@ff100000 index 7
- * driver rockchip_rk3328_grf parent None
- */
-static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
-	.reg			= {0xff100000, 0x1000},
-};
-U_BOOT_DRVINFO(syscon_at_ff100000) = {
-	.name		= "rockchip_rk3328_grf",
-	.plat		= &dtv_syscon_at_ff100000,
-	.plat_size	= sizeof(dtv_syscon_at_ff100000),
-	.parent_idx	= -1,
-};
-

package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h

@@ -1,63 +0,0 @@
-/*
- * DO NOT MODIFY
- *
- * Defines the structs used to hold devicetree data.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-#include <stdbool.h>
-#include <linux/libfdt.h>
-struct dtd_jedec_spi_nor {
-	fdt32_t		reg[1];
-	fdt32_t		spi_max_frequency;
-};
-struct dtd_ns16550_serial {
-	fdt32_t		clock_frequency;
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0;
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	fdt32_t		reg_io_width;
-	fdt32_t		reg_shift;
-};
-struct dtd_rockchip_rk3288_dw_mshc {
-	fdt32_t		bus_width;
-	bool		cap_mmc_highspeed;
-	bool		cap_sd_highspeed;
-	struct phandle_1_arg clocks[4];
-	bool		disable_wp;
-	fdt32_t		fifo_depth;
-	fdt32_t		interrupts[3];
-	fdt32_t		max_frequency;
-	bool		mmc_hs200_1_8v;
-	bool		non_removable;
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-	bool		u_boot_spl_fifo_mode;
-	fdt32_t		vmmc_supply;
-	fdt32_t		vqmmc_supply;
-};
-struct dtd_rockchip_rk3328_cru {
-	fdt64_t		reg[2];
-	fdt32_t		rockchip_grf;
-};
-struct dtd_rockchip_rk3328_dmc {
-	fdt64_t		reg[12];
-	fdt32_t		rockchip_sdram_params[196];
-};
-struct dtd_rockchip_rk3328_grf {
-	fdt64_t		reg[2];
-};
-struct dtd_rockchip_rk3328_spi {
-	struct phandle_1_arg clocks[2];
-	const char *	dma_names[2];
-	fdt32_t		dmas[4];
-	fdt32_t		interrupts[3];
-	fdt32_t		pinctrl_0[4];
-	const char *	pinctrl_names;
-	fdt64_t		reg[2];
-};