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+From 02693ffdb93bffcbe772bd91a399dabd123b8c19 Mon Sep 17 00:00:00 2001
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+From: Linus Walleij <[email protected]>
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+Date: Tue, 19 Sep 2023 16:02:15 +0200
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+Subject: [PATCH 4/4] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
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+
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+This is a USRobotics NAS/Firewall/router that has been supported
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+by OpenWrt in the past. It had dedicated users so let's get it
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+properly supported.
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+
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+Signed-off-by: Linus Walleij <[email protected]>
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+---
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+ arch/arm/boot/dts/Makefile | 3 +-
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+ .../dts/intel-ixp42x-usrobotics-usr8200.dts | 229 ++++++++++++++++++
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+ 2 files changed, 231 insertions(+), 1 deletion(-)
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+ create mode 100644 arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
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+
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+--- a/arch/arm/boot/dts/Makefile
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++++ b/arch/arm/boot/dts/Makefile
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+@@ -292,7 +292,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
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+ intel-ixp43x-gateworks-gw2358.dtb \
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+ intel-ixp42x-netgear-wg302v1.dtb \
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+ intel-ixp42x-arcom-vulcan.dtb \
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+- intel-ixp42x-gateway-7001.dtb
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++ intel-ixp42x-gateway-7001.dtb \
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++ intel-ixp42x-usrobotics-usr8200.dtb
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+ dtb-$(CONFIG_ARCH_KEYSTONE) += \
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+ keystone-k2hk-evm.dtb \
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+ keystone-k2l-evm.dtb \
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+--- /dev/null
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++++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
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+@@ -0,0 +1,229 @@
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++// SPDX-License-Identifier: ISC
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++/*
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++ * Device Tree file for the USRobotics USR8200 firewall
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++ * VPN and NAS. Based on know-how from Peter Denison.
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++ *
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++ * This machine is based on IXP422, the USR internal codename
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++ * is "Jeeves".
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++ */
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++
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++/dts-v1/;
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++
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++#include "intel-ixp42x.dtsi"
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++#include <dt-bindings/input/input.h>
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++
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++/ {
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++ model = "USRobotics USR8200";
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++ compatible = "usr,usr8200", "intel,ixp42x";
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++
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++ memory@0 {
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++ device_type = "memory";
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++ reg = <0x00000000 0x4000000>;
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++ };
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++
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++ chosen {
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++ bootargs = "console=ttyS0,115200n8";
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++ stdout-path = "uart1:115200n8";
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++ };
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++
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++ aliases {
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++ /* These are switched around */
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++ serial0 = &uart1;
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++ serial1 = &uart0;
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++ };
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++
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++ leds {
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++ compatible = "gpio-leds";
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++ ieee1394_led: led-1394 {
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++ label = "usr8200:green:1394";
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++ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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++ default-state = "off";
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++ };
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++ usb1_led: led-usb1 {
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++ label = "usr8200:green:usb1";
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++ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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++ default-state = "off";
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++ };
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++ usb2_led: led-usb2 {
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++ label = "usr8200:green:usb2";
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++ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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++ default-state = "off";
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++ };
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++ wireless_led: led-wireless {
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++ /*
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++ * This LED is mounted inside the case but cannot be
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++ * seen from the outside: probably USR planned at one
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++ * point for the device to have a wireless card, then
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++ * changed their mind and didn't mount it, leaving the
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++ * LED in place.
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++ */
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++ label = "usr8200:green:wireless";
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++ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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++ default-state = "off";
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++ };
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++ pwr_led: led-pwr {
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++ label = "usr8200:green:pwr";
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++ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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++ default-state = "on";
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++ linux,default-trigger = "heartbeat";
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++ };
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++ };
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++
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++ gpio_keys {
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++ compatible = "gpio-keys";
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++
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++ button-reset {
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++ wakeup-source;
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++ linux,code = <KEY_RESTART>;
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++ label = "reset";
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++ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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++ };
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++ };
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++
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++ soc {
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++ bus@c4000000 {
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++ flash@0,0 {
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++ compatible = "intel,ixp4xx-flash", "cfi-flash";
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++ bank-width = <2>;
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++ /* Enable writes on the expansion bus */
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++ intel,ixp4xx-eb-write-enable = <1>;
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++ /* 16 MB of Flash mapped in at CS0 */
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++ reg = <0 0x00000000 0x1000000>;
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++
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++ partitions {
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++ compatible = "redboot-fis";
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++ /* Eraseblock at 0x0fe0000 */
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++ fis-index-block = <0x7f>;
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++ };
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++ };
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++ rtc@2,0 {
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++ /* EPSON RTC7301 DG DIL-capsule */
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++ compatible = "epson,rtc7301dg";
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++ /*
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++ * These timing settings were found in the boardfile patch:
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++ * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
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++ * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
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++ */
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++ intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
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++ intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
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++ intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
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++ intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
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++ intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
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++ intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
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++ intel,ixp4xx-eb-byte-access-on-halfword = <0>;
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++ intel,ixp4xx-eb-mux-address-and-data = <0>;
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++ intel,ixp4xx-eb-ahb-split-transfers = <0>;
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++ intel,ixp4xx-eb-write-enable = <1>;
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++ intel,ixp4xx-eb-byte-access = <1>;
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++ /* 512 bytes at CS2 */
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++ reg = <2 0x00000000 0x0000200>;
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++ reg-io-width = <1>;
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++ native-endian;
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++ /* FIXME: try to check if there is an IRQ for the RTC? */
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++ };
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++ };
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++
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++ pci@c0000000 {
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++ status = "okay";
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++
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++ /*
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++ * Taken from USR8200 boardfile from OpenWrt
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++ *
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++ * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
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++ * We assume the same IRQ for all pins on the remaining slots, that
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++ * is what the boardfile was doing.
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++ */
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++ #interrupt-cells = <1>;
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++ interrupt-map-mask = <0xf800 0 0 7>;
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++ interrupt-map =
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++ /* IDSEL 14 used for "Wireless" in the board file */
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++ <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
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++ /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
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++ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
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++ /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
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++ <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
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++ <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
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++ <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
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++ };
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++
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++ gpio@c8004000 {
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++ /* Enable clock out on GPIO 15 */
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++ intel,ixp4xx-gpio15-clkout;
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++ };
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++
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++ /* EthB WAN */
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++ ethernet@c8009000 {
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++ status = "okay";
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++ queue-rx = <&qmgr 3>;
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++ queue-txready = <&qmgr 20>;
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++ phy-mode = "rgmii";
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++ phy-handle = <&phy9>;
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++
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++ mdio {
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ phy9: ethernet-phy@9 {
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++ reg = <9>;
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++ };
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++
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++ /* The switch uses MDIO addresses 16 thru 31 */
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++ switch@16 {
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++ compatible = "marvell,mv88e6060";
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++ reg = <16>;
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++
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++ ports {
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ port@0 {
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++ reg = <0>;
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++ label = "lan1";
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++ };
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++
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++ port@1 {
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++ reg = <1>;
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++ label = "lan2";
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++ };
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++
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++ port@2 {
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++ reg = <2>;
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++ label = "lan3";
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++ };
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++
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++ port@3 {
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++ reg = <3>;
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++ label = "lan4";
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++ };
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++
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++ port@5 {
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++ /* Port 5 is the CPU port according to the MV88E6060 datasheet */
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++ reg = <5>;
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++ phy-mode = "rgmii-id";
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++ ethernet = <ðc>;
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++ label = "cpu";
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++ fixed-link {
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++ speed = <100>;
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++ full-duplex;
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++ };
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++ };
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++ };
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++ };
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++ };
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++ };
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++
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++ /* EthC LAN connected to the Marvell DSA Switch */
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++ ethc: ethernet@c800a000 {
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++ status = "okay";
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++ queue-rx = <&qmgr 4>;
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++ queue-txready = <&qmgr 21>;
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++ phy-mode = "rgmii";
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++ fixed-link {
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++ speed = <100>;
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++ full-duplex;
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++ };
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++ };
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++ };
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++};
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Linus Walleij