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@@ -0,0 +1,270 @@
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+From: Franky Lin <[email protected]>
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+Date: Wed, 20 May 2015 14:09:51 +0200
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+Subject: [PATCH] brcmfmac: add support for dma indices feature
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+
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+PCIe full dongle firmware can support a dma indices feature with which
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+firmware can update/fetch the read/write indices of message buffer
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+rings on both host to dongle and dongle to host directions. The support is
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+announced by firmware through shared flags.
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+
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+Reviewed-by: Arend Van Spriel <[email protected]>
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+Reviewed-by: Pieter-Paul Giesberts <[email protected]>
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+Signed-off-by: Franky Lin <[email protected]>
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+Signed-off-by: Arend van Spriel <[email protected]>
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+Signed-off-by: Kalle Valo <[email protected]>
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+---
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+
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+--- a/drivers/net/wireless/brcm80211/brcmfmac/pcie.c
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++++ b/drivers/net/wireless/brcm80211/brcmfmac/pcie.c
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+@@ -115,6 +115,8 @@ enum brcmf_pcie_state {
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+ #define BRCMF_PCIE_MIN_SHARED_VERSION 5
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+ #define BRCMF_PCIE_MAX_SHARED_VERSION 5
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+ #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
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++#define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
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++#define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
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+
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+ #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
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+ #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
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+@@ -146,6 +148,10 @@ enum brcmf_pcie_state {
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+ #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8
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+ #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12
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+ #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16
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++#define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET 20
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++#define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET 28
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++#define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET 36
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++#define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET 44
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+ #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0
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+ #define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52
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+
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+@@ -247,6 +253,13 @@ struct brcmf_pciedev_info {
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+ bool mbdata_completed;
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+ bool irq_allocated;
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+ bool wowl_enabled;
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++ u8 dma_idx_sz;
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++ void *idxbuf;
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++ u32 idxbuf_sz;
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++ dma_addr_t idxbuf_dmahandle;
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++ u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
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++ void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
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++ u16 value);
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+ };
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+
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+ struct brcmf_pcie_ringbuf {
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+@@ -323,6 +336,25 @@ brcmf_pcie_write_tcm16(struct brcmf_pcie
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+ }
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+
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+
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++static u16
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++brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
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++{
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++ u16 *address = devinfo->idxbuf + mem_offset;
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++
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++ return (*(address));
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++}
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++
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++
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++static void
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++brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
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++ u16 value)
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++{
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++ u16 *address = devinfo->idxbuf + mem_offset;
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++
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++ *(address) = value;
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++}
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++
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++
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+ static u32
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+ brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
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+ {
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+@@ -868,7 +900,7 @@ static int brcmf_pcie_ring_mb_write_rptr
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+ brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
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+ commonring->w_ptr, ring->id);
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+
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+- brcmf_pcie_write_tcm16(devinfo, ring->r_idx_addr, commonring->r_ptr);
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++ devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
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+
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+ return 0;
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+ }
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+@@ -886,7 +918,7 @@ static int brcmf_pcie_ring_mb_write_wptr
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+ brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
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+ commonring->r_ptr, ring->id);
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+
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+- brcmf_pcie_write_tcm16(devinfo, ring->w_idx_addr, commonring->w_ptr);
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++ devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
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+
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+ return 0;
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+ }
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+@@ -915,7 +947,7 @@ static int brcmf_pcie_ring_mb_update_rpt
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+ if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
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+ return -EIO;
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+
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+- commonring->r_ptr = brcmf_pcie_read_tcm16(devinfo, ring->r_idx_addr);
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++ commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
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+
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+ brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
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+ commonring->w_ptr, ring->id);
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+@@ -933,7 +965,7 @@ static int brcmf_pcie_ring_mb_update_wpt
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+ if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
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+ return -EIO;
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+
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+- commonring->w_ptr = brcmf_pcie_read_tcm16(devinfo, ring->w_idx_addr);
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++ commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
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+
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+ brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
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+ commonring->r_ptr, ring->id);
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+@@ -1038,6 +1070,13 @@ static void brcmf_pcie_release_ringbuffe
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+ }
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+ kfree(devinfo->shared.flowrings);
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+ devinfo->shared.flowrings = NULL;
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++ if (devinfo->idxbuf) {
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++ dma_free_coherent(&devinfo->pdev->dev,
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++ devinfo->idxbuf_sz,
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++ devinfo->idxbuf,
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++ devinfo->idxbuf_dmahandle);
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++ devinfo->idxbuf = NULL;
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++ }
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+ }
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+
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+
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+@@ -1053,19 +1092,72 @@ static int brcmf_pcie_init_ringbuffers(s
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+ u32 addr;
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+ u32 ring_mem_ptr;
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+ u32 i;
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++ u64 address;
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++ u32 bufsz;
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+ u16 max_sub_queues;
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++ u8 idx_offset;
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+
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+ ring_addr = devinfo->shared.ring_info_addr;
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+ brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
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++ addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
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++ max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
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+
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+- addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
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+- d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
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+- addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
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+- d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
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+- addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
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+- h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
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+- addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
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+- h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
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++ if (devinfo->dma_idx_sz != 0) {
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++ bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
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++ devinfo->dma_idx_sz * 2;
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++ devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
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++ &devinfo->idxbuf_dmahandle,
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++ GFP_KERNEL);
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++ if (!devinfo->idxbuf)
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++ devinfo->dma_idx_sz = 0;
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++ }
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++
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++ if (devinfo->dma_idx_sz == 0) {
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++ addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
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++ d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
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++ addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
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++ d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
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++ addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
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++ h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
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++ addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
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++ h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
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++ idx_offset = sizeof(u32);
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++ devinfo->write_ptr = brcmf_pcie_write_tcm16;
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++ devinfo->read_ptr = brcmf_pcie_read_tcm16;
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++ brcmf_dbg(PCIE, "Using TCM indices\n");
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++ } else {
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++ memset(devinfo->idxbuf, 0, bufsz);
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++ devinfo->idxbuf_sz = bufsz;
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++ idx_offset = devinfo->dma_idx_sz;
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++ devinfo->write_ptr = brcmf_pcie_write_idx;
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++ devinfo->read_ptr = brcmf_pcie_read_idx;
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++
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++ h2d_w_idx_ptr = 0;
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++ addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
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++ address = (u64)devinfo->idxbuf_dmahandle;
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++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
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++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
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++
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++ h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
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++ addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
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++ address += max_sub_queues * idx_offset;
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++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
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++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
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++
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++ d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
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++ addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
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++ address += max_sub_queues * idx_offset;
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++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
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++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
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++
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++ d2h_r_idx_ptr = d2h_w_idx_ptr +
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++ BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
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++ addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
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++ address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
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++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
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++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
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++ brcmf_dbg(PCIE, "Using host memory indices\n");
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++ }
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+
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+ addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
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+ ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
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+@@ -1079,8 +1171,8 @@ static int brcmf_pcie_init_ringbuffers(s
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+ ring->id = i;
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+ devinfo->shared.commonrings[i] = ring;
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+
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+- h2d_w_idx_ptr += sizeof(u32);
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+- h2d_r_idx_ptr += sizeof(u32);
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++ h2d_w_idx_ptr += idx_offset;
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++ h2d_r_idx_ptr += idx_offset;
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+ ring_mem_ptr += BRCMF_RING_MEM_SZ;
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+ }
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+
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+@@ -1094,13 +1186,11 @@ static int brcmf_pcie_init_ringbuffers(s
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+ ring->id = i;
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+ devinfo->shared.commonrings[i] = ring;
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+
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+- d2h_w_idx_ptr += sizeof(u32);
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+- d2h_r_idx_ptr += sizeof(u32);
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++ d2h_w_idx_ptr += idx_offset;
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++ d2h_r_idx_ptr += idx_offset;
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+ ring_mem_ptr += BRCMF_RING_MEM_SZ;
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+ }
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+
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+- addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
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+- max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
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+ devinfo->shared.nrof_flowrings =
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+ max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
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+ rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
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+@@ -1124,15 +1214,15 @@ static int brcmf_pcie_init_ringbuffers(s
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+ ring);
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+ ring->w_idx_addr = h2d_w_idx_ptr;
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+ ring->r_idx_addr = h2d_r_idx_ptr;
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+- h2d_w_idx_ptr += sizeof(u32);
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+- h2d_r_idx_ptr += sizeof(u32);
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++ h2d_w_idx_ptr += idx_offset;
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++ h2d_r_idx_ptr += idx_offset;
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+ }
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+ devinfo->shared.flowrings = rings;
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+
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+ return 0;
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+
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+ fail:
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+- brcmf_err("Allocating commonring buffers failed\n");
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++ brcmf_err("Allocating ring buffers failed\n");
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+ brcmf_pcie_release_ringbuffers(devinfo);
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+ return -ENOMEM;
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+ }
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+@@ -1269,6 +1359,14 @@ brcmf_pcie_init_share_ram_info(struct br
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+ return -EINVAL;
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+ }
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+
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++ /* check firmware support dma indicies */
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++ if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
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++ if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
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++ devinfo->dma_idx_sz = sizeof(u16);
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++ else
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++ devinfo->dma_idx_sz = sizeof(u32);
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++ }
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++
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+ addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
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+ shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
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+ if (shared->max_rxbufpost == 0)
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Rafał Miłecki