generic: 6.6: backport upstream v6.15 r8169 patches

b48688ea3c9ac r8169: disable RTL8126 ZRX-DC timeout
3d9b8ac534126 r8169: enable RTL8168H/RTL8168EP/RTL8168FP ASPM support
473367a5ffe16 r8169: increase max jumbo packet size on RTL8125/RTL8126
853e80369cfce r8169: add PHY c45 ops for MDIO_MMD_VENDOR2 registers
d30460f42675f r8169: add support for Intel Killer E5000
faac69a4ae5ab r8169: don't scan PHY addresses > 0
135c3c86a7cef r8169: make Kconfig option for LED support user-visible

Signed-off-by: Álvaro Fernández Rojas <[email protected]>
(cherry picked from commit 36623119b3e6532a3d051a37e93b2fbaa3dd1f6d)

target/linux/generic/backport-6.6/780-50-v6.15-r8169-make-Kconfig-option-for-LED-support-user-visib.patch

@@ -0,0 +1,28 @@
+From 135c3c86a7cef4ba3d368da15b16c275b74582d3 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <[email protected]>
+Date: Mon, 3 Feb 2025 21:35:24 +0100
+Subject: [PATCH] r8169: make Kconfig option for LED support user-visible
+
+Make config option R8169_LEDS user-visible, so that users can remove
+support if not needed.
+
+Signed-off-by: Heiner Kallweit <[email protected]>
+Reviewed-by: Simon Horman <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/realtek/Kconfig | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/realtek/Kconfig
++++ b/drivers/net/ethernet/realtek/Kconfig
+@@ -114,7 +114,8 @@ config R8169
+ 	  will be called r8169.  This is recommended.
+ 
+ config R8169_LEDS
+-	def_bool R8169 && LEDS_TRIGGER_NETDEV
++	bool "Support for controlling the NIC LEDs"
++	depends on R8169 && LEDS_TRIGGER_NETDEV
+ 	depends on !(R8169=y && LEDS_CLASS=m)
+ 	help
+ 	  Optional support for controlling the NIC LED's with the netdev

target/linux/generic/backport-6.6/780-51-v6.15-r8169-don-t-scan-PHY-addresses-0.patch

@@ -0,0 +1,26 @@
+From faac69a4ae5abb49e62c79c66b51bb905c9aa5ec Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <[email protected]>
+Date: Tue, 4 Feb 2025 07:58:17 +0100
+Subject: [PATCH] r8169: don't scan PHY addresses > 0
+
+The PHY address is a dummy, because r8169 PHY access registers
+don't support a PHY address. Therefore scan address 0 only.
+
+Signed-off-by: Heiner Kallweit <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/realtek/r8169_main.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -5230,6 +5230,7 @@ static int r8169_mdio_register(struct rt
+ 	new_bus->priv = tp;
+ 	new_bus->parent = &pdev->dev;
+ 	new_bus->irq[0] = PHY_MAC_INTERRUPT;
++	new_bus->phy_mask = GENMASK(31, 1);
+ 	snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
+ 		 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
+ 

target/linux/generic/backport-6.6/780-52-v6.15-r8169-add-support-for-Intel-Killer-E5000.patch

@@ -0,0 +1,25 @@
+From d30460f42675fef5cd4b44ffbc49b545524555e3 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <[email protected]>
+Date: Wed, 12 Feb 2025 08:03:56 +0100
+Subject: [PATCH] r8169: add support for Intel Killer E5000
+
+This adds support for the Intel Killer E5000 which seems to be a
+rebranded RTL8126. Copied from r8126 vendor driver.
+
+Signed-off-by: Heiner Kallweit <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/realtek/r8169_main.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -169,6 +169,7 @@ static const struct pci_device_id rtl816
+ 	{ PCI_VDEVICE(REALTEK,	0x8125) },
+ 	{ PCI_VDEVICE(REALTEK,	0x8126) },
+ 	{ PCI_VDEVICE(REALTEK,	0x3000) },
++	{ PCI_VDEVICE(REALTEK,	0x5000) },
+ 	{}
+ };
+ 

target/linux/generic/backport-6.6/780-53-v6.15-r8169-add-PHY-c45-ops-for-MDIO_MMD_VENDOR2-registers.patch

@@ -0,0 +1,67 @@
+From 853e80369cfceb2331bf34f251ba11c6602cc67f Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <[email protected]>
+Date: Thu, 13 Feb 2025 20:15:42 +0100
+Subject: [PATCH] r8169: add PHY c45 ops for MDIO_MMD_VENDOR2 registers
+
+The integrated PHYs on chip versions from RTL8168g allow to address
+MDIO_MMD_VEND2 registers. All c22 standard registers are mapped to
+MDIO_MMD_VEND2 registers. So far the paging mechanism is used to
+address PHY registers. Add support for c45 ops to address MDIO_MMD_VEND2
+registers directly, w/o the paging.
+
+Signed-off-by: Heiner Kallweit <[email protected]>
+Reviewed-by: Andrew Lunn <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/realtek/r8169_main.c | 32 +++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -5208,6 +5208,33 @@ static int r8169_mdio_write_reg(struct m
+ 	return 0;
+ }
+ 
++static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr,
++				   int devnum, int regnum)
++{
++	struct rtl8169_private *tp = mii_bus->priv;
++
++	if (addr > 0)
++		return -ENODEV;
++
++	if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2)
++		return r8168_phy_ocp_read(tp, regnum);
++
++	return 0;
++}
++
++static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr,
++				    int devnum, int regnum, u16 val)
++{
++	struct rtl8169_private *tp = mii_bus->priv;
++
++	if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2)
++		return -ENODEV;
++
++	r8168_phy_ocp_write(tp, regnum, val);
++
++	return 0;
++}
++
+ static int r8169_mdio_register(struct rtl8169_private *tp)
+ {
+ 	struct pci_dev *pdev = tp->pci_dev;
+@@ -5238,6 +5265,11 @@ static int r8169_mdio_register(struct rt
+ 	new_bus->read = r8169_mdio_read_reg;
+ 	new_bus->write = r8169_mdio_write_reg;
+ 
++	if (tp->mac_version >= RTL_GIGA_MAC_VER_40) {
++		new_bus->read_c45 = r8169_mdio_read_reg_c45;
++		new_bus->write_c45 = r8169_mdio_write_reg_c45;
++	}
++
+ 	ret = devm_mdiobus_register(&pdev->dev, new_bus);
+ 	if (ret)
+ 		return ret;

target/linux/generic/backport-6.6/780-54-v6.15-r8169-increase-max-jumbo-packet-size-on-RTL8125-RTL8.patch

@@ -0,0 +1,40 @@
+From 473367a5ffe1607a61be481e2feda684eb5faea9 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <[email protected]>
+Date: Fri, 7 Mar 2025 08:29:47 +0100
+Subject: [PATCH] r8169: increase max jumbo packet size on RTL8125/RTL8126
+
+Realtek confirmed that all RTL8125/RTL8126 chip versions support up to
+16K jumbo packets. Reflect this in the driver.
+
+Tested by Rui on RTL8125B with 12K jumbo packets.
+
+Suggested-by: Rui Salvaterra <[email protected]>
+Tested-by: Rui Salvaterra <[email protected]>
+Signed-off-by: Heiner Kallweit <[email protected]>
+Reviewed-by: Simon Horman <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/realtek/r8169_main.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -89,6 +89,7 @@
+ #define JUMBO_6K	(6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
+ #define JUMBO_7K	(7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
+ #define JUMBO_9K	(9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
++#define JUMBO_16K	(SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN)
+ 
+ static const struct {
+ 	const char *name;
+@@ -5368,6 +5369,9 @@ static int rtl_jumbo_max(struct rtl8169_
+ 	/* RTL8168c */
+ 	case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
+ 		return JUMBO_6K;
++	/* RTL8125/8126 */
++	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:
++		return JUMBO_16K;
+ 	default:
+ 		return JUMBO_9K;
+ 	}

target/linux/generic/backport-6.6/780-55-v6.15-r8169-enable-RTL8168H-RTL8168EP-RTL8168FP-ASPM-suppo.patch

@@ -0,0 +1,27 @@
+From 3d9b8ac5341269d31e59fd5d58d47266ac78bc32 Mon Sep 17 00:00:00 2001
+From: ChunHao Lin <[email protected]>
+Date: Tue, 18 Mar 2025 16:37:20 +0800
+Subject: [PATCH] r8169: enable RTL8168H/RTL8168EP/RTL8168FP ASPM support
+
+This patch will enable RTL8168H/RTL8168EP/RTL8168FP ASPM support on
+the platforms that have tested with ASPM enabled.
+
+Signed-off-by: ChunHao Lin <[email protected]>
+Reviewed-by: Heiner Kallweit <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/realtek/r8169_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -5406,7 +5406,7 @@ done:
+ /* register is set if system vendor successfully tested ASPM 1.2 */
+ static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
+ {
+-	if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
++	if (tp->mac_version >= RTL_GIGA_MAC_VER_46 &&
+ 	    r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
+ 		return true;
+ 

target/linux/generic/backport-6.6/780-56-v6.15-r8169-disable-RTL8126-ZRX-DC-timeout.patch

@@ -0,0 +1,60 @@
+From b48688ea3c9ac8d5d910c6e91fb7f80d846581f0 Mon Sep 17 00:00:00 2001
+From: ChunHao Lin <[email protected]>
+Date: Tue, 18 Mar 2025 16:37:21 +0800
+Subject: [PATCH] r8169: disable RTL8126 ZRX-DC timeout
+
+Disable it due to it dose not meet ZRX-DC specification. If it is enabled,
+device will exit L1 substate every 100ms. Disable it for saving more power
+in L1 substate.
+
+Signed-off-by: ChunHao Lin <[email protected]>
+Reviewed-by: Heiner Kallweit <[email protected]>
+Link: https://patch.msgid.link/[email protected]
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ drivers/net/ethernet/realtek/r8169_main.c | 27 +++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -2856,6 +2856,32 @@ static u32 rtl_csi_read(struct rtl8169_p
+ 		RTL_R32(tp, CSIDR) : ~0;
+ }
+ 
++static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp)
++{
++	struct pci_dev *pdev = tp->pci_dev;
++	u32 csi;
++	int rc;
++	u8 val;
++
++#define RTL_GEN3_RELATED_OFF	0x0890
++#define RTL_GEN3_ZRXDC_NONCOMPL	0x1
++	if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) {
++		rc = pci_read_config_byte(pdev, RTL_GEN3_RELATED_OFF, &val);
++		if (rc == PCIBIOS_SUCCESSFUL) {
++			val &= ~RTL_GEN3_ZRXDC_NONCOMPL;
++			rc = pci_write_config_byte(pdev, RTL_GEN3_RELATED_OFF,
++						   val);
++			if (rc == PCIBIOS_SUCCESSFUL)
++				return;
++		}
++	}
++
++	netdev_notice_once(tp->dev,
++		"No native access to PCI extended config space, falling back to CSI\n");
++	csi = rtl_csi_read(tp, RTL_GEN3_RELATED_OFF);
++	rtl_csi_write(tp, RTL_GEN3_RELATED_OFF, csi & ~RTL_GEN3_ZRXDC_NONCOMPL);
++}
++
+ static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
+ {
+ 	struct pci_dev *pdev = tp->pci_dev;
+@@ -3828,6 +3854,7 @@ static void rtl_hw_start_8125d(struct rt
+ 
+ static void rtl_hw_start_8126a(struct rtl8169_private *tp)
+ {
++	rtl_disable_zrxdc_timeout(tp);
+ 	rtl_set_def_aspm_entry_latency(tp);
+ 	rtl_hw_start_8125_common(tp);
+ }