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mediatek: remove left-overs from Linux 5.10

Remove patches and configuration for Linux 5.10 which have been left
in the tree despite the target having been switched to Linux 5.15.

Fixes: c283defa88 ("mediatek: switch to 5.15")
Signed-off-by: Daniel Golle <[email protected]>
Daniel Golle 3 years ago
parent
eb96f1413a
commit
593fe90b53
49 changed files with 0 additions and 4508 deletions
Unified View Show Diff Stats
  1. 0 465
      target/linux/mediatek/mt7622/config-5.10
  2. 0 633
      target/linux/mediatek/mt7623/config-5.10
  3. 0 305
      target/linux/mediatek/mt7629/config-5.10
  4. 0 119
      target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch
  5. 0 60
      target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch
  6. 0 25
      target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch
  7. 0 10
      target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch
  8. 0 11
      target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch
  9. 0 37
      target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch
  10. 0 56
      target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch
  11. 0 21
      target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch
  12. 0 41
      target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch
  13. 0 77
      target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch
  14. 0 81
      target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch
  15. 0 18
      target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
  16. 0 23
      target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch
  17. 0 11
      target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch
  18. 0 11
      target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch
  19. 0 29
      target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch
  20. 0 10
      target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch
  21. 0 195
      target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch
  22. 0 25
      target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch
  23. 0 23
      target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch
  24. 0 69
      target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch
  25. 0 13
      target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
  26. 0 66
      target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
  27. 0 36
      target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch
  28. 0 11
      target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch
  29. 0 21
      target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch
  30. 0 27
      target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch
  31. 0 26
      target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch
  32. 0 33
      target/linux/mediatek/patches-5.10/410-bt-mtk-serial-fix.patch
  33. 0 28
      target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch
  34. 0 25
      target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch
  35. 0 24
      target/linux/mediatek/patches-5.10/510-net-mediatek-add-flow-offload-for-mt7623.patch
  36. 0 415
      target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch
  37. 0 217
      target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch
  38. 0 417
      target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
  39. 0 203
      target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
  40. 0 24
      target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch
  41. 0 128
      target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch
  42. 0 53
      target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch
  43. 0 128
      target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch
  44. 0 10
      target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch
  45. 0 96
      target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
  46. 0 27
      target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch
  47. 0 29
      target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch
  48. 0 65
      target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
  49. 0 31
      target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch

+ 0 - 465
target/linux/mediatek/mt7622/config-5.10
View File 

@@ -1,465 +0,0 @@
 
-CONFIG_64BIT=y
 
-# CONFIG_AHCI_MTK is not set
 
-CONFIG_AQUANTIA_PHY=y
 
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
 
-CONFIG_ARCH_KEEP_MEMBLOCK=y
 
-CONFIG_ARCH_MEDIATEK=y
 
-CONFIG_ARCH_MMAP_RND_BITS=18
 
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
 
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
 
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
 
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
 
-CONFIG_ARCH_PROC_KCORE_TEXT=y
 
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
 
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
 
-CONFIG_ARCH_STACKWALK=y
 
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
-CONFIG_ARM64=y
 
-CONFIG_ARM64_4K_PAGES=y
 
-# CONFIG_ARM64_CNP is not set
 
-CONFIG_ARM64_CRYPTO=y
 
-CONFIG_ARM64_ERRATUM_843419=y
 
-CONFIG_ARM64_ERRATUM_845719=y
 
-CONFIG_ARM64_MODULE_PLTS=y
 
-CONFIG_ARM64_PAGE_SHIFT=12
 
-CONFIG_ARM64_PA_BITS=48
 
-CONFIG_ARM64_PA_BITS_48=y
 
-# CONFIG_ARM64_PTR_AUTH is not set
 
-# CONFIG_ARM64_SVE is not set
 
-# CONFIG_ARM64_SW_TTBR0_PAN is not set
 
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
 
-CONFIG_ARM64_VA_BITS=39
 
-CONFIG_ARM64_VA_BITS_39=y
 
-# CONFIG_ARMV8_DEPRECATED is not set
 
-CONFIG_ARM_AMBA=y
 
-CONFIG_ARM_ARCH_TIMER=y
 
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
 
-CONFIG_ARM_GIC=y
 
-CONFIG_ARM_GIC_V2M=y
 
-CONFIG_ARM_GIC_V3=y
 
-CONFIG_ARM_GIC_V3_ITS=y
 
-CONFIG_ARM_GIC_V3_ITS_PCI=y
 
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
 
-CONFIG_ARM_PMU=y
 
-CONFIG_ARM_PSCI_FW=y
 
-CONFIG_ATA=y
 
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 
-CONFIG_BLK_DEV_LOOP=y
 
-CONFIG_BLK_DEV_SD=y
 
-CONFIG_BLK_MQ_PCI=y
 
-CONFIG_BLK_PM=y
 
-CONFIG_BLK_SCSI_REQUEST=y
 
-CONFIG_BLOCK_COMPAT=y
 
-CONFIG_BSD_PROCESS_ACCT=y
 
-CONFIG_BSD_PROCESS_ACCT_V3=y
 
-CONFIG_CLKDEV_LOOKUP=y
 
-CONFIG_CLKSRC_MMIO=y
 
-CONFIG_CLONE_BACKWARDS=y
 
-CONFIG_COMMON_CLK=y
 
-CONFIG_COMMON_CLK_MEDIATEK=y
 
-CONFIG_COMMON_CLK_MT2712=y
 
-# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
 
-# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
 
-# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
 
-# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
 
-# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
 
-# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
 
-# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
 
-# CONFIG_COMMON_CLK_MT6779 is not set
 
-# CONFIG_COMMON_CLK_MT6797 is not set
 
-CONFIG_COMMON_CLK_MT7622=y
 
-CONFIG_COMMON_CLK_MT7622_AUDSYS=y
 
-CONFIG_COMMON_CLK_MT7622_ETHSYS=y
 
-CONFIG_COMMON_CLK_MT7622_HIFSYS=y
 
-# CONFIG_COMMON_CLK_MT8173 is not set
 
-CONFIG_COMMON_CLK_MT8183=y
 
-# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set
 
-# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set
 
-# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set
 
-# CONFIG_COMMON_CLK_MT8183_IPU_ADL is not set
 
-# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set
 
-# CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set
 
-# CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set
 
-# CONFIG_COMMON_CLK_MT8183_MFGCFG is not set
 
-# CONFIG_COMMON_CLK_MT8183_MMSYS is not set
 
-# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set
 
-# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set
 
-CONFIG_COMMON_CLK_MT8516=y
 
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
 
-CONFIG_COMPAT=y
 
-CONFIG_COMPAT_32BIT_TIME=y
 
-CONFIG_COMPAT_BINFMT_ELF=y
 
-CONFIG_COMPAT_NETLINK_MESSAGES=y
 
-CONFIG_COMPAT_OLD_SIGACTION=y
 
-CONFIG_CONFIGFS_FS=y
 
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
 
-# CONFIG_CPUFREQ_DT is not set
 
-CONFIG_CPU_FREQ=y
 
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
 
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
 
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
 
-CONFIG_CPU_FREQ_GOV_COMMON=y
 
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
 
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
 
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
 
-CONFIG_CPU_FREQ_STAT=y
 
-CONFIG_CPU_RMAP=y
 
-CONFIG_CPU_THERMAL=y
 
-CONFIG_CRC16=y
 
-CONFIG_CRYPTO_ACOMP2=y
 
-CONFIG_CRYPTO_AES_ARM64=y
 
-CONFIG_CRYPTO_AES_ARM64_CE=y
 
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
 
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
 
-CONFIG_CRYPTO_CMAC=y
 
-CONFIG_CRYPTO_CRC32=y
 
-CONFIG_CRYPTO_CRC32C=y
 
-CONFIG_CRYPTO_CRYPTD=y
 
-CONFIG_CRYPTO_DEFLATE=y
 
-CONFIG_CRYPTO_DRBG=y
 
-CONFIG_CRYPTO_DRBG_HMAC=y
 
-CONFIG_CRYPTO_DRBG_MENU=y
 
-CONFIG_CRYPTO_ECB=y
 
-CONFIG_CRYPTO_ECC=y
 
-CONFIG_CRYPTO_ECDH=y
 
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
 
-CONFIG_CRYPTO_HASH_INFO=y
 
-CONFIG_CRYPTO_HMAC=y
 
-CONFIG_CRYPTO_JITTERENTROPY=y
 
-CONFIG_CRYPTO_KPP=y
 
-CONFIG_CRYPTO_KPP2=y
 
-CONFIG_CRYPTO_LIB_SHA256=y
 
-CONFIG_CRYPTO_LZO=y
 
-CONFIG_CRYPTO_RNG=y
 
-CONFIG_CRYPTO_RNG2=y
 
-CONFIG_CRYPTO_RNG_DEFAULT=y
 
-CONFIG_CRYPTO_SHA256=y
 
-CONFIG_CRYPTO_SHA256_ARM64=y
 
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
 
-CONFIG_CRYPTO_SIMD=y
 
-CONFIG_CRYPTO_ZSTD=y
 
-CONFIG_DCACHE_WORD_ACCESS=y
 
-CONFIG_DEBUG_MISC=y
 
-CONFIG_DIMLIB=y
 
-CONFIG_DMADEVICES=y
 
-CONFIG_DMATEST=y
 
-CONFIG_DMA_DIRECT_REMAP=y
 
-CONFIG_DMA_ENGINE=y
 
-CONFIG_DMA_ENGINE_RAID=y
 
-CONFIG_DMA_OF=y
 
-CONFIG_DMA_REMAP=y
 
-CONFIG_DMA_VIRTUAL_CHANNELS=y
 
-CONFIG_DTC=y
 
-CONFIG_DYNAMIC_DEBUG=y
 
-CONFIG_EDAC_SUPPORT=y
 
-CONFIG_EINT_MTK=y
 
-CONFIG_EXT4_FS=y
 
-CONFIG_F2FS_FS=y
 
-CONFIG_FIT_PARTITION=y
 
-CONFIG_FIXED_PHY=y
 
-CONFIG_FIX_EARLYCON_MEM=y
 
-# CONFIG_FLATMEM_MANUAL is not set
 
-CONFIG_FRAME_POINTER=y
 
-CONFIG_FS_IOMAP=y
 
-CONFIG_FS_MBCACHE=y
 
-CONFIG_FW_LOADER_PAGED_BUF=y
 
-CONFIG_GENERIC_ALLOCATOR=y
 
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
 
-CONFIG_GENERIC_BUG=y
 
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
 
-CONFIG_GENERIC_CLOCKEVENTS=y
 
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 
-CONFIG_GENERIC_CPU_AUTOPROBE=y
 
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
 
-CONFIG_GENERIC_CSUM=y
 
-CONFIG_GENERIC_EARLY_IOREMAP=y
 
-CONFIG_GENERIC_GETTIMEOFDAY=y
 
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
 
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
 
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
 
-CONFIG_GENERIC_IRQ_SHOW=y
 
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 
-CONFIG_GENERIC_MSI_IRQ=y
 
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 
-CONFIG_GENERIC_PCI_IOMAP=y
 
-CONFIG_GENERIC_PHY=y
 
-CONFIG_GENERIC_PINCONF=y
 
-CONFIG_GENERIC_PINCTRL_GROUPS=y
 
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 
-CONFIG_GENERIC_SCHED_CLOCK=y
 
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
 
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
 
-CONFIG_GENERIC_STRNLEN_USER=y
 
-CONFIG_GENERIC_TIME_VSYSCALL=y
 
-CONFIG_GLOB=y
 
-CONFIG_GPIOLIB=y
 
-CONFIG_GRO_CELLS=y
 
-CONFIG_HANDLE_DOMAIN_IRQ=y
 
-CONFIG_HARDIRQS_SW_RESEND=y
 
-CONFIG_HAS_DMA=y
 
-CONFIG_HAS_IOMEM=y
 
-CONFIG_HAS_IOPORT_MAP=y
 
-CONFIG_HOLES_IN_ZONE=y
 
-CONFIG_HW_RANDOM=y
 
-CONFIG_HW_RANDOM_MTK=y
 
-CONFIG_I2C=y
 
-CONFIG_I2C_BOARDINFO=y
 
-CONFIG_I2C_CHARDEV=y
 
-CONFIG_I2C_MT65XX=y
 
-CONFIG_ICPLUS_PHY=y
 
-CONFIG_IIO=y
 
-CONFIG_IKCONFIG=y
 
-CONFIG_IKCONFIG_PROC=y
 
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
 
-CONFIG_INITRAMFS_SOURCE=""
 
-CONFIG_IO_URING=y
 
-CONFIG_IRQCHIP=y
 
-CONFIG_IRQ_DOMAIN=y
 
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
 
-CONFIG_IRQ_FORCED_THREADING=y
 
-CONFIG_IRQ_TIME_ACCOUNTING=y
 
-CONFIG_IRQ_WORK=y
 
-CONFIG_JBD2=y
 
-CONFIG_JUMP_LABEL=y
 
-# CONFIG_KEYBOARD_MTK_PMIC is not set
 
-CONFIG_LEDS_UBNT_LEDBAR=y
 
-CONFIG_LIBFDT=y
 
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
 
-CONFIG_LOCK_SPIN_ON_OWNER=y
 
-CONFIG_LZO_COMPRESS=y
 
-CONFIG_LZO_DECOMPRESS=y
 
-CONFIG_MAGIC_SYSRQ=y
 
-CONFIG_MDIO_BUS=y
 
-CONFIG_MDIO_DEVICE=y
 
-CONFIG_MDIO_DEVRES=y
 
-CONFIG_MEDIATEK_GE_PHY=y
 
-CONFIG_MEDIATEK_MT6577_AUXADC=y
 
-CONFIG_MEDIATEK_WATCHDOG=y
 
-CONFIG_MEMFD_CREATE=y
 
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
 
-CONFIG_MFD_SYSCON=y
 
-CONFIG_MIGRATION=y
 
-CONFIG_MMC=y
 
-CONFIG_MMC_BLOCK=y
 
-CONFIG_MMC_CQHCI=y
 
-CONFIG_MMC_MTK=y
 
-CONFIG_MODULES_TREE_LOOKUP=y
 
-CONFIG_MODULES_USE_ELF_RELA=y
 
-CONFIG_MTD_NAND_CORE=y
 
-CONFIG_MTD_NAND_ECC=y
 
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
 
-CONFIG_MTD_NAND_MTK=y
 
-CONFIG_MTD_NAND_MTK_BMT=y
 
-CONFIG_MTD_PARSER_TRX=y
 
-CONFIG_MTD_RAW_NAND=y
 
-CONFIG_MTD_SPI_NAND=y
 
-CONFIG_MTD_SPI_NOR=y
 
-CONFIG_MTD_SPLIT_FIRMWARE=y
 
-CONFIG_MTD_SPLIT_FIT_FW=y
 
-CONFIG_MTD_UBI=y
 
-CONFIG_MTD_UBI_BEB_LIMIT=20
 
-CONFIG_MTD_UBI_BLOCK=y
 
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
 
-# CONFIG_MTK_CMDQ is not set
 
-# CONFIG_MTK_CQDMA is not set
 
-CONFIG_MTK_EFUSE=y
 
-CONFIG_MTK_HSDMA=y
 
-CONFIG_MTK_INFRACFG=y
 
-CONFIG_MTK_PMIC_WRAP=y
 
-CONFIG_MTK_SCPSYS=y
 
-CONFIG_MTK_SPI_NAND=y
 
-CONFIG_MTK_THERMAL=y
 
-CONFIG_MTK_TIMER=y
 
-# CONFIG_MTK_UART_APDMA is not set
 
-CONFIG_MUTEX_SPIN_ON_OWNER=y
 
-CONFIG_NEED_DMA_MAP_STATE=y
 
-CONFIG_NEED_SG_DMA_LENGTH=y
 
-CONFIG_NET_DEVLINK=y
 
-CONFIG_NET_DSA=y
 
-CONFIG_NET_DSA_MT7530=y
 
-CONFIG_NET_DSA_TAG_MTK=y
 
-CONFIG_NET_FLOW_LIMIT=y
 
-CONFIG_NET_MEDIATEK_SOC=y
 
-CONFIG_NET_SWITCHDEV=y
 
-CONFIG_NET_VENDOR_MEDIATEK=y
 
-CONFIG_NLS=y
 
-CONFIG_NO_HZ_COMMON=y
 
-CONFIG_NO_HZ_IDLE=y
 
-CONFIG_NR_CPUS=2
 
-CONFIG_NVMEM=y
 
-CONFIG_NVMEM_SYSFS=y
 
-CONFIG_OF=y
 
-CONFIG_OF_ADDRESS=y
 
-CONFIG_OF_CONFIGFS=y
 
-CONFIG_OF_EARLY_FLATTREE=y
 
-CONFIG_OF_FLATTREE=y
 
-CONFIG_OF_GPIO=y
 
-CONFIG_OF_IRQ=y
 
-CONFIG_OF_KOBJ=y
 
-CONFIG_OF_MDIO=y
 
-CONFIG_OF_NET=y
 
-CONFIG_OF_OVERLAY=y
 
-CONFIG_OLD_SIGSUSPEND3=y
 
-CONFIG_PADATA=y
 
-CONFIG_PARTITION_PERCPU=y
 
-CONFIG_PCI=y
 
-CONFIG_PCIEAER=y
 
-CONFIG_PCIEASPM=y
 
-# CONFIG_PCIEASPM_DEFAULT is not set
 
-CONFIG_PCIEASPM_PERFORMANCE=y
 
-# CONFIG_PCIEASPM_POWERSAVE is not set
 
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
 
-CONFIG_PCIEPORTBUS=y
 
-CONFIG_PCIE_MEDIATEK=y
 
-CONFIG_PCIE_PME=y
 
-CONFIG_PCI_DEBUG=y
 
-CONFIG_PCI_DOMAINS=y
 
-CONFIG_PCI_DOMAINS_GENERIC=y
 
-CONFIG_PCI_MSI=y
 
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
 
-CONFIG_PERF_EVENTS=y
 
-CONFIG_PGTABLE_LEVELS=3
 
-CONFIG_PHYLIB=y
 
-CONFIG_PHYLINK=y
 
-CONFIG_PHYS_ADDR_T_64BIT=y
 
-CONFIG_PHY_MTK_TPHY=y
 
-# CONFIG_PHY_MTK_UFS is not set
 
-# CONFIG_PHY_MTK_XSPHY is not set
 
-CONFIG_PINCTRL=y
 
-# CONFIG_PINCTRL_MT2712 is not set
 
-# CONFIG_PINCTRL_MT6765 is not set
 
-# CONFIG_PINCTRL_MT6797 is not set
 
-CONFIG_PINCTRL_MT7622=y
 
-# CONFIG_PINCTRL_MT8173 is not set
 
-# CONFIG_PINCTRL_MT8183 is not set
 
-CONFIG_PINCTRL_MT8516=y
 
-CONFIG_PINCTRL_MTK=y
 
-CONFIG_PINCTRL_MTK_MOORE=y
 
-CONFIG_PINCTRL_MTK_V2=y
 
-CONFIG_PM=y
 
-CONFIG_PM_CLK=y
 
-CONFIG_PM_GENERIC_DOMAINS=y
 
-CONFIG_PM_GENERIC_DOMAINS_OF=y
 
-CONFIG_PM_OPP=y
 
-CONFIG_POWER_RESET=y
 
-CONFIG_POWER_RESET_SYSCON=y
 
-CONFIG_POWER_SUPPLY=y
 
-CONFIG_PRINTK_TIME=y
 
-CONFIG_PSTORE=y
 
-# CONFIG_PSTORE_842_COMPRESS is not set
 
-# CONFIG_PSTORE_BLK is not set
 
-CONFIG_PSTORE_COMPRESS=y
 
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
 
-CONFIG_PSTORE_CONSOLE=y
 
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
 
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
 
-# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
 
-# CONFIG_PSTORE_LZ4_COMPRESS is not set
 
-# CONFIG_PSTORE_LZO_COMPRESS is not set
 
-CONFIG_PSTORE_PMSG=y
 
-CONFIG_PSTORE_RAM=y
 
-# CONFIG_PSTORE_ZSTD_COMPRESS is not set
 
-CONFIG_PWM=y
 
-CONFIG_PWM_MEDIATEK=y
 
-# CONFIG_PWM_MTK_DISP is not set
 
-CONFIG_PWM_SYSFS=y
 
-CONFIG_QUEUED_RWLOCKS=y
 
-CONFIG_QUEUED_SPINLOCKS=y
 
-CONFIG_RAS=y
 
-CONFIG_RATIONAL=y
 
-# CONFIG_RAVE_SP_CORE is not set
 
-CONFIG_REALTEK_PHY=y
 
-CONFIG_REED_SOLOMON=y
 
-CONFIG_REED_SOLOMON_DEC8=y
 
-CONFIG_REED_SOLOMON_ENC8=y
 
-CONFIG_REGMAP=y
 
-CONFIG_REGMAP_MMIO=y
 
-CONFIG_REGULATOR=y
 
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
 
-CONFIG_REGULATOR_MT6380=y
 
-CONFIG_RESET_CONTROLLER=y
 
-CONFIG_RFS_ACCEL=y
 
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
 
-CONFIG_RPS=y
 
-CONFIG_RTC_CLASS=y
 
-CONFIG_RTC_DRV_MT7622=y
 
-CONFIG_RTC_I2C_AND_SPI=y
 
-CONFIG_RTL8367S_GSW=y
 
-CONFIG_RWSEM_SPIN_ON_OWNER=y
 
-CONFIG_SCSI=y
 
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
 
-CONFIG_SERIAL_8250_FSL=y
 
-CONFIG_SERIAL_8250_MT6577=y
 
-CONFIG_SERIAL_8250_NR_UARTS=3
 
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
 
-CONFIG_SERIAL_DEV_BUS=y
 
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
 
-CONFIG_SERIAL_MCTRL_GPIO=y
 
-CONFIG_SERIAL_OF_PLATFORM=y
 
-CONFIG_SGL_ALLOC=y
 
-CONFIG_SG_POOL=y
 
-CONFIG_SMP=y
 
-# CONFIG_SND_SOC_MT6359 is not set
 
-CONFIG_SPARSEMEM=y
 
-CONFIG_SPARSEMEM_EXTREME=y
 
-CONFIG_SPARSEMEM_MANUAL=y
 
-CONFIG_SPARSEMEM_VMEMMAP=y
 
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
 
-CONFIG_SPARSE_IRQ=y
 
-CONFIG_SPI=y
 
-CONFIG_SPI_MASTER=y
 
-CONFIG_SPI_MEM=y
 
-CONFIG_SPI_MT65XX=y
 
-CONFIG_SPI_MTK_NOR=y
 
-CONFIG_SPI_MTK_SNFI=y
 
-CONFIG_SRCU=y
 
-CONFIG_SWCONFIG=y
 
-CONFIG_SWIOTLB=y
 
-CONFIG_SWPHY=y
 
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
 
-CONFIG_SYSVIPC_COMPAT=y
 
-CONFIG_SYS_SUPPORTS_HUGETLBFS=y
 
-CONFIG_THERMAL=y
 
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
 
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
 
-CONFIG_THERMAL_EMULATION=y
 
-CONFIG_THERMAL_GOV_BANG_BANG=y
 
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
 
-CONFIG_THERMAL_GOV_STEP_WISE=y
 
-CONFIG_THERMAL_GOV_USER_SPACE=y
 
-CONFIG_THERMAL_OF=y
 
-CONFIG_THERMAL_WRITABLE_TRIPS=y
 
-CONFIG_THREAD_INFO_IN_TASK=y
 
-CONFIG_TICK_CPU_ACCOUNTING=y
 
-CONFIG_TIMER_OF=y
 
-CONFIG_TIMER_PROBE=y
 
-CONFIG_TREE_RCU=y
 
-CONFIG_TREE_SRCU=y
 
-CONFIG_UBIFS_FS=y
 
-# CONFIG_UCLAMP_TASK is not set
 
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
 
-CONFIG_USB=y
 
-CONFIG_USB_COMMON=y
 
-CONFIG_USB_SUPPORT=y
 
-CONFIG_USB_XHCI_HCD=y
 
-CONFIG_USB_XHCI_MTK=y
 
-# CONFIG_USB_XHCI_PLATFORM is not set
 
-CONFIG_VMAP_STACK=y
 
-CONFIG_WATCHDOG_CORE=y
 
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
 
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
 
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
 
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
 
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
 
-CONFIG_WATCHDOG_SYSFS=y
 
-CONFIG_XPS=y
 
-CONFIG_XXHASH=y
 
-CONFIG_ZLIB_DEFLATE=y
 
-CONFIG_ZLIB_INFLATE=y
 
-CONFIG_ZONE_DMA32=y
 
-CONFIG_ZSTD_COMPRESS=y
 
-CONFIG_ZSTD_DECOMPRESS=y

+ 0 - 633
target/linux/mediatek/mt7623/config-5.10
View File 

@@ -1,633 +0,0 @@
 
-# CONFIG_AIO is not set
 
-CONFIG_ALIGNMENT_TRAP=y
 
-CONFIG_ARCH_32BIT_OFF_T=y
 
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 
-CONFIG_ARCH_KEEP_MEMBLOCK=y
 
-CONFIG_ARCH_MEDIATEK=y
 
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 
-CONFIG_ARCH_MULTIPLATFORM=y
 
-CONFIG_ARCH_MULTI_V6_V7=y
 
-CONFIG_ARCH_MULTI_V7=y
 
-CONFIG_ARCH_NR_GPIO=0
 
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
 
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
 
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
 
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
-CONFIG_ARM=y
 
-CONFIG_ARM_APPENDED_DTB=y
 
-CONFIG_ARM_ARCH_TIMER=y
 
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
 
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
 
-CONFIG_ARM_CPU_SUSPEND=y
 
-# CONFIG_ARM_CPU_TOPOLOGY is not set
 
-CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
 
-CONFIG_ARM_DMA_USE_IOMMU=y
 
-CONFIG_ARM_GIC=y
 
-CONFIG_ARM_HAS_SG_CHAIN=y
 
-CONFIG_ARM_L1_CACHE_SHIFT=6
 
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
 
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
 
-CONFIG_ARM_PATCH_IDIV=y
 
-CONFIG_ARM_PATCH_PHYS_VIRT=y
 
-# CONFIG_ARM_SMMU is not set
 
-CONFIG_ARM_THUMB=y
 
-CONFIG_ARM_THUMBEE=y
 
-CONFIG_ARM_UNWIND=y
 
-CONFIG_ARM_VIRT_EXT=y
 
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
 
-CONFIG_ATAGS=y
 
-CONFIG_AUTO_ZRELADDR=y
 
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
 
-CONFIG_BACKLIGHT_GPIO=y
 
-CONFIG_BACKLIGHT_LED=y
 
-CONFIG_BACKLIGHT_PWM=y
 
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
 
-CONFIG_BLK_CMDLINE_PARSER=y
 
-CONFIG_BLK_DEV_LOOP=y
 
-CONFIG_BLK_MQ_PCI=y
 
-CONFIG_BLK_PM=y
 
-CONFIG_BOUNCE=y
 
-# CONFIG_CACHE_L2X0 is not set
 
-CONFIG_CLEANCACHE=y
 
-CONFIG_CLKDEV_LOOKUP=y
 
-CONFIG_CLKSRC_MMIO=y
 
-CONFIG_CLONE_BACKWARDS=y
 
-CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
 
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
 
-CONFIG_CMDLINE_PARTITION=y
 
-CONFIG_COMMON_CLK=y
 
-CONFIG_COMMON_CLK_MEDIATEK=y
 
-CONFIG_COMMON_CLK_MT2701=y
 
-CONFIG_COMMON_CLK_MT2701_AUDSYS=y
 
-CONFIG_COMMON_CLK_MT2701_BDPSYS=y
 
-CONFIG_COMMON_CLK_MT2701_ETHSYS=y
 
-CONFIG_COMMON_CLK_MT2701_G3DSYS=y
 
-CONFIG_COMMON_CLK_MT2701_HIFSYS=y
 
-CONFIG_COMMON_CLK_MT2701_IMGSYS=y
 
-CONFIG_COMMON_CLK_MT2701_MMSYS=y
 
-CONFIG_COMMON_CLK_MT2701_VDECSYS=y
 
-# CONFIG_COMMON_CLK_MT7622 is not set
 
-# CONFIG_COMMON_CLK_MT7629 is not set
 
-# CONFIG_COMMON_CLK_MT8135 is not set
 
-# CONFIG_COMMON_CLK_MT8173 is not set
 
-CONFIG_COMMON_CLK_MT8516=y
 
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
 
-CONFIG_COMPAT_32BIT_TIME=y
 
-CONFIG_CONFIGFS_FS=y
 
-CONFIG_CONSOLE_TRANSLATIONS=y
 
-CONFIG_COREDUMP=y
 
-# CONFIG_CPUFREQ_DT is not set
 
-CONFIG_CPU_32v6K=y
 
-CONFIG_CPU_32v7=y
 
-CONFIG_CPU_ABRT_EV7=y
 
-CONFIG_CPU_CACHE_V7=y
 
-CONFIG_CPU_CACHE_VIPT=y
 
-CONFIG_CPU_COPY_V6=y
 
-CONFIG_CPU_CP15=y
 
-CONFIG_CPU_CP15_MMU=y
 
-CONFIG_CPU_FREQ=y
 
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
 
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
 
-CONFIG_CPU_FREQ_GOV_COMMON=y
 
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
 
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
 
-CONFIG_CPU_FREQ_STAT=y
 
-CONFIG_CPU_HAS_ASID=y
 
-CONFIG_CPU_PABRT_V7=y
 
-CONFIG_CPU_PM=y
 
-CONFIG_CPU_RMAP=y
 
-CONFIG_CPU_SPECTRE=y
 
-CONFIG_CPU_THUMB_CAPABLE=y
 
-CONFIG_CPU_TLB_V7=y
 
-CONFIG_CPU_V7=y
 
-CONFIG_CRC16=y
 
-# CONFIG_CRC32_SARWATE is not set
 
-CONFIG_CRC32_SLICEBY8=y
 
-CONFIG_CROSS_MEMORY_ATTACH=y
 
-CONFIG_CRYPTO_CRC32=y
 
-CONFIG_CRYPTO_CRC32C=y
 
-CONFIG_CRYPTO_DEFLATE=y
 
-CONFIG_CRYPTO_DEV_MEDIATEK=y
 
-CONFIG_CRYPTO_DRBG=y
 
-CONFIG_CRYPTO_DRBG_HMAC=y
 
-CONFIG_CRYPTO_DRBG_MENU=y
 
-CONFIG_CRYPTO_HASH_INFO=y
 
-CONFIG_CRYPTO_HMAC=y
 
-CONFIG_CRYPTO_HW=y
 
-CONFIG_CRYPTO_JITTERENTROPY=y
 
-CONFIG_CRYPTO_LIB_SHA256=y
 
-CONFIG_CRYPTO_LZO=y
 
-CONFIG_CRYPTO_RNG=y
 
-CONFIG_CRYPTO_RNG2=y
 
-CONFIG_CRYPTO_RNG_DEFAULT=y
 
-CONFIG_CRYPTO_SEQIV=y
 
-CONFIG_CRYPTO_SHA1=y
 
-CONFIG_CRYPTO_SHA256=y
 
-CONFIG_CRYPTO_SHA512=y
 
-CONFIG_CRYPTO_ZSTD=y
 
-CONFIG_DCACHE_WORD_ACCESS=y
 
-CONFIG_DEBUG_ALIGN_RODATA=y
 
-CONFIG_DEBUG_BUGVERBOSE=y
 
-CONFIG_DEBUG_GPIO=y
 
-CONFIG_DEBUG_INFO=y
 
-CONFIG_DEBUG_LL=y
 
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
 
-CONFIG_DEBUG_MISC=y
 
-CONFIG_DEBUG_MT6589_UART0=y
 
-# CONFIG_DEBUG_MT8127_UART0 is not set
 
-# CONFIG_DEBUG_MT8135_UART3 is not set
 
-CONFIG_DEBUG_PREEMPT=y
 
-CONFIG_DEBUG_UART_8250=y
 
-CONFIG_DEBUG_UART_8250_SHIFT=2
 
-CONFIG_DEBUG_UART_PHYS=0x11004000
 
-CONFIG_DEBUG_UART_VIRT=0xf1004000
 
-CONFIG_DEBUG_UNCOMPRESS=y
 
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
 
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
 
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
 
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
 
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
 
-# CONFIG_DEVFREQ_THERMAL is not set
 
-CONFIG_DIMLIB=y
 
-CONFIG_DMADEVICES=y
 
-CONFIG_DMA_ENGINE=y
 
-CONFIG_DMA_OF=y
 
-CONFIG_DMA_OPS=y
 
-CONFIG_DMA_REMAP=y
 
-CONFIG_DMA_SHARED_BUFFER=y
 
-CONFIG_DMA_VIRTUAL_CHANNELS=y
 
-CONFIG_DRM=y
 
-CONFIG_DRM_BRIDGE=y
 
-CONFIG_DRM_DISPLAY_CONNECTOR=y
 
-CONFIG_DRM_FBDEV_EMULATION=y
 
-CONFIG_DRM_FBDEV_OVERALLOC=100
 
-CONFIG_DRM_GEM_CMA_HELPER=y
 
-CONFIG_DRM_GEM_SHMEM_HELPER=y
 
-CONFIG_DRM_KMS_FB_HELPER=y
 
-CONFIG_DRM_KMS_HELPER=y
 
-CONFIG_DRM_LIMA=y
 
-CONFIG_DRM_LVDS_CODEC=y
 
-CONFIG_DRM_MEDIATEK=y
 
-CONFIG_DRM_MEDIATEK_HDMI=y
 
-CONFIG_DRM_MIPI_DSI=y
 
-CONFIG_DRM_PANEL=y
 
-# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
 
-# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
 
-# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
 
-CONFIG_DRM_PANEL_BRIDGE=y
 
-# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
 
-# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
 
-# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
 
-# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
 
-# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
 
-# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
 
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
 
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
 
-# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
 
-# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
 
-# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
 
-CONFIG_DRM_SCHED=y
 
-CONFIG_DRM_SIMPLE_BRIDGE=y
 
-CONFIG_DTC=y
 
-CONFIG_DUMMY_CONSOLE=y
 
-CONFIG_FONT_8x16=y
 
-CONFIG_FONT_8x8=y
 
-CONFIG_FONT_SUPPORT=y
 
-CONFIG_FRAMEBUFFER_CONSOLE=y
 
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 
-CONFIG_EARLY_PRINTK=y
 
-CONFIG_EDAC_ATOMIC_SCRUB=y
 
-CONFIG_EDAC_SUPPORT=y
 
-CONFIG_EINT_MTK=y
 
-CONFIG_ELF_CORE=y
 
-CONFIG_EXT4_FS=y
 
-CONFIG_EXTCON=y
 
-CONFIG_F2FS_FS=y
 
-CONFIG_FB=y
 
-CONFIG_FB_CFB_COPYAREA=y
 
-CONFIG_FB_CFB_FILLRECT=y
 
-CONFIG_FB_CFB_IMAGEBLIT=y
 
-CONFIG_FB_CMDLINE=y
 
-CONFIG_FB_DEFERRED_IO=y
 
-CONFIG_FB_SYS_COPYAREA=y
 
-CONFIG_FB_SYS_FILLRECT=y
 
-CONFIG_FB_SYS_FOPS=y
 
-CONFIG_FB_SYS_IMAGEBLIT=y
 
-CONFIG_FIT_PARTITION=y
 
-CONFIG_FIXED_PHY=y
 
-CONFIG_FIX_EARLYCON_MEM=y
 
-CONFIG_FREEZER=y
 
-CONFIG_FS_IOMAP=y
 
-CONFIG_FS_MBCACHE=y
 
-CONFIG_FW_CACHE=y
 
-CONFIG_FW_LOADER_PAGED_BUF=y
 
-CONFIG_GENERIC_ALLOCATOR=y
 
-CONFIG_GENERIC_BUG=y
 
-CONFIG_GENERIC_CLOCKEVENTS=y
 
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 
-CONFIG_GENERIC_CPU_AUTOPROBE=y
 
-CONFIG_GENERIC_EARLY_IOREMAP=y
 
-CONFIG_GENERIC_GETTIMEOFDAY=y
 
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
 
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
 
-CONFIG_GENERIC_IRQ_MIGRATION=y
 
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
 
-CONFIG_GENERIC_IRQ_SHOW=y
 
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 
-CONFIG_GENERIC_MSI_IRQ=y
 
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 
-CONFIG_GENERIC_PCI_IOMAP=y
 
-CONFIG_GENERIC_PHY=y
 
-CONFIG_GENERIC_PINCONF=y
 
-CONFIG_GENERIC_PINCTRL_GROUPS=y
 
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 
-CONFIG_GENERIC_SCHED_CLOCK=y
 
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
 
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
 
-CONFIG_GENERIC_STRNLEN_USER=y
 
-CONFIG_GENERIC_TIME_VSYSCALL=y
 
-CONFIG_GENERIC_VDSO_32=y
 
-CONFIG_GPIOLIB=y
 
-CONFIG_GRO_CELLS=y
 
-CONFIG_HANDLE_DOMAIN_IRQ=y
 
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
 
-CONFIG_HARDIRQS_SW_RESEND=y
 
-CONFIG_HAS_DMA=y
 
-CONFIG_HAS_IOMEM=y
 
-CONFIG_HAS_IOPORT_MAP=y
 
-CONFIG_HAVE_ARM_ARCH_TIMER=y
 
-CONFIG_HAVE_SMP=y
 
-CONFIG_HDMI=y
 
-CONFIG_HID=y
 
-CONFIG_HIGHMEM=y
 
-CONFIG_HIGHPTE=y
 
-CONFIG_HOTPLUG_CPU=y
 
-CONFIG_HW_CONSOLE=y
 
-CONFIG_HWMON=y
 
-CONFIG_HW_RANDOM=y
 
-CONFIG_HW_RANDOM_MTK=y
 
-CONFIG_HZ_FIXED=0
 
-CONFIG_I2C=y
 
-CONFIG_I2C_ALGOBIT=y
 
-CONFIG_I2C_BOARDINFO=y
 
-CONFIG_I2C_CHARDEV=y
 
-CONFIG_I2C_HID=y
 
-CONFIG_I2C_MT65XX=y
 
-CONFIG_ICPLUS_PHY=y
 
-CONFIG_IIO=y
 
-CONFIG_INITRAMFS_SOURCE=""
 
-CONFIG_INPUT=y
 
-CONFIG_INPUT_EVDEV=y
 
-CONFIG_INPUT_JOYSTICK=y
 
-CONFIG_INPUT_KEYBOARD=y
 
-CONFIG_INPUT_MOUSE=y
 
-CONFIG_INPUT_MOUSEDEV=y
 
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 
-CONFIG_INPUT_TABLET=y
 
-CONFIG_INPUT_TOUCHSCREEN=y
 
-CONFIG_IOMMU_API=y
 
-# CONFIG_IOMMU_DEBUGFS is not set
 
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
 
-CONFIG_IOMMU_IO_PGTABLE=y
 
-CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
 
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
 
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
 
-CONFIG_IOMMU_SUPPORT=y
 
-CONFIG_IO_URING=y
 
-CONFIG_IRQCHIP=y
 
-CONFIG_IRQ_DOMAIN=y
 
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
 
-CONFIG_IRQ_FORCED_THREADING=y
 
-CONFIG_IRQ_WORK=y
 
-CONFIG_JBD2=y
 
-# CONFIG_JOYSTICK_A3D is not set
 
-# CONFIG_JOYSTICK_ADC is not set
 
-# CONFIG_JOYSTICK_ADI is not set
 
-# CONFIG_JOYSTICK_ANALOG is not set
 
-# CONFIG_JOYSTICK_AS5011 is not set
 
-# CONFIG_JOYSTICK_COBRA is not set
 
-# CONFIG_JOYSTICK_DB9 is not set
 
-# CONFIG_JOYSTICK_FSIA6B is not set
 
-# CONFIG_JOYSTICK_GAMECON is not set
 
-# CONFIG_JOYSTICK_GF2K is not set
 
-# CONFIG_JOYSTICK_GRIP is not set
 
-# CONFIG_JOYSTICK_GRIP_MP is not set
 
-# CONFIG_JOYSTICK_GUILLEMOT is not set
 
-# CONFIG_JOYSTICK_IFORCE is not set
 
-# CONFIG_JOYSTICK_INTERACT is not set
 
-# CONFIG_JOYSTICK_JOYDUMP is not set
 
-# CONFIG_JOYSTICK_MAGELLAN is not set
 
-# CONFIG_JOYSTICK_PSXPAD_SPI is not set
 
-# CONFIG_JOYSTICK_PXRC is not set
 
-# CONFIG_JOYSTICK_SIDEWINDER is not set
 
-# CONFIG_JOYSTICK_SPACEBALL is not set
 
-# CONFIG_JOYSTICK_SPACEORB is not set
 
-# CONFIG_JOYSTICK_STINGER is not set
 
-# CONFIG_JOYSTICK_TMDC is not set
 
-# CONFIG_JOYSTICK_TWIDJOY is not set
 
-# CONFIG_JOYSTICK_TURBOGRAFX is not set
 
-# CONFIG_JOYSTICK_WALKERA0701 is not set
 
-# CONFIG_JOYSTICK_WARRIOR is not set
 
-# CONFIG_JOYSTICK_XPAD is not set
 
-# CONFIG_JOYSTICK_ZHENHUA is not set
 
-CONFIG_KALLSYMS=y
 
-CONFIG_KCMP=y
 
-CONFIG_KEYBOARD_MTK_PMIC=y
 
-CONFIG_LCD_CLASS_DEVICE=y
 
-CONFIG_LCD_PLATFORM=y
 
-CONFIG_LEDS_MT6323=y
 
-# CONFIG_LEDS_UBNT_LEDBAR is not set
 
-CONFIG_LIBFDT=y
 
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
 
-CONFIG_LOCK_SPIN_ON_OWNER=y
 
-CONFIG_LOGO=y
 
-CONFIG_LOGO_LINUX_CLUT224=y
 
-# CONFIG_LOGO_LINUX_MONO is not set
 
-# CONFIG_LOGO_LINUX_VGA16 is not set
 
-CONFIG_LZO_COMPRESS=y
 
-CONFIG_LZO_DECOMPRESS=y
 
-# CONFIG_MACH_MT2701 is not set
 
-# CONFIG_MACH_MT6589 is not set
 
-# CONFIG_MACH_MT6592 is not set
 
-CONFIG_MACH_MT7623=y
 
-# CONFIG_MACH_MT7629 is not set
 
-# CONFIG_MACH_MT8127 is not set
 
-# CONFIG_MACH_MT8135 is not set
 
-CONFIG_MAGIC_SYSRQ=y
 
-CONFIG_MAILBOX=y
 
-# CONFIG_MAILBOX_TEST is not set
 
-CONFIG_MDIO_BITBANG=y
 
-CONFIG_MDIO_BUS=y
 
-CONFIG_MDIO_DEVICE=y
 
-CONFIG_MDIO_DEVRES=y
 
-CONFIG_MDIO_GPIO=y
 
-CONFIG_MEDIATEK_GE_PHY=y
 
-CONFIG_MEDIATEK_MT6577_AUXADC=y
 
-CONFIG_MEDIATEK_WATCHDOG=y
 
-CONFIG_MEMFD_CREATE=y
 
-CONFIG_MEMORY=y
 
-CONFIG_MFD_CORE=y
 
-# CONFIG_MFD_HI6421_SPMI is not set
 
-CONFIG_MFD_MT6397=y
 
-CONFIG_MFD_SYSCON=y
 
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
 
-CONFIG_MIGRATION=y
 
-CONFIG_MMC=y
 
-CONFIG_MMC_BLOCK=y
 
-CONFIG_MMC_CQHCI=y
 
-CONFIG_MMC_MTK=y
 
-CONFIG_MMC_SDHCI=y
 
-# CONFIG_MMC_SDHCI_PCI is not set
 
-CONFIG_MMC_SDHCI_PLTFM=y
 
-CONFIG_MODULES_USE_ELF_REL=y
 
-# CONFIG_MOUSE_BCM5974 is not set
 
-# CONFIG_MOUSE_CYAPA is not set
 
-# CONFIG_MOUSE_PS2 is not set
 
-# CONFIG_MOUSE_SERIAL is not set
 
-# CONFIG_MOUSE_VSXXXAA is not set
 
-CONFIG_MTD_CMDLINE_PARTS=y
 
-# CONFIG_MTD_NAND_MTK_BMT is not set
 
-# CONFIG_MTD_PARSER_TRX is not set
 
-CONFIG_MTD_SPI_NOR=y
 
-CONFIG_MTD_SPLIT_FIRMWARE=y
 
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
 
-CONFIG_MTD_UBI=y
 
-CONFIG_MTD_UBI_BEB_LIMIT=20
 
-CONFIG_MTD_UBI_BLOCK=y
 
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
 
-CONFIG_MTK_CMDQ=y
 
-CONFIG_MTK_CMDQ_MBOX=y
 
-CONFIG_MTK_CQDMA=y
 
-CONFIG_MTK_EFUSE=y
 
-# CONFIG_MTK_HSDMA is not set
 
-CONFIG_MTK_INFRACFG=y
 
-CONFIG_MTK_IOMMU=y
 
-CONFIG_MTK_IOMMU_V1=y
 
-CONFIG_MTK_MMSYS=y
 
-CONFIG_MTK_PMIC_WRAP=y
 
-CONFIG_MTK_SCPSYS=y
 
-CONFIG_MTK_SMI=y
 
-# CONFIG_MTK_SPI_NAND is not set
 
-CONFIG_MTK_THERMAL=y
 
-CONFIG_MTK_TIMER=y
 
-# CONFIG_MTK_UART_APDMA is not set
 
-# CONFIG_MUSB_PIO_ONLY is not set
 
-CONFIG_MUTEX_SPIN_ON_OWNER=y
 
-CONFIG_NEED_DMA_MAP_STATE=y
 
-CONFIG_NEED_SG_DMA_LENGTH=y
 
-CONFIG_NEON=y
 
-CONFIG_NET_DEVLINK=y
 
-CONFIG_NET_DSA=y
 
-CONFIG_NET_DSA_MT7530=y
 
-CONFIG_NET_DSA_TAG_MTK=y
 
-CONFIG_NET_FLOW_LIMIT=y
 
-CONFIG_NET_MEDIATEK_SOC=y
 
-CONFIG_NET_SWITCHDEV=y
 
-# CONFIG_NET_VENDOR_AURORA is not set
 
-CONFIG_NET_VENDOR_MEDIATEK=y
 
-# CONFIG_NET_VENDOR_WIZNET is not set
 
-CONFIG_NLS=y
 
-CONFIG_NOP_USB_XCEIV=y
 
-CONFIG_NO_HZ=y
 
-CONFIG_NO_HZ_COMMON=y
 
-CONFIG_NO_HZ_IDLE=y
 
-CONFIG_NR_CPUS=4
 
-CONFIG_NVMEM=y
 
-# CONFIG_NVMEM_SPMI_SDAM is not set
 
-CONFIG_NVMEM_SYSFS=y
 
-CONFIG_OF=y
 
-CONFIG_OF_ADDRESS=y
 
-CONFIG_OF_CONFIGFS=y
 
-CONFIG_OF_EARLY_FLATTREE=y
 
-CONFIG_OF_FLATTREE=y
 
-CONFIG_OF_GPIO=y
 
-CONFIG_OF_IOMMU=y
 
-CONFIG_OF_IRQ=y
 
-CONFIG_OF_KOBJ=y
 
-CONFIG_OF_MDIO=y
 
-CONFIG_OF_NET=y
 
-CONFIG_OF_OVERLAY=y
 
-CONFIG_OLD_SIGACTION=y
 
-CONFIG_OLD_SIGSUSPEND3=y
 
-CONFIG_PADATA=y
 
-CONFIG_PAGE_OFFSET=0xC0000000
 
-CONFIG_PCI=y
 
-CONFIG_PCIEAER=y
 
-CONFIG_PCIEPORTBUS=y
 
-CONFIG_PCIE_MEDIATEK=y
 
-CONFIG_PCIE_PME=y
 
-CONFIG_PCI_DOMAINS=y
 
-CONFIG_PCI_DOMAINS_GENERIC=y
 
-CONFIG_PCI_MSI=y
 
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
 
-CONFIG_PERF_USE_VMALLOC=y
 
-CONFIG_PGTABLE_LEVELS=2
 
-CONFIG_PHYLIB=y
 
-CONFIG_PHYLINK=y
 
-CONFIG_PHY_MTK_HDMI=y
 
-CONFIG_PHY_MTK_TPHY=y
 
-# CONFIG_PHY_MTK_UFS is not set
 
-# CONFIG_PHY_MTK_XSPHY is not set
 
-CONFIG_PINCTRL=y
 
-CONFIG_PINCTRL_MT2701=y
 
-CONFIG_PINCTRL_MT6397=y
 
-CONFIG_PINCTRL_MT7623=y
 
-CONFIG_PINCTRL_MTK=y
 
-CONFIG_PINCTRL_MTK_MOORE=y
 
-CONFIG_PINCTRL_MTK_V2=y
 
-CONFIG_PM=y
 
-CONFIG_PM_CLK=y
 
-CONFIG_PM_DEVFREQ=y
 
-# CONFIG_PM_DEVFREQ_EVENT is not set
 
-CONFIG_PM_GENERIC_DOMAINS=y
 
-CONFIG_PM_GENERIC_DOMAINS_OF=y
 
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
 
-CONFIG_PM_OPP=y
 
-CONFIG_PM_SLEEP=y
 
-CONFIG_PM_SLEEP_SMP=y
 
-CONFIG_POWER_RESET=y
 
-# CONFIG_POWER_RESET_MT6323 is not set
 
-CONFIG_POWER_SUPPLY=y
 
-CONFIG_POWER_SUPPLY_HWMON=y
 
-CONFIG_PREEMPT=y
 
-CONFIG_PREEMPTION=y
 
-CONFIG_PREEMPT_COUNT=y
 
-# CONFIG_PREEMPT_NONE is not set
 
-CONFIG_PREEMPT_RCU=y
 
-CONFIG_PRINTK_TIME=y
 
-CONFIG_PWM=y
 
-CONFIG_PWM_MEDIATEK=y
 
-# CONFIG_PWM_MTK_DISP is not set
 
-CONFIG_PWM_SYSFS=y
 
-CONFIG_RAS=y
 
-CONFIG_RATIONAL=y
 
-CONFIG_REGMAP=y
 
-CONFIG_REGMAP_MMIO=y
 
-CONFIG_REGULATOR=y
 
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
 
-CONFIG_REGULATOR_GPIO=y
 
-CONFIG_REGULATOR_MT6323=y
 
-# CONFIG_REGULATOR_MT6358 is not set
 
-# CONFIG_REGULATOR_MT6380 is not set
 
-# CONFIG_REGULATOR_MT6397 is not set
 
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
 
-# CONFIG_REGULATOR_QCOM_SPMI is not set
 
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
 
-CONFIG_RESET_CONTROLLER=y
 
-CONFIG_RFS_ACCEL=y
 
-CONFIG_RPS=y
 
-CONFIG_RTC_CLASS=y
 
-# CONFIG_RTC_DRV_MT6397 is not set
 
-# CONFIG_RTC_DRV_MT7622 is not set
 
-CONFIG_RTC_I2C_AND_SPI=y
 
-CONFIG_RTC_MC146818_LIB=y
 
-# CONFIG_RTL8367S_GSW is not set
 
-CONFIG_RWSEM_SPIN_ON_OWNER=y
 
-# CONFIG_SERIAL_8250_DMA is not set
 
-CONFIG_SERIAL_8250_FSL=y
 
-CONFIG_SERIAL_8250_MT6577=y
 
-CONFIG_SERIAL_8250_NR_UARTS=4
 
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 
-CONFIG_SERIAL_MCTRL_GPIO=y
 
-CONFIG_SGL_ALLOC=y
 
-CONFIG_SMP=y
 
-# CONFIG_SMP_ON_UP is not set
 
-# CONFIG_SND_SOC_MT6359 is not set
 
-CONFIG_SPARSE_IRQ=y
 
-CONFIG_SPI=y
 
-CONFIG_SPI_BITBANG=y
 
-CONFIG_SPI_MASTER=y
 
-CONFIG_SPI_MEM=y
 
-CONFIG_SPI_MT65XX=y
 
-# CONFIG_SPI_MTK_NOR is not set
 
-CONFIG_SPMI=y
 
-# CONFIG_SPMI_HISI3670 is not set
 
-CONFIG_SRCU=y
 
-# CONFIG_STRIP_ASM_SYMS is not set
 
-CONFIG_SUSPEND=y
 
-CONFIG_SUSPEND_FREEZER=y
 
-CONFIG_SWCONFIG=y
 
-CONFIG_SWPHY=y
 
-CONFIG_SWP_EMULATE=y
 
-CONFIG_SYNC_FILE=y
 
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 
-# CONFIG_TABLET_SERIAL_WACOM4 is not set
 
-# CONFIG_TABLET_USB_ACECAD is not set
 
-# CONFIG_TABLET_USB_AIPTEK is not set
 
-# CONFIG_TABLET_USB_GTCO is not set
 
-# CONFIG_TABLET_USB_HANWANG is not set
 
-# CONFIG_TABLET_USB_KBTAB is not set
 
-# CONFIG_TABLET_USB_PEGASUS is not set
 
-CONFIG_THERMAL=y
 
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
 
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
 
-CONFIG_THERMAL_GOV_STEP_WISE=y
 
-CONFIG_THERMAL_OF=y
 
-CONFIG_TICK_CPU_ACCOUNTING=y
 
-CONFIG_TIMER_OF=y
 
-CONFIG_TIMER_PROBE=y
 
-CONFIG_TOUCHSCREEN_EDT_FT5X06=y
 
-CONFIG_TOUCHSCREEN_PROPERTIES=y
 
-CONFIG_TREE_RCU=y
 
-CONFIG_TREE_SRCU=y
 
-# CONFIG_UACCE is not set
 
-CONFIG_UBIFS_FS=y
 
-CONFIG_UEVENT_HELPER_PATH=""
 
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 
-CONFIG_UNINLINE_SPIN_UNLOCK=y
 
-CONFIG_UNWINDER_ARM=y
 
-CONFIG_USB=y
 
-CONFIG_USB_COMMON=y
 
-CONFIG_USB_F_ACM=y
 
-CONFIG_USB_F_ECM=y
 
-CONFIG_USB_F_MASS_STORAGE=y
 
-CONFIG_USB_GADGET=y
 
-CONFIG_USB_GPIO_VBUS=y
 
-CONFIG_USB_G_MULTI=y
 
-CONFIG_USB_G_MULTI_CDC=y
 
-# CONFIG_USB_G_MULTI_RNDIS is not set
 
-CONFIG_USB_HID=y
 
-CONFIG_USB_HIDDEV=y
 
-CONFIG_USB_INVENTRA_DMA=y
 
-CONFIG_USB_LIBCOMPOSITE=y
 
-CONFIG_USB_MUSB_DUAL_ROLE=y
 
-# CONFIG_USB_MUSB_GADGET is not set
 
-CONFIG_USB_MUSB_HDRC=y
 
-# CONFIG_USB_MUSB_HOST is not set
 
-CONFIG_USB_MUSB_MEDIATEK=y
 
-CONFIG_USB_OTG=y
 
-CONFIG_USB_PHY=y
 
-CONFIG_USB_ROLE_SWITCH=y
 
-CONFIG_USB_SUPPORT=y
 
-CONFIG_USB_U_ETHER=y
 
-CONFIG_USB_U_SERIAL=y
 
-CONFIG_USB_XHCI_HCD=y
 
-CONFIG_USB_XHCI_MTK=y
 
-CONFIG_USB_XHCI_PLATFORM=y
 
-CONFIG_USE_OF=y
 
-CONFIG_VFP=y
 
-CONFIG_VFPv3=y
 
-CONFIG_VIDEOMODE_HELPERS=y
 
-CONFIG_VM_EVENT_COUNTERS=y
 
-CONFIG_VT=y
 
-CONFIG_VT_CONSOLE=y
 
-CONFIG_VT_CONSOLE_SLEEP=y
 
-CONFIG_VT_HW_CONSOLE_BINDING=y
 
-CONFIG_WATCHDOG_CORE=y
 
-CONFIG_XPS=y
 
-CONFIG_XXHASH=y
 
-CONFIG_XZ_DEC_ARM=y
 
-CONFIG_XZ_DEC_BCJ=y
 
-CONFIG_ZBOOT_ROM_BSS=0
 
-CONFIG_ZBOOT_ROM_TEXT=0
 
-CONFIG_ZLIB_DEFLATE=y
 
-CONFIG_ZLIB_INFLATE=y
 
-CONFIG_ZSTD_COMPRESS=y
 
-CONFIG_ZSTD_DECOMPRESS=y

+ 0 - 305
target/linux/mediatek/mt7629/config-5.10
View File 

@@ -1,305 +0,0 @@
 
-CONFIG_ALIGNMENT_TRAP=y
 
-CONFIG_ARCH_32BIT_OFF_T=y
 
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 
-CONFIG_ARCH_KEEP_MEMBLOCK=y
 
-CONFIG_ARCH_MEDIATEK=y
 
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 
-CONFIG_ARCH_MULTIPLATFORM=y
 
-CONFIG_ARCH_MULTI_V6_V7=y
 
-CONFIG_ARCH_MULTI_V7=y
 
-CONFIG_ARCH_NR_GPIO=0
 
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
 
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
 
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
 
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
-CONFIG_ARM=y
 
-CONFIG_ARM_GIC=y
 
-CONFIG_ARM_HAS_SG_CHAIN=y
 
-CONFIG_ARM_HEAVY_MB=y
 
-CONFIG_ARM_L1_CACHE_SHIFT=6
 
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
 
-CONFIG_ARM_PATCH_IDIV=y
 
-CONFIG_ARM_PATCH_PHYS_VIRT=y
 
-CONFIG_ARM_THUMB=y
 
-CONFIG_ARM_UNWIND=y
 
-CONFIG_ARM_VIRT_EXT=y
 
-CONFIG_ATAGS=y
 
-CONFIG_AUTO_ZRELADDR=y
 
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
 
-CONFIG_BLK_DEV_SD=y
 
-CONFIG_BLK_MQ_PCI=y
 
-CONFIG_BLK_PM=y
 
-CONFIG_BLK_SCSI_REQUEST=y
 
-CONFIG_BSD_PROCESS_ACCT=y
 
-CONFIG_BSD_PROCESS_ACCT_V3=y
 
-CONFIG_CACHE_L2X0=y
 
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
 
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 
-CONFIG_CHR_DEV_SCH=y
 
-CONFIG_CLKDEV_LOOKUP=y
 
-CONFIG_CLKSRC_MMIO=y
 
-CONFIG_CLONE_BACKWARDS=y
 
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
 
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
 
-CONFIG_COMMON_CLK=y
 
-CONFIG_COMMON_CLK_MEDIATEK=y
 
-# CONFIG_COMMON_CLK_MT2701 is not set
 
-# CONFIG_COMMON_CLK_MT7622 is not set
 
-CONFIG_COMMON_CLK_MT7629=y
 
-CONFIG_COMMON_CLK_MT7629_ETHSYS=y
 
-CONFIG_COMMON_CLK_MT7629_HIFSYS=y
 
-# CONFIG_COMMON_CLK_MT8135 is not set
 
-# CONFIG_COMMON_CLK_MT8173 is not set
 
-CONFIG_COMMON_CLK_MT8516=y
 
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
 
-CONFIG_COMPAT_32BIT_TIME=y
 
-CONFIG_CPU_32v6K=y
 
-CONFIG_CPU_32v7=y
 
-CONFIG_CPU_ABRT_EV7=y
 
-CONFIG_CPU_CACHE_V7=y
 
-CONFIG_CPU_CACHE_VIPT=y
 
-CONFIG_CPU_COPY_V6=y
 
-CONFIG_CPU_CP15=y
 
-CONFIG_CPU_CP15_MMU=y
 
-CONFIG_CPU_HAS_ASID=y
 
-CONFIG_CPU_IDLE=y
 
-CONFIG_CPU_IDLE_GOV_MENU=y
 
-CONFIG_CPU_PABRT_V7=y
 
-CONFIG_CPU_PM=y
 
-CONFIG_CPU_RMAP=y
 
-CONFIG_CPU_SPECTRE=y
 
-CONFIG_CPU_THUMB_CAPABLE=y
 
-CONFIG_CPU_TLB_V7=y
 
-CONFIG_CPU_V7=y
 
-CONFIG_CRC16=y
 
-CONFIG_CRYPTO_DEFLATE=y
 
-CONFIG_CRYPTO_HASH_INFO=y
 
-CONFIG_CRYPTO_LZO=y
 
-CONFIG_CRYPTO_RNG2=y
 
-CONFIG_CRYPTO_ZSTD=y
 
-CONFIG_DCACHE_WORD_ACCESS=y
 
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
 
-CONFIG_DEBUG_MISC=y
 
-CONFIG_DEFAULT_HOSTNAME="(mt7629)"
 
-CONFIG_DIMLIB=y
 
-CONFIG_DMA_OPS=y
 
-CONFIG_DMA_REMAP=y
 
-CONFIG_DTC=y
 
-CONFIG_EDAC_ATOMIC_SCRUB=y
 
-CONFIG_EDAC_SUPPORT=y
 
-CONFIG_EINT_MTK=y
 
-CONFIG_FIXED_PHY=y
 
-CONFIG_FIX_EARLYCON_MEM=y
 
-CONFIG_FW_LOADER_PAGED_BUF=y
 
-CONFIG_GENERIC_ALLOCATOR=y
 
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
 
-CONFIG_GENERIC_BUG=y
 
-CONFIG_GENERIC_CLOCKEVENTS=y
 
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 
-CONFIG_GENERIC_CPU_AUTOPROBE=y
 
-CONFIG_GENERIC_EARLY_IOREMAP=y
 
-CONFIG_GENERIC_GETTIMEOFDAY=y
 
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
 
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
 
-CONFIG_GENERIC_IRQ_MIGRATION=y
 
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
 
-CONFIG_GENERIC_IRQ_SHOW=y
 
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 
-CONFIG_GENERIC_MSI_IRQ=y
 
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 
-CONFIG_GENERIC_PCI_IOMAP=y
 
-CONFIG_GENERIC_PHY=y
 
-CONFIG_GENERIC_PINCONF=y
 
-CONFIG_GENERIC_PINCTRL_GROUPS=y
 
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 
-CONFIG_GENERIC_SCHED_CLOCK=y
 
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
 
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
 
-CONFIG_GENERIC_STRNLEN_USER=y
 
-CONFIG_GENERIC_TIME_VSYSCALL=y
 
-CONFIG_GENERIC_VDSO_32=y
 
-CONFIG_GPIOLIB=y
 
-CONFIG_HANDLE_DOMAIN_IRQ=y
 
-# CONFIG_HARDENED_USERCOPY is not set
 
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
 
-CONFIG_HARDIRQS_SW_RESEND=y
 
-CONFIG_HAS_DMA=y
 
-CONFIG_HAS_IOMEM=y
 
-CONFIG_HAS_IOPORT_MAP=y
 
-CONFIG_HAVE_SMP=y
 
-CONFIG_HOTPLUG_CPU=y
 
-CONFIG_HW_RANDOM=y
 
-CONFIG_HW_RANDOM_MTK=y
 
-CONFIG_HZ_FIXED=0
 
-CONFIG_INITRAMFS_SOURCE=""
 
-CONFIG_IO_URING=y
 
-CONFIG_IRQCHIP=y
 
-CONFIG_IRQ_DOMAIN=y
 
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
 
-CONFIG_IRQ_FORCED_THREADING=y
 
-CONFIG_IRQ_TIME_ACCOUNTING=y
 
-CONFIG_IRQ_WORK=y
 
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
 
-# CONFIG_LEDS_UBNT_LEDBAR is not set
 
-CONFIG_LIBFDT=y
 
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
 
-CONFIG_LOCK_SPIN_ON_OWNER=y
 
-CONFIG_LZO_COMPRESS=y
 
-CONFIG_LZO_DECOMPRESS=y
 
-# CONFIG_MACH_MT2701 is not set
 
-# CONFIG_MACH_MT6589 is not set
 
-# CONFIG_MACH_MT6592 is not set
 
-# CONFIG_MACH_MT7623 is not set
 
-CONFIG_MACH_MT7629=y
 
-# CONFIG_MACH_MT8127 is not set
 
-# CONFIG_MACH_MT8135 is not set
 
-CONFIG_MDIO_BUS=y
 
-CONFIG_MDIO_DEVICE=y
 
-CONFIG_MDIO_DEVRES=y
 
-# CONFIG_MEDIATEK_MT6577_AUXADC is not set
 
-CONFIG_MEDIATEK_WATCHDOG=y
 
-CONFIG_MEMFD_CREATE=y
 
-CONFIG_MFD_SYSCON=y
 
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
 
-CONFIG_MIGRATION=y
 
-CONFIG_MODULES_USE_ELF_REL=y
 
-CONFIG_MTD_NAND_CORE=y
 
-CONFIG_MTD_NAND_ECC=y
 
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
 
-CONFIG_MTD_NAND_MTK=y
 
-CONFIG_MTD_NAND_MTK_BMT=y
 
-# CONFIG_MTD_PARSER_TRX is not set
 
-CONFIG_MTD_RAW_NAND=y
 
-CONFIG_MTD_SPI_NAND=y
 
-CONFIG_MTD_SPI_NOR=y
 
-CONFIG_MTD_SPLIT_FIRMWARE=y
 
-CONFIG_MTD_SPLIT_FIT_FW=y
 
-CONFIG_MTD_UBI=y
 
-CONFIG_MTD_UBI_BEB_LIMIT=20
 
-CONFIG_MTD_UBI_BLOCK=y
 
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
 
-# CONFIG_MTK_CMDQ is not set
 
-# CONFIG_MTK_EFUSE is not set
 
-CONFIG_MTK_INFRACFG=y
 
-# CONFIG_MTK_PMIC_WRAP is not set
 
-CONFIG_MTK_SCPSYS=y
 
-CONFIG_MTK_SPI_NAND=y
 
-# CONFIG_MTK_THERMAL is not set
 
-CONFIG_MTK_TIMER=y
 
-CONFIG_MUTEX_SPIN_ON_OWNER=y
 
-CONFIG_NEED_DMA_MAP_STATE=y
 
-CONFIG_NETFILTER=y
 
-CONFIG_NET_FLOW_LIMIT=y
 
-CONFIG_NET_MEDIATEK_SOC=y
 
-CONFIG_NET_VENDOR_MEDIATEK=y
 
-CONFIG_NLS=y
 
-CONFIG_NO_HZ_COMMON=y
 
-CONFIG_NO_HZ_IDLE=y
 
-CONFIG_NR_CPUS=2
 
-CONFIG_NVMEM=y
 
-CONFIG_NVMEM_SYSFS=y
 
-CONFIG_OF=y
 
-CONFIG_OF_ADDRESS=y
 
-CONFIG_OF_EARLY_FLATTREE=y
 
-CONFIG_OF_FLATTREE=y
 
-CONFIG_OF_GPIO=y
 
-CONFIG_OF_IRQ=y
 
-CONFIG_OF_KOBJ=y
 
-CONFIG_OF_MDIO=y
 
-CONFIG_OF_NET=y
 
-CONFIG_OLD_SIGACTION=y
 
-CONFIG_OLD_SIGSUSPEND3=y
 
-CONFIG_OUTER_CACHE=y
 
-CONFIG_OUTER_CACHE_SYNC=y
 
-CONFIG_PADATA=y
 
-CONFIG_PAGE_OFFSET=0xC0000000
 
-CONFIG_PCI=y
 
-CONFIG_PCIEAER=y
 
-CONFIG_PCIEPORTBUS=y
 
-CONFIG_PCIE_MEDIATEK=y
 
-CONFIG_PCIE_PME=y
 
-CONFIG_PCI_DOMAINS=y
 
-CONFIG_PCI_DOMAINS_GENERIC=y
 
-CONFIG_PCI_MSI=y
 
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
 
-CONFIG_PERF_USE_VMALLOC=y
 
-CONFIG_PGTABLE_LEVELS=2
 
-CONFIG_PHYLIB=y
 
-CONFIG_PHYLINK=y
 
-CONFIG_PHY_MTK_TPHY=y
 
-# CONFIG_PHY_MTK_UFS is not set
 
-# CONFIG_PHY_MTK_XSPHY is not set
 
-CONFIG_PINCTRL=y
 
-CONFIG_PINCTRL_MT7629=y
 
-CONFIG_PINCTRL_MTK_MOORE=y
 
-CONFIG_PINCTRL_MTK_V2=y
 
-CONFIG_PM=y
 
-CONFIG_PM_CLK=y
 
-CONFIG_PM_GENERIC_DOMAINS=y
 
-CONFIG_PM_GENERIC_DOMAINS_OF=y
 
-CONFIG_PWM=y
 
-CONFIG_PWM_MEDIATEK=y
 
-# CONFIG_PWM_MTK_DISP is not set
 
-CONFIG_PWM_SYSFS=y
 
-CONFIG_RAS=y
 
-CONFIG_RATIONAL=y
 
-CONFIG_REGMAP=y
 
-CONFIG_REGMAP_MMIO=y
 
-CONFIG_RESET_CONTROLLER=y
 
-CONFIG_RFS_ACCEL=y
 
-CONFIG_RPS=y
 
-# CONFIG_RTL8367S_GSW is not set
 
-CONFIG_RWSEM_SPIN_ON_OWNER=y
 
-CONFIG_SCSI=y
 
-CONFIG_SERIAL_8250_FSL=y
 
-CONFIG_SERIAL_8250_MT6577=y
 
-CONFIG_SERIAL_8250_NR_UARTS=3
 
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
 
-CONFIG_SERIAL_MCTRL_GPIO=y
 
-CONFIG_SERIAL_OF_PLATFORM=y
 
-CONFIG_SGL_ALLOC=y
 
-CONFIG_SG_POOL=y
 
-CONFIG_SMP=y
 
-CONFIG_SMP_ON_UP=y
 
-CONFIG_SPARSE_IRQ=y
 
-CONFIG_SPI=y
 
-CONFIG_SPI_MASTER=y
 
-CONFIG_SPI_MEM=y
 
-CONFIG_SPI_MT65XX=y
 
-CONFIG_SPI_MTK_NOR=y
 
-CONFIG_SRCU=y
 
-CONFIG_STACKTRACE=y
 
-# CONFIG_SWAP is not set
 
-CONFIG_SWCONFIG=y
 
-CONFIG_SWPHY=y
 
-CONFIG_SWP_EMULATE=y
 
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 
-CONFIG_TICK_CPU_ACCOUNTING=y
 
-CONFIG_TIMER_OF=y
 
-CONFIG_TIMER_PROBE=y
 
-CONFIG_TREE_RCU=y
 
-CONFIG_TREE_SRCU=y
 
-CONFIG_UBIFS_FS=y
 
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 
-CONFIG_UNWINDER_ARM=y
 
-CONFIG_USB=y
 
-CONFIG_USB_COMMON=y
 
-CONFIG_USB_SUPPORT=y
 
-CONFIG_USB_XHCI_HCD=y
 
-CONFIG_USB_XHCI_MTK=y
 
-# CONFIG_USB_XHCI_PLATFORM is not set
 
-CONFIG_USE_OF=y
 
-# CONFIG_VFP is not set
 
-CONFIG_WATCHDOG_CORE=y
 
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
 
-CONFIG_XPS=y
 
-CONFIG_XXHASH=y
 
-CONFIG_XZ_DEC_ARM=y
 
-CONFIG_XZ_DEC_BCJ=y
 
-CONFIG_ZBOOT_ROM_BSS=0
 
-CONFIG_ZBOOT_ROM_TEXT=0
 
-CONFIG_ZLIB_DEFLATE=y
 
-CONFIG_ZLIB_INFLATE=y
 
-CONFIG_ZSTD_COMPRESS=y
 
-CONFIG_ZSTD_DECOMPRESS=y

+ 0 - 119
target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch
View File 

@@ -1,119 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-@@ -1,7 +1,6 @@
 
- /*
 
-- * Copyright (c) 2017 MediaTek Inc.
 
-- * Author: Ming Huang <[email protected]>
 
-- *	   Sean Wang <[email protected]>
 
-+ * Copyright (c) 2018 MediaTek Inc.
 
-+ * Author: Ryder Lee <[email protected]>
 
-  *
 
-  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 
-  */
 
-@@ -23,7 +22,7 @@
 
- 
- 	chosen {
 
- 		stdout-path = "serial0:115200n8";
 
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
 
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
 
- 	};
 
- 
- 	cpus {
 
-@@ -40,23 +39,22 @@
 
- 
- 	gpio-keys {
 
- 		compatible = "gpio-keys";
 
--		poll-interval = <100>;
 
- 
- 		factory {
 
- 			label = "factory";
 
- 			linux,code = <BTN_0>;
 
--			gpios = <&pio 0 0>;
 
-+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
 
- 		};
 
- 
- 		wps {
 
- 			label = "wps";
 
- 			linux,code = <KEY_WPS_BUTTON>;
 
--			gpios = <&pio 102 0>;
 
-+			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
 
- 		};
 
- 	};
 
- 
- 	memory {
 
--		reg = <0 0x40000000 0 0x20000000>;
 
-+		reg = <0 0x40000000 0 0x40000000>;
 
- 	};
 
- 
- 	reg_1p8v: regulator-1p8v {
 
-@@ -132,22 +130,22 @@
 
- 
- 				port@0 {
 
- 					reg = <0>;
 
--					label = "lan0";
 
-+					label = "lan1";
 
- 				};
 
- 
- 				port@1 {
 
- 					reg = <1>;
 
--					label = "lan1";
 
-+					label = "lan2";
 
- 				};
 
- 
- 				port@2 {
 
- 					reg = <2>;
 
--					label = "lan2";
 
-+					label = "lan3";
 
- 				};
 
- 
- 				port@3 {
 
- 					reg = <3>;
 
--					label = "lan3";
 
-+					label = "lan4";
 
- 				};
 
- 
- 				port@4 {
 
-@@ -236,15 +234,28 @@
 
- 
- &pcie {
 
- 	pinctrl-names = "default";
 
--	pinctrl-0 = <&pcie0_pins>;
 
-+	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 
- 	status = "okay";
 
- 
- 	pcie@0,0 {
 
- 		status = "okay";
 
- 	};
 
-+
 
-+	pcie@1,0 {
 
-+		status = "okay";
 
-+	};
 
- };
 
- 
- &pio {
 
-+	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 
-+	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
 
-+	 */
 
-+	asm_sel {
 
-+		gpio-hog;
 
-+		gpios = <90 GPIO_ACTIVE_HIGH>;
 
-+		output-high;
 
-+	};
 
-+
 
- 	/* eMMC is shared pin with parallel NAND */
 
- 	emmc_pins_default: emmc-pins-default {
 
- 		mux {
 
-@@ -511,11 +522,11 @@
 
- };
 
- 
- &sata {
 
--	status = "okay";
 
-+	status = "disabled";
 
- };
 
- 
- &sata_phy {
 
--	status = "okay";
 
-+	status = "disabled";
 
- };
 
- 
- &spi0 {

+ 0 - 60
target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch
View File 

@@ -1,60 +0,0 @@
 
---- a/arch/arm/boot/dts/mt7629-rfb.dts
 
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
 
-@@ -18,6 +18,7 @@
 
- 
- 	chosen {
 
- 		stdout-path = "serial0:115200n8";
 
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
 
- 	};
 
- 
- 	gpio-keys {
 
-@@ -70,6 +71,10 @@
 
- 		compatible = "mediatek,eth-mac";
 
- 		reg = <0>;
 
- 		phy-mode = "2500base-x";
 
-+
 
-+		nvmem-cells = <&macaddr_factory_2a>;
 
-+		nvmem-cell-names = "mac-address";
 
-+
 
- 		fixed-link {
 
- 			speed = <2500>;
 
- 			full-duplex;
 
-@@ -82,6 +87,9 @@
 
- 		reg = <1>;
 
- 		phy-mode = "gmii";
 
- 		phy-handle = <&phy0>;
 
-+
 
-+		nvmem-cells = <&macaddr_factory_24>;
 
-+		nvmem-cell-names = "mac-address";
 
- 	};
 
- 
- 	mdio: mdio-bus {
 
-@@ -133,8 +141,9 @@
 
- 			};
 
- 
- 			partition@b0000 {
 
--				label = "kernel";
 
-+				label = "firmware";
 
- 				reg = <0xb0000 0xb50000>;
 
-+				compatible = "denx,fit";
 
- 			};
 
- 		};
 
- 	};
 
-@@ -272,3 +281,17 @@
 
- 	pinctrl-0 = <&watchdog_pins>;
 
- 	status = "okay";
 
- };
 
-+
 
-+&factory {
 
-+	compatible = "nvmem-cells";
 
-+	#address-cells = <1>;
 
-+	#size-cells = <1>;
 
-+
 
-+	macaddr_factory_24: macaddr@24 {
 
-+		reg = <0x24 0x6>;
 
-+	};
 
-+
 
-+	macaddr_factory_2a: macaddr@2a {
 
-+		reg = <0x2a 0x6>;
 
-+	};
 
-+};

+ 0 - 25
target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch
View File 

@@ -1,25 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-@@ -111,7 +111,7 @@
 
- 	};
 
- 
- 	psci {
 
--		compatible  = "arm,psci-0.2";
 
-+		compatible  = "arm,psci-1.0";
 
- 		method      = "smc";
 
- 	};
 
- 
-@@ -127,6 +127,13 @@
 
- 		#size-cells = <2>;
 
- 		ranges;
 
- 
-+		/* 64 KiB reserved for ramoops/pstore */
 
-+		ramoops@42ff0000 {
 
-+			compatible = "ramoops";
 
-+			reg = <0 0x42ff0000 0 0x10000>;
 
-+			record-size = <0x1000>;
 
-+		};
 
-+
 
- 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 
- 		secmon_reserved: secmon@43000000 {
 
- 			reg = <0 0x43000000 0 0x30000>;

+ 0 - 10
target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch
View File 

@@ -1,10 +0,0 @@
 
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-@@ -19,6 +19,7 @@
 
- 
- 	chosen {
 
- 		stdout-path = "serial2:115200n8";
 
-+		bootargs = "console=ttyS2,115200n8 console=tty1";
 
- 	};
 
- 
- 	connector {

+ 0 - 11
target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch
View File 

@@ -1,11 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-@@ -22,7 +22,7 @@
 
- 
- 	chosen {
 
- 		stdout-path = "serial0:115200n8";
 
--		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
 
-+		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
 
- 	};
 
- 
- 	cpus {

+ 0 - 37
target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch
View File 

@@ -1,37 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-@@ -18,6 +18,7 @@
 
- 
- 	aliases {
 
- 		serial0 = &uart0;
 
-+		ethernet0 = &gmac0;
 
- 	};
 
- 
- 	chosen {
 
-@@ -160,22 +161,22 @@
 
- 
- 				port@1 {
 
- 					reg = <1>;
 
--					label = "lan0";
 
-+					label = "lan1";
 
- 				};
 
- 
- 				port@2 {
 
- 					reg = <2>;
 
--					label = "lan1";
 
-+					label = "lan2";
 
- 				};
 
- 
- 				port@3 {
 
- 					reg = <3>;
 
--					label = "lan2";
 
-+					label = "lan3";
 
- 				};
 
- 
- 				port@4 {
 
- 					reg = <4>;
 
--					label = "lan3";
 
-+					label = "lan4";
 
- 				};
 
- 
- 				port@6 {

+ 0 - 56
target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch
View File 

@@ -1,56 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-@@ -19,6 +19,10 @@
 
- 	aliases {
 
- 		serial0 = &uart0;
 
- 		ethernet0 = &gmac0;
 
-+		led-boot = &led_system_green;
 
-+		led-failsafe = &led_system_blue;
 
-+		led-running = &led_system_green;
 
-+		led-upgrade = &led_system_blue;
 
- 	};
 
- 
- 	chosen {
 
-@@ -42,8 +46,8 @@
 
- 		compatible = "gpio-keys";
 
- 
- 		factory {
 
--			label = "factory";
 
--			linux,code = <BTN_0>;
 
-+			label = "reset";
 
-+			linux,code = <KEY_RESTART>;
 
- 			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
 
- 		};
 
- 
-@@ -57,17 +61,25 @@
 
- 	leds {
 
- 		compatible = "gpio-leds";
 
- 
--		green {
 
--			label = "bpi-r64:pio:green";
 
--			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
 
-+		led_system_blue: blue {
 
-+			label = "bpi-r64:pio:blue";
 
-+			gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
 
- 			default-state = "off";
 
- 		};
 
- 
--		red {
 
--			label = "bpi-r64:pio:red";
 
--			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
 
-+		led_system_green: green {
 
-+			label = "bpi-r64:pio:green";
 
-+			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
 
- 			default-state = "off";
 
- 		};
 
-+
 
-+/*
 
-+ *		red {
 
-+ *			label = "bpi-r64:pio:red";
 
-+ *			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
 
-+ *			default-state = "off";
 
-+ *		};
 
-+ */
 
- 	};
 
- 
- 	memory {

+ 0 - 21
target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch
View File 

@@ -1,21 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-@@ -559,12 +559,16 @@
 
- 	status = "okay";
 
- };
 
- 
-+&rtc {
 
-+	status = "disabled";
 
-+};
 
-+
 
- &sata {
 
--	status = "disable";
 
-+	status = "disabled";
 
- };
 
- 
- &sata_phy {
 
--	status = "disable";
 
-+	status = "disabled";
 
- };
 
- 
- &spi0 {

+ 0 - 41
target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch
View File 

@@ -1,41 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-@@ -259,14 +259,32 @@
 
- 	status = "disabled";
 
- };
 
- 
--&nor_flash {
 
-+&snand {
 
- 	pinctrl-names = "default";
 
--	pinctrl-0 = <&spi_nor_pins>;
 
--	status = "disabled";
 
-+	pinctrl-0 = <&serial_nand_pins>;
 
-+	mediatek,quad-spi;
 
-+	status = "okay";
 
-+	partitions {
 
-+		compatible = "fixed-partitions";
 
-+		#address-cells = <1>;
 
-+		#size-cells = <1>;
 
-+
 
-+		partition@0 {
 
-+			label = "bl2";
 
-+			reg = <0x0 0x80000>;
 
-+			read-only;
 
-+		};
 
-+
 
-+		partition@80000 {
 
-+			label = "fip";
 
-+			reg = <0x80000 0x200000>;
 
-+			read-only;
 
-+		};
 
- 
--	flash@0 {
 
--		compatible = "jedec,spi-nor";
 
--		reg = <0>;
 
-+		partition@280000 {
 
-+			label = "ubi";
 
-+			reg = <0x280000 0x7d80000>;
 
-+		};
 
- 	};
 
- };
 
-

+ 0 - 77
target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch
View File 

@@ -1,77 +0,0 @@
 
-From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
 
-From: Xiangsheng Hou <[email protected]>
 
-Date: Thu, 6 Jun 2019 16:29:04 +0800
 
-Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
 
-
 
-Signed-off-by: Xiangsheng Hou <[email protected]>
 
----
 
- arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
 
- arch/arm/boot/dts/mt7629.dtsi    | 22 ++++++++++++++++
 
- 3 files changed, 79 insertions(+)
 
-
 
---- a/arch/arm/boot/dts/mt7629.dtsi
 
-+++ b/arch/arm/boot/dts/mt7629.dtsi
 
-@@ -272,6 +272,22 @@
 
- 			status = "disabled";
 
- 		};
 
- 
-+		snand: snfi@1100d000 {
 
-+			pinctrl-names = "default";
 
-+ 			pinctrl-0 = <&serial_nand_pins>;
 
-+			compatible = "mediatek,mt7629-snand";
 
-+			reg = <0x1100d000 0x1000>, <0x1100e000 0x1000>;
 
-+			reg-names = "nfi", "ecc";
 
-+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 
-+			clocks = <&pericfg CLK_PERI_NFI_PD>,
 
-+				 <&pericfg CLK_PERI_SNFI_PD>,
 
-+				 <&pericfg CLK_PERI_NFIECC_PD>;
 
-+			clock-names = "nfi_clk", "pad_clk", "ecc_clk";
 
-+			#address-cells = <1>;
 
-+			#size-cells = <0>;
 
-+			status = "disabled";
 
-+		};
 
-+
 
- 		spi: spi@1100a000 {
 
- 			compatible = "mediatek,mt7629-spi",
 
- 				     "mediatek,mt7622-spi";
 
---- a/arch/arm/boot/dts/mt7629-rfb.dts
 
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
 
-@@ -254,6 +254,38 @@
 
- 	};
 
- };
 
- 
-+&snand {
 
-+	status = "okay";
 
-+	mediatek,quad-spi;
 
-+
 
-+	partitions {
 
-+		compatible = "fixed-partitions";
 
-+		#address-cells = <1>;
 
-+		#size-cells = <1>;
 
-+
 
-+		partition@0 {
 
-+			label = "Bootloader";
 
-+			reg = <0x00000 0x0100000>;
 
-+			read-only;
 
-+		};
 
-+
 
-+		partition@100000 {
 
-+			label = "Config";
 
-+			reg = <0x100000 0x0040000>;
 
-+		};
 
-+
 
-+		partition@140000 {
 
-+			label = "factory";
 
-+			reg = <0x140000 0x0080000>;
 
-+		};
 
-+
 
-+		partition@1c0000 {
 
-+			label = "firmware";
 
-+			reg = <0x1c0000 0x1000000>;
 
-+		};
 
-+	};
 
-+};
 
-+
 
- &spi {
 
- 	pinctrl-names = "default";
 
- 	pinctrl-0 = <&spi_pins>;

+ 0 - 81
target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch
View File 

@@ -1,81 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-@@ -561,6 +561,20 @@
 
- 		status = "disabled";
 
- 	};
 
- 
-+	snand: snfi@1100d000 {
 
-+		compatible = "mediatek,mt7622-snand";
 
-+		reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
 
-+		reg-names = "nfi", "ecc";
 
-+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 
-+		clocks = <&pericfg CLK_PERI_NFI_PD>,
 
-+			 <&pericfg CLK_PERI_SNFI_PD>,
 
-+			 <&pericfg CLK_PERI_NFIECC_PD>;
 
-+		clock-names = "nfi_clk", "pad_clk", "ecc_clk";
 
-+		#address-cells = <1>;
 
-+		#size-cells = <0>;
 
-+		status = "disabled";
 
-+	};
 
-+
 
- 	nor_flash: spi@11014000 {
 
- 		compatible = "mediatek,mt7622-nor",
 
- 			     "mediatek,mt8173-nor";
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-@@ -529,6 +529,55 @@
 
- 	status = "disabled";
 
- };
 
- 
-+&snand {
 
-+	mediatek,quad-spi;
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&serial_nand_pins>;
 
-+	status = "okay";
 
-+
 
-+	partitions {
 
-+		compatible = "fixed-partitions";
 
-+		#address-cells = <1>;
 
-+		#size-cells = <1>;
 
-+
 
-+		partition@0 {
 
-+			label = "Preloader";
 
-+			reg = <0x00000 0x0080000>;
 
-+			read-only;
 
-+		};
 
-+
 
-+		partition@80000 {
 
-+			label = "ATF";
 
-+			reg = <0x80000 0x0040000>;
 
-+		};
 
-+
 
-+		partition@c0000 {
 
-+			label = "Bootloader";
 
-+			reg = <0xc0000 0x0080000>;
 
-+		};
 
-+
 
-+		partition@140000 {
 
-+			label = "Config";
 
-+			reg = <0x140000 0x0080000>;
 
-+		};
 
-+
 
-+		partition@1c0000 {
 
-+			label = "Factory";
 
-+			reg = <0x1c0000 0x0100000>;
 
-+		};
 
-+
 
-+		partition@200000 {
 
-+			label = "firmware";
 
-+			reg = <0x2c0000 0x2000000>;
 
-+		};
 
-+
 
-+		partition@2200000 {
 
-+			label = "User_data";
 
-+			reg = <0x22c0000 0x4000000>;
 
-+		};
 
-+	};
 
-+};
 
-+
 
- &spi0 {
 
- 	pinctrl-names = "default";
 
- 	pinctrl-0 = <&spic0_pins>;

+ 0 - 18
target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch
View File 

@@ -1,18 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-@@ -561,7 +561,7 @@
 
- 			reg = <0x140000 0x0080000>;
 
- 		};
 
- 
--		partition@1c0000 {
 
-+		factory: partition@1c0000 {
 
- 			label = "Factory";
 
- 			reg = <0x1c0000 0x0100000>;
 
- 		};
 
-@@ -619,5 +619,6 @@
 
- };
 
- 
- &wmac {
 
-+	mediatek,mtd-eeprom = <&factory 0x0000>;
 
- 	status = "okay";
 
- };

+ 0 - 23
target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch
View File 

@@ -1,23 +0,0 @@
 
---- a/arch/arm/boot/dts/mt7623.dtsi
 
-+++ b/arch/arm/boot/dts/mt7623.dtsi
 
-@@ -949,17 +949,14 @@
 
- 	};
 
- 
- 	crypto: crypto@1b240000 {
 
--		compatible = "mediatek,eip97-crypto";
 
-+		compatible = "inside-secure,safexcel-eip97";
 
- 		reg = <0 0x1b240000 0 0x20000>;
 
- 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
 
- 			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
 
- 			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
 
--			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
 
--			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
 
-+			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 
-+		interrupt-names = "ring0", "ring1", "ring2", "ring3";
 
- 		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
 
--		clock-names = "cryp";
 
--		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 
--		status = "disabled";
 
- 	};
 
- 
- 	bdpsys: syscon@1c000000 {

+ 0 - 11
target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch
View File 

@@ -1,11 +0,0 @@
 
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-@@ -19,7 +19,7 @@
 
- 
- 	chosen {
 
- 		stdout-path = "serial2:115200n8";
 
--		bootargs = "console=ttyS2,115200n8 console=tty1";
 
-+		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
 
- 	};
 
- 
- 	connector {

+ 0 - 11
target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch
View File 

@@ -1,11 +0,0 @@
 
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-@@ -15,6 +15,8 @@
 
- 
- 	aliases {
 
- 		serial2 = &uart2;
 
-+		mmc0 = &mmc0;
 
-+		mmc1 = &mmc1;
 
- 	};
 
- 
- 	chosen {

+ 0 - 29
target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch
View File 

@@ -1,29 +0,0 @@
 
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-@@ -17,6 +17,10 @@
 
- 		serial2 = &uart2;
 
- 		mmc0 = &mmc0;
 
- 		mmc1 = &mmc1;
 
-+		led-boot = &led_system_green;
 
-+		led-failsafe = &led_system_blue;
 
-+		led-running = &led_system_green;
 
-+		led-upgrade = &led_system_blue;
 
- 	};
 
- 
- 	chosen {
 
-@@ -112,13 +116,13 @@
 
- 		pinctrl-names = "default";
 
- 		pinctrl-0 = <&led_pins_a>;
 
- 
--		blue {
 
-+		led_system_blue: blue {
 
- 			label = "bpi-r2:pio:blue";
 
- 			gpios = <&pio 240 GPIO_ACTIVE_LOW>;
 
- 			default-state = "off";
 
- 		};
 
- 
--		green {
 
-+		led_system_green: green {
 
- 			label = "bpi-r2:pio:green";
 
- 			gpios = <&pio 241 GPIO_ACTIVE_LOW>;
 
- 			default-state = "off";

+ 0 - 10
target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch
View File 

@@ -1,10 +0,0 @@
 
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 
-@@ -15,6 +15,7 @@
 
- 
- 	aliases {
 
- 		serial2 = &uart2;
 
-+		ethernet0 = &gmac0;
 
- 		mmc0 = &mmc0;
 
- 		mmc1 = &mmc1;
 
- 		led-boot = &led_system_green;

+ 0 - 195
target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch
View File 

@@ -1,195 +0,0 @@
 
-From f9924caf5d952594b2d912e2ec318189ce64cf04 Mon Sep 17 00:00:00 2001
 
-From: Chunfeng Yun <[email protected]>
 
-Date: Fri, 25 Dec 2020 15:52:55 +0800
 
-Subject: [PATCH] dt-bindings: usb: convert mediatek, musb.txt to YAML schema
 
-
 
-Convert mediatek,musb.txt to YAML schema mediatek,musb.yaml
 
-
 
-Cc: Min Guo <[email protected]>
 
-Reviewed-by: Rob Herring <[email protected]>
 
-Signed-off-by: Chunfeng Yun <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
 
----
 
- .../devicetree/bindings/usb/mediatek,musb.txt |  57 ---------
 
- .../bindings/usb/mediatek,musb.yaml           | 113 ++++++++++++++++++
 
- 2 files changed, 113 insertions(+), 57 deletions(-)
 
- delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.txt
 
- create mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.yaml
 
-
 
---- a/Documentation/devicetree/bindings/usb/mediatek,musb.txt
 
-+++ /dev/null
 
-@@ -1,57 +0,0 @@
 
--MediaTek musb DRD/OTG controller
 
---------------------------------------------
 
--
 
--Required properties:
 
-- - compatible      : should be one of:
 
--                     "mediatek,mt2701-musb"
 
--                     ...
 
--                     followed by "mediatek,mtk-musb"
 
-- - reg             : specifies physical base address and size of
 
--                     the registers
 
-- - interrupts      : interrupt used by musb controller
 
-- - interrupt-names : must be "mc"
 
-- - phys            : PHY specifier for the OTG phy
 
-- - dr_mode         : should be one of "host", "peripheral" or "otg",
 
--                     refer to usb/generic.txt
 
-- - clocks          : a list of phandle + clock-specifier pairs, one for
 
--                     each entry in clock-names
 
-- - clock-names     : must contain "main", "mcu", "univpll"
 
--                     for clocks of controller
 
--
 
--Optional properties:
 
-- - power-domains   : a phandle to USB power domain node to control USB's
 
--                     MTCMOS
 
--
 
--Required child nodes:
 
-- usb connector node as defined in bindings/connector/usb-connector.yaml
 
--Optional properties:
 
-- - id-gpios        : input GPIO for USB ID pin.
 
-- - vbus-gpios      : input GPIO for USB VBUS pin.
 
-- - vbus-supply     : reference to the VBUS regulator, needed when supports
 
--                     dual-role mode
 
-- - usb-role-switch : use USB Role Switch to support dual-role switch, see
 
--                     usb/generic.txt.
 
--
 
--Example:
 
--
 
--usb2: usb@11200000 {
 
--	compatible = "mediatek,mt2701-musb",
 
--		     "mediatek,mtk-musb";
 
--	reg = <0 0x11200000 0 0x1000>;
 
--	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
 
--	interrupt-names = "mc";
 
--	phys = <&u2port2 PHY_TYPE_USB2>;
 
--	dr_mode = "otg";
 
--	clocks = <&pericfg CLK_PERI_USB0>,
 
--		 <&pericfg CLK_PERI_USB0_MCU>,
 
--		 <&pericfg CLK_PERI_USB_SLV>;
 
--	clock-names = "main","mcu","univpll";
 
--	power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 
--	usb-role-switch;
 
--	connector{
 
--		compatible = "gpio-usb-b-connector", "usb-b-connector";
 
--		type = "micro";
 
--		id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
 
--		vbus-supply = <&usb_vbus>;
 
--	};
 
--};
 
---- /dev/null
 
-+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
 
-@@ -0,0 +1,113 @@
 
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 
-+# Copyright (c) 2020 MediaTek
 
-+%YAML 1.2
 
-+---
 
-+$id: http://devicetree.org/schemas/usb/mediatek,musb.yaml#
 
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
-+
 
-+title: MediaTek MUSB DRD/OTG Controller Device Tree Bindings
 
-+
 
-+maintainers:
 
-+  - Min Guo <[email protected]>
 
-+
 
-+properties:
 
-+  $nodename:
 
-+    pattern: '^usb@[0-9a-f]+$'
 
-+
 
-+  compatible:
 
-+    items:
 
-+      - enum:
 
-+          - mediatek,mt2701-musb
 
-+      - const: mediatek,mtk-musb
 
-+
 
-+  reg:
 
-+    maxItems: 1
 
-+
 
-+  interrupts:
 
-+    maxItems: 1
 
-+
 
-+  interrupt-names:
 
-+    items:
 
-+      - const: mc
 
-+
 
-+  clocks:
 
-+    items:
 
-+      - description: The main/core clock
 
-+      - description: The system bus clock
 
-+      - description: The 48Mhz clock
 
-+
 
-+  clock-names:
 
-+    items:
 
-+      - const: main
 
-+      - const: mcu
 
-+      - const: univpll
 
-+
 
-+  phys:
 
-+    maxItems: 1
 
-+
 
-+  usb-role-switch:
 
-+    $ref: /schemas/types.yaml#/definitions/flag
 
-+    description: Support role switch. See usb/generic.txt
 
-+    type: boolean
 
-+
 
-+  dr_mode:
 
-+    enum:
 
-+      - host
 
-+      - otg
 
-+      - peripheral
 
-+
 
-+  power-domains:
 
-+    description: A phandle to USB power domain node to control USB's MTCMOS
 
-+    maxItems: 1
 
-+
 
-+  connector:
 
-+    $ref: /connector/usb-connector.yaml#
 
-+    description: Connector for dual role switch
 
-+    type: object
 
-+
 
-+dependencies:
 
-+  usb-role-switch: [ 'connector' ]
 
-+  connector: [ 'usb-role-switch' ]
 
-+
 
-+required:
 
-+  - compatible
 
-+  - reg
 
-+  - interrupts
 
-+  - interrupt-names
 
-+  - phys
 
-+  - clocks
 
-+  - clock-names
 
-+
 
-+additionalProperties: false
 
-+
 
-+examples:
 
-+  - |
 
-+    #include <dt-bindings/clock/mt2701-clk.h>
 
-+    #include <dt-bindings/gpio/gpio.h>
 
-+    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-+    #include <dt-bindings/interrupt-controller/irq.h>
 
-+    #include <dt-bindings/phy/phy.h>
 
-+    #include <dt-bindings/power/mt2701-power.h>
 
-+
 
-+    usb@11200000 {
 
-+        compatible = "mediatek,mt2701-musb", "mediatek,mtk-musb";
 
-+        reg = <0x11200000 0x1000>;
 
-+        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
 
-+        interrupt-names = "mc";
 
-+        phys = <&u2port2 PHY_TYPE_USB2>;
 
-+        dr_mode = "otg";
 
-+        clocks = <&pericfg CLK_PERI_USB0>,
 
-+                 <&pericfg CLK_PERI_USB0_MCU>,
 
-+                 <&pericfg CLK_PERI_USB_SLV>;
 
-+        clock-names = "main","mcu","univpll";
 
-+        power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 
-+        usb-role-switch;
 
-+
 
-+        connector {
 
-+            compatible = "gpio-usb-b-connector", "usb-b-connector";
 
-+            type = "micro";
 
-+            id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
 
-+            vbus-supply = <&usb_vbus>;
 
-+        };
 
-+    };
 
-+...

+ 0 - 25
target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch
View File 

@@ -1,25 +0,0 @@
 
-From b5a12546e779d4f5586f58e60e0ef5070a833a64 Mon Sep 17 00:00:00 2001
 
-From: Chunfeng Yun <[email protected]>
 
-Date: Mon, 1 Feb 2021 15:00:08 +0800
 
-Subject: [PATCH] dt-bindings: usb: mediatek: musb: add mt8516 compatbile
 
-
 
-Add support mt8516 compatbile
 
-
 
-Reviewed-by: Rob Herring <[email protected]>
 
-Signed-off-by: Chunfeng Yun <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
 
----
 
- Documentation/devicetree/bindings/usb/mediatek,musb.yaml | 1 +
 
- 1 file changed, 1 insertion(+)
 
-
 
---- a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
 
-+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
 
-@@ -17,6 +17,7 @@ properties:
 
-   compatible:
 
-     items:
 
-       - enum:
 
-+          - mediatek,mt8516-musb
 
-           - mediatek,mt2701-musb
 
-       - const: mediatek,mtk-musb
 
-

+ 0 - 23
target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch
View File 

@@ -1,23 +0,0 @@
 
-From b7e4218ece0b7a1b9142491056ae0c4f1af80041 Mon Sep 17 00:00:00 2001
 
-From: Sungbo Eo <[email protected]>
 
-Date: Sun, 8 Aug 2021 21:38:39 +0900
 
-Subject: [PATCH 1/2] dt-bindings: usb: mtk-musb: add MT7623 compatible
 
-
 
-Document MT7623 compatible for mtk-musb.
 
-
 
-Signed-off-by: Sungbo Eo <[email protected]>
 
-Reviewed-by: Matthias Brugger <[email protected]>
 
----
 
- Documentation/devicetree/bindings/usb/mediatek,musb.yaml | 1 +
 
- 1 file changed, 1 insertion(+)
 
-
 
---- a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
 
-+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
 
-@@ -19,6 +19,7 @@ properties:
 
-       - enum:
 
-           - mediatek,mt8516-musb
 
-           - mediatek,mt2701-musb
 
-+          - mediatek,mt7623-musb
 
-       - const: mediatek,mtk-musb
 
- 
-   reg:

+ 0 - 69
target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch
View File 

@@ -1,69 +0,0 @@
 
-From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
 
-From: Sungbo Eo <[email protected]>
 
-Date: Sun, 8 Aug 2021 21:38:40 +0900
 
-Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
 
-
 
-MT7623 has an musb controller that is compatible with the one from MT2701.
 
-
 
-Signed-off-by: Sungbo Eo <[email protected]>
 
----
 
- arch/arm/boot/dts/mt7623.dtsi  | 34 ++++++++++++++++++++++++++++++++++
 
- arch/arm/boot/dts/mt7623a.dtsi |  4 ++++
 
- 2 files changed, 38 insertions(+)
 
-
 
---- a/arch/arm/boot/dts/mt7623.dtsi
 
-+++ b/arch/arm/boot/dts/mt7623.dtsi
 
-@@ -585,6 +585,40 @@
 
- 		status = "disabled";
 
- 	};
 
- 
-+	usb0: usb@11200000 {
 
-+		compatible = "mediatek,mt7623-musb",
 
-+			     "mediatek,mtk-musb";
 
-+		reg = <0 0x11200000 0 0x1000>;
 
-+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
 
-+		interrupt-names = "mc";
 
-+		phys = <&u2port2 PHY_TYPE_USB2>;
 
-+		dr_mode = "otg";
 
-+		clocks = <&pericfg CLK_PERI_USB0>,
 
-+			 <&pericfg CLK_PERI_USB0_MCU>,
 
-+			 <&pericfg CLK_PERI_USB_SLV>;
 
-+		clock-names = "main","mcu","univpll";
 
-+		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 
-+		status = "disabled";
 
-+	};
 
-+
 
-+	u2phy1: t-phy@11210000 {
 
-+		compatible = "mediatek,mt7623-tphy",
 
-+			     "mediatek,generic-tphy-v1";
 
-+		reg = <0 0x11210000 0 0x0800>;
 
-+		#address-cells = <2>;
 
-+		#size-cells = <2>;
 
-+		ranges;
 
-+		status = "disabled";
 
-+
 
-+		u2port2: usb-phy@11210800 {
 
-+			reg = <0 0x11210800 0 0x0100>;
 
-+			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 
-+			clock-names = "ref";
 
-+			#phy-cells = <1>;
 
-+			status = "okay";
 
-+		};
 
-+	};
 
-+
 
- 	audsys: clock-controller@11220000 {
 
- 		compatible = "mediatek,mt7623-audsys",
 
- 			     "mediatek,mt2701-audsys",
 
---- a/arch/arm/boot/dts/mt7623a.dtsi
 
-+++ b/arch/arm/boot/dts/mt7623a.dtsi
 
-@@ -35,6 +35,10 @@
 
- 	clock-names = "ethif";
 
- };
 
- 
-+&usb0 {
 
-+	power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
 
-+};
 
-+
 
- &usb1 {
 
- 	power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
 
- };

+ 0 - 13
target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch
View File 

@@ -1,13 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-@@ -160,6 +160,10 @@
 
- 		switch@0 {
 
- 			compatible = "mediatek,mt7531";
 
- 			reg = <0>;
 
-+			interrupt-controller;
 
-+			#interrupt-cells = <1>;
 
-+			interrupt-parent = <&pio>;
 
-+			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 
- 			reset-gpios = <&pio 54 0>;
 
- 
- 			ports {

+ 0 - 66
target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch
View File 

@@ -1,66 +0,0 @@
 
-From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
 
-From: Kristian Evensen <[email protected]>
 
-Date: Mon, 30 Apr 2018 14:38:01 +0200
 
-Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
 
-
 
----
 
- drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
 
- 1 file changed, 20 insertions(+)
 
-
 
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
 
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
 
-@@ -15,6 +15,8 @@
 
- #include <linux/of_device.h>
 
- #include <linux/phy/phy.h>
 
- #include <linux/platform_device.h>
 
-+#include <linux/mfd/syscon.h>
 
-+#include <linux/regmap.h>
 
- 
- /* version V1 sub-banks offset base address */
 
- /* banks shared by multiple phys */
 
-@@ -267,6 +269,9 @@
 
- #define RG_CDR_BIRLTD0_GEN3_MSK		GENMASK(4, 0)
 
- #define RG_CDR_BIRLTD0_GEN3_VAL(x)	(0x1f & (x))
 
- 
-+#define HIF_SYSCFG1			0x14
 
-+#define HIF_SYSCFG1_PHY2_MASK		(0x3 << 20)
 
-+
 
- enum mtk_phy_version {
 
- 	MTK_PHY_V1 = 1,
 
- 	MTK_PHY_V2,
 
-@@ -315,6 +320,7 @@ struct mtk_tphy {
 
- 	void __iomem *sif_base;	/* only shared sif */
 
- 	const struct mtk_phy_pdata *pdata;
 
- 	struct mtk_phy_instance **phys;
 
-+	struct regmap *hif;
 
- 	int nphys;
 
- 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
 
- 	int src_coef; /* coefficient for slew rate calibrate */
 
-@@ -634,6 +640,10 @@ static void pcie_phy_instance_init(struc
 
- 	if (tphy->pdata->version != MTK_PHY_V1)
 
- 		return;
 
- 
-+	if (tphy->hif)
 
-+		regmap_update_bits(tphy->hif, HIF_SYSCFG1,
 
-+				   HIF_SYSCFG1_PHY2_MASK, 0);
 
-+
 
- 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
 
- 	tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
 
- 	tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
 
-@@ -1136,6 +1146,16 @@ static int mtk_tphy_probe(struct platfor
 
- 		&tphy->src_ref_clk);
 
- 	device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
 
- 
-+	if (of_find_property(np, "mediatek,phy-switch", NULL)) {
 
-+		tphy->hif = syscon_regmap_lookup_by_phandle(np,
 
-+							    "mediatek,phy-switch");
 
-+		if (IS_ERR(tphy->hif)) {
 
-+			dev_err(&pdev->dev,
 
-+				"missing \"mediatek,phy-switch\" phandle\n");
 
-+			return PTR_ERR(tphy->hif);
 
-+		}
 
-+	}
 
-+
 
- 	port = 0;
 
- 	for_each_child_of_node(np, child_np) {
 
- 		struct mtk_phy_instance *instance;

+ 0 - 36
target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch
View File 

@@ -1,36 +0,0 @@
 
---- a/drivers/mtd/mtk-snand/mtk-snand-mtd.c
 
-+++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c
 
-@@ -16,6 +16,7 @@
 
- #include <linux/dma-mapping.h>
 
- #include <linux/wait.h>
 
- #include <linux/mtd/mtd.h>
 
-+#include <linux/mtd/mtk_bmt.h>
 
- #include <linux/mtd/partitions.h>
 
- #include <linux/of_platform.h>
 
- 
-@@ -612,6 +613,8 @@ static int mtk_snand_probe(struct platfo
 
- 	mtd->_block_isbad = mtk_snand_mtd_block_isbad;
 
- 	mtd->_block_markbad = mtk_snand_mtd_block_markbad;
 
- 
-+	mtk_bmt_attach(mtd);
 
-+
 
- 	ret = mtd_device_register(mtd, NULL, 0);
 
- 	if (ret) {
 
- 		dev_err(msm->pdev.dev, "failed to register mtd partition\n");
 
-@@ -623,6 +626,7 @@ static int mtk_snand_probe(struct platfo
 
- 	return 0;
 
- 
- errout4:
 
-+	mtk_bmt_detach(mtd);
 
- 	devm_kfree(msm->pdev.dev, msm->page_cache);
 
- 
- errout3:
 
-@@ -650,6 +654,8 @@ static int mtk_snand_remove(struct platf
 
- 	if (ret)
 
- 		return ret;
 
- 
-+	mtk_bmt_detach(mtd);
 
-+
 
- 	mtk_snand_cleanup(msm->snf);
 
- 
- 	if (msm->irq >= 0)

+ 0 - 11
target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch
View File 

@@ -1,11 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-@@ -535,6 +535,8 @@
 
- 	pinctrl-0 = <&serial_nand_pins>;
 
- 	status = "okay";
 
- 
-+	mediatek,bmt-v2;
 
-+
 
- 	partitions {
 
- 		compatible = "fixed-partitions";
 
- 		#address-cells = <1>;

+ 0 - 21
target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch
View File 

@@ -1,21 +0,0 @@
 
---- a/drivers/mtd/Kconfig
 
-+++ b/drivers/mtd/Kconfig
 
-@@ -238,6 +238,8 @@ source "drivers/mtd/ubi/Kconfig"
 
- 
- source "drivers/mtd/hyperbus/Kconfig"
 
- 
-+source "drivers/mtd/mtk-snand/Kconfig"
 
-+
 
- source "drivers/mtd/composite/Kconfig"
 
- 
- endif # MTD
 
---- a/drivers/mtd/Makefile
 
-+++ b/drivers/mtd/Makefile
 
-@@ -34,5 +34,7 @@ obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor/
 
- obj-$(CONFIG_MTD_UBI)		+= ubi/
 
- obj-$(CONFIG_MTD_HYPERBUS)	+= hyperbus/
 
- 
-+obj-$(CONFIG_MTK_SPI_NAND)	+= mtk-snand/
 
-+
 
- # Composite drivers must be loaded last
 
- obj-y				+= composite/

+ 0 - 27
target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch
View File 

@@ -1,27 +0,0 @@
 
---- a/drivers/crypto/inside-secure/safexcel.c
 
-+++ b/drivers/crypto/inside-secure/safexcel.c
 
-@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex
 
- 		val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
 
- 		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
 
- 	}
 
-+	/*
 
-+	 * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
 
-+	 */
 
-+	else {
 
-+		val = 0;
 
-+		val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
 
-+		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
 
-+	}
 
- 
- 	/* Configure wr/rd cache values */
 
- 	writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
 
---- a/drivers/crypto/inside-secure/safexcel.h
 
-+++ b/drivers/crypto/inside-secure/safexcel.h
 
-@@ -314,6 +314,7 @@
 
- #define EIP197_MST_CTRL_RD_CACHE(n)		(((n) & 0xf) << 0)
 
- #define EIP197_MST_CTRL_WD_CACHE(n)		(((n) & 0xf) << 4)
 
- #define EIP197_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 20)
 
-+#define EIP97_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 4)
 
- #define EIP197_MST_CTRL_BYTE_SWAP		BIT(24)
 
- #define EIP197_MST_CTRL_NO_BYTE_SWAP		BIT(25)
 
- #define EIP197_MST_CTRL_BYTE_SWAP_BITS          GENMASK(25, 24)

+ 0 - 26
target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch
View File 

@@ -1,26 +0,0 @@
 
---- a/drivers/crypto/inside-secure/safexcel.h
 
-+++ b/drivers/crypto/inside-secure/safexcel.h
 
-@@ -736,6 +736,9 @@ enum safexcel_eip_version {
 
- /* Priority we use for advertising our algorithms */
 
- #define SAFEXCEL_CRA_PRIORITY		300
 
- 
-+/* System cache line size */
 
-+#define SYSTEM_CACHELINE_SIZE		64
 
-+
 
- /* SM3 digest result for zero length message */
 
- #define EIP197_SM3_ZEROM_HASH	"\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
 
- 				"\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
 
---- a/drivers/crypto/inside-secure/safexcel_hash.c
 
-+++ b/drivers/crypto/inside-secure/safexcel_hash.c
 
-@@ -53,9 +53,9 @@ struct safexcel_ahash_req {
 
- 	u8 block_sz;    /* block size, only set once */
 
- 	u8 digest_sz;   /* output digest size, only set once */
 
- 	__le32 state[SHA3_512_BLOCK_SIZE /
 
--		     sizeof(__le32)] __aligned(sizeof(__le32));
 
-+		     sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
 
- 
--	u64 len;
 
-+	u64 len __aligned(SYSTEM_CACHELINE_SIZE);
 
- 	u64 processed;
 
- 
- 	u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));

+ 0 - 33
target/linux/mediatek/patches-5.10/410-bt-mtk-serial-fix.patch
View File 

@@ -1,33 +0,0 @@
 
---- a/drivers/tty/serial/8250/8250.h
 
-+++ b/drivers/tty/serial/8250/8250.h
 
-@@ -82,6 +82,7 @@ struct serial8250_config {
 
- #define UART_CAP_MINI	(1 << 17)	/* Mini UART on BCM283X family lacks:
 
- 					 * STOP PARITY EPAR SPAR WLEN5 WLEN6
 
- 					 */
 
-+#define UART_CAP_NMOD	(1 << 18)	/* UART doesn't do termios */
 
- 
- #define UART_BUG_QUOT	(1 << 0)	/* UART has buggy quot LSB */
 
- #define UART_BUG_TXEN	(1 << 1)	/* UART has buggy TX IIR status */
 
---- a/drivers/tty/serial/8250/8250_port.c
 
-+++ b/drivers/tty/serial/8250/8250_port.c
 
-@@ -288,7 +288,7 @@ static const struct serial8250_config ua
 
- 		.tx_loadsz	= 16,
 
- 		.fcr		= UART_FCR_ENABLE_FIFO |
 
- 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
 
--		.flags		= UART_CAP_FIFO,
 
-+		.flags		= UART_CAP_FIFO | UART_CAP_NMOD,
 
- 	},
 
- 	[PORT_NPCM] = {
 
- 		.name		= "Nuvoton 16550",
 
-@@ -2735,6 +2735,11 @@ serial8250_do_set_termios(struct uart_po
 
- 	unsigned long flags;
 
- 	unsigned int baud, quot, frac = 0;
 
- 
-+	if (up->capabilities & UART_CAP_NMOD) {
 
-+		termios->c_cflag = 0;
 
-+		return;
 
-+	}
 
-+
 
- 	if (up->capabilities & UART_CAP_MINI) {
 
- 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
 
- 		if ((termios->c_cflag & CSIZE) == CS5 ||

+ 0 - 28
target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch
View File 

@@ -1,28 +0,0 @@
 
-From: David Bauer <[email protected]>
 
-To: [email protected]
 
-Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV
 
-Date: Sat, 13 Feb 2021 16:10:47 +0100
 
-
 
-The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K
 
-sectors as well as block protection and Dual-/Quad-read.
 
-
 
-Tested on: Ubiquiti UniFi 6 LR
 
-
 
-Signed-off-by: David Bauer <[email protected]>
 
----
 
- drivers/mtd/spi-nor/winbond.c | 4 ++++
 
- 1 file changed, 4 insertions(+)
 
-
 
---- a/drivers/mtd/spi-nor/winbond.c
 
-+++ b/drivers/mtd/spi-nor/winbond.c
 
-@@ -95,6 +95,10 @@ static const struct flash_info winbond_p
 
- 			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 
- 	{ "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
 
- 			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 
-+	{ "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024,
 
-+			    SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ |
 
-+			    SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
 
-+			    SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
 
- 	{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
 
- 			    SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
 
- };

+ 0 - 25
target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch
View File 

@@ -1,25 +0,0 @@
 
---- a/drivers/net/phy/Kconfig
 
-+++ b/drivers/net/phy/Kconfig
 
-@@ -340,6 +340,12 @@ config ROCKCHIP_PHY
 
- 	help
 
- 	  Currently supports the integrated Ethernet PHY.
 
- 
-+config RTL8367S_GSW
 
-+	tristate "rtl8367 Gigabit Switch support for mt7622"
 
-+	depends on NET_VENDOR_MEDIATEK
 
-+	help
 
-+	  This driver supports rtl8367s in mt7622
 
-+
 
- config SMSC_PHY
 
- 	tristate "SMSC PHYs"
 
- 	help
 
---- a/drivers/net/phy/Makefile
 
-+++ b/drivers/net/phy/Makefile
 
-@@ -89,6 +89,7 @@ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
 
- obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
 
- obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
 
- obj-$(CONFIG_ROCKCHIP_PHY)	+= rockchip.o
 
-+obj-$(CONFIG_RTL8367S_GSW)	+= rtk/
 
- obj-$(CONFIG_SMSC_PHY)		+= smsc.o
 
- obj-$(CONFIG_STE10XP)		+= ste10Xp.o
 
- obj-$(CONFIG_TERANETICS_PHY)	+= teranetics.o

+ 0 - 24
target/linux/mediatek/patches-5.10/510-net-mediatek-add-flow-offload-for-mt7623.patch
View File 

@@ -1,24 +0,0 @@
 
-From 4823778b116c08e9c55dbc5b5042223289ea6a0c Mon Sep 17 00:00:00 2001
 
-From: Frank Wunderlich <[email protected]>
 
-Date: Wed, 31 Mar 2021 15:34:37 +0200
 
-Subject: [PATCH] net: mediatek: add flow offload for mt7623
 
-
 
-mt7623 uses offload version 2 too
 
-
 
-tested on Bananapi-R2
 
-
 
-Signed-off-by: Frank Wunderlich <[email protected]>
 
----
 
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 +
 
- 1 file changed, 1 insertion(+)
 
-
 
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 
-@@ -3375,6 +3375,7 @@ static const struct mtk_soc_data mt7623_
 
- 	.hw_features = MTK_HW_FEATURES,
 
- 	.required_clks = MT7623_CLKS_BITMAP,
 
- 	.required_pctl = true,
 
-+	.offload_version = 2,
 
- };
 
- 
- static const struct mtk_soc_data mt7629_data = {

+ 0 - 415
target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch
View File 

@@ -1,415 +0,0 @@
 
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-From: <[email protected]>
 
-To: <[email protected]>, <[email protected]>, <[email protected]>
 
-Subject: [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding
 
-Date: Thu, 28 May 2020 14:16:45 +0800
 
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-
 
-From: "chuanjia.liu" <[email protected]>
 
-
 
-There are two independent PCIe controllers in MT2712/MT7622 platform,
 
-and each of them should contain an independent MSI domain.
 
-
 
-In current architecture, MSI domain will be inherited from the root
 
-bridge, and all of the devices will share the same MSI domain.
 
-Hence that, the PCIe devices will not work properly if the irq number
 
-which required is more than 32.
 
-
 
-Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
 
-comply with the hardware design.
 
-
 
-Signed-off-by: chuanjia.liu <[email protected]>
 
----
 
- .../bindings/pci/mediatek-pcie-cfg.yaml       |  38 +++++
 
- .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++-------
 
- 2 files changed, 129 insertions(+), 53 deletions(-)
 
- create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
 
-
 
---- /dev/null
 
-+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
 
-@@ -0,0 +1,38 @@
 
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
 
-+%YAML 1.2
 
-+---
 
-+$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
 
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
-+
 
-+title: Mediatek PCIECFG controller
 
-+
 
-+maintainers:
 
-+  - Chuanjia Liu <[email protected]>
 
-+  - Jianjun Wang <[email protected]>
 
-+
 
-+description: |
 
-+  The MediaTek PCIECFG controller controls some feature about
 
-+  LTSSM, ASPM and so on.
 
-+
 
-+properties:
 
-+  compatible:
 
-+      items:
 
-+        - enum:
 
-+            - mediatek,mt7622-pciecfg
 
-+            - mediatek,mt7629-pciecfg
 
-+        - const: syscon
 
-+
 
-+  reg:
 
-+    maxItems: 1
 
-+
 
-+required:
 
-+  - compatible
 
-+  - reg
 
-+
 
-+examples:
 
-+  - |
 
-+    pciecfg: pciecfg@1a140000 {
 
-+        compatible = "mediatek,mt7622-pciecfg", "syscon";
 
-+        reg = <0 0x1a140000 0 0x1000>;
 
-+    };
 
-+...
 
---- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 
-+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 
-@@ -8,7 +8,7 @@ Required properties:
 
- 	"mediatek,mt7623-pcie"
 
- 	"mediatek,mt7629-pcie"
 
- - device_type: Must be "pci"
 
--- reg: Base addresses and lengths of the PCIe subsys and root ports.
 
-+- reg: Base addresses and lengths of the root ports.
 
- - reg-names: Names of the above areas to use during resource lookup.
 
- - #address-cells: Address representation for root ports (must be 3)
 
- - #size-cells: Size representation for root ports (must be 2)
 
-@@ -19,10 +19,10 @@ Required properties:
 
-    - sys_ckN :transaction layer and data link layer clock
 
-   Required entries for MT2701/MT7623:
 
-    - free_ck :for reference clock of PCIe subsys
 
--  Required entries for MT2712/MT7622:
 
-+  Required entries for MT2712/MT7622/MT7629:
 
-    - ahb_ckN :AHB slave interface operating clock for CSR access and RC
 
- 	      initiated MMIO access
 
--  Required entries for MT7622:
 
-+  Required entries for MT7622/MT7629:
 
-    - axi_ckN :application layer MMIO channel operating clock
 
-    - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
 
- 	      pcie_mac_ck/pcie_pipe_ck is turned off
 
-@@ -47,10 +47,13 @@ Required properties for MT7623/MT2701:
 
- - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
 
-   number of root ports.
 
- 
--Required properties for MT2712/MT7622:
 
-+Required properties for MT2712/MT7622/MT7629:
 
- -interrupts: A list of interrupt outputs of the controller, must have one
 
- 	     entry for each PCIe port
 
- 
-+Required properties for MT7622/MT7629:
 
-+- mediatek,pcie-subsys: Should be a phandle of the pciecfg node.
 
-+
 
- In addition, the device tree node must have sub-nodes describing each
 
- PCIe port interface, having the following mandatory properties:
 
- 
-@@ -143,56 +146,73 @@ Examples for MT7623:
 
- 
- Examples for MT2712:
 
- 
--	pcie: pcie@11700000 {
 
-+	pcie1: pcie@112ff000 {
 
- 		compatible = "mediatek,mt2712-pcie";
 
- 		device_type = "pci";
 
--		reg = <0 0x11700000 0 0x1000>,
 
--		      <0 0x112ff000 0 0x1000>;
 
--		reg-names = "port0", "port1";
 
-+		reg = <0 0x112ff000 0 0x1000>;
 
-+		reg-names = "port1";
 
- 		#address-cells = <3>;
 
- 		#size-cells = <2>;
 
--		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 
--			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 
--		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
 
--			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
 
--			 <&pericfg CLK_PERI_PCIE0>,
 
-+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 
-+		interrupt-names = "pcie_irq";
 
-+		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
 
- 			 <&pericfg CLK_PERI_PCIE1>;
 
--		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
 
--		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
 
--		phy-names = "pcie-phy0", "pcie-phy1";
 
-+		clock-names = "sys_ck1", "ahb_ck1";
 
-+		phys = <&u3port1 PHY_TYPE_PCIE>;
 
-+		phy-names = "pcie-phy1";
 
- 		bus-range = <0x00 0xff>;
 
--		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
 
-+		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
 
-+		status = "disabled";
 
- 
--		pcie0: pcie@0,0 {
 
--			reg = <0x0000 0 0 0 0>;
 
-+		slot1: pcie@1,0 {
 
-+			reg = <0x0800 0 0 0 0>;
 
- 			#address-cells = <3>;
 
- 			#size-cells = <2>;
 
- 			#interrupt-cells = <1>;
 
- 			ranges;
 
- 			interrupt-map-mask = <0 0 0 7>;
 
--			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 
--					<0 0 0 2 &pcie_intc0 1>,
 
--					<0 0 0 3 &pcie_intc0 2>,
 
--					<0 0 0 4 &pcie_intc0 3>;
 
--			pcie_intc0: interrupt-controller {
 
-+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 
-+					<0 0 0 2 &pcie_intc1 1>,
 
-+					<0 0 0 3 &pcie_intc1 2>,
 
-+					<0 0 0 4 &pcie_intc1 3>;
 
-+			pcie_intc1: interrupt-controller {
 
- 				interrupt-controller;
 
- 				#address-cells = <0>;
 
- 				#interrupt-cells = <1>;
 
- 			};
 
- 		};
 
-+	};
 
- 
--		pcie1: pcie@1,0 {
 
--			reg = <0x0800 0 0 0 0>;
 
-+	pcie0: pcie@11700000 {
 
-+		compatible = "mediatek,mt2712-pcie";
 
-+		device_type = "pci";
 
-+		reg = <0 0x11700000 0 0x1000>;
 
-+		reg-names = "port0";
 
-+		#address-cells = <3>;
 
-+		#size-cells = <2>;
 
-+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 
-+		interrupt-names = "pcie_irq";
 
-+		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
 
-+			 <&pericfg CLK_PERI_PCIE0>;
 
-+		clock-names = "sys_ck0", "ahb_ck0";
 
-+		phys = <&u3port0 PHY_TYPE_PCIE>;
 
-+		phy-names = "pcie-phy0";
 
-+		bus-range = <0x00 0xff>;
 
-+		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
 
-+		status = "disabled";
 
-+
 
-+		slot0: pcie@0,0 {
 
-+			reg = <0x0000 0 0 0 0>;
 
- 			#address-cells = <3>;
 
- 			#size-cells = <2>;
 
- 			#interrupt-cells = <1>;
 
- 			ranges;
 
- 			interrupt-map-mask = <0 0 0 7>;
 
--			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 
--					<0 0 0 2 &pcie_intc1 1>,
 
--					<0 0 0 3 &pcie_intc1 2>,
 
--					<0 0 0 4 &pcie_intc1 3>;
 
--			pcie_intc1: interrupt-controller {
 
-+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 
-+					<0 0 0 2 &pcie_intc0 1>,
 
-+					<0 0 0 3 &pcie_intc0 2>,
 
-+					<0 0 0 4 &pcie_intc0 3>;
 
-+			pcie_intc0: interrupt-controller {
 
- 				interrupt-controller;
 
- 				#address-cells = <0>;
 
- 				#interrupt-cells = <1>;
 
-@@ -202,39 +222,31 @@ Examples for MT2712:
 
- 
- Examples for MT7622:
 
- 
--	pcie: pcie@1a140000 {
 
-+	pcie0: pcie@1a143000 {
 
- 		compatible = "mediatek,mt7622-pcie";
 
- 		device_type = "pci";
 
--		reg = <0 0x1a140000 0 0x1000>,
 
--		      <0 0x1a143000 0 0x1000>,
 
--		      <0 0x1a145000 0 0x1000>;
 
--		reg-names = "subsys", "port0", "port1";
 
-+		reg = <0 0x1a143000 0 0x1000>;
 
-+		reg-names = "port0";
 
-+		mediatek,pcie-cfg = <&pciecfg>;
 
- 		#address-cells = <3>;
 
- 		#size-cells = <2>;
 
--		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 
--			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 
-+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
 
-+		interrupt-names = "pcie_irq";
 
- 		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 
--			 <&pciesys CLK_PCIE_P1_MAC_EN>,
 
- 			 <&pciesys CLK_PCIE_P0_AHB_EN>,
 
--			 <&pciesys CLK_PCIE_P1_AHB_EN>,
 
- 			 <&pciesys CLK_PCIE_P0_AUX_EN>,
 
--			 <&pciesys CLK_PCIE_P1_AUX_EN>,
 
- 			 <&pciesys CLK_PCIE_P0_AXI_EN>,
 
--			 <&pciesys CLK_PCIE_P1_AXI_EN>,
 
- 			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
 
--			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
 
--			 <&pciesys CLK_PCIE_P0_PIPE_EN>,
 
--			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
 
--		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 
--			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 
--			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 
--		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
 
--		phy-names = "pcie-phy0", "pcie-phy1";
 
-+			 <&pciesys CLK_PCIE_P0_PIPE_EN>;
 
-+		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
 
-+			      "axi_ck0", "obff_ck0", "pipe_ck0";
 
-+
 
- 		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 
- 		bus-range = <0x00 0xff>;
 
--		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
 
-+		ranges = <0x82000000 0 0x20000000  0 0x20000000  0 0x8000000>;
 
-+		status = "disabled";
 
- 
--		pcie0: pcie@0,0 {
 
-+		slot0: pcie@0,0 {
 
- 			reg = <0x0000 0 0 0 0>;
 
- 			#address-cells = <3>;
 
- 			#size-cells = <2>;
 
-@@ -251,8 +263,34 @@ Examples for MT7622:
 
- 				#interrupt-cells = <1>;
 
- 			};
 
- 		};
 
-+	};
 
-+
 
-+	pcie1: pcie@1a145000 {
 
-+		compatible = "mediatek,mt7622-pcie";
 
-+		device_type = "pci";
 
-+		reg = <0 0x1a145000 0 0x1000>;
 
-+		reg-names = "port1";
 
-+		mediatek,pcie-cfg = <&pciecfg>;
 
-+		#address-cells = <3>;
 
-+		#size-cells = <2>;
 
-+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 
-+		interrupt-names = "pcie_irq";
 
-+		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
 
-+			 /* designer has connect RC1 with p0_ahb clock */
 
-+			 <&pciesys CLK_PCIE_P0_AHB_EN>,
 
-+			 <&pciesys CLK_PCIE_P1_AUX_EN>,
 
-+			 <&pciesys CLK_PCIE_P1_AXI_EN>,
 
-+			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
 
-+			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
 
-+		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
 
-+			      "axi_ck1", "obff_ck1", "pipe_ck1";
 
-+
 
-+		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 
-+		bus-range = <0x00 0xff>;
 
-+		ranges = <0x82000000 0 0x28000000  0 0x28000000  0 0x8000000>;
 
-+		status = "disabled";
 
- 
--		pcie1: pcie@1,0 {
 
-+		slot1: pcie@1,0 {
 
- 			reg = <0x0800 0 0 0 0>;
 
- 			#address-cells = <3>;
 
- 			#size-cells = <2>;

+ 0 - 217
target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch
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-Subject: [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base
 
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-From: "chuanjia.liu" <[email protected]>
 
-
 
-Use regmap to get shared pcie-cfg base and change
 
-the method to get pcie irq.
 
-
 
-Signed-off-by: chuanjia.liu <[email protected]>
 
----
 
- drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++-------
 
- 1 file changed, 18 insertions(+), 7 deletions(-)
 
-
 
---- a/drivers/pci/controller/pcie-mediatek.c
 
-+++ b/drivers/pci/controller/pcie-mediatek.c
 
-@@ -14,6 +14,7 @@
 
- #include <linux/irqchip/chained_irq.h>
 
- #include <linux/irqdomain.h>
 
- #include <linux/kernel.h>
 
-+#include <linux/mfd/syscon.h>
 
- #include <linux/msi.h>
 
- #include <linux/module.h>
 
- #include <linux/of_address.h>
 
-@@ -23,6 +24,7 @@
 
- #include <linux/phy/phy.h>
 
- #include <linux/platform_device.h>
 
- #include <linux/pm_runtime.h>
 
-+#include <linux/regmap.h>
 
- #include <linux/reset.h>
 
- 
- #include "../pci.h"
 
-@@ -207,6 +209,7 @@ struct mtk_pcie_port {
 
-  * struct mtk_pcie - PCIe host information
 
-  * @dev: pointer to PCIe device
 
-  * @base: IO mapped register base
 
-+ * @cfg: IO mapped register map for PCIe config
 
-  * @free_ck: free-run reference clock
 
-  * @mem: non-prefetchable memory resource
 
-  * @ports: pointer to PCIe port information
 
-@@ -215,6 +218,7 @@ struct mtk_pcie_port {
 
- struct mtk_pcie {
 
- 	struct device *dev;
 
- 	void __iomem *base;
 
-+	struct regmap *cfg;
 
- 	struct clk *free_ck;
 
- 
- 	struct list_head ports;
 
-@@ -650,7 +654,7 @@ static int mtk_pcie_setup_irq(struct mtk
 
- 		return err;
 
- 	}
 
- 
--	port->irq = platform_get_irq(pdev, port->slot);
 
-+	port->irq = platform_get_irq_byname(pdev, "pcie_irq");
 
- 	if (port->irq < 0)
 
- 		return port->irq;
 
- 
-@@ -676,12 +680,11 @@ static int mtk_pcie_startup_port_v2(stru
 
- 	if (!mem)
 
- 		return -EINVAL;
 
- 
--	/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
 
--	if (pcie->base) {
 
--		val = readl(pcie->base + PCIE_SYS_CFG_V2);
 
--		val |= PCIE_CSR_LTSSM_EN(port->slot) |
 
--		       PCIE_CSR_ASPM_L1_EN(port->slot);
 
--		writel(val, pcie->base + PCIE_SYS_CFG_V2);
 
-+	/* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */
 
-+	if (pcie->cfg) {
 
-+		val = PCIE_CSR_LTSSM_EN(port->slot) |
 
-+		      PCIE_CSR_ASPM_L1_EN(port->slot);
 
-+		regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
 
- 	}
 
- 
- 	/* Assert all reset signals */
 
-@@ -985,6 +988,7 @@ static int mtk_pcie_subsys_powerup(struc
 
- 	struct device *dev = pcie->dev;
 
- 	struct platform_device *pdev = to_platform_device(dev);
 
- 	struct resource *regs;
 
-+	struct device_node *cfg_node;
 
- 	int err;
 
- 
- 	/* get shared registers, which are optional */
 
-@@ -997,6 +1001,13 @@ static int mtk_pcie_subsys_powerup(struc
 
- 		}
 
- 	}
 
- 
-+	cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0);
 
-+	if (cfg_node) {
 
-+		pcie->cfg = syscon_node_to_regmap(cfg_node);
 
-+		if (IS_ERR(pcie->cfg))
 
-+			return PTR_ERR(pcie->cfg);
 
-+	}
 
-+
 
- 	pcie->free_ck = devm_clk_get(dev, "free_ck");
 
- 	if (IS_ERR(pcie->free_ck)) {
 
- 		if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)

+ 0 - 417
target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
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-To: <[email protected]>, <[email protected]>, <[email protected]>
 
-Subject: [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for
 
- MT2712/MT7622
 
-Date: Thu, 28 May 2020 14:16:47 +0800
 
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-
 
-From: "chuanjia.liu" <[email protected]>
 
-
 
-There are two independent PCIe controllers in MT2712/MT7622 platform,
 
-and each of them should contain an independent MSI domain.
 
-
 
-In current architecture, MSI domain will be inherited from the root
 
-bridge, and all of the devices will share the same MSI domain.
 
-Hence that, the PCIe devices will not work properly if the irq number
 
-which required is more than 32.
 
-
 
-Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
 
-comply with the hardware design.
 
-
 
-Signed-off-by: chuanjia.liu <[email protected]>
 
----
 
- arch/arm64/boot/dts/mediatek/mt2712e.dtsi     | 75 +++++++++++--------
 
- .../dts/mediatek/mt7622-bananapi-bpi-r64.dts  | 16 ++--
 
- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts  |  6 +-
 
- arch/arm64/boot/dts/mediatek/mt7622.dtsi      | 68 +++++++++++------
 
- 4 files changed, 96 insertions(+), 69 deletions(-)
 
-
 
---- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
 
-+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
 
-@@ -915,60 +915,73 @@
 
- 		};
 
- 	};
 
- 
--	pcie: pcie@11700000 {
 
-+	pcie1: pcie@112ff000 {
 
- 		compatible = "mediatek,mt2712-pcie";
 
- 		device_type = "pci";
 
--		reg = <0 0x11700000 0 0x1000>,
 
--		      <0 0x112ff000 0 0x1000>;
 
--		reg-names = "port0", "port1";
 
-+		reg = <0 0x112ff000 0 0x1000>;
 
-+		reg-names = "port1";
 
- 		#address-cells = <3>;
 
- 		#size-cells = <2>;
 
--		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 
--			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 
--		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
 
--			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
 
--			 <&pericfg CLK_PERI_PCIE0>,
 
-+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 
-+		interrupt-names = "pcie_irq";
 
-+		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
 
- 			 <&pericfg CLK_PERI_PCIE1>;
 
--		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
 
--		phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
 
--		phy-names = "pcie-phy0", "pcie-phy1";
 
-+		clock-names = "sys_ck1", "ahb_ck1";
 
-+		phys = <&u3port1 PHY_TYPE_PCIE>;
 
-+		phy-names = "pcie-phy1";
 
- 		bus-range = <0x00 0xff>;
 
--		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;
 
-+		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
 
-+		status = "disabled";
 
- 
--		pcie0: pcie@0,0 {
 
--			device_type = "pci";
 
--			status = "disabled";
 
--			reg = <0x0000 0 0 0 0>;
 
-+		slot1: pcie@1,0 {
 
-+			reg = <0x0800 0 0 0 0>;
 
- 			#address-cells = <3>;
 
- 			#size-cells = <2>;
 
- 			#interrupt-cells = <1>;
 
- 			ranges;
 
- 			interrupt-map-mask = <0 0 0 7>;
 
--			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 
--					<0 0 0 2 &pcie_intc0 1>,
 
--					<0 0 0 3 &pcie_intc0 2>,
 
--					<0 0 0 4 &pcie_intc0 3>;
 
--			pcie_intc0: interrupt-controller {
 
-+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 
-+					<0 0 0 2 &pcie_intc1 1>,
 
-+					<0 0 0 3 &pcie_intc1 2>,
 
-+					<0 0 0 4 &pcie_intc1 3>;
 
-+			pcie_intc1: interrupt-controller {
 
- 				interrupt-controller;
 
- 				#address-cells = <0>;
 
- 				#interrupt-cells = <1>;
 
- 			};
 
- 		};
 
-+	};
 
- 
--		pcie1: pcie@1,0 {
 
--			device_type = "pci";
 
--			status = "disabled";
 
--			reg = <0x0800 0 0 0 0>;
 
-+	pcie0: pcie@11700000 {
 
-+		compatible = "mediatek,mt2712-pcie";
 
-+		device_type = "pci";
 
-+		reg = <0 0x11700000 0 0x1000>;
 
-+		reg-names = "port0";
 
-+		#address-cells = <3>;
 
-+		#size-cells = <2>;
 
-+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 
-+		interrupt-names = "pcie_irq";
 
-+		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
 
-+			 <&pericfg CLK_PERI_PCIE0>;
 
-+		clock-names = "sys_ck0", "ahb_ck0";
 
-+		phys = <&u3port0 PHY_TYPE_PCIE>;
 
-+		phy-names = "pcie-phy0";
 
-+		bus-range = <0x00 0xff>;
 
-+		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
 
-+		status = "disabled";
 
-+
 
-+		slot0: pcie@0,0 {
 
-+			reg = <0x0000 0 0 0 0>;
 
- 			#address-cells = <3>;
 
- 			#size-cells = <2>;
 
- 			#interrupt-cells = <1>;
 
- 			ranges;
 
- 			interrupt-map-mask = <0 0 0 7>;
 
--			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 
--					<0 0 0 2 &pcie_intc1 1>,
 
--					<0 0 0 3 &pcie_intc1 2>,
 
--					<0 0 0 4 &pcie_intc1 3>;
 
--			pcie_intc1: interrupt-controller {
 
-+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 
-+					<0 0 0 2 &pcie_intc0 1>,
 
-+					<0 0 0 3 &pcie_intc0 2>,
 
-+					<0 0 0 4 &pcie_intc0 3>;
 
-+			pcie_intc0: interrupt-controller {
 
- 				interrupt-controller;
 
- 				#address-cells = <0>;
 
- 				#interrupt-cells = <1>;
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-@@ -292,18 +292,16 @@
 
- 	};
 
- };
 
- 
--&pcie {
 
-+&pcie0 {
 
- 	pinctrl-names = "default";
 
--	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 
-+	pinctrl-0 = <&pcie0_pins>;
 
- 	status = "okay";
 
-+};
 
- 
--	pcie@0,0 {
 
--		status = "okay";
 
--	};
 
--
 
--	pcie@1,0 {
 
--		status = "okay";
 
--	};
 
-+&pcie1 {
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&pcie1_pins>;
 
-+	status = "okay";
 
- };
 
- 
- &pio {
 
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-@@ -802,45 +802,41 @@
 
- 		#reset-cells = <1>;
 
- 	};
 
- 
--	pcie: pcie@1a140000 {
 
-+	pciecfg: pciecfg@1a140000 {
 
-+		compatible = "mediatek,mt7622-pciecfg", "syscon";
 
-+		reg = <0 0x1a140000 0 0x1000>;
 
-+	};
 
-+
 
-+	pcie0: pcie@1a143000 {
 
- 		compatible = "mediatek,mt7622-pcie";
 
- 		device_type = "pci";
 
--		reg = <0 0x1a140000 0 0x1000>,
 
--		      <0 0x1a143000 0 0x1000>,
 
--		      <0 0x1a145000 0 0x1000>;
 
--		reg-names = "subsys", "port0", "port1";
 
-+		reg = <0 0x1a143000 0 0x1000>;
 
-+		reg-names = "port0";
 
-+		mediatek,pcie-cfg = <&pciecfg>;
 
- 		#address-cells = <3>;
 
- 		#size-cells = <2>;
 
--		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 
--			     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 
-+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
 
-+		interrupt-names = "pcie_irq";
 
- 		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 
--			 <&pciesys CLK_PCIE_P1_MAC_EN>,
 
--			 <&pciesys CLK_PCIE_P0_AHB_EN>,
 
- 			 <&pciesys CLK_PCIE_P0_AHB_EN>,
 
- 			 <&pciesys CLK_PCIE_P0_AUX_EN>,
 
--			 <&pciesys CLK_PCIE_P1_AUX_EN>,
 
- 			 <&pciesys CLK_PCIE_P0_AXI_EN>,
 
--			 <&pciesys CLK_PCIE_P1_AXI_EN>,
 
- 			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
 
--			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
 
--			 <&pciesys CLK_PCIE_P0_PIPE_EN>,
 
--			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
 
--		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 
--			      "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 
--			      "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 
-+			 <&pciesys CLK_PCIE_P0_PIPE_EN>;
 
-+		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
 
-+			      "axi_ck0", "obff_ck0", "pipe_ck0";
 
-+
 
- 		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 
- 		bus-range = <0x00 0xff>;
 
--		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
 
-+		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x8000000>;
 
- 		status = "disabled";
 
- 
--		pcie0: pcie@0,0 {
 
-+		slot0: pcie@0,0 {
 
- 			reg = <0x0000 0 0 0 0>;
 
- 			#address-cells = <3>;
 
- 			#size-cells = <2>;
 
- 			#interrupt-cells = <1>;
 
- 			ranges;
 
--			status = "disabled";
 
--
 
- 			interrupt-map-mask = <0 0 0 7>;
 
- 			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 
- 					<0 0 0 2 &pcie_intc0 1>,
 
-@@ -852,15 +848,39 @@
 
- 				#interrupt-cells = <1>;
 
- 			};
 
- 		};
 
-+	};
 
- 
--		pcie1: pcie@1,0 {
 
-+	pcie1: pcie@1a145000 {
 
-+		compatible = "mediatek,mt7622-pcie";
 
-+		device_type = "pci";
 
-+		reg = <0 0x1a145000 0 0x1000>;
 
-+		reg-names = "port1";
 
-+		mediatek,pcie-cfg = <&pciecfg>;
 
-+		#address-cells = <3>;
 
-+		#size-cells = <2>;
 
-+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 
-+		interrupt-names = "pcie_irq";
 
-+		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
 
-+			 /* designer has connect RC1 with p0_ahb clock */
 
-+			 <&pciesys CLK_PCIE_P0_AHB_EN>,
 
-+			 <&pciesys CLK_PCIE_P1_AUX_EN>,
 
-+			 <&pciesys CLK_PCIE_P1_AXI_EN>,
 
-+			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
 
-+			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
 
-+		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
 
-+			      "axi_ck1", "obff_ck1", "pipe_ck1";
 
-+
 
-+		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 
-+		bus-range = <0x00 0xff>;
 
-+		ranges = <0x82000000 0 0x28000000  0x0 0x28000000  0 0x8000000>;
 
-+		status = "disabled";
 
-+
 
-+		slot1: pcie@1,0 {
 
- 			reg = <0x0800 0 0 0 0>;
 
- 			#address-cells = <3>;
 
- 			#size-cells = <2>;
 
- 			#interrupt-cells = <1>;
 
- 			ranges;
 
--			status = "disabled";
 
--
 
- 			interrupt-map-mask = <0 0 0 7>;
 
- 			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 
- 					<0 0 0 2 &pcie_intc1 1>,
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 
-@@ -232,18 +232,16 @@
 
- 	};
 
- };
 
- 
--&pcie {
 
-+&pcie0 {
 
- 	pinctrl-names = "default";
 
--	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 
-+	pinctrl-0 = <&pcie0_pins>;
 
- 	status = "okay";
 
-+};
 
- 
--	pcie@0,0 {
 
--		status = "okay";
 
--	};
 
--
 
--	pcie@1,0 {
 
--		status = "okay";
 
--	};
 
-+&pcie1 {
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&pcie1_pins>;
 
-+	status = "okay";
 
- };
 
- 
- &pio {

+ 0 - 203
target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch
View File 

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-From: <[email protected]>
 
-To: <[email protected]>, <[email protected]>, <[email protected]>
 
-Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node
 
-Date: Thu, 28 May 2020 14:16:48 +0800
 
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-From: "chuanjia.liu" <[email protected]>
 
-
 
-Remove unused property and add pciecfg node.
 
-
 
-Signed-off-by: chuanjia.liu <[email protected]>
 
----
 
- arch/arm/boot/dts/mt7629-rfb.dts |  3 ++-
 
- arch/arm/boot/dts/mt7629.dtsi    | 23 +++++++++++++----------
 
- 2 files changed, 15 insertions(+), 11 deletions(-)
 
-
 
---- a/arch/arm/boot/dts/mt7629-rfb.dts
 
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
 
-@@ -149,9 +149,10 @@
 
- 	};
 
- };
 
- 
--&pcie {
 
-+&pcie1 {
 
- 	pinctrl-names = "default";
 
- 	pinctrl-0 = <&pcie_pins>;
 
-+	status = "okay";
 
- };
 
- 
- &pciephy1 {
 
---- a/arch/arm/boot/dts/mt7629.dtsi
 
-+++ b/arch/arm/boot/dts/mt7629.dtsi
 
-@@ -376,16 +376,21 @@
 
- 			#reset-cells = <1>;
 
- 		};
 
- 
--		pcie: pcie@1a140000 {
 
-+		pciecfg: pciecfg@1a140000 {
 
-+			compatible = "mediatek,mt7629-pciecfg", "syscon";
 
-+			reg = <0x1a140000 0x1000>;
 
-+		};
 
-+
 
-+		pcie1: pcie@1a145000 {
 
- 			compatible = "mediatek,mt7629-pcie";
 
- 			device_type = "pci";
 
--			reg = <0x1a140000 0x1000>,
 
--			      <0x1a145000 0x1000>;
 
--			reg-names = "subsys","port1";
 
-+			reg = <0x1a145000 0x1000>;
 
-+			reg-names = "port1";
 
-+			mediatek,pcie-cfg = <&pciecfg>;
 
- 			#address-cells = <3>;
 
- 			#size-cells = <2>;
 
--			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
 
--				     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 
-+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 
-+			interrupt-names = "pcie_irq";
 
- 			clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
 
- 				 <&pciesys CLK_PCIE_P0_AHB_EN>,
 
- 				 <&pciesys CLK_PCIE_P1_AUX_EN>,
 
-@@ -406,21 +411,19 @@
 
- 			power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 
- 			bus-range = <0x00 0xff>;
 
- 			ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
 
-+			status = "disabled";
 
- 
--			pcie1: pcie@1,0 {
 
--				device_type = "pci";
 
-+			slot1: pcie@1,0 {
 
- 				reg = <0x0800 0 0 0 0>;
 
- 				#address-cells = <3>;
 
- 				#size-cells = <2>;
 
- 				#interrupt-cells = <1>;
 
- 				ranges;
 
--				num-lanes = <1>;
 
- 				interrupt-map-mask = <0 0 0 7>;
 
- 				interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 
- 						<0 0 0 2 &pcie_intc1 1>,
 
- 						<0 0 0 3 &pcie_intc1 2>,
 
- 						<0 0 0 4 &pcie_intc1 3>;
 
--
 
- 				pcie_intc1: interrupt-controller {
 
- 					interrupt-controller;
 
- 					#address-cells = <0>;

+ 0 - 24
target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch
View File 

@@ -1,24 +0,0 @@
 
-From: Felix Fietkau <[email protected]>
 
-Date: Fri, 4 Sep 2020 18:33:27 +0200
 
-Subject: [PATCH] pcie-mediatek: fix clearing interrupt status
 
-
 
-Clearing the status needs to happen after running the handler, otherwise
 
-we will get an extra spurious interrupt after the cause has been cleared
 
-
 
-Signed-off-by: Felix Fietkau <[email protected]>
 
----
 
-
 
---- a/drivers/pci/controller/pcie-mediatek.c
 
-+++ b/drivers/pci/controller/pcie-mediatek.c
 
-@@ -615,10 +615,10 @@ static void mtk_pcie_intr_handler(struct
 
- 	if (status & INTX_MASK) {
 
- 		for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
 
- 			/* Clear the INTx */
 
--			writel(1 << bit, port->base + PCIE_INT_STATUS);
 
- 			virq = irq_find_mapping(port->irq_domain,
 
- 						bit - INTX_SHIFT);
 
- 			generic_handle_irq(virq);
 
-+			writel(1 << bit, port->base + PCIE_INT_STATUS);
 
- 		}
 
- 	}
 
-

+ 0 - 128
target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch
View File 

@@ -1,128 +0,0 @@
 
-From eda80b249df7bbc7b3dd13907343a3e59bfc57fd Mon Sep 17 00:00:00 2001
 
-From: Daniel Golle <[email protected]>
 
-Date: Tue, 4 Jan 2022 12:06:22 +0000
 
-Subject: [PATCH 1/3] net: ethernet: mtk_eth_soc: fix return values and
 
- refactor MDIO ops
 
-
 
-Instead of returning -1 (-EPERM) when MDIO bus is stuck busy
 
-while writing or 0xffff if it happens while reading, return the
 
-appropriate -ETIMEDOUT. Also fix return type to int instead of u32.
 
-Refactor functions to use bitfield helpers instead of having various
 
-masking and shifting constants in the code, which also results in the
 
-register definitions in the header file being more obviously related
 
-to what is stated in the MediaTek's Reference Manual.
 
-
 
-Fixes: 656e705243fd0 ("net-next: mediatek: add support for MT7623 ethernet")
 
-Signed-off-by: Daniel Golle <[email protected]>
 
-Signed-off-by: David S. Miller <[email protected]>
 
----
 
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 53 ++++++++++++---------
 
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 16 +++++--
 
- 2 files changed, 41 insertions(+), 28 deletions(-)
 
-
 
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 
-@@ -94,46 +94,53 @@ static int mtk_mdio_busy_wait(struct mtk
 
- 	}
 
- 
- 	dev_err(eth->dev, "mdio: MDIO timeout\n");
 
--	return -1;
 
-+	return -ETIMEDOUT;
 
- }
 
- 
--static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
 
--			   u32 phy_register, u32 write_data)
 
-+static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
 
-+			   u32 write_data)
 
- {
 
--	if (mtk_mdio_busy_wait(eth))
 
--		return -1;
 
-+	int ret;
 
- 
--	write_data &= 0xffff;
 
--
 
--	mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
 
--		(phy_register << PHY_IAC_REG_SHIFT) |
 
--		(phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
 
-+	ret = mtk_mdio_busy_wait(eth);
 
-+	if (ret < 0)
 
-+		return ret;
 
-+
 
-+	mtk_w32(eth, PHY_IAC_ACCESS |
 
-+		     PHY_IAC_START_C22 |
 
-+		     PHY_IAC_CMD_WRITE |
 
-+		     PHY_IAC_REG(phy_reg) |
 
-+		     PHY_IAC_ADDR(phy_addr) |
 
-+		     PHY_IAC_DATA(write_data),
 
- 		MTK_PHY_IAC);
 
- 
--	if (mtk_mdio_busy_wait(eth))
 
--		return -1;
 
-+	ret = mtk_mdio_busy_wait(eth);
 
-+	if (ret < 0)
 
-+		return ret;
 
- 
- 	return 0;
 
- }
 
- 
--static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
 
-+static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
 
- {
 
--	u32 d;
 
--
 
--	if (mtk_mdio_busy_wait(eth))
 
--		return 0xffff;
 
-+	int ret;
 
- 
--	mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
 
--		(phy_reg << PHY_IAC_REG_SHIFT) |
 
--		(phy_addr << PHY_IAC_ADDR_SHIFT),
 
-+	ret = mtk_mdio_busy_wait(eth);
 
-+	if (ret < 0)
 
-+		return ret;
 
-+
 
-+	mtk_w32(eth, PHY_IAC_ACCESS |
 
-+		     PHY_IAC_START_C22 |
 
-+		     PHY_IAC_CMD_C22_READ |
 
-+		     PHY_IAC_REG(phy_reg) |
 
-+		     PHY_IAC_ADDR(phy_addr),
 
- 		MTK_PHY_IAC);
 
- 
--	if (mtk_mdio_busy_wait(eth))
 
--		return 0xffff;
 
--
 
--	d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
 
-+	ret = mtk_mdio_busy_wait(eth);
 
-+	if (ret < 0)
 
-+		return ret;
 
- 
--	return d;
 
-+	return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
 
- }
 
- 
- static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
 
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 
-@@ -344,11 +344,17 @@
 
- /* PHY Indirect Access Control registers */
 
- #define MTK_PHY_IAC		0x10004
 
- #define PHY_IAC_ACCESS		BIT(31)
 
--#define PHY_IAC_READ		BIT(19)
 
--#define PHY_IAC_WRITE		BIT(18)
 
--#define PHY_IAC_START		BIT(16)
 
--#define PHY_IAC_ADDR_SHIFT	20
 
--#define PHY_IAC_REG_SHIFT	25
 
-+#define PHY_IAC_REG_MASK	GENMASK(29, 25)
 
-+#define PHY_IAC_REG(x)		FIELD_PREP(PHY_IAC_REG_MASK, (x))
 
-+#define PHY_IAC_ADDR_MASK	GENMASK(24, 20)
 
-+#define PHY_IAC_ADDR(x)		FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
 
-+#define PHY_IAC_CMD_MASK	GENMASK(19, 18)
 
-+#define PHY_IAC_CMD_WRITE	FIELD_PREP(PHY_IAC_CMD_MASK, 1)
 
-+#define PHY_IAC_CMD_C22_READ	FIELD_PREP(PHY_IAC_CMD_MASK, 2)
 
-+#define PHY_IAC_START_MASK	GENMASK(17, 16)
 
-+#define PHY_IAC_START_C22	FIELD_PREP(PHY_IAC_START_MASK, 1)
 
-+#define PHY_IAC_DATA_MASK	GENMASK(15, 0)
 
-+#define PHY_IAC_DATA(x)		FIELD_PREP(PHY_IAC_DATA_MASK, (x))
 
- #define PHY_IAC_TIMEOUT		HZ
 
- 
- #define MTK_MAC_MISC		0x1000c

+ 0 - 53
target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch
View File 

@@ -1,53 +0,0 @@
 
-From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001
 
-From: "Russell King (Oracle)" <[email protected]>
 
-Date: Tue, 4 Jan 2022 12:07:00 +0000
 
-Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and
 
- devad fields
 
-
 
-Add a couple of helpers and definitions to extract the clause 45 regad
 
-and devad fields from the regnum passed into MDIO drivers.
 
-
 
-Tested-by: Daniel Golle <[email protected]>
 
-Reviewed-by: Andrew Lunn <[email protected]>
 
-Signed-off-by: Russell King (Oracle) <[email protected]>
 
-Signed-off-by: Daniel Golle <[email protected]>
 
-Signed-off-by: David S. Miller <[email protected]>
 
----
 
- include/linux/mdio.h | 12 ++++++++++++
 
- 1 file changed, 12 insertions(+)
 
-
 
---- a/include/linux/mdio.h
 
-+++ b/include/linux/mdio.h
 
-@@ -7,6 +7,7 @@
 
- #define __LINUX_MDIO_H__
 
- 
- #include <uapi/linux/mdio.h>
 
-+#include <linux/bitfield.h>
 
- #include <linux/mod_devicetable.h>
 
- 
- /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
 
-@@ -14,6 +15,7 @@
 
-  */
 
- #define MII_ADDR_C45		(1<<30)
 
- #define MII_DEVADDR_C45_SHIFT	16
 
-+#define MII_DEVADDR_C45_MASK	GENMASK(20, 16)
 
- #define MII_REGADDR_C45_MASK	GENMASK(15, 0)
 
- 
- struct gpio_desc;
 
-@@ -342,6 +344,16 @@ static inline u32 mdiobus_c45_addr(int d
 
- 	return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;
 
- }
 
- 
-+static inline u16 mdiobus_c45_regad(u32 regnum)
 
-+{
 
-+	return FIELD_GET(MII_REGADDR_C45_MASK, regnum);
 
-+}
 
-+
 
-+static inline u16 mdiobus_c45_devad(u32 regnum)
 
-+{
 
-+	return FIELD_GET(MII_DEVADDR_C45_MASK, regnum);
 
-+}
 
-+
 
- static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,
 
- 				     u16 regnum)
 
- {

+ 0 - 128
target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch
View File 

@@ -1,128 +0,0 @@
 
-From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001
 
-From: Daniel Golle <[email protected]>
 
-Date: Tue, 4 Jan 2022 12:07:46 +0000
 
-Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
 
- access
 
-
 
-Implement read and write access to IEEE 802.3 Clause 45 Ethernet
 
-phy registers while making use of new mdiobus_c45_regad and
 
-mdiobus_c45_devad helpers.
 
-
 
-Tested on the Ubiquiti UniFi 6 LR access point featuring
 
-MediaTek MT7622BV WiSoC with Aquantia AQR112C.
 
-
 
-Signed-off-by: Daniel Golle <[email protected]>
 
-Signed-off-by: David S. Miller <[email protected]>
 
----
 
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++----
 
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +
 
- 2 files changed, 60 insertions(+), 13 deletions(-)
 
-
 
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 
-@@ -106,13 +106,35 @@ static int _mtk_mdio_write(struct mtk_et
 
- 	if (ret < 0)
 
- 		return ret;
 
- 
--	mtk_w32(eth, PHY_IAC_ACCESS |
 
--		     PHY_IAC_START_C22 |
 
--		     PHY_IAC_CMD_WRITE |
 
--		     PHY_IAC_REG(phy_reg) |
 
--		     PHY_IAC_ADDR(phy_addr) |
 
--		     PHY_IAC_DATA(write_data),
 
--		MTK_PHY_IAC);
 
-+	if (phy_reg & MII_ADDR_C45) {
 
-+		mtk_w32(eth, PHY_IAC_ACCESS |
 
-+			     PHY_IAC_START_C45 |
 
-+			     PHY_IAC_CMD_C45_ADDR |
 
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
 
-+			     PHY_IAC_ADDR(phy_addr) |
 
-+			     PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
 
-+			MTK_PHY_IAC);
 
-+
 
-+		ret = mtk_mdio_busy_wait(eth);
 
-+		if (ret < 0)
 
-+			return ret;
 
-+
 
-+		mtk_w32(eth, PHY_IAC_ACCESS |
 
-+			     PHY_IAC_START_C45 |
 
-+			     PHY_IAC_CMD_WRITE |
 
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
 
-+			     PHY_IAC_ADDR(phy_addr) |
 
-+			     PHY_IAC_DATA(write_data),
 
-+			MTK_PHY_IAC);
 
-+	} else {
 
-+		mtk_w32(eth, PHY_IAC_ACCESS |
 
-+			     PHY_IAC_START_C22 |
 
-+			     PHY_IAC_CMD_WRITE |
 
-+			     PHY_IAC_REG(phy_reg) |
 
-+			     PHY_IAC_ADDR(phy_addr) |
 
-+			     PHY_IAC_DATA(write_data),
 
-+			MTK_PHY_IAC);
 
-+	}
 
- 
- 	ret = mtk_mdio_busy_wait(eth);
 
- 	if (ret < 0)
 
-@@ -129,12 +151,33 @@ static int _mtk_mdio_read(struct mtk_eth
 
- 	if (ret < 0)
 
- 		return ret;
 
- 
--	mtk_w32(eth, PHY_IAC_ACCESS |
 
--		     PHY_IAC_START_C22 |
 
--		     PHY_IAC_CMD_C22_READ |
 
--		     PHY_IAC_REG(phy_reg) |
 
--		     PHY_IAC_ADDR(phy_addr),
 
--		MTK_PHY_IAC);
 
-+	if (phy_reg & MII_ADDR_C45) {
 
-+		mtk_w32(eth, PHY_IAC_ACCESS |
 
-+			     PHY_IAC_START_C45 |
 
-+			     PHY_IAC_CMD_C45_ADDR |
 
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
 
-+			     PHY_IAC_ADDR(phy_addr) |
 
-+			     PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
 
-+			MTK_PHY_IAC);
 
-+
 
-+		ret = mtk_mdio_busy_wait(eth);
 
-+		if (ret < 0)
 
-+			return ret;
 
-+
 
-+		mtk_w32(eth, PHY_IAC_ACCESS |
 
-+			     PHY_IAC_START_C45 |
 
-+			     PHY_IAC_CMD_C45_READ |
 
-+			     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
 
-+			     PHY_IAC_ADDR(phy_addr),
 
-+			MTK_PHY_IAC);
 
-+	} else {
 
-+		mtk_w32(eth, PHY_IAC_ACCESS |
 
-+			     PHY_IAC_START_C22 |
 
-+			     PHY_IAC_CMD_C22_READ |
 
-+			     PHY_IAC_REG(phy_reg) |
 
-+			     PHY_IAC_ADDR(phy_addr),
 
-+			MTK_PHY_IAC);
 
-+	}
 
- 
- 	ret = mtk_mdio_busy_wait(eth);
 
- 	if (ret < 0)
 
-@@ -593,6 +636,7 @@ static int mtk_mdio_init(struct mtk_eth
 
- 	eth->mii_bus->name = "mdio";
 
- 	eth->mii_bus->read = mtk_mdio_read;
 
- 	eth->mii_bus->write = mtk_mdio_write;
 
-+	eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
 
- 	eth->mii_bus->priv = eth;
 
- 	eth->mii_bus->parent = eth->dev;
 
- 
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 
-@@ -349,9 +349,12 @@
 
- #define PHY_IAC_ADDR_MASK	GENMASK(24, 20)
 
- #define PHY_IAC_ADDR(x)		FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
 
- #define PHY_IAC_CMD_MASK	GENMASK(19, 18)
 
-+#define PHY_IAC_CMD_C45_ADDR	FIELD_PREP(PHY_IAC_CMD_MASK, 0)
 
- #define PHY_IAC_CMD_WRITE	FIELD_PREP(PHY_IAC_CMD_MASK, 1)
 
- #define PHY_IAC_CMD_C22_READ	FIELD_PREP(PHY_IAC_CMD_MASK, 2)
 
-+#define PHY_IAC_CMD_C45_READ	FIELD_PREP(PHY_IAC_CMD_MASK, 3)
 
- #define PHY_IAC_START_MASK	GENMASK(17, 16)
 
-+#define PHY_IAC_START_C45	FIELD_PREP(PHY_IAC_START_MASK, 0)
 
- #define PHY_IAC_START_C22	FIELD_PREP(PHY_IAC_START_MASK, 1)
 
- #define PHY_IAC_DATA_MASK	GENMASK(15, 0)
 
- #define PHY_IAC_DATA(x)		FIELD_PREP(PHY_IAC_DATA_MASK, (x))

+ 0 - 10
target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch
View File 

@@ -1,10 +0,0 @@
 
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 
-@@ -577,6 +577,7 @@ static void mtk_validate(struct phylink_
 
- 		if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
 
- 			phylink_set(mask, 1000baseT_Full);
 
- 			phylink_set(mask, 1000baseX_Full);
 
-+			phylink_set(mask, 2500baseT_Full);
 
- 			phylink_set(mask, 2500baseX_Full);
 
- 		}
 
- 		if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) {

+ 0 - 96
target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
View File 

@@ -1,96 +0,0 @@
 
-From: Felix Fietkau <[email protected]>
 
-Date: Fri, 4 Sep 2020 18:42:42 +0200
 
-Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
 
-
 
-It improves performance by eliminating the need for a cache flush for DMA on
 
-attached devices
 
-
 
-Signed-off-by: Felix Fietkau <[email protected]>
 
----
 
-
 
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-@@ -813,6 +813,8 @@
 
- 		reg = <0 0x1a143000 0 0x1000>;
 
- 		reg-names = "port0";
 
- 		mediatek,pcie-cfg = <&pciecfg>;
 
-+		mediatek,hifsys = <&hifsys>;
 
-+		mediatek,cci-control = <&cci_control2>;
 
- 		#address-cells = <3>;
 
- 		#size-cells = <2>;
 
- 		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
 
-@@ -830,6 +832,7 @@
 
- 		bus-range = <0x00 0xff>;
 
- 		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x8000000>;
 
- 		status = "disabled";
 
-+		dma-coherent;
 
- 
- 		slot0: pcie@0,0 {
 
- 			reg = <0x0000 0 0 0 0>;
 
-@@ -856,6 +859,8 @@
 
- 		reg = <0 0x1a145000 0 0x1000>;
 
- 		reg-names = "port1";
 
- 		mediatek,pcie-cfg = <&pciecfg>;
 
-+		mediatek,hifsys = <&hifsys>;
 
-+		mediatek,cci-control = <&cci_control2>;
 
- 		#address-cells = <3>;
 
- 		#size-cells = <2>;
 
- 		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 
-@@ -874,6 +879,7 @@
 
- 		bus-range = <0x00 0xff>;
 
- 		ranges = <0x82000000 0 0x28000000  0x0 0x28000000  0 0x8000000>;
 
- 		status = "disabled";
 
-+		dma-coherent;
 
- 
- 		slot1: pcie@1,0 {
 
- 			reg = <0x0800 0 0 0 0>;
 
---- a/drivers/pci/controller/pcie-mediatek.c
 
-+++ b/drivers/pci/controller/pcie-mediatek.c
 
-@@ -20,6 +20,7 @@
 
- #include <linux/of_address.h>
 
- #include <linux/of_pci.h>
 
- #include <linux/of_platform.h>
 
-+#include <linux/of_address.h>
 
- #include <linux/pci.h>
 
- #include <linux/phy/phy.h>
 
- #include <linux/platform_device.h>
 
-@@ -139,6 +140,11 @@
 
- #define PCIE_LINK_STATUS_V2	0x804
 
- #define PCIE_PORT_LINKUP_V2	BIT(10)
 
- 
-+/* DMA channel mapping */
 
-+#define HIFSYS_DMA_AG_MAP	0x008
 
-+#define HIFSYS_DMA_AG_MAP_PCIE0	BIT(0)
 
-+#define HIFSYS_DMA_AG_MAP_PCIE1	BIT(1)
 
-+
 
- struct mtk_pcie_port;
 
- 
- /**
 
-@@ -1042,6 +1048,27 @@ static int mtk_pcie_setup(struct mtk_pci
 
- 	struct mtk_pcie_port *port, *tmp;
 
- 	int err;
 
- 
-+	if (of_dma_is_coherent(node)) {
 
-+		struct regmap *con;
 
-+		u32 mask;
 
-+
 
-+		con = syscon_regmap_lookup_by_phandle(node,
 
-+						      "mediatek,cci-control");
 
-+		/* enable CPU/bus coherency */
 
-+		if (!IS_ERR(con))
 
-+			regmap_write(con, 0, 3);
 
-+
 
-+		con = syscon_regmap_lookup_by_phandle(node,
 
-+						      "mediatek,hifsys");
 
-+		if (IS_ERR(con)) {
 
-+			dev_err(dev, "missing hifsys node\n");
 
-+			return PTR_ERR(con);
 
-+		}
 
-+
 
-+		mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
 
-+		regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
 
-+	}
 
-+
 
- 	for_each_available_child_of_node(node, child) {
 
- 		int slot;
 
-

+ 0 - 27
target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch
View File 

@@ -1,27 +0,0 @@
 
-From: Jip de Beer <[email protected]>
 
-Date: Sun, 9 Jan 2022 13:14:04 +0100
 
-Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts
 
-
 
-The lowest frequency should be 300MHz, since that is the label
 
-assigned to the OPP in the mt7622.dtsi device tree, while there is one
 
-missing zero in the actual value.
 
-
 
-To be clear, the lowest frequency should be 300MHz instead of 30MHz.
 
-
 
-As mentioned @dangowrt on the OpenWrt forum there is no benefit in
 
-leaving 30MHz as the lowest frequency.
 
-
 
-Signed-off-by: Jip de Beer <[email protected]>
 
-Signed-off-by: Fritz D. Ansel <[email protected]>
 
----
 
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 
-@@ -24,7 +24,7 @@
 
- 		compatible = "operating-points-v2";
 
- 		opp-shared;
 
- 		opp-300000000 {
 
--			opp-hz = /bits/ 64 <30000000>;
 
-+			opp-hz = /bits/ 64 <300000000>;
 
- 			opp-microvolt = <950000>;
 
- 		};
 
-

+ 0 - 29
target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch
View File 

@@ -1,29 +0,0 @@
 
---- a/drivers/leds/Kconfig
 
-+++ b/drivers/leds/Kconfig
 
-@@ -929,6 +929,16 @@ config LEDS_ACER_A500
 
- 	  This option enables support for the Power Button LED of
 
- 	  Acer Iconia Tab A500.
 
- 
-+config LEDS_UBNT_LEDBAR
 
-+	tristate "LED support for Ubiquiti UniFi 6 LR"
 
-+	depends on LEDS_CLASS && I2C && OF
 
-+	help
 
-+	  This option enables support for the Ubiquiti LEDBAR
 
-+	  LED driver.
 
-+
 
-+	  To compile this driver as a module, choose M here: the module
 
-+	  will be called leds-ubnt-ledbar.
 
-+
 
- comment "LED Triggers"
 
- source "drivers/leds/trigger/Kconfig"
 
- 
---- a/drivers/leds/Makefile
 
-+++ b/drivers/leds/Makefile
 
-@@ -93,6 +93,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA)		+= leds
 
- obj-$(CONFIG_LEDS_WM831X_STATUS)	+= leds-wm831x-status.o
 
- obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
 
- obj-$(CONFIG_LEDS_WRAP)			+= leds-wrap.o
 
-+obj-$(CONFIG_LEDS_UBNT_LEDBAR)		+= leds-ubnt-ledbar.o
 
- 
- # LED SPI Drivers
 
- obj-$(CONFIG_LEDS_CR0014114)		+= leds-cr0014114.o

+ 0 - 65
target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch
View File 

@@ -1,65 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-@@ -308,7 +308,7 @@
 
- 	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 
- 	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
 
- 	 */
 
--	asm_sel {
 
-+	asmsel: asm_sel {
 
- 		gpio-hog;
 
- 		gpios = <90 GPIO_ACTIVE_HIGH>;
 
- 		output-high;
 
---- /dev/null
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dts
 
-@@ -0,0 +1,31 @@
 
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
 
-+
 
-+#include <dt-bindings/gpio/gpio.h>
 
-+
 
-+/dts-v1/;
 
-+/plugin/;
 
-+
 
-+/ {
 
-+	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
 
-+
 
-+	fragment@0 {
 
-+		target = <&asmsel>;
 
-+		__overlay__ {
 
-+			gpios = <90 GPIO_ACTIVE_LOW>;
 
-+		};
 
-+	};
 
-+
 
-+	fragment@1 {
 
-+		target = <&sata>;
 
-+		__overlay__ {
 
-+			status = "okay";
 
-+		};
 
-+	};
 
-+
 
-+	fragment@2 {
 
-+		target = <&sata_phy>;
 
-+		__overlay__ {
 
-+			status = "okay";
 
-+		};
 
-+	};
 
-+};
 
---- /dev/null
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dts
 
-@@ -0,0 +1,17 @@
 
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
 
-+
 
-+#include <dt-bindings/gpio/gpio.h>
 
-+
 
-+/dts-v1/;
 
-+/plugin/;
 
-+
 
-+/ {
 
-+	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
 
-+
 
-+	fragment@0 {
 
-+		target = <&asmsel>;
 
-+		__overlay__ {
 
-+			gpios = <90 GPIO_ACTIVE_HIGH>;
 
-+		};
 
-+	};
 
-+};

+ 0 - 31
target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch
View File 

@@ -1,31 +0,0 @@
 
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
 
-@@ -632,5 +632,28 @@
 
- };
 
- 
- &wmac {
 
-+	mediatek,eeprom-data = <0x22760500	0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x0		0x44000020	0x0		0x10002000
 
-+				0x4400		0x4000000	0x0		0x0
 
-+				0x200000b3	0x40b6c3c3	0x26000000	0x41c42600
 
-+				0x41c4		0x26000000	0xc0c52600	0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0xc6c6
 
-+				0xc3c3c2c1	0xc300c3	0x818181	0x83c1c182
 
-+				0x83838382	0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x84002e00	0x90000087	0x8a000000	0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0xb000009	0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x0
 
-+				0x0		0x0		0x0		0x7707>;
 
-+
 
- 	status = "okay";
 
- };